1 /**************************************************************************
3 Copyright 2002 ATI Technologies Inc., Ontario, Canada, and
8 Permission is hereby granted, free of charge, to any person obtaining a
9 copy of this software and associated documentation files (the "Software"),
10 to deal in the Software without restriction, including without limitation
11 on the rights to use, copy, modify, merge, publish, distribute, sub
12 license, and/or sell copies of the Software, and to permit persons to whom
13 the Software is furnished to do so, subject to the following conditions:
15 The above copyright notice and this permission notice (including the next
16 paragraph) shall be included in all copies or substantial portions of the
19 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
22 ATI, VMWARE AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
23 DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
24 OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
25 USE OR OTHER DEALINGS IN THE SOFTWARE.
27 **************************************************************************/
31 * Keith Whitwell <keithw@vmware.com>
37 #include "main/glheader.h"
38 #include "main/imports.h"
40 #include "r200_context.h"
41 #include "r200_sanity.h"
42 #include "radeon_reg.h"
45 /* Set this '1' to get more verbiage.
47 #define MORE_VERBOSE 1
50 #define VERBOSE (R200_DEBUG & RADEON_VERBOSE)
54 #define NORMAL (R200_DEBUG & RADEON_VERBOSE)
58 /* New (1.3) state mechanism. 3 commands (packet, scalar, vector) in
59 * 1.3 cmdbuffers allow all previous state to be updated as well as
60 * the tcl scalar and vector areas.
66 } packet
[RADEON_MAX_STATE_PACKETS
] = {
67 { RADEON_PP_MISC
,7,"RADEON_PP_MISC" },
68 { RADEON_PP_CNTL
,3,"RADEON_PP_CNTL" },
69 { RADEON_RB3D_COLORPITCH
,1,"RADEON_RB3D_COLORPITCH" },
70 { RADEON_RE_LINE_PATTERN
,2,"RADEON_RE_LINE_PATTERN" },
71 { RADEON_SE_LINE_WIDTH
,1,"RADEON_SE_LINE_WIDTH" },
72 { RADEON_PP_LUM_MATRIX
,1,"RADEON_PP_LUM_MATRIX" },
73 { RADEON_PP_ROT_MATRIX_0
,2,"RADEON_PP_ROT_MATRIX_0" },
74 { RADEON_RB3D_STENCILREFMASK
,3,"RADEON_RB3D_STENCILREFMASK" },
75 { RADEON_SE_VPORT_XSCALE
,6,"RADEON_SE_VPORT_XSCALE" },
76 { RADEON_SE_CNTL
,2,"RADEON_SE_CNTL" },
77 { RADEON_SE_CNTL_STATUS
,1,"RADEON_SE_CNTL_STATUS" },
78 { RADEON_RE_MISC
,1,"RADEON_RE_MISC" },
79 { RADEON_PP_TXFILTER_0
,6,"RADEON_PP_TXFILTER_0" },
80 { RADEON_PP_BORDER_COLOR_0
,1,"RADEON_PP_BORDER_COLOR_0" },
81 { RADEON_PP_TXFILTER_1
,6,"RADEON_PP_TXFILTER_1" },
82 { RADEON_PP_BORDER_COLOR_1
,1,"RADEON_PP_BORDER_COLOR_1" },
83 { RADEON_PP_TXFILTER_2
,6,"RADEON_PP_TXFILTER_2" },
84 { RADEON_PP_BORDER_COLOR_2
,1,"RADEON_PP_BORDER_COLOR_2" },
85 { RADEON_SE_ZBIAS_FACTOR
,2,"RADEON_SE_ZBIAS_FACTOR" },
86 { RADEON_SE_TCL_OUTPUT_VTX_FMT
,11,"RADEON_SE_TCL_OUTPUT_VTX_FMT" },
87 { RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED
,17,"RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED" },
88 { R200_PP_TXCBLEND_0
, 4, "R200_EMIT_PP_TXCBLEND_0" },
89 { R200_PP_TXCBLEND_1
, 4, "R200_PP_TXCBLEND_1" },
90 { R200_PP_TXCBLEND_2
, 4, "R200_PP_TXCBLEND_2" },
91 { R200_PP_TXCBLEND_3
, 4, "R200_PP_TXCBLEND_3" },
92 { R200_PP_TXCBLEND_4
, 4, "R200_PP_TXCBLEND_4" },
93 { R200_PP_TXCBLEND_5
, 4, "R200_PP_TXCBLEND_5" },
94 { R200_PP_TXCBLEND_6
, 4, "R200_PP_TXCBLEND_6" },
95 { R200_PP_TXCBLEND_7
, 4, "R200_PP_TXCBLEND_7" },
96 { R200_SE_TCL_LIGHT_MODEL_CTL_0
, 6, "R200_SE_TCL_LIGHT_MODEL_CTL_0" },
97 { R200_PP_TFACTOR_0
, 6, "R200_PP_TFACTOR_0" },
98 { R200_SE_VTX_FMT_0
, 4, "R200_SE_VTX_FMT_0" },
99 { R200_SE_VAP_CNTL
, 1, "R200_SE_VAP_CNTL" },
100 { R200_SE_TCL_MATRIX_SEL_0
, 5, "R200_SE_TCL_MATRIX_SEL_0" },
101 { R200_SE_TCL_TEX_PROC_CTL_2
, 5, "R200_SE_TCL_TEX_PROC_CTL_2" },
102 { R200_SE_TCL_UCP_VERT_BLEND_CTL
, 1, "R200_SE_TCL_UCP_VERT_BLEND_CTL" },
103 { R200_PP_TXFILTER_0
, 6, "R200_PP_TXFILTER_0" },
104 { R200_PP_TXFILTER_1
, 6, "R200_PP_TXFILTER_1" },
105 { R200_PP_TXFILTER_2
, 6, "R200_PP_TXFILTER_2" },
106 { R200_PP_TXFILTER_3
, 6, "R200_PP_TXFILTER_3" },
107 { R200_PP_TXFILTER_4
, 6, "R200_PP_TXFILTER_4" },
108 { R200_PP_TXFILTER_5
, 6, "R200_PP_TXFILTER_5" },
109 { R200_PP_TXOFFSET_0
, 1, "R200_PP_TXOFFSET_0" },
110 { R200_PP_TXOFFSET_1
, 1, "R200_PP_TXOFFSET_1" },
111 { R200_PP_TXOFFSET_2
, 1, "R200_PP_TXOFFSET_2" },
112 { R200_PP_TXOFFSET_3
, 1, "R200_PP_TXOFFSET_3" },
113 { R200_PP_TXOFFSET_4
, 1, "R200_PP_TXOFFSET_4" },
114 { R200_PP_TXOFFSET_5
, 1, "R200_PP_TXOFFSET_5" },
115 { R200_SE_VTE_CNTL
, 1, "R200_SE_VTE_CNTL" },
116 { R200_SE_TCL_OUTPUT_VTX_COMP_SEL
, 1, "R200_SE_TCL_OUTPUT_VTX_COMP_SEL" },
117 { R200_PP_TAM_DEBUG3
, 1, "R200_PP_TAM_DEBUG3" },
118 { R200_PP_CNTL_X
, 1, "R200_PP_CNTL_X" },
119 { R200_RB3D_DEPTHXY_OFFSET
, 1, "R200_RB3D_DEPTHXY_OFFSET" },
120 { R200_RE_AUX_SCISSOR_CNTL
, 1, "R200_RE_AUX_SCISSOR_CNTL" },
121 { R200_RE_SCISSOR_TL_0
, 2, "R200_RE_SCISSOR_TL_0" },
122 { R200_RE_SCISSOR_TL_1
, 2, "R200_RE_SCISSOR_TL_1" },
123 { R200_RE_SCISSOR_TL_2
, 2, "R200_RE_SCISSOR_TL_2" },
124 { R200_SE_VAP_CNTL_STATUS
, 1, "R200_SE_VAP_CNTL_STATUS" },
125 { R200_SE_VTX_STATE_CNTL
, 1, "R200_SE_VTX_STATE_CNTL" },
126 { R200_RE_POINTSIZE
, 1, "R200_RE_POINTSIZE" },
127 { R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0
, 4, "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0" },
128 { R200_PP_CUBIC_FACES_0
, 1, "R200_PP_CUBIC_FACES_0" }, /* 61 */
129 { R200_PP_CUBIC_OFFSET_F1_0
, 5, "R200_PP_CUBIC_OFFSET_F1_0" }, /* 62 */
130 { R200_PP_CUBIC_FACES_1
, 1, "R200_PP_CUBIC_FACES_1" },
131 { R200_PP_CUBIC_OFFSET_F1_1
, 5, "R200_PP_CUBIC_OFFSET_F1_1" },
132 { R200_PP_CUBIC_FACES_2
, 1, "R200_PP_CUBIC_FACES_2" },
133 { R200_PP_CUBIC_OFFSET_F1_2
, 5, "R200_PP_CUBIC_OFFSET_F1_2" },
134 { R200_PP_CUBIC_FACES_3
, 1, "R200_PP_CUBIC_FACES_3" },
135 { R200_PP_CUBIC_OFFSET_F1_3
, 5, "R200_PP_CUBIC_OFFSET_F1_3" },
136 { R200_PP_CUBIC_FACES_4
, 1, "R200_PP_CUBIC_FACES_4" },
137 { R200_PP_CUBIC_OFFSET_F1_4
, 5, "R200_PP_CUBIC_OFFSET_F1_4" },
138 { R200_PP_CUBIC_FACES_5
, 1, "R200_PP_CUBIC_FACES_5" },
139 { R200_PP_CUBIC_OFFSET_F1_5
, 5, "R200_PP_CUBIC_OFFSET_F1_5" },
140 { RADEON_PP_TEX_SIZE_0
, 2, "RADEON_PP_TEX_SIZE_0" },
141 { RADEON_PP_TEX_SIZE_1
, 2, "RADEON_PP_TEX_SIZE_1" },
142 { RADEON_PP_TEX_SIZE_2
, 2, "RADEON_PP_TEX_SIZE_2" },
143 { R200_RB3D_BLENDCOLOR
, 3, "R200_RB3D_BLENDCOLOR" },
144 { R200_SE_TCL_POINT_SPRITE_CNTL
, 1, "R200_SE_TCL_POINT_SPRITE_CNTL" },
145 { RADEON_PP_CUBIC_FACES_0
, 1, "RADEON_PP_CUBIC_FACES_0" },
146 { RADEON_PP_CUBIC_OFFSET_T0_0
, 5, "RADEON_PP_CUBIC_OFFSET_T0_0" },
147 { RADEON_PP_CUBIC_FACES_1
, 1, "RADEON_PP_CUBIC_FACES_1" },
148 { RADEON_PP_CUBIC_OFFSET_T1_0
, 5, "RADEON_PP_CUBIC_OFFSET_T1_0" },
149 { RADEON_PP_CUBIC_FACES_2
, 1, "RADEON_PP_CUBIC_FACES_2" },
150 { RADEON_PP_CUBIC_OFFSET_T2_0
, 5, "RADEON_PP_CUBIC_OFFSET_T2_0" },
151 { R200_PP_TRI_PERF
, 2, "R200_PP_TRI_PERF" },
152 { R200_PP_TXCBLEND_8
, 32, "R200_PP_AFS_0"}, /* 85 */
153 { R200_PP_TXCBLEND_0
, 32, "R200_PP_AFS_1"},
154 { R200_PP_TFACTOR_0
, 8, "R200_ATF_TFACTOR"},
155 { R200_PP_TXFILTER_0
, 8, "R200_PP_TXCTLALL_0"},
156 { R200_PP_TXFILTER_1
, 8, "R200_PP_TXCTLALL_1"},
157 { R200_PP_TXFILTER_2
, 8, "R200_PP_TXCTLALL_2"},
158 { R200_PP_TXFILTER_3
, 8, "R200_PP_TXCTLALL_3"},
159 { R200_PP_TXFILTER_4
, 8, "R200_PP_TXCTLALL_4"},
160 { R200_PP_TXFILTER_5
, 8, "R200_PP_TXCTLALL_5"},
161 { R200_VAP_PVS_CNTL_1
, 2, "R200_VAP_PVS_CNTL"},
169 static struct reg_names reg_names
[] = {
170 { R200_PP_MISC
, "R200_PP_MISC" },
171 { R200_PP_FOG_COLOR
, "R200_PP_FOG_COLOR" },
172 { R200_RE_SOLID_COLOR
, "R200_RE_SOLID_COLOR" },
173 { R200_RB3D_BLENDCNTL
, "R200_RB3D_BLENDCNTL" },
174 { R200_RB3D_DEPTHOFFSET
, "R200_RB3D_DEPTHOFFSET" },
175 { R200_RB3D_DEPTHPITCH
, "R200_RB3D_DEPTHPITCH" },
176 { R200_RB3D_ZSTENCILCNTL
, "R200_RB3D_ZSTENCILCNTL" },
177 { R200_PP_CNTL
, "R200_PP_CNTL" },
178 { R200_RB3D_CNTL
, "R200_RB3D_CNTL" },
179 { R200_RB3D_COLOROFFSET
, "R200_RB3D_COLOROFFSET" },
180 { R200_RE_WIDTH_HEIGHT
, "R200_RE_WIDTH_HEIGHT" },
181 { R200_RB3D_COLORPITCH
, "R200_RB3D_COLORPITCH" },
182 { R200_SE_CNTL
, "R200_SE_CNTL" },
183 { R200_RE_CNTL
, "R200_RE_CNTL" },
184 { R200_RE_MISC
, "R200_RE_MISC" },
185 { R200_RE_STIPPLE_ADDR
, "R200_RE_STIPPLE_ADDR" },
186 { R200_RE_STIPPLE_DATA
, "R200_RE_STIPPLE_DATA" },
187 { R200_RE_LINE_PATTERN
, "R200_RE_LINE_PATTERN" },
188 { R200_RE_LINE_STATE
, "R200_RE_LINE_STATE" },
189 { R200_RE_SCISSOR_TL_0
, "R200_RE_SCISSOR_TL_0" },
190 { R200_RE_SCISSOR_BR_0
, "R200_RE_SCISSOR_BR_0" },
191 { R200_RE_SCISSOR_TL_1
, "R200_RE_SCISSOR_TL_1" },
192 { R200_RE_SCISSOR_BR_1
, "R200_RE_SCISSOR_BR_1" },
193 { R200_RE_SCISSOR_TL_2
, "R200_RE_SCISSOR_TL_2" },
194 { R200_RE_SCISSOR_BR_2
, "R200_RE_SCISSOR_BR_2" },
195 { R200_RB3D_DEPTHXY_OFFSET
, "R200_RB3D_DEPTHXY_OFFSET" },
196 { R200_RB3D_STENCILREFMASK
, "R200_RB3D_STENCILREFMASK" },
197 { R200_RB3D_ROPCNTL
, "R200_RB3D_ROPCNTL" },
198 { R200_RB3D_PLANEMASK
, "R200_RB3D_PLANEMASK" },
199 { R200_SE_VPORT_XSCALE
, "R200_SE_VPORT_XSCALE" },
200 { R200_SE_VPORT_XOFFSET
, "R200_SE_VPORT_XOFFSET" },
201 { R200_SE_VPORT_YSCALE
, "R200_SE_VPORT_YSCALE" },
202 { R200_SE_VPORT_YOFFSET
, "R200_SE_VPORT_YOFFSET" },
203 { R200_SE_VPORT_ZSCALE
, "R200_SE_VPORT_ZSCALE" },
204 { R200_SE_VPORT_ZOFFSET
, "R200_SE_VPORT_ZOFFSET" },
205 { R200_SE_ZBIAS_FACTOR
, "R200_SE_ZBIAS_FACTOR" },
206 { R200_SE_ZBIAS_CONSTANT
, "R200_SE_ZBIAS_CONSTANT" },
207 { R200_SE_LINE_WIDTH
, "R200_SE_LINE_WIDTH" },
208 { R200_SE_VAP_CNTL
, "R200_SE_VAP_CNTL" },
209 { R200_SE_VF_CNTL
, "R200_SE_VF_CNTL" },
210 { R200_SE_VTX_FMT_0
, "R200_SE_VTX_FMT_0" },
211 { R200_SE_VTX_FMT_1
, "R200_SE_VTX_FMT_1" },
212 { R200_SE_TCL_OUTPUT_VTX_FMT_0
, "R200_SE_TCL_OUTPUT_VTX_FMT_0" },
213 { R200_SE_TCL_OUTPUT_VTX_FMT_1
, "R200_SE_TCL_OUTPUT_VTX_FMT_1" },
214 { R200_SE_VTE_CNTL
, "R200_SE_VTE_CNTL" },
215 { R200_SE_VTX_NUM_ARRAYS
, "R200_SE_VTX_NUM_ARRAYS" },
216 { R200_SE_VTX_AOS_ATTR01
, "R200_SE_VTX_AOS_ATTR01" },
217 { R200_SE_VTX_AOS_ADDR0
, "R200_SE_VTX_AOS_ADDR0" },
218 { R200_SE_VTX_AOS_ADDR1
, "R200_SE_VTX_AOS_ADDR1" },
219 { R200_SE_VTX_AOS_ATTR23
, "R200_SE_VTX_AOS_ATTR23" },
220 { R200_SE_VTX_AOS_ADDR2
, "R200_SE_VTX_AOS_ADDR2" },
221 { R200_SE_VTX_AOS_ADDR3
, "R200_SE_VTX_AOS_ADDR3" },
222 { R200_SE_VTX_AOS_ATTR45
, "R200_SE_VTX_AOS_ATTR45" },
223 { R200_SE_VTX_AOS_ADDR4
, "R200_SE_VTX_AOS_ADDR4" },
224 { R200_SE_VTX_AOS_ADDR5
, "R200_SE_VTX_AOS_ADDR5" },
225 { R200_SE_VTX_AOS_ATTR67
, "R200_SE_VTX_AOS_ATTR67" },
226 { R200_SE_VTX_AOS_ADDR6
, "R200_SE_VTX_AOS_ADDR6" },
227 { R200_SE_VTX_AOS_ADDR7
, "R200_SE_VTX_AOS_ADDR7" },
228 { R200_SE_VTX_AOS_ATTR89
, "R200_SE_VTX_AOS_ATTR89" },
229 { R200_SE_VTX_AOS_ADDR8
, "R200_SE_VTX_AOS_ADDR8" },
230 { R200_SE_VTX_AOS_ADDR9
, "R200_SE_VTX_AOS_ADDR9" },
231 { R200_SE_VTX_AOS_ATTR1011
, "R200_SE_VTX_AOS_ATTR1011" },
232 { R200_SE_VTX_AOS_ADDR10
, "R200_SE_VTX_AOS_ADDR10" },
233 { R200_SE_VTX_AOS_ADDR11
, "R200_SE_VTX_AOS_ADDR11" },
234 { R200_SE_VF_MAX_VTX_INDX
, "R200_SE_VF_MAX_VTX_INDX" },
235 { R200_SE_VF_MIN_VTX_INDX
, "R200_SE_VF_MIN_VTX_INDX" },
236 { R200_SE_VTX_STATE_CNTL
, "R200_SE_VTX_STATE_CNTL" },
237 { R200_SE_TCL_VECTOR_INDX_REG
, "R200_SE_TCL_VECTOR_INDX_REG" },
238 { R200_SE_TCL_VECTOR_DATA_REG
, "R200_SE_TCL_VECTOR_DATA_REG" },
239 { R200_SE_TCL_SCALAR_INDX_REG
, "R200_SE_TCL_SCALAR_INDX_REG" },
240 { R200_SE_TCL_SCALAR_DATA_REG
, "R200_SE_TCL_SCALAR_DATA_REG" },
241 { R200_SE_TCL_MATRIX_SEL_0
, "R200_SE_TCL_MATRIX_SEL_0" },
242 { R200_SE_TCL_MATRIX_SEL_1
, "R200_SE_TCL_MATRIX_SEL_1" },
243 { R200_SE_TCL_MATRIX_SEL_2
, "R200_SE_TCL_MATRIX_SEL_2" },
244 { R200_SE_TCL_MATRIX_SEL_3
, "R200_SE_TCL_MATRIX_SEL_3" },
245 { R200_SE_TCL_MATRIX_SEL_4
, "R200_SE_TCL_MATRIX_SEL_4" },
246 { R200_SE_TCL_LIGHT_MODEL_CTL_0
, "R200_SE_TCL_LIGHT_MODEL_CTL_0" },
247 { R200_SE_TCL_LIGHT_MODEL_CTL_1
, "R200_SE_TCL_LIGHT_MODEL_CTL_1" },
248 { R200_SE_TCL_PER_LIGHT_CTL_0
, "R200_SE_TCL_PER_LIGHT_CTL_0" },
249 { R200_SE_TCL_PER_LIGHT_CTL_1
, "R200_SE_TCL_PER_LIGHT_CTL_1" },
250 { R200_SE_TCL_PER_LIGHT_CTL_2
, "R200_SE_TCL_PER_LIGHT_CTL_2" },
251 { R200_SE_TCL_PER_LIGHT_CTL_3
, "R200_SE_TCL_PER_LIGHT_CTL_3" },
252 { R200_SE_TCL_TEX_PROC_CTL_2
, "R200_SE_TCL_TEX_PROC_CTL_2" },
253 { R200_SE_TCL_TEX_PROC_CTL_3
, "R200_SE_TCL_TEX_PROC_CTL_3" },
254 { R200_SE_TCL_TEX_PROC_CTL_0
, "R200_SE_TCL_TEX_PROC_CTL_0" },
255 { R200_SE_TCL_TEX_PROC_CTL_1
, "R200_SE_TCL_TEX_PROC_CTL_1" },
256 { R200_SE_TC_TEX_CYL_WRAP_CTL
, "R200_SE_TC_TEX_CYL_WRAP_CTL" },
257 { R200_SE_TCL_UCP_VERT_BLEND_CTL
, "R200_SE_TCL_UCP_VERT_BLEND_CTL" },
258 { R200_SE_TCL_POINT_SPRITE_CNTL
, "R200_SE_TCL_POINT_SPRITE_CNTL" },
259 { R200_SE_VTX_ST_POS_0_X_4
, "R200_SE_VTX_ST_POS_0_X_4" },
260 { R200_SE_VTX_ST_POS_0_Y_4
, "R200_SE_VTX_ST_POS_0_Y_4" },
261 { R200_SE_VTX_ST_POS_0_Z_4
, "R200_SE_VTX_ST_POS_0_Z_4" },
262 { R200_SE_VTX_ST_POS_0_W_4
, "R200_SE_VTX_ST_POS_0_W_4" },
263 { R200_SE_VTX_ST_NORM_0_X
, "R200_SE_VTX_ST_NORM_0_X" },
264 { R200_SE_VTX_ST_NORM_0_Y
, "R200_SE_VTX_ST_NORM_0_Y" },
265 { R200_SE_VTX_ST_NORM_0_Z
, "R200_SE_VTX_ST_NORM_0_Z" },
266 { R200_SE_VTX_ST_PVMS
, "R200_SE_VTX_ST_PVMS" },
267 { R200_SE_VTX_ST_CLR_0_R
, "R200_SE_VTX_ST_CLR_0_R" },
268 { R200_SE_VTX_ST_CLR_0_G
, "R200_SE_VTX_ST_CLR_0_G" },
269 { R200_SE_VTX_ST_CLR_0_B
, "R200_SE_VTX_ST_CLR_0_B" },
270 { R200_SE_VTX_ST_CLR_0_A
, "R200_SE_VTX_ST_CLR_0_A" },
271 { R200_SE_VTX_ST_CLR_1_R
, "R200_SE_VTX_ST_CLR_1_R" },
272 { R200_SE_VTX_ST_CLR_1_G
, "R200_SE_VTX_ST_CLR_1_G" },
273 { R200_SE_VTX_ST_CLR_1_B
, "R200_SE_VTX_ST_CLR_1_B" },
274 { R200_SE_VTX_ST_CLR_1_A
, "R200_SE_VTX_ST_CLR_1_A" },
275 { R200_SE_VTX_ST_CLR_2_R
, "R200_SE_VTX_ST_CLR_2_R" },
276 { R200_SE_VTX_ST_CLR_2_G
, "R200_SE_VTX_ST_CLR_2_G" },
277 { R200_SE_VTX_ST_CLR_2_B
, "R200_SE_VTX_ST_CLR_2_B" },
278 { R200_SE_VTX_ST_CLR_2_A
, "R200_SE_VTX_ST_CLR_2_A" },
279 { R200_SE_VTX_ST_CLR_3_R
, "R200_SE_VTX_ST_CLR_3_R" },
280 { R200_SE_VTX_ST_CLR_3_G
, "R200_SE_VTX_ST_CLR_3_G" },
281 { R200_SE_VTX_ST_CLR_3_B
, "R200_SE_VTX_ST_CLR_3_B" },
282 { R200_SE_VTX_ST_CLR_3_A
, "R200_SE_VTX_ST_CLR_3_A" },
283 { R200_SE_VTX_ST_CLR_4_R
, "R200_SE_VTX_ST_CLR_4_R" },
284 { R200_SE_VTX_ST_CLR_4_G
, "R200_SE_VTX_ST_CLR_4_G" },
285 { R200_SE_VTX_ST_CLR_4_B
, "R200_SE_VTX_ST_CLR_4_B" },
286 { R200_SE_VTX_ST_CLR_4_A
, "R200_SE_VTX_ST_CLR_4_A" },
287 { R200_SE_VTX_ST_CLR_5_R
, "R200_SE_VTX_ST_CLR_5_R" },
288 { R200_SE_VTX_ST_CLR_5_G
, "R200_SE_VTX_ST_CLR_5_G" },
289 { R200_SE_VTX_ST_CLR_5_B
, "R200_SE_VTX_ST_CLR_5_B" },
290 { R200_SE_VTX_ST_CLR_5_A
, "R200_SE_VTX_ST_CLR_5_A" },
291 { R200_SE_VTX_ST_CLR_6_R
, "R200_SE_VTX_ST_CLR_6_R" },
292 { R200_SE_VTX_ST_CLR_6_G
, "R200_SE_VTX_ST_CLR_6_G" },
293 { R200_SE_VTX_ST_CLR_6_B
, "R200_SE_VTX_ST_CLR_6_B" },
294 { R200_SE_VTX_ST_CLR_6_A
, "R200_SE_VTX_ST_CLR_6_A" },
295 { R200_SE_VTX_ST_CLR_7_R
, "R200_SE_VTX_ST_CLR_7_R" },
296 { R200_SE_VTX_ST_CLR_7_G
, "R200_SE_VTX_ST_CLR_7_G" },
297 { R200_SE_VTX_ST_CLR_7_B
, "R200_SE_VTX_ST_CLR_7_B" },
298 { R200_SE_VTX_ST_CLR_7_A
, "R200_SE_VTX_ST_CLR_7_A" },
299 { R200_SE_VTX_ST_TEX_0_S
, "R200_SE_VTX_ST_TEX_0_S" },
300 { R200_SE_VTX_ST_TEX_0_T
, "R200_SE_VTX_ST_TEX_0_T" },
301 { R200_SE_VTX_ST_TEX_0_R
, "R200_SE_VTX_ST_TEX_0_R" },
302 { R200_SE_VTX_ST_TEX_0_Q
, "R200_SE_VTX_ST_TEX_0_Q" },
303 { R200_SE_VTX_ST_TEX_1_S
, "R200_SE_VTX_ST_TEX_1_S" },
304 { R200_SE_VTX_ST_TEX_1_T
, "R200_SE_VTX_ST_TEX_1_T" },
305 { R200_SE_VTX_ST_TEX_1_R
, "R200_SE_VTX_ST_TEX_1_R" },
306 { R200_SE_VTX_ST_TEX_1_Q
, "R200_SE_VTX_ST_TEX_1_Q" },
307 { R200_SE_VTX_ST_TEX_2_S
, "R200_SE_VTX_ST_TEX_2_S" },
308 { R200_SE_VTX_ST_TEX_2_T
, "R200_SE_VTX_ST_TEX_2_T" },
309 { R200_SE_VTX_ST_TEX_2_R
, "R200_SE_VTX_ST_TEX_2_R" },
310 { R200_SE_VTX_ST_TEX_2_Q
, "R200_SE_VTX_ST_TEX_2_Q" },
311 { R200_SE_VTX_ST_TEX_3_S
, "R200_SE_VTX_ST_TEX_3_S" },
312 { R200_SE_VTX_ST_TEX_3_T
, "R200_SE_VTX_ST_TEX_3_T" },
313 { R200_SE_VTX_ST_TEX_3_R
, "R200_SE_VTX_ST_TEX_3_R" },
314 { R200_SE_VTX_ST_TEX_3_Q
, "R200_SE_VTX_ST_TEX_3_Q" },
315 { R200_SE_VTX_ST_TEX_4_S
, "R200_SE_VTX_ST_TEX_4_S" },
316 { R200_SE_VTX_ST_TEX_4_T
, "R200_SE_VTX_ST_TEX_4_T" },
317 { R200_SE_VTX_ST_TEX_4_R
, "R200_SE_VTX_ST_TEX_4_R" },
318 { R200_SE_VTX_ST_TEX_4_Q
, "R200_SE_VTX_ST_TEX_4_Q" },
319 { R200_SE_VTX_ST_TEX_5_S
, "R200_SE_VTX_ST_TEX_5_S" },
320 { R200_SE_VTX_ST_TEX_5_T
, "R200_SE_VTX_ST_TEX_5_T" },
321 { R200_SE_VTX_ST_TEX_5_R
, "R200_SE_VTX_ST_TEX_5_R" },
322 { R200_SE_VTX_ST_TEX_5_Q
, "R200_SE_VTX_ST_TEX_5_Q" },
323 { R200_SE_VTX_ST_PNT_SPRT_SZ
, "R200_SE_VTX_ST_PNT_SPRT_SZ" },
324 { R200_SE_VTX_ST_DISC_FOG
, "R200_SE_VTX_ST_DISC_FOG" },
325 { R200_SE_VTX_ST_SHININESS_0
, "R200_SE_VTX_ST_SHININESS_0" },
326 { R200_SE_VTX_ST_SHININESS_1
, "R200_SE_VTX_ST_SHININESS_1" },
327 { R200_SE_VTX_ST_BLND_WT_0
, "R200_SE_VTX_ST_BLND_WT_0" },
328 { R200_SE_VTX_ST_BLND_WT_1
, "R200_SE_VTX_ST_BLND_WT_1" },
329 { R200_SE_VTX_ST_BLND_WT_2
, "R200_SE_VTX_ST_BLND_WT_2" },
330 { R200_SE_VTX_ST_BLND_WT_3
, "R200_SE_VTX_ST_BLND_WT_3" },
331 { R200_SE_VTX_ST_POS_1_X
, "R200_SE_VTX_ST_POS_1_X" },
332 { R200_SE_VTX_ST_POS_1_Y
, "R200_SE_VTX_ST_POS_1_Y" },
333 { R200_SE_VTX_ST_POS_1_Z
, "R200_SE_VTX_ST_POS_1_Z" },
334 { R200_SE_VTX_ST_POS_1_W
, "R200_SE_VTX_ST_POS_1_W" },
335 { R200_SE_VTX_ST_NORM_1_X
, "R200_SE_VTX_ST_NORM_1_X" },
336 { R200_SE_VTX_ST_NORM_1_Y
, "R200_SE_VTX_ST_NORM_1_Y" },
337 { R200_SE_VTX_ST_NORM_1_Z
, "R200_SE_VTX_ST_NORM_1_Z" },
338 { R200_SE_VTX_ST_USR_CLR_0_R
, "R200_SE_VTX_ST_USR_CLR_0_R" },
339 { R200_SE_VTX_ST_USR_CLR_0_G
, "R200_SE_VTX_ST_USR_CLR_0_G" },
340 { R200_SE_VTX_ST_USR_CLR_0_B
, "R200_SE_VTX_ST_USR_CLR_0_B" },
341 { R200_SE_VTX_ST_USR_CLR_0_A
, "R200_SE_VTX_ST_USR_CLR_0_A" },
342 { R200_SE_VTX_ST_USR_CLR_1_R
, "R200_SE_VTX_ST_USR_CLR_1_R" },
343 { R200_SE_VTX_ST_USR_CLR_1_G
, "R200_SE_VTX_ST_USR_CLR_1_G" },
344 { R200_SE_VTX_ST_USR_CLR_1_B
, "R200_SE_VTX_ST_USR_CLR_1_B" },
345 { R200_SE_VTX_ST_USR_CLR_1_A
, "R200_SE_VTX_ST_USR_CLR_1_A" },
346 { R200_SE_VTX_ST_CLR_0_PKD
, "R200_SE_VTX_ST_CLR_0_PKD" },
347 { R200_SE_VTX_ST_CLR_1_PKD
, "R200_SE_VTX_ST_CLR_1_PKD" },
348 { R200_SE_VTX_ST_CLR_2_PKD
, "R200_SE_VTX_ST_CLR_2_PKD" },
349 { R200_SE_VTX_ST_CLR_3_PKD
, "R200_SE_VTX_ST_CLR_3_PKD" },
350 { R200_SE_VTX_ST_CLR_4_PKD
, "R200_SE_VTX_ST_CLR_4_PKD" },
351 { R200_SE_VTX_ST_CLR_5_PKD
, "R200_SE_VTX_ST_CLR_5_PKD" },
352 { R200_SE_VTX_ST_CLR_6_PKD
, "R200_SE_VTX_ST_CLR_6_PKD" },
353 { R200_SE_VTX_ST_CLR_7_PKD
, "R200_SE_VTX_ST_CLR_7_PKD" },
354 { R200_SE_VTX_ST_POS_0_X_2
, "R200_SE_VTX_ST_POS_0_X_2" },
355 { R200_SE_VTX_ST_POS_0_Y_2
, "R200_SE_VTX_ST_POS_0_Y_2" },
356 { R200_SE_VTX_ST_PAR_CLR_LD
, "R200_SE_VTX_ST_PAR_CLR_LD" },
357 { R200_SE_VTX_ST_USR_CLR_PKD
, "R200_SE_VTX_ST_USR_CLR_PKD" },
358 { R200_SE_VTX_ST_POS_0_X_3
, "R200_SE_VTX_ST_POS_0_X_3" },
359 { R200_SE_VTX_ST_POS_0_Y_3
, "R200_SE_VTX_ST_POS_0_Y_3" },
360 { R200_SE_VTX_ST_POS_0_Z_3
, "R200_SE_VTX_ST_POS_0_Z_3" },
361 { R200_SE_VTX_ST_END_OF_PKT
, "R200_SE_VTX_ST_END_OF_PKT" },
362 { R200_RE_POINTSIZE
, "R200_RE_POINTSIZE" },
363 { R200_RE_TOP_LEFT
, "R200_RE_TOP_LEFT" },
364 { R200_RE_AUX_SCISSOR_CNTL
, "R200_RE_AUX_SCISSOR_CNTL" },
365 { R200_PP_TXFILTER_0
, "R200_PP_TXFILTER_0" },
366 { R200_PP_TXFORMAT_0
, "R200_PP_TXFORMAT_0" },
367 { R200_PP_TXSIZE_0
, "R200_PP_TXSIZE_0" },
368 { R200_PP_TXFORMAT_X_0
, "R200_PP_TXFORMAT_X_0" },
369 { R200_PP_TXPITCH_0
, "R200_PP_TXPITCH_0" },
370 { R200_PP_BORDER_COLOR_0
, "R200_PP_BORDER_COLOR_0" },
371 { R200_PP_CUBIC_FACES_0
, "R200_PP_CUBIC_FACES_0" },
372 { R200_PP_TXMULTI_CTL_0
, "R200_PP_TXMULTI_CTL_0" },
373 { R200_PP_TXFILTER_1
, "R200_PP_TXFILTER_1" },
374 { R200_PP_TXFORMAT_1
, "R200_PP_TXFORMAT_1" },
375 { R200_PP_TXSIZE_1
, "R200_PP_TXSIZE_1" },
376 { R200_PP_TXFORMAT_X_1
, "R200_PP_TXFORMAT_X_1" },
377 { R200_PP_TXPITCH_1
, "R200_PP_TXPITCH_1" },
378 { R200_PP_BORDER_COLOR_1
, "R200_PP_BORDER_COLOR_1" },
379 { R200_PP_CUBIC_FACES_1
, "R200_PP_CUBIC_FACES_1" },
380 { R200_PP_TXMULTI_CTL_1
, "R200_PP_TXMULTI_CTL_1" },
381 { R200_PP_TXFILTER_2
, "R200_PP_TXFILTER_2" },
382 { R200_PP_TXFORMAT_2
, "R200_PP_TXFORMAT_2" },
383 { R200_PP_TXSIZE_2
, "R200_PP_TXSIZE_2" },
384 { R200_PP_TXFORMAT_X_2
, "R200_PP_TXFORMAT_X_2" },
385 { R200_PP_TXPITCH_2
, "R200_PP_TXPITCH_2" },
386 { R200_PP_BORDER_COLOR_2
, "R200_PP_BORDER_COLOR_2" },
387 { R200_PP_CUBIC_FACES_2
, "R200_PP_CUBIC_FACES_2" },
388 { R200_PP_TXMULTI_CTL_2
, "R200_PP_TXMULTI_CTL_2" },
389 { R200_PP_TXFILTER_3
, "R200_PP_TXFILTER_3" },
390 { R200_PP_TXFORMAT_3
, "R200_PP_TXFORMAT_3" },
391 { R200_PP_TXSIZE_3
, "R200_PP_TXSIZE_3" },
392 { R200_PP_TXFORMAT_X_3
, "R200_PP_TXFORMAT_X_3" },
393 { R200_PP_TXPITCH_3
, "R200_PP_TXPITCH_3" },
394 { R200_PP_BORDER_COLOR_3
, "R200_PP_BORDER_COLOR_3" },
395 { R200_PP_CUBIC_FACES_3
, "R200_PP_CUBIC_FACES_3" },
396 { R200_PP_TXMULTI_CTL_3
, "R200_PP_TXMULTI_CTL_3" },
397 { R200_PP_TXFILTER_4
, "R200_PP_TXFILTER_4" },
398 { R200_PP_TXFORMAT_4
, "R200_PP_TXFORMAT_4" },
399 { R200_PP_TXSIZE_4
, "R200_PP_TXSIZE_4" },
400 { R200_PP_TXFORMAT_X_4
, "R200_PP_TXFORMAT_X_4" },
401 { R200_PP_TXPITCH_4
, "R200_PP_TXPITCH_4" },
402 { R200_PP_BORDER_COLOR_4
, "R200_PP_BORDER_COLOR_4" },
403 { R200_PP_CUBIC_FACES_4
, "R200_PP_CUBIC_FACES_4" },
404 { R200_PP_TXMULTI_CTL_4
, "R200_PP_TXMULTI_CTL_4" },
405 { R200_PP_TXFILTER_5
, "R200_PP_TXFILTER_5" },
406 { R200_PP_TXFORMAT_5
, "R200_PP_TXFORMAT_5" },
407 { R200_PP_TXSIZE_5
, "R200_PP_TXSIZE_5" },
408 { R200_PP_TXFORMAT_X_5
, "R200_PP_TXFORMAT_X_5" },
409 { R200_PP_TXPITCH_5
, "R200_PP_TXPITCH_5" },
410 { R200_PP_BORDER_COLOR_5
, "R200_PP_BORDER_COLOR_5" },
411 { R200_PP_CUBIC_FACES_5
, "R200_PP_CUBIC_FACES_5" },
412 { R200_PP_TXMULTI_CTL_5
, "R200_PP_TXMULTI_CTL_5" },
413 { R200_PP_TXOFFSET_0
, "R200_PP_TXOFFSET_0" },
414 { R200_PP_CUBIC_OFFSET_F1_0
, "R200_PP_CUBIC_OFFSET_F1_0" },
415 { R200_PP_CUBIC_OFFSET_F2_0
, "R200_PP_CUBIC_OFFSET_F2_0" },
416 { R200_PP_CUBIC_OFFSET_F3_0
, "R200_PP_CUBIC_OFFSET_F3_0" },
417 { R200_PP_CUBIC_OFFSET_F4_0
, "R200_PP_CUBIC_OFFSET_F4_0" },
418 { R200_PP_CUBIC_OFFSET_F5_0
, "R200_PP_CUBIC_OFFSET_F5_0" },
419 { R200_PP_TXOFFSET_1
, "R200_PP_TXOFFSET_1" },
420 { R200_PP_CUBIC_OFFSET_F1_1
, "R200_PP_CUBIC_OFFSET_F1_1" },
421 { R200_PP_CUBIC_OFFSET_F2_1
, "R200_PP_CUBIC_OFFSET_F2_1" },
422 { R200_PP_CUBIC_OFFSET_F3_1
, "R200_PP_CUBIC_OFFSET_F3_1" },
423 { R200_PP_CUBIC_OFFSET_F4_1
, "R200_PP_CUBIC_OFFSET_F4_1" },
424 { R200_PP_CUBIC_OFFSET_F5_1
, "R200_PP_CUBIC_OFFSET_F5_1" },
425 { R200_PP_TXOFFSET_2
, "R200_PP_TXOFFSET_2" },
426 { R200_PP_CUBIC_OFFSET_F1_2
, "R200_PP_CUBIC_OFFSET_F1_2" },
427 { R200_PP_CUBIC_OFFSET_F2_2
, "R200_PP_CUBIC_OFFSET_F2_2" },
428 { R200_PP_CUBIC_OFFSET_F3_2
, "R200_PP_CUBIC_OFFSET_F3_2" },
429 { R200_PP_CUBIC_OFFSET_F4_2
, "R200_PP_CUBIC_OFFSET_F4_2" },
430 { R200_PP_CUBIC_OFFSET_F5_2
, "R200_PP_CUBIC_OFFSET_F5_2" },
431 { R200_PP_TXOFFSET_3
, "R200_PP_TXOFFSET_3" },
432 { R200_PP_CUBIC_OFFSET_F1_3
, "R200_PP_CUBIC_OFFSET_F1_3" },
433 { R200_PP_CUBIC_OFFSET_F2_3
, "R200_PP_CUBIC_OFFSET_F2_3" },
434 { R200_PP_CUBIC_OFFSET_F3_3
, "R200_PP_CUBIC_OFFSET_F3_3" },
435 { R200_PP_CUBIC_OFFSET_F4_3
, "R200_PP_CUBIC_OFFSET_F4_3" },
436 { R200_PP_CUBIC_OFFSET_F5_3
, "R200_PP_CUBIC_OFFSET_F5_3" },
437 { R200_PP_TXOFFSET_4
, "R200_PP_TXOFFSET_4" },
438 { R200_PP_CUBIC_OFFSET_F1_4
, "R200_PP_CUBIC_OFFSET_F1_4" },
439 { R200_PP_CUBIC_OFFSET_F2_4
, "R200_PP_CUBIC_OFFSET_F2_4" },
440 { R200_PP_CUBIC_OFFSET_F3_4
, "R200_PP_CUBIC_OFFSET_F3_4" },
441 { R200_PP_CUBIC_OFFSET_F4_4
, "R200_PP_CUBIC_OFFSET_F4_4" },
442 { R200_PP_CUBIC_OFFSET_F5_4
, "R200_PP_CUBIC_OFFSET_F5_4" },
443 { R200_PP_TXOFFSET_5
, "R200_PP_TXOFFSET_5" },
444 { R200_PP_CUBIC_OFFSET_F1_5
, "R200_PP_CUBIC_OFFSET_F1_5" },
445 { R200_PP_CUBIC_OFFSET_F2_5
, "R200_PP_CUBIC_OFFSET_F2_5" },
446 { R200_PP_CUBIC_OFFSET_F3_5
, "R200_PP_CUBIC_OFFSET_F3_5" },
447 { R200_PP_CUBIC_OFFSET_F4_5
, "R200_PP_CUBIC_OFFSET_F4_5" },
448 { R200_PP_CUBIC_OFFSET_F5_5
, "R200_PP_CUBIC_OFFSET_F5_5" },
449 { R200_PP_TAM_DEBUG3
, "R200_PP_TAM_DEBUG3" },
450 { R200_PP_TFACTOR_0
, "R200_PP_TFACTOR_0" },
451 { R200_PP_TFACTOR_1
, "R200_PP_TFACTOR_1" },
452 { R200_PP_TFACTOR_2
, "R200_PP_TFACTOR_2" },
453 { R200_PP_TFACTOR_3
, "R200_PP_TFACTOR_3" },
454 { R200_PP_TFACTOR_4
, "R200_PP_TFACTOR_4" },
455 { R200_PP_TFACTOR_5
, "R200_PP_TFACTOR_5" },
456 { R200_PP_TFACTOR_6
, "R200_PP_TFACTOR_6" },
457 { R200_PP_TFACTOR_7
, "R200_PP_TFACTOR_7" },
458 { R200_PP_TXCBLEND_0
, "R200_PP_TXCBLEND_0" },
459 { R200_PP_TXCBLEND2_0
, "R200_PP_TXCBLEND2_0" },
460 { R200_PP_TXABLEND_0
, "R200_PP_TXABLEND_0" },
461 { R200_PP_TXABLEND2_0
, "R200_PP_TXABLEND2_0" },
462 { R200_PP_TXCBLEND_1
, "R200_PP_TXCBLEND_1" },
463 { R200_PP_TXCBLEND2_1
, "R200_PP_TXCBLEND2_1" },
464 { R200_PP_TXABLEND_1
, "R200_PP_TXABLEND_1" },
465 { R200_PP_TXABLEND2_1
, "R200_PP_TXABLEND2_1" },
466 { R200_PP_TXCBLEND_2
, "R200_PP_TXCBLEND_2" },
467 { R200_PP_TXCBLEND2_2
, "R200_PP_TXCBLEND2_2" },
468 { R200_PP_TXABLEND_2
, "R200_PP_TXABLEND_2" },
469 { R200_PP_TXABLEND2_2
, "R200_PP_TXABLEND2_2" },
470 { R200_PP_TXCBLEND_3
, "R200_PP_TXCBLEND_3" },
471 { R200_PP_TXCBLEND2_3
, "R200_PP_TXCBLEND2_3" },
472 { R200_PP_TXABLEND_3
, "R200_PP_TXABLEND_3" },
473 { R200_PP_TXABLEND2_3
, "R200_PP_TXABLEND2_3" },
474 { R200_PP_TXCBLEND_4
, "R200_PP_TXCBLEND_4" },
475 { R200_PP_TXCBLEND2_4
, "R200_PP_TXCBLEND2_4" },
476 { R200_PP_TXABLEND_4
, "R200_PP_TXABLEND_4" },
477 { R200_PP_TXABLEND2_4
, "R200_PP_TXABLEND2_4" },
478 { R200_PP_TXCBLEND_5
, "R200_PP_TXCBLEND_5" },
479 { R200_PP_TXCBLEND2_5
, "R200_PP_TXCBLEND2_5" },
480 { R200_PP_TXABLEND_5
, "R200_PP_TXABLEND_5" },
481 { R200_PP_TXABLEND2_5
, "R200_PP_TXABLEND2_5" },
482 { R200_PP_TXCBLEND_6
, "R200_PP_TXCBLEND_6" },
483 { R200_PP_TXCBLEND2_6
, "R200_PP_TXCBLEND2_6" },
484 { R200_PP_TXABLEND_6
, "R200_PP_TXABLEND_6" },
485 { R200_PP_TXABLEND2_6
, "R200_PP_TXABLEND2_6" },
486 { R200_PP_TXCBLEND_7
, "R200_PP_TXCBLEND_7" },
487 { R200_PP_TXCBLEND2_7
, "R200_PP_TXCBLEND2_7" },
488 { R200_PP_TXABLEND_7
, "R200_PP_TXABLEND_7" },
489 { R200_PP_TXABLEND2_7
, "R200_PP_TXABLEND2_7" },
490 { R200_RB3D_BLENDCOLOR
, "R200_RB3D_BLENDCOLOR" },
491 { R200_RB3D_ABLENDCNTL
, "R200_RB3D_ABLENDCNTL" },
492 { R200_RB3D_CBLENDCNTL
, "R200_RB3D_CBLENDCNTL" },
493 { R200_SE_TCL_OUTPUT_VTX_COMP_SEL
, "R200_SE_TCL_OUTPUT_VTX_COMP_SEL" },
494 { R200_PP_CNTL_X
, "R200_PP_CNTL_X" },
495 { R200_SE_VAP_CNTL_STATUS
, "R200_SE_VAP_CNTL_STATUS" },
496 { R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0
, "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0" },
497 { R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_1
, "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_1" },
498 { R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_2
, "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_2" },
499 { R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_3
, "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_3" },
500 { R200_PP_TRI_PERF
, "R200_PP_TRI_PERF" },
501 { R200_PP_PERF_CNTL
, "R200_PP_PERF_CNTL" },
502 { R200_PP_TXCBLEND_8
, "R200_PP_TXCBLEND_8" },
503 { R200_PP_TXCBLEND2_8
, "R200_PP_TXCBLEND2_8" },
504 { R200_PP_TXABLEND_8
, "R200_PP_TXABLEND_8" },
505 { R200_PP_TXABLEND2_8
, "R200_PP_TXABLEND2_8" },
506 { R200_PP_TXCBLEND_9
, "R200_PP_TXCBLEND_9" },
507 { R200_PP_TXCBLEND2_9
, "R200_PP_TXCBLEND2_9" },
508 { R200_PP_TXABLEND_9
, "R200_PP_TXABLEND_9" },
509 { R200_PP_TXABLEND2_9
, "R200_PP_TXABLEND2_9" },
510 { R200_PP_TXCBLEND_10
, "R200_PP_TXCBLEND_10" },
511 { R200_PP_TXCBLEND2_10
, "R200_PP_TXCBLEND2_10" },
512 { R200_PP_TXABLEND_10
, "R200_PP_TXABLEND_10" },
513 { R200_PP_TXABLEND2_10
, "R200_PP_TXABLEND2_10" },
514 { R200_PP_TXCBLEND_11
, "R200_PP_TXCBLEND_11" },
515 { R200_PP_TXCBLEND2_11
, "R200_PP_TXCBLEND2_11" },
516 { R200_PP_TXABLEND_11
, "R200_PP_TXABLEND_11" },
517 { R200_PP_TXABLEND2_11
, "R200_PP_TXABLEND2_11" },
518 { R200_PP_TXCBLEND_12
, "R200_PP_TXCBLEND_12" },
519 { R200_PP_TXCBLEND2_12
, "R200_PP_TXCBLEND2_12" },
520 { R200_PP_TXABLEND_12
, "R200_PP_TXABLEND_12" },
521 { R200_PP_TXABLEND2_12
, "R200_PP_TXABLEND2_12" },
522 { R200_PP_TXCBLEND_13
, "R200_PP_TXCBLEND_13" },
523 { R200_PP_TXCBLEND2_13
, "R200_PP_TXCBLEND2_13" },
524 { R200_PP_TXABLEND_13
, "R200_PP_TXABLEND_13" },
525 { R200_PP_TXABLEND2_13
, "R200_PP_TXABLEND2_13" },
526 { R200_PP_TXCBLEND_14
, "R200_PP_TXCBLEND_14" },
527 { R200_PP_TXCBLEND2_14
, "R200_PP_TXCBLEND2_14" },
528 { R200_PP_TXABLEND_14
, "R200_PP_TXABLEND_14" },
529 { R200_PP_TXABLEND2_14
, "R200_PP_TXABLEND2_14" },
530 { R200_PP_TXCBLEND_15
, "R200_PP_TXCBLEND_15" },
531 { R200_PP_TXCBLEND2_15
, "R200_PP_TXCBLEND2_15" },
532 { R200_PP_TXABLEND_15
, "R200_PP_TXABLEND_15" },
533 { R200_PP_TXABLEND2_15
, "R200_PP_TXABLEND2_15" },
534 { R200_VAP_PVS_CNTL_1
, "R200_VAP_PVS_CNTL_1" },
535 { R200_VAP_PVS_CNTL_2
, "R200_VAP_PVS_CNTL_2" },
538 static struct reg_names scalar_names
[] = {
539 { R200_SS_LIGHT_DCD_ADDR
, "R200_SS_LIGHT_DCD_ADDR" },
540 { R200_SS_LIGHT_DCM_ADDR
, "R200_SS_LIGHT_DCM_ADDR" },
541 { R200_SS_LIGHT_SPOT_EXPONENT_ADDR
, "R200_SS_LIGHT_SPOT_EXPONENT_ADDR" },
542 { R200_SS_LIGHT_SPOT_CUTOFF_ADDR
, "R200_SS_LIGHT_SPOT_CUTOFF_ADDR" },
543 { R200_SS_LIGHT_SPECULAR_THRESH_ADDR
, "R200_SS_LIGHT_SPECULAR_THRESH_ADDR" },
544 { R200_SS_LIGHT_RANGE_CUTOFF_SQRD
, "R200_SS_LIGHT_RANGE_CUTOFF_SQRD" },
545 { R200_SS_LIGHT_RANGE_ATT_CONST
, "R200_SS_LIGHT_RANGE_ATT_CONST" },
546 { R200_SS_VERT_GUARD_CLIP_ADJ_ADDR
, "R200_SS_VERT_GUARD_CLIP_ADJ_ADDR" },
547 { R200_SS_VERT_GUARD_DISCARD_ADJ_ADDR
, "R200_SS_VERT_GUARD_DISCARD_ADJ_ADDR" },
548 { R200_SS_HORZ_GUARD_CLIP_ADJ_ADDR
, "R200_SS_HORZ_GUARD_CLIP_ADJ_ADDR" },
549 { R200_SS_HORZ_GUARD_DISCARD_ADJ_ADDR
, "R200_SS_HORZ_GUARD_DISCARD_ADJ_ADDR" },
550 { R200_SS_MAT_0_SHININESS
, "R200_SS_MAT_0_SHININESS" },
551 { R200_SS_MAT_1_SHININESS
, "R200_SS_MAT_1_SHININESS" },
555 /* Puff these out to make them look like normal (dword) registers.
557 static struct reg_names vector_names
[] = {
559 { R200_VS_LIGHT_AMBIENT_ADDR
, "R200_VS_LIGHT_AMBIENT_ADDR" },
560 { R200_VS_LIGHT_DIFFUSE_ADDR
, "R200_VS_LIGHT_DIFFUSE_ADDR" },
561 { R200_VS_LIGHT_SPECULAR_ADDR
, "R200_VS_LIGHT_SPECULAR_ADDR" },
562 { R200_VS_LIGHT_DIRPOS_ADDR
, "R200_VS_LIGHT_DIRPOS_ADDR" },
563 { R200_VS_LIGHT_HWVSPOT_ADDR
, "R200_VS_LIGHT_HWVSPOT_ADDR" },
564 { R200_VS_LIGHT_ATTENUATION_ADDR
, "R200_VS_LIGHT_ATTENUATION_ADDR" },
565 { R200_VS_SPOT_DUAL_CONE
, "R200_VS_SPOT_DUAL_CONE" },
566 { R200_VS_GLOBAL_AMBIENT_ADDR
, "R200_VS_GLOBAL_AMBIENT_ADDR" },
567 { R200_VS_FOG_PARAM_ADDR
, "R200_VS_FOG_PARAM_ADDR" },
568 { R200_VS_EYE_VECTOR_ADDR
, "R200_VS_EYE_VECTOR_ADDR" },
569 { R200_VS_UCP_ADDR
, "R200_VS_UCP_ADDR" },
570 { R200_VS_PNT_SPRITE_VPORT_SCALE
, "R200_VS_PNT_SPRITE_VPORT_SCALE" },
571 { R200_VS_MATRIX_0_MV
, "R200_VS_MATRIX_0_MV" },
572 { R200_VS_MATRIX_1_INV_MV
, "R200_VS_MATRIX_1_INV_MV" },
573 { R200_VS_MATRIX_2_MVP
, "R200_VS_MATRIX_2_MVP" },
574 { R200_VS_MATRIX_3_TEX0
, "R200_VS_MATRIX_3_TEX0" },
575 { R200_VS_MATRIX_4_TEX1
, "R200_VS_MATRIX_4_TEX1" },
576 { R200_VS_MATRIX_5_TEX2
, "R200_VS_MATRIX_5_TEX2" },
577 { R200_VS_MATRIX_6_TEX3
, "R200_VS_MATRIX_6_TEX3" },
578 { R200_VS_MATRIX_7_TEX4
, "R200_VS_MATRIX_7_TEX4" },
579 { R200_VS_MATRIX_8_TEX5
, "R200_VS_MATRIX_8_TEX5" },
580 { R200_VS_MAT_0_EMISS
, "R200_VS_MAT_0_EMISS" },
581 { R200_VS_MAT_0_AMB
, "R200_VS_MAT_0_AMB" },
582 { R200_VS_MAT_0_DIF
, "R200_VS_MAT_0_DIF" },
583 { R200_VS_MAT_0_SPEC
, "R200_VS_MAT_0_SPEC" },
584 { R200_VS_MAT_1_EMISS
, "R200_VS_MAT_1_EMISS" },
585 { R200_VS_MAT_1_AMB
, "R200_VS_MAT_1_AMB" },
586 { R200_VS_MAT_1_DIF
, "R200_VS_MAT_1_DIF" },
587 { R200_VS_MAT_1_SPEC
, "R200_VS_MAT_1_SPEC" },
588 { R200_VS_EYE2CLIP_MTX
, "R200_VS_EYE2CLIP_MTX" },
589 { R200_VS_PNT_SPRITE_ATT_CONST
, "R200_VS_PNT_SPRITE_ATT_CONST" },
590 { R200_VS_PNT_SPRITE_EYE_IN_MODEL
, "R200_VS_PNT_SPRITE_EYE_IN_MODEL" },
591 { R200_VS_PNT_SPRITE_CLAMP
, "R200_VS_PNT_SPRITE_CLAMP" },
592 { R200_VS_MAX
, "R200_VS_MAX" },
602 struct reg_names
*closest
;
612 static struct reg regs
[ARRAY_SIZE(reg_names
)+1];
613 static struct reg scalars
[512+1];
614 static struct reg vectors
[512*4+1];
616 static int total
, total_changed
, bufs
;
618 static void init_regs( void )
620 struct reg_names
*tmp
;
623 for (i
= 0 ; i
< ARRAY_SIZE(reg_names
) ; i
++) {
624 regs
[i
].idx
= reg_names
[i
].idx
;
625 regs
[i
].closest
= ®_names
[i
];
629 for (i
= 0, tmp
= scalar_names
; i
< ARRAY_SIZE(scalars
) ; i
++) {
630 if (tmp
[1].idx
== i
) tmp
++;
632 scalars
[i
].closest
= tmp
;
633 scalars
[i
].flags
= ISFLOAT
;
636 for (i
= 0, tmp
= vector_names
; i
< ARRAY_SIZE(vectors
) ; i
++) {
637 if (tmp
[1].idx
*4 == i
) tmp
++;
639 vectors
[i
].closest
= tmp
;
640 vectors
[i
].flags
= ISFLOAT
|ISVEC
;
643 regs
[ARRAY_SIZE(regs
)-1].idx
= -1;
644 scalars
[ARRAY_SIZE(scalars
)-1].idx
= -1;
645 vectors
[ARRAY_SIZE(vectors
)-1].idx
= -1;
648 static int find_or_add_value( struct reg
*reg
, int val
)
652 for ( j
= 0 ; j
< reg
->nvalues
; j
++)
653 if ( val
== reg
->values
[j
].i
)
656 if (j
== reg
->nalloc
) {
659 reg
->values
= realloc( reg
->values
, reg
->nalloc
* sizeof(union fi
) );
662 reg
->values
[reg
->nvalues
++].i
= val
;
666 static struct reg
*lookup_reg( struct reg
*tab
, int reg
)
670 for (i
= 0 ; tab
[i
].idx
!= -1 ; i
++) {
671 if (tab
[i
].idx
== reg
)
675 fprintf(stderr
, "*** unknown reg 0x%x\n", reg
);
680 static const char *get_reg_name( struct reg
*reg
)
684 if (reg
->idx
== reg
->closest
->idx
)
685 return reg
->closest
->name
;
688 if (reg
->flags
& ISVEC
) {
689 if (reg
->idx
/4 != reg
->closest
->idx
)
690 sprintf(tmp
, "%s+%d[%d]",
692 (reg
->idx
/4) - reg
->closest
->idx
,
695 sprintf(tmp
, "%s[%d]", reg
->closest
->name
, reg
->idx
%4);
698 if (reg
->idx
!= reg
->closest
->idx
)
699 sprintf(tmp
, "%s+%d", reg
->closest
->name
, reg
->idx
- reg
->closest
->idx
);
701 sprintf(tmp
, "%s", reg
->closest
->name
);
707 static int print_int_reg_assignment( struct reg
*reg
, int data
)
709 int changed
= (reg
->current
.i
!= data
);
710 int ever_seen
= find_or_add_value( reg
, data
);
712 if (VERBOSE
|| (NORMAL
&& (changed
|| !ever_seen
)))
713 fprintf(stderr
, " %s <-- 0x%x", get_reg_name(reg
), data
);
717 fprintf(stderr
, " *** BRAND NEW VALUE");
719 fprintf(stderr
, " *** CHANGED");
722 reg
->current
.i
= data
;
724 if (VERBOSE
|| (NORMAL
&& (changed
|| !ever_seen
)))
725 fprintf(stderr
, "\n");
731 static int print_float_reg_assignment( struct reg
*reg
, float data
)
733 int changed
= (reg
->current
.f
!= data
);
734 int newmin
= (data
< reg
->vmin
);
735 int newmax
= (data
> reg
->vmax
);
737 if (VERBOSE
|| (NORMAL
&& (newmin
|| newmax
|| changed
)))
738 fprintf(stderr
, " %s <-- %.3f", get_reg_name(reg
), data
);
742 fprintf(stderr
, " *** NEW MIN (prev %.3f)", reg
->vmin
);
746 fprintf(stderr
, " *** NEW MAX (prev %.3f)", reg
->vmax
);
750 fprintf(stderr
, " *** CHANGED");
754 reg
->current
.f
= data
;
756 if (VERBOSE
|| (NORMAL
&& (newmin
|| newmax
|| changed
)))
757 fprintf(stderr
, "\n");
762 static int print_reg_assignment( struct reg
*reg
, int data
)
764 float_ui32_type datau
;
766 reg
->flags
|= TOUCHED
;
767 if (reg
->flags
& ISFLOAT
)
768 return print_float_reg_assignment( reg
, datau
.f
);
770 return print_int_reg_assignment( reg
, data
);
773 static void print_reg( struct reg
*reg
)
775 if (reg
->flags
& TOUCHED
) {
776 if (reg
->flags
& ISFLOAT
) {
777 fprintf(stderr
, " %s == %f\n", get_reg_name(reg
), reg
->current
.f
);
779 fprintf(stderr
, " %s == 0x%x\n", get_reg_name(reg
), reg
->current
.i
);
785 static void dump_state( void )
789 for (i
= 0 ; i
< ARRAY_SIZE(regs
) ; i
++)
790 print_reg( ®s
[i
] );
792 for (i
= 0 ; i
< ARRAY_SIZE(scalars
) ; i
++)
793 print_reg( &scalars
[i
] );
795 for (i
= 0 ; i
< ARRAY_SIZE(vectors
) ; i
++)
796 print_reg( &vectors
[i
] );
801 static int radeon_emit_packets(
802 drm_radeon_cmd_header_t header
,
803 drm_radeon_cmd_buffer_t
*cmdbuf
)
805 int id
= (int)header
.packet
.packet_id
;
806 int sz
= packet
[id
].len
;
807 int *data
= (int *)cmdbuf
->buf
;
810 if (sz
* sizeof(int) > cmdbuf
->bufsz
) {
811 fprintf(stderr
, "Packet overflows cmdbuf\n");
815 if (!packet
[id
].name
) {
816 fprintf(stderr
, "*** Unknown packet 0 nr %d\n", id
);
822 fprintf(stderr
, "Packet 0 reg %s nr %d\n", packet
[id
].name
, sz
);
824 for ( i
= 0 ; i
< sz
; i
++) {
825 struct reg
*reg
= lookup_reg( regs
, packet
[id
].start
+ i
*4 );
826 if (print_reg_assignment( reg
, data
[i
] ))
831 cmdbuf
->buf
+= sz
* sizeof(int);
832 cmdbuf
->bufsz
-= sz
* sizeof(int);
837 static int radeon_emit_scalars(
838 drm_radeon_cmd_header_t header
,
839 drm_radeon_cmd_buffer_t
*cmdbuf
)
841 int sz
= header
.scalars
.count
;
842 int *data
= (int *)cmdbuf
->buf
;
843 int start
= header
.scalars
.offset
;
844 int stride
= header
.scalars
.stride
;
848 fprintf(stderr
, "emit scalars, start %d stride %d nr %d (end %d)\n",
849 start
, stride
, sz
, start
+ stride
* sz
);
852 for (i
= 0 ; i
< sz
; i
++, start
+= stride
) {
853 struct reg
*reg
= lookup_reg( scalars
, start
);
854 if (print_reg_assignment( reg
, data
[i
] ))
859 cmdbuf
->buf
+= sz
* sizeof(int);
860 cmdbuf
->bufsz
-= sz
* sizeof(int);
865 static int radeon_emit_scalars2(
866 drm_radeon_cmd_header_t header
,
867 drm_radeon_cmd_buffer_t
*cmdbuf
)
869 int sz
= header
.scalars
.count
;
870 int *data
= (int *)cmdbuf
->buf
;
871 int start
= header
.scalars
.offset
+ 0x100;
872 int stride
= header
.scalars
.stride
;
876 fprintf(stderr
, "emit scalars2, start %d stride %d nr %d (end %d)\n",
877 start
, stride
, sz
, start
+ stride
* sz
);
879 if (start
+ stride
* sz
> 258) {
880 fprintf(stderr
, "emit scalars OVERFLOW %d/%d/%d\n", start
, stride
, sz
);
884 for (i
= 0 ; i
< sz
; i
++, start
+= stride
) {
885 struct reg
*reg
= lookup_reg( scalars
, start
);
886 if (print_reg_assignment( reg
, data
[i
] ))
891 cmdbuf
->buf
+= sz
* sizeof(int);
892 cmdbuf
->bufsz
-= sz
* sizeof(int);
896 /* Check: inf/nan/extreme-size?
897 * Check: table start, end, nr, etc.
899 static int radeon_emit_vectors(
900 drm_radeon_cmd_header_t header
,
901 drm_radeon_cmd_buffer_t
*cmdbuf
)
903 int sz
= header
.vectors
.count
;
904 int *data
= (int *)cmdbuf
->buf
;
905 int start
= header
.vectors
.offset
;
906 int stride
= header
.vectors
.stride
;
910 fprintf(stderr
, "emit vectors, start %d stride %d nr %d (end %d) (0x%x)\n",
911 start
, stride
, sz
, start
+ stride
* sz
, header
.i
);
913 /* if (start + stride * (sz/4) > 128) { */
914 /* fprintf(stderr, "emit vectors OVERFLOW %d/%d/%d\n", start, stride, sz); */
918 for (i
= 0 ; i
< sz
; start
+= stride
) {
920 for (j
= 0 ; j
< 4 ; i
++,j
++) {
921 struct reg
*reg
= lookup_reg( vectors
, start
*4+j
);
922 if (print_reg_assignment( reg
, data
[i
] ))
931 cmdbuf
->buf
+= sz
* sizeof(int);
932 cmdbuf
->bufsz
-= sz
* sizeof(int);
936 static int radeon_emit_veclinear(
937 drm_radeon_cmd_header_t header
,
938 drm_radeon_cmd_buffer_t
*cmdbuf
)
940 int sz
= header
.veclinear
.count
* 4;
941 int *data
= (int *)cmdbuf
->buf
;
942 float *fdata
=(float *)cmdbuf
->buf
;
943 int start
= header
.veclinear
.addr_lo
| (header
.veclinear
.addr_hi
<< 8);
947 fprintf(stderr
, "emit vectors linear, start %d nr %d (end %d) (0x%x)\n",
948 start
, sz
>> 2, start
+ (sz
>> 2), header
.i
);
952 for (i
= 0 ; i
< sz
; i
+= 4) {
953 fprintf(stderr
, "R200_VS_PARAM %d 0 %f\n", (i
>> 2) + start
, fdata
[i
]);
954 fprintf(stderr
, "R200_VS_PARAM %d 1 %f\n", (i
>> 2) + start
, fdata
[i
+1]);
955 fprintf(stderr
, "R200_VS_PARAM %d 2 %f\n", (i
>> 2) + start
, fdata
[i
+2]);
956 fprintf(stderr
, "R200_VS_PARAM %d 3 %f\n", (i
>> 2) + start
, fdata
[i
+3]);
959 else if ((start
>= 0x100) && (start
< 0x160)) {
960 for (i
= 0 ; i
< sz
; i
+= 4) {
961 fprintf(stderr
, "R200_VS_PARAM %d 0 %f\n", (i
>> 2) + start
- 0x100 + 0x60, fdata
[i
]);
962 fprintf(stderr
, "R200_VS_PARAM %d 1 %f\n", (i
>> 2) + start
- 0x100 + 0x60, fdata
[i
+1]);
963 fprintf(stderr
, "R200_VS_PARAM %d 2 %f\n", (i
>> 2) + start
- 0x100 + 0x60, fdata
[i
+2]);
964 fprintf(stderr
, "R200_VS_PARAM %d 3 %f\n", (i
>> 2) + start
- 0x100 + 0x60, fdata
[i
+3]);
967 else if ((start
>= 0x80) && (start
< 0xc0)) {
968 for (i
= 0 ; i
< sz
; i
+= 4) {
969 fprintf(stderr
, "R200_VS_PROG %d OPDST %08x\n", (i
>> 2) + start
- 0x80, data
[i
]);
970 fprintf(stderr
, "R200_VS_PROG %d SRC1 %08x\n", (i
>> 2) + start
- 0x80, data
[i
+1]);
971 fprintf(stderr
, "R200_VS_PROG %d SRC2 %08x\n", (i
>> 2) + start
- 0x80, data
[i
+2]);
972 fprintf(stderr
, "R200_VS_PROG %d SRC3 %08x\n", (i
>> 2) + start
- 0x80, data
[i
+3]);
975 else if ((start
>= 0x180) && (start
< 0x1c0)) {
976 for (i
= 0 ; i
< sz
; i
+= 4) {
977 fprintf(stderr
, "R200_VS_PROG %d OPDST %08x\n", (i
>> 2) + start
- 0x180 + 0x40, data
[i
]);
978 fprintf(stderr
, "R200_VS_PROG %d SRC1 %08x\n", (i
>> 2) + start
- 0x180 + 0x40, data
[i
+1]);
979 fprintf(stderr
, "R200_VS_PROG %d SRC2 %08x\n", (i
>> 2) + start
- 0x180 + 0x40, data
[i
+2]);
980 fprintf(stderr
, "R200_VS_PROG %d SRC3 %08x\n", (i
>> 2) + start
- 0x180 + 0x40, data
[i
+3]);
984 fprintf(stderr
, "write to unknown vector area\n");
987 cmdbuf
->buf
+= sz
* sizeof(int);
988 cmdbuf
->bufsz
-= sz
* sizeof(int);
993 static int print_vertex_format( int vfmt
)
996 fprintf(stderr
, " %s(%x): %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
1000 (vfmt
& R200_VTX_Z0
) ? "z," : "",
1001 (vfmt
& R200_VTX_W0
) ? "w0," : "",
1002 (vfmt
& R200_VTX_FPCOLOR
) ? "fpcolor," : "",
1003 (vfmt
& R200_VTX_FPALPHA
) ? "fpalpha," : "",
1004 (vfmt
& R200_VTX_PKCOLOR
) ? "pkcolor," : "",
1005 (vfmt
& R200_VTX_FPSPEC
) ? "fpspec," : "",
1006 (vfmt
& R200_VTX_FPFOG
) ? "fpfog," : "",
1007 (vfmt
& R200_VTX_PKSPEC
) ? "pkspec," : "",
1008 (vfmt
& R200_VTX_ST0
) ? "st0," : "",
1009 (vfmt
& R200_VTX_ST1
) ? "st1," : "",
1010 (vfmt
& R200_VTX_Q1
) ? "q1," : "",
1011 (vfmt
& R200_VTX_ST2
) ? "st2," : "",
1012 (vfmt
& R200_VTX_Q2
) ? "q2," : "",
1013 (vfmt
& R200_VTX_ST3
) ? "st3," : "",
1014 (vfmt
& R200_VTX_Q3
) ? "q3," : "",
1015 (vfmt
& R200_VTX_Q0
) ? "q0," : "",
1016 (vfmt
& R200_VTX_N0
) ? "n0," : "",
1017 (vfmt
& R200_VTX_XY1
) ? "xy1," : "",
1018 (vfmt
& R200_VTX_Z1
) ? "z1," : "",
1019 (vfmt
& R200_VTX_W1
) ? "w1," : "",
1020 (vfmt
& R200_VTX_N1
) ? "n1," : "");
1023 if (!find_or_add_value( &others
[V_VTXFMT
], vfmt
))
1024 fprintf(stderr
, " *** NEW VALUE");
1026 fprintf(stderr
, "\n");
1033 static char *primname
[0x10] = {
1052 static int print_prim_and_flags( int prim
)
1057 fprintf(stderr
, " %s(%x): %s%s%s%s%s%s\n",
1060 ((prim
& 0x30) == R200_VF_PRIM_WALK_IND
) ? "IND," : "",
1061 ((prim
& 0x30) == R200_VF_PRIM_WALK_LIST
) ? "LIST," : "",
1062 ((prim
& 0x30) == R200_VF_PRIM_WALK_RING
) ? "RING," : "",
1063 (prim
& R200_VF_COLOR_ORDER_RGBA
) ? "RGBA," : "BGRA, ",
1064 (prim
& R200_VF_INDEX_SZ_4
) ? "INDX-32," : "",
1065 (prim
& R200_VF_TCL_OUTPUT_VTX_ENABLE
) ? "TCL_OUT_VTX," : "");
1067 numverts
= prim
>>16;
1070 fprintf(stderr
, " prim: %s numverts %d\n", primname
[prim
&0xf], numverts
);
1072 switch (prim
& 0xf) {
1073 case R200_VF_PRIM_NONE
:
1074 case R200_VF_PRIM_POINTS
:
1076 fprintf(stderr
, "Bad nr verts for line %d\n", numverts
);
1080 case R200_VF_PRIM_LINES
:
1081 case R200_VF_PRIM_POINT_SPRITES
:
1082 if ((numverts
& 1) || numverts
== 0) {
1083 fprintf(stderr
, "Bad nr verts for line %d\n", numverts
);
1087 case R200_VF_PRIM_LINE_STRIP
:
1088 case R200_VF_PRIM_LINE_LOOP
:
1090 fprintf(stderr
, "Bad nr verts for line_strip %d\n", numverts
);
1094 case R200_VF_PRIM_TRIANGLES
:
1095 case R200_VF_PRIM_3VRT_POINTS
:
1096 case R200_VF_PRIM_3VRT_LINES
:
1097 case R200_VF_PRIM_RECT_LIST
:
1098 if (numverts
% 3 || numverts
== 0) {
1099 fprintf(stderr
, "Bad nr verts for tri %d\n", numverts
);
1103 case R200_VF_PRIM_TRIANGLE_FAN
:
1104 case R200_VF_PRIM_TRIANGLE_STRIP
:
1105 case R200_VF_PRIM_POLYGON
:
1107 fprintf(stderr
, "Bad nr verts for strip/fan %d\n", numverts
);
1111 case R200_VF_PRIM_QUADS
:
1112 if (numverts
% 4 || numverts
== 0) {
1113 fprintf(stderr
, "Bad nr verts for quad %d\n", numverts
);
1117 case R200_VF_PRIM_QUAD_STRIP
:
1118 if (numverts
% 2 || numverts
< 4) {
1119 fprintf(stderr
, "Bad nr verts for quadstrip %d\n", numverts
);
1124 fprintf(stderr
, "Bad primitive\n");
1130 /* build in knowledge about each packet type
1132 static int radeon_emit_packet3( drm_radeon_cmd_buffer_t
*cmdbuf
)
1135 int *cmd
= (int *)cmdbuf
->buf
;
1137 int i
, stride
, size
, start
;
1139 cmdsz
= 2 + ((cmd
[0] & RADEON_CP_PACKET_COUNT_MASK
) >> 16);
1141 if ((cmd
[0] & RADEON_CP_PACKET_MASK
) != RADEON_CP_PACKET3
||
1142 cmdsz
* 4 > cmdbuf
->bufsz
||
1143 cmdsz
> RADEON_CP_PACKET_MAX_DWORDS
) {
1144 fprintf(stderr
, "Bad packet\n");
1148 switch( cmd
[0] & ~RADEON_CP_PACKET_COUNT_MASK
) {
1149 case R200_CP_CMD_NOP
:
1151 fprintf(stderr
, "PACKET3_NOP, %d dwords\n", cmdsz
);
1153 case R200_CP_CMD_NEXT_CHAR
:
1155 fprintf(stderr
, "PACKET3_NEXT_CHAR, %d dwords\n", cmdsz
);
1157 case R200_CP_CMD_PLY_NEXTSCAN
:
1159 fprintf(stderr
, "PACKET3_PLY_NEXTSCAN, %d dwords\n", cmdsz
);
1161 case R200_CP_CMD_SET_SCISSORS
:
1163 fprintf(stderr
, "PACKET3_SET_SCISSORS, %d dwords\n", cmdsz
);
1165 case R200_CP_CMD_LOAD_MICROCODE
:
1167 fprintf(stderr
, "PACKET3_LOAD_MICROCODE, %d dwords\n", cmdsz
);
1169 case R200_CP_CMD_WAIT_FOR_IDLE
:
1171 fprintf(stderr
, "PACKET3_WAIT_FOR_IDLE, %d dwords\n", cmdsz
);
1174 case R200_CP_CMD_3D_DRAW_VBUF
:
1176 fprintf(stderr
, "PACKET3_3D_DRAW_VBUF, %d dwords\n", cmdsz
);
1177 /* print_vertex_format(cmd[1]); */
1178 if (print_prim_and_flags(cmd
[2]))
1182 case R200_CP_CMD_3D_DRAW_IMMD
:
1184 fprintf(stderr
, "PACKET3_3D_DRAW_IMMD, %d dwords\n", cmdsz
);
1186 case R200_CP_CMD_3D_DRAW_INDX
: {
1189 fprintf(stderr
, "PACKET3_3D_DRAW_INDX, %d dwords\n", cmdsz
);
1190 /* print_vertex_format(cmd[1]); */
1191 if (print_prim_and_flags(cmd
[2]))
1193 neltdwords
= cmd
[2]>>16;
1194 neltdwords
+= neltdwords
& 1;
1196 if (neltdwords
+ 3 != cmdsz
)
1197 fprintf(stderr
, "Mismatch in DRAW_INDX, %d vs cmdsz %d\n",
1201 case R200_CP_CMD_LOAD_PALETTE
:
1203 fprintf(stderr
, "PACKET3_LOAD_PALETTE, %d dwords\n", cmdsz
);
1205 case R200_CP_CMD_3D_LOAD_VBPNTR
:
1207 fprintf(stderr
, "PACKET3_3D_LOAD_VBPNTR, %d dwords\n", cmdsz
);
1208 fprintf(stderr
, " nr arrays: %d\n", cmd
[1]);
1211 if (((cmd
[1]/2)*3) + ((cmd
[1]%2)*2) != cmdsz
- 2) {
1212 fprintf(stderr
, " ****** MISMATCH %d/%d *******\n",
1213 ((cmd
[1]/2)*3) + ((cmd
[1]%2)*2) + 2, cmdsz
);
1219 for (i
= 0 ; i
< cmd
[1] ; i
++) {
1221 stride
= (tmp
[0]>>24) & 0xff;
1222 size
= (tmp
[0]>>16) & 0xff;
1227 stride
= (tmp
[0]>>8) & 0xff;
1228 size
= (tmp
[0]) & 0xff;
1231 fprintf(stderr
, " array %d: start 0x%x vsize %d vstride %d\n",
1232 i
, start
, size
, stride
);
1236 case R200_CP_CMD_PAINT
:
1238 fprintf(stderr
, "PACKET3_CNTL_PAINT, %d dwords\n", cmdsz
);
1240 case R200_CP_CMD_BITBLT
:
1242 fprintf(stderr
, "PACKET3_CNTL_BITBLT, %d dwords\n", cmdsz
);
1244 case R200_CP_CMD_SMALLTEXT
:
1246 fprintf(stderr
, "PACKET3_CNTL_SMALLTEXT, %d dwords\n", cmdsz
);
1248 case R200_CP_CMD_HOSTDATA_BLT
:
1250 fprintf(stderr
, "PACKET3_CNTL_HOSTDATA_BLT, %d dwords\n",
1253 case R200_CP_CMD_POLYLINE
:
1255 fprintf(stderr
, "PACKET3_CNTL_POLYLINE, %d dwords\n", cmdsz
);
1257 case R200_CP_CMD_POLYSCANLINES
:
1259 fprintf(stderr
, "PACKET3_CNTL_POLYSCANLINES, %d dwords\n",
1262 case R200_CP_CMD_PAINT_MULTI
:
1264 fprintf(stderr
, "PACKET3_CNTL_PAINT_MULTI, %d dwords\n",
1267 case R200_CP_CMD_BITBLT_MULTI
:
1269 fprintf(stderr
, "PACKET3_CNTL_BITBLT_MULTI, %d dwords\n",
1272 case R200_CP_CMD_TRANS_BITBLT
:
1274 fprintf(stderr
, "PACKET3_CNTL_TRANS_BITBLT, %d dwords\n",
1277 case R200_CP_CMD_3D_DRAW_VBUF_2
:
1279 fprintf(stderr
, "R200_CP_CMD_3D_DRAW_VBUF_2, %d dwords\n",
1281 if (print_prim_and_flags(cmd
[1]))
1284 case R200_CP_CMD_3D_DRAW_IMMD_2
:
1286 fprintf(stderr
, "R200_CP_CMD_3D_DRAW_IMMD_2, %d dwords\n",
1288 if (print_prim_and_flags(cmd
[1]))
1291 case R200_CP_CMD_3D_DRAW_INDX_2
:
1293 fprintf(stderr
, "R200_CP_CMD_3D_DRAW_INDX_2, %d dwords\n",
1295 if (print_prim_and_flags(cmd
[1]))
1299 fprintf(stderr
, "UNKNOWN PACKET, %d dwords\n", cmdsz
);
1303 cmdbuf
->buf
+= cmdsz
* 4;
1304 cmdbuf
->bufsz
-= cmdsz
* 4;
1309 /* Check cliprects for bounds, then pass on to above:
1311 static int radeon_emit_packet3_cliprect( drm_radeon_cmd_buffer_t
*cmdbuf
)
1313 drm_clip_rect_t
*boxes
= (drm_clip_rect_t
*)cmdbuf
->boxes
;
1316 if (VERBOSE
&& total_changed
) {
1323 if ( i
< cmdbuf
->nbox
) {
1324 fprintf(stderr
, "Emit box %d/%d %d,%d %d,%d\n",
1326 boxes
[i
].x1
, boxes
[i
].y1
, boxes
[i
].x2
, boxes
[i
].y2
);
1328 } while ( ++i
< cmdbuf
->nbox
);
1331 if (cmdbuf
->nbox
== 1)
1334 return radeon_emit_packet3( cmdbuf
);
1338 int r200SanityCmdBuffer( r200ContextPtr rmesa
,
1340 drm_clip_rect_t
*boxes
)
1343 drm_radeon_cmd_buffer_t cmdbuf
;
1344 drm_radeon_cmd_header_t header
;
1345 static int inited
= 0;
1353 cmdbuf
.buf
= rmesa
->store
.cmd_buf
;
1354 cmdbuf
.bufsz
= rmesa
->store
.cmd_used
;
1355 cmdbuf
.boxes
= (drm_clip_rect_t
*)boxes
;
1358 while ( cmdbuf
.bufsz
>= sizeof(header
) ) {
1360 header
.i
= *(int *)cmdbuf
.buf
;
1361 cmdbuf
.buf
+= sizeof(header
);
1362 cmdbuf
.bufsz
-= sizeof(header
);
1364 switch (header
.header
.cmd_type
) {
1365 case RADEON_CMD_PACKET
:
1366 if (radeon_emit_packets( header
, &cmdbuf
)) {
1367 fprintf(stderr
,"radeon_emit_packets failed\n");
1372 case RADEON_CMD_SCALARS
:
1373 if (radeon_emit_scalars( header
, &cmdbuf
)) {
1374 fprintf(stderr
,"radeon_emit_scalars failed\n");
1379 case RADEON_CMD_SCALARS2
:
1380 if (radeon_emit_scalars2( header
, &cmdbuf
)) {
1381 fprintf(stderr
,"radeon_emit_scalars failed\n");
1386 case RADEON_CMD_VECTORS
:
1387 if (radeon_emit_vectors( header
, &cmdbuf
)) {
1388 fprintf(stderr
,"radeon_emit_vectors failed\n");
1393 case RADEON_CMD_DMA_DISCARD
:
1394 idx
= header
.dma
.buf_idx
;
1396 fprintf(stderr
, "RADEON_CMD_DMA_DISCARD buf %d\n", idx
);
1400 case RADEON_CMD_PACKET3
:
1401 if (radeon_emit_packet3( &cmdbuf
)) {
1402 fprintf(stderr
,"radeon_emit_packet3 failed\n");
1407 case RADEON_CMD_PACKET3_CLIP
:
1408 if (radeon_emit_packet3_cliprect( &cmdbuf
)) {
1409 fprintf(stderr
,"radeon_emit_packet3_clip failed\n");
1414 case RADEON_CMD_WAIT
:
1417 case RADEON_CMD_VECLINEAR
:
1418 if (radeon_emit_veclinear( header
, &cmdbuf
)) {
1419 fprintf(stderr
,"radeon_emit_veclinear failed\n");
1425 fprintf(stderr
,"bad cmd_type %d at %p\n",
1426 header
.header
.cmd_type
,
1427 cmdbuf
.buf
- sizeof(header
));
1437 fprintf(stderr
, "Bufs %d Total emitted %d real changes %d (%.2f%%)\n",
1439 total
, total_changed
,
1440 ((float)total_changed
/(float)total
*100.0));
1441 fprintf(stderr
, "Total emitted per buf: %.2f\n",
1442 (float)total
/(float)bufs
);
1443 fprintf(stderr
, "Real changes per buf: %.2f\n",
1444 (float)total_changed
/(float)bufs
);
1446 bufs
= n
= total
= total_changed
= 0;
1450 fprintf(stderr
, "leaving %s\n\n\n", __func__
);