src/mesa/drivers/dri/r200/r200_sanity.c

   1 /* $XFree86: xc/lib/GL/mesa/src/drv/r200/r200_sanity.c,v 1.1 2002/10/30 12:51:52 alanh Exp $ */
   2 /**************************************************************************
   3
   4 Copyright 2002 ATI Technologies Inc., Ontario, Canada, and
   5                      Tungsten Graphics Inc, Cedar Park, TX.
   6
   7 All Rights Reserved.
   8
   9 Permission is hereby granted, free of charge, to any person obtaining a
  10 copy of this software and associated documentation files (the "Software"),
  11 to deal in the Software without restriction, including without limitation
  12 on the rights to use, copy, modify, merge, publish, distribute, sub
  13 license, and/or sell copies of the Software, and to permit persons to whom
  14 the Software is furnished to do so, subject to the following conditions:
  15
  16 The above copyright notice and this permission notice (including the next
  17 paragraph) shall be included in all copies or substantial portions of the
  18 Software.
  19
  20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  21 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  22 FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  23 ATI, TUNGSTEN GRAPHICS AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  24 DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  25 OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  26 USE OR OTHER DEALINGS IN THE SOFTWARE.
  27
  28 **************************************************************************/
  29
  30 /*
  31  * Authors:
  32  *   Keith Whitwell <keith@tungstengraphics.com>
  33  *
  34  */
  35
  36 #include <errno.h>
  37
  38 #include "glheader.h"
  39 #include "imports.h"
  40
  41 #include "r200_context.h"
  42 #include "r200_ioctl.h"
  43 #include "r200_sanity.h"
  44 #include "radeon_reg.h"
  45 #include "r200_reg.h"
  46
  47 /* Set this '1' to get more verbiage.
  48  */
  49 #define MORE_VERBOSE 1
  50
  51 #if MORE_VERBOSE
  52 #define VERBOSE (R200_DEBUG & DEBUG_VERBOSE)
  53 #define NORMAL  (1)
  54 #else
  55 #define VERBOSE 0
  56 #define NORMAL  (R200_DEBUG & DEBUG_VERBOSE)
  57 #endif
  58
  59
  60 /* New (1.3) state mechanism.  3 commands (packet, scalar, vector) in
  61  * 1.3 cmdbuffers allow all previous state to be updated as well as
  62  * the tcl scalar and vector areas.
  63  */
  64 static struct {
  65    int start;
  66    int len;
  67    const char *name;
  68 } packet[RADEON_MAX_STATE_PACKETS] = {
  69    { RADEON_PP_MISC,7,"RADEON_PP_MISC" },
  70    { RADEON_PP_CNTL,3,"RADEON_PP_CNTL" },
  71    { RADEON_RB3D_COLORPITCH,1,"RADEON_RB3D_COLORPITCH" },
  72    { RADEON_RE_LINE_PATTERN,2,"RADEON_RE_LINE_PATTERN" },
  73    { RADEON_SE_LINE_WIDTH,1,"RADEON_SE_LINE_WIDTH" },
  74    { RADEON_PP_LUM_MATRIX,1,"RADEON_PP_LUM_MATRIX" },
  75    { RADEON_PP_ROT_MATRIX_0,2,"RADEON_PP_ROT_MATRIX_0" },
  76    { RADEON_RB3D_STENCILREFMASK,3,"RADEON_RB3D_STENCILREFMASK" },
  77    { RADEON_SE_VPORT_XSCALE,6,"RADEON_SE_VPORT_XSCALE" },
  78    { RADEON_SE_CNTL,2,"RADEON_SE_CNTL" },
  79    { RADEON_SE_CNTL_STATUS,1,"RADEON_SE_CNTL_STATUS" },
  80    { RADEON_RE_MISC,1,"RADEON_RE_MISC" },
  81    { RADEON_PP_TXFILTER_0,6,"RADEON_PP_TXFILTER_0" },
  82    { RADEON_PP_BORDER_COLOR_0,1,"RADEON_PP_BORDER_COLOR_0" },
  83    { RADEON_PP_TXFILTER_1,6,"RADEON_PP_TXFILTER_1" },
  84    { RADEON_PP_BORDER_COLOR_1,1,"RADEON_PP_BORDER_COLOR_1" },
  85    { RADEON_PP_TXFILTER_2,6,"RADEON_PP_TXFILTER_2" },
  86    { RADEON_PP_BORDER_COLOR_2,1,"RADEON_PP_BORDER_COLOR_2" },
  87    { RADEON_SE_ZBIAS_FACTOR,2,"RADEON_SE_ZBIAS_FACTOR" },
  88    { RADEON_SE_TCL_OUTPUT_VTX_FMT,11,"RADEON_SE_TCL_OUTPUT_VTX_FMT" },
  89    { RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED,17,"RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED" },
  90    { R200_PP_TXCBLEND_0, 4, "R200_EMIT_PP_TXCBLEND_0" },
  91    { R200_PP_TXCBLEND_1, 4, "R200_PP_TXCBLEND_1" },
  92    { R200_PP_TXCBLEND_2, 4, "R200_PP_TXCBLEND_2" },
  93    { R200_PP_TXCBLEND_3, 4, "R200_PP_TXCBLEND_3" },
  94    { R200_PP_TXCBLEND_4, 4, "R200_PP_TXCBLEND_4" },
  95    { R200_PP_TXCBLEND_5, 4, "R200_PP_TXCBLEND_5" },
  96    { R200_PP_TXCBLEND_6, 4, "R200_PP_TXCBLEND_6" },
  97    { R200_PP_TXCBLEND_7, 4, "R200_PP_TXCBLEND_7" },
  98    { R200_SE_TCL_LIGHT_MODEL_CTL_0, 6, "R200_SE_TCL_LIGHT_MODEL_CTL_0" },
  99    { R200_PP_TFACTOR_0, 6, "R200_PP_TFACTOR_0" },
 100    { R200_SE_VTX_FMT_0, 4, "R200_SE_VTX_FMT_0" },
 101    { R200_SE_VAP_CNTL, 1, "R200_SE_VAP_CNTL" },
 102    { R200_SE_TCL_MATRIX_SEL_0, 5, "R200_SE_TCL_MATRIX_SEL_0" },
 103    { R200_SE_TCL_TEX_PROC_CTL_2, 5, "R200_SE_TCL_TEX_PROC_CTL_2" },
 104    { R200_SE_TCL_UCP_VERT_BLEND_CTL, 1, "R200_SE_TCL_UCP_VERT_BLEND_CTL" },
 105    { R200_PP_TXFILTER_0, 6, "R200_PP_TXFILTER_0" },
 106    { R200_PP_TXFILTER_1, 6, "R200_PP_TXFILTER_1" },
 107    { R200_PP_TXFILTER_2, 6, "R200_PP_TXFILTER_2" },
 108    { R200_PP_TXFILTER_3, 6, "R200_PP_TXFILTER_3" },
 109    { R200_PP_TXFILTER_4, 6, "R200_PP_TXFILTER_4" },
 110    { R200_PP_TXFILTER_5, 6, "R200_PP_TXFILTER_5" },
 111    { R200_PP_TXOFFSET_0, 1, "R200_PP_TXOFFSET_0" },
 112    { R200_PP_TXOFFSET_1, 1, "R200_PP_TXOFFSET_1" },
 113    { R200_PP_TXOFFSET_2, 1, "R200_PP_TXOFFSET_2" },
 114    { R200_PP_TXOFFSET_3, 1, "R200_PP_TXOFFSET_3" },
 115    { R200_PP_TXOFFSET_4, 1, "R200_PP_TXOFFSET_4" },
 116    { R200_PP_TXOFFSET_5, 1, "R200_PP_TXOFFSET_5" },
 117    { R200_SE_VTE_CNTL, 1, "R200_SE_VTE_CNTL" },
 118    { R200_SE_TCL_OUTPUT_VTX_COMP_SEL, 1, "R200_SE_TCL_OUTPUT_VTX_COMP_SEL" },
 119    { R200_PP_TAM_DEBUG3, 1, "R200_PP_TAM_DEBUG3" },
 120    { R200_PP_CNTL_X, 1, "R200_PP_CNTL_X" },
 121    { R200_RB3D_DEPTHXY_OFFSET, 1, "R200_RB3D_DEPTHXY_OFFSET" },
 122    { R200_RE_AUX_SCISSOR_CNTL, 1, "R200_RE_AUX_SCISSOR_CNTL" },
 123    { R200_RE_SCISSOR_TL_0, 2, "R200_RE_SCISSOR_TL_0" },
 124    { R200_RE_SCISSOR_TL_1, 2, "R200_RE_SCISSOR_TL_1" },
 125    { R200_RE_SCISSOR_TL_2, 2, "R200_RE_SCISSOR_TL_2" },
 126    { R200_SE_VAP_CNTL_STATUS, 1, "R200_SE_VAP_CNTL_STATUS" },
 127    { R200_SE_VTX_STATE_CNTL, 1, "R200_SE_VTX_STATE_CNTL" },
 128    { R200_RE_POINTSIZE, 1, "R200_RE_POINTSIZE" },
 129    { R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0, 4, "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0" },
 130    { R200_PP_CUBIC_FACES_0, 1, "R200_PP_CUBIC_FACES_0" }, /* 61 */
 131    { R200_PP_CUBIC_OFFSET_F1_0, 5, "R200_PP_CUBIC_OFFSET_F1_0" }, /* 62 */
 132    { R200_PP_CUBIC_FACES_1, 1, "R200_PP_CUBIC_FACES_1" },
 133    { R200_PP_CUBIC_OFFSET_F1_1, 5, "R200_PP_CUBIC_OFFSET_F1_1" },
 134    { R200_PP_CUBIC_FACES_2, 1, "R200_PP_CUBIC_FACES_2" },
 135    { R200_PP_CUBIC_OFFSET_F1_2, 5, "R200_PP_CUBIC_OFFSET_F1_2" },
 136    { R200_PP_CUBIC_FACES_3, 1, "R200_PP_CUBIC_FACES_3" },
 137    { R200_PP_CUBIC_OFFSET_F1_3, 5, "R200_PP_CUBIC_OFFSET_F1_3" },
 138    { R200_PP_CUBIC_FACES_4, 1, "R200_PP_CUBIC_FACES_4" },
 139    { R200_PP_CUBIC_OFFSET_F1_4, 5, "R200_PP_CUBIC_OFFSET_F1_4" },
 140    { R200_PP_CUBIC_FACES_5, 1, "R200_PP_CUBIC_FACES_5" },
 141    { R200_PP_CUBIC_OFFSET_F1_5, 5, "R200_PP_CUBIC_OFFSET_F1_5" },
 142    { RADEON_PP_TEX_SIZE_0, 2, "RADEON_PP_TEX_SIZE_0" },
 143    { RADEON_PP_TEX_SIZE_1, 2, "RADEON_PP_TEX_SIZE_1" },
 144    { RADEON_PP_TEX_SIZE_2, 2, "RADEON_PP_TEX_SIZE_2" },
 145    { R200_RB3D_BLENDCOLOR, 3, "R200_RB3D_BLENDCOLOR" },
 146    { R200_SE_TCL_POINT_SPRITE_CNTL, 1, "R200_SE_TCL_POINT_SPRITE_CNTL" },
 147 };
 148
 149 struct reg_names {
 150    int idx;
 151    const char *name;
 152 };
 153
 154 static struct reg_names reg_names[] = {
 155    { R200_PP_MISC, "R200_PP_MISC" },
 156    { R200_PP_FOG_COLOR, "R200_PP_FOG_COLOR" },
 157    { R200_RE_SOLID_COLOR, "R200_RE_SOLID_COLOR" },
 158    { R200_RB3D_BLENDCNTL, "R200_RB3D_BLENDCNTL" },
 159    { R200_RB3D_DEPTHOFFSET, "R200_RB3D_DEPTHOFFSET" },
 160    { R200_RB3D_DEPTHPITCH, "R200_RB3D_DEPTHPITCH" },
 161    { R200_RB3D_ZSTENCILCNTL, "R200_RB3D_ZSTENCILCNTL" },
 162    { R200_PP_CNTL, "R200_PP_CNTL" },
 163    { R200_RB3D_CNTL, "R200_RB3D_CNTL" },
 164    { R200_RB3D_COLOROFFSET, "R200_RB3D_COLOROFFSET" },
 165    { R200_RE_WIDTH_HEIGHT, "R200_RE_WIDTH_HEIGHT" },
 166    { R200_RB3D_COLORPITCH, "R200_RB3D_COLORPITCH" },
 167    { R200_SE_CNTL, "R200_SE_CNTL" },
 168    { R200_RE_CNTL, "R200_RE_CNTL" },
 169    { R200_RE_MISC, "R200_RE_MISC" },
 170    { R200_RE_STIPPLE_ADDR, "R200_RE_STIPPLE_ADDR" },
 171    { R200_RE_STIPPLE_DATA, "R200_RE_STIPPLE_DATA" },
 172    { R200_RE_LINE_PATTERN, "R200_RE_LINE_PATTERN" },
 173    { R200_RE_LINE_STATE, "R200_RE_LINE_STATE" },
 174    { R200_RE_SCISSOR_TL_0, "R200_RE_SCISSOR_TL_0" },
 175    { R200_RE_SCISSOR_BR_0, "R200_RE_SCISSOR_BR_0" },
 176    { R200_RE_SCISSOR_TL_1, "R200_RE_SCISSOR_TL_1" },
 177    { R200_RE_SCISSOR_BR_1, "R200_RE_SCISSOR_BR_1" },
 178    { R200_RE_SCISSOR_TL_2, "R200_RE_SCISSOR_TL_2" },
 179    { R200_RE_SCISSOR_BR_2, "R200_RE_SCISSOR_BR_2" },
 180    { R200_RB3D_DEPTHXY_OFFSET, "R200_RB3D_DEPTHXY_OFFSET" },
 181    { R200_RB3D_STENCILREFMASK, "R200_RB3D_STENCILREFMASK" },
 182    { R200_RB3D_ROPCNTL, "R200_RB3D_ROPCNTL" },
 183    { R200_RB3D_PLANEMASK, "R200_RB3D_PLANEMASK" },
 184    { R200_SE_VPORT_XSCALE, "R200_SE_VPORT_XSCALE" },
 185    { R200_SE_VPORT_XOFFSET, "R200_SE_VPORT_XOFFSET" },
 186    { R200_SE_VPORT_YSCALE, "R200_SE_VPORT_YSCALE" },
 187    { R200_SE_VPORT_YOFFSET, "R200_SE_VPORT_YOFFSET" },
 188    { R200_SE_VPORT_ZSCALE, "R200_SE_VPORT_ZSCALE" },
 189    { R200_SE_VPORT_ZOFFSET, "R200_SE_VPORT_ZOFFSET" },
 190    { R200_SE_ZBIAS_FACTOR, "R200_SE_ZBIAS_FACTOR" },
 191    { R200_SE_ZBIAS_CONSTANT, "R200_SE_ZBIAS_CONSTANT" },
 192    { R200_SE_LINE_WIDTH, "R200_SE_LINE_WIDTH" },
 193    { R200_SE_VAP_CNTL, "R200_SE_VAP_CNTL" },
 194    { R200_SE_VF_CNTL, "R200_SE_VF_CNTL" },
 195    { R200_SE_VTX_FMT_0, "R200_SE_VTX_FMT_0" },
 196    { R200_SE_VTX_FMT_1, "R200_SE_VTX_FMT_1" },
 197    { R200_SE_TCL_OUTPUT_VTX_FMT_0, "R200_SE_TCL_OUTPUT_VTX_FMT_0" },
 198    { R200_SE_TCL_OUTPUT_VTX_FMT_1, "R200_SE_TCL_OUTPUT_VTX_FMT_1" },
 199    { R200_SE_VTE_CNTL, "R200_SE_VTE_CNTL" },
 200    { R200_SE_VTX_NUM_ARRAYS, "R200_SE_VTX_NUM_ARRAYS" },
 201    { R200_SE_VTX_AOS_ATTR01, "R200_SE_VTX_AOS_ATTR01" },
 202    { R200_SE_VTX_AOS_ADDR0, "R200_SE_VTX_AOS_ADDR0" },
 203    { R200_SE_VTX_AOS_ADDR1, "R200_SE_VTX_AOS_ADDR1" },
 204    { R200_SE_VTX_AOS_ATTR23, "R200_SE_VTX_AOS_ATTR23" },
 205    { R200_SE_VTX_AOS_ADDR2, "R200_SE_VTX_AOS_ADDR2" },
 206    { R200_SE_VTX_AOS_ADDR3, "R200_SE_VTX_AOS_ADDR3" },
 207    { R200_SE_VTX_AOS_ATTR45, "R200_SE_VTX_AOS_ATTR45" },
 208    { R200_SE_VTX_AOS_ADDR4, "R200_SE_VTX_AOS_ADDR4" },
 209    { R200_SE_VTX_AOS_ADDR5, "R200_SE_VTX_AOS_ADDR5" },
 210    { R200_SE_VTX_AOS_ATTR67, "R200_SE_VTX_AOS_ATTR67" },
 211    { R200_SE_VTX_AOS_ADDR6, "R200_SE_VTX_AOS_ADDR6" },
 212    { R200_SE_VTX_AOS_ADDR7, "R200_SE_VTX_AOS_ADDR7" },
 213    { R200_SE_VTX_AOS_ATTR89, "R200_SE_VTX_AOS_ATTR89" },
 214    { R200_SE_VTX_AOS_ADDR8, "R200_SE_VTX_AOS_ADDR8" },
 215    { R200_SE_VTX_AOS_ADDR9, "R200_SE_VTX_AOS_ADDR9" },
 216    { R200_SE_VTX_AOS_ATTR1011, "R200_SE_VTX_AOS_ATTR1011" },
 217    { R200_SE_VTX_AOS_ADDR10, "R200_SE_VTX_AOS_ADDR10" },
 218    { R200_SE_VTX_AOS_ADDR11, "R200_SE_VTX_AOS_ADDR11" },
 219    { R200_SE_VF_MAX_VTX_INDX, "R200_SE_VF_MAX_VTX_INDX" },
 220    { R200_SE_VF_MIN_VTX_INDX, "R200_SE_VF_MIN_VTX_INDX" },
 221    { R200_SE_VTX_STATE_CNTL, "R200_SE_VTX_STATE_CNTL" },
 222    { R200_SE_TCL_VECTOR_INDX_REG, "R200_SE_TCL_VECTOR_INDX_REG" },
 223    { R200_SE_TCL_VECTOR_DATA_REG, "R200_SE_TCL_VECTOR_DATA_REG" },
 224    { R200_SE_TCL_SCALAR_INDX_REG, "R200_SE_TCL_SCALAR_INDX_REG" },
 225    { R200_SE_TCL_SCALAR_DATA_REG, "R200_SE_TCL_SCALAR_DATA_REG" },
 226    { R200_SE_TCL_MATRIX_SEL_0, "R200_SE_TCL_MATRIX_SEL_0" },
 227    { R200_SE_TCL_MATRIX_SEL_1, "R200_SE_TCL_MATRIX_SEL_1" },
 228    { R200_SE_TCL_MATRIX_SEL_2, "R200_SE_TCL_MATRIX_SEL_2" },
 229    { R200_SE_TCL_MATRIX_SEL_3, "R200_SE_TCL_MATRIX_SEL_3" },
 230    { R200_SE_TCL_MATRIX_SEL_4, "R200_SE_TCL_MATRIX_SEL_4" },
 231    { R200_SE_TCL_LIGHT_MODEL_CTL_0, "R200_SE_TCL_LIGHT_MODEL_CTL_0" },
 232    { R200_SE_TCL_LIGHT_MODEL_CTL_1, "R200_SE_TCL_LIGHT_MODEL_CTL_1" },
 233    { R200_SE_TCL_PER_LIGHT_CTL_0, "R200_SE_TCL_PER_LIGHT_CTL_0" },
 234    { R200_SE_TCL_PER_LIGHT_CTL_1, "R200_SE_TCL_PER_LIGHT_CTL_1" },
 235    { R200_SE_TCL_PER_LIGHT_CTL_2, "R200_SE_TCL_PER_LIGHT_CTL_2" },
 236    { R200_SE_TCL_PER_LIGHT_CTL_3, "R200_SE_TCL_PER_LIGHT_CTL_3" },
 237    { R200_SE_TCL_TEX_PROC_CTL_2, "R200_SE_TCL_TEX_PROC_CTL_2" },
 238    { R200_SE_TCL_TEX_PROC_CTL_3, "R200_SE_TCL_TEX_PROC_CTL_3" },
 239    { R200_SE_TCL_TEX_PROC_CTL_0, "R200_SE_TCL_TEX_PROC_CTL_0" },
 240    { R200_SE_TCL_TEX_PROC_CTL_1, "R200_SE_TCL_TEX_PROC_CTL_1" },
 241    { R200_SE_TC_TEX_CYL_WRAP_CTL, "R200_SE_TC_TEX_CYL_WRAP_CTL" },
 242    { R200_SE_TCL_UCP_VERT_BLEND_CTL, "R200_SE_TCL_UCP_VERT_BLEND_CTL" },
 243    { R200_SE_TCL_POINT_SPRITE_CNTL, "R200_SE_TCL_POINT_SPRITE_CNTL" },
 244    { R200_SE_VTX_ST_POS_0_X_4, "R200_SE_VTX_ST_POS_0_X_4" },
 245    { R200_SE_VTX_ST_POS_0_Y_4, "R200_SE_VTX_ST_POS_0_Y_4" },
 246    { R200_SE_VTX_ST_POS_0_Z_4, "R200_SE_VTX_ST_POS_0_Z_4" },
 247    { R200_SE_VTX_ST_POS_0_W_4, "R200_SE_VTX_ST_POS_0_W_4" },
 248    { R200_SE_VTX_ST_NORM_0_X, "R200_SE_VTX_ST_NORM_0_X" },
 249    { R200_SE_VTX_ST_NORM_0_Y, "R200_SE_VTX_ST_NORM_0_Y" },
 250    { R200_SE_VTX_ST_NORM_0_Z, "R200_SE_VTX_ST_NORM_0_Z" },
 251    { R200_SE_VTX_ST_PVMS, "R200_SE_VTX_ST_PVMS" },
 252    { R200_SE_VTX_ST_CLR_0_R, "R200_SE_VTX_ST_CLR_0_R" },
 253    { R200_SE_VTX_ST_CLR_0_G, "R200_SE_VTX_ST_CLR_0_G" },
 254    { R200_SE_VTX_ST_CLR_0_B, "R200_SE_VTX_ST_CLR_0_B" },
 255    { R200_SE_VTX_ST_CLR_0_A, "R200_SE_VTX_ST_CLR_0_A" },
 256    { R200_SE_VTX_ST_CLR_1_R, "R200_SE_VTX_ST_CLR_1_R" },
 257    { R200_SE_VTX_ST_CLR_1_G, "R200_SE_VTX_ST_CLR_1_G" },
 258    { R200_SE_VTX_ST_CLR_1_B, "R200_SE_VTX_ST_CLR_1_B" },
 259    { R200_SE_VTX_ST_CLR_1_A, "R200_SE_VTX_ST_CLR_1_A" },
 260    { R200_SE_VTX_ST_CLR_2_R, "R200_SE_VTX_ST_CLR_2_R" },
 261    { R200_SE_VTX_ST_CLR_2_G, "R200_SE_VTX_ST_CLR_2_G" },
 262    { R200_SE_VTX_ST_CLR_2_B, "R200_SE_VTX_ST_CLR_2_B" },
 263    { R200_SE_VTX_ST_CLR_2_A, "R200_SE_VTX_ST_CLR_2_A" },
 264    { R200_SE_VTX_ST_CLR_3_R, "R200_SE_VTX_ST_CLR_3_R" },
 265    { R200_SE_VTX_ST_CLR_3_G, "R200_SE_VTX_ST_CLR_3_G" },
 266    { R200_SE_VTX_ST_CLR_3_B, "R200_SE_VTX_ST_CLR_3_B" },
 267    { R200_SE_VTX_ST_CLR_3_A, "R200_SE_VTX_ST_CLR_3_A" },
 268    { R200_SE_VTX_ST_CLR_4_R, "R200_SE_VTX_ST_CLR_4_R" },
 269    { R200_SE_VTX_ST_CLR_4_G, "R200_SE_VTX_ST_CLR_4_G" },
 270    { R200_SE_VTX_ST_CLR_4_B, "R200_SE_VTX_ST_CLR_4_B" },
 271    { R200_SE_VTX_ST_CLR_4_A, "R200_SE_VTX_ST_CLR_4_A" },
 272    { R200_SE_VTX_ST_CLR_5_R, "R200_SE_VTX_ST_CLR_5_R" },
 273    { R200_SE_VTX_ST_CLR_5_G, "R200_SE_VTX_ST_CLR_5_G" },
 274    { R200_SE_VTX_ST_CLR_5_B, "R200_SE_VTX_ST_CLR_5_B" },
 275    { R200_SE_VTX_ST_CLR_5_A, "R200_SE_VTX_ST_CLR_5_A" },
 276    { R200_SE_VTX_ST_CLR_6_R, "R200_SE_VTX_ST_CLR_6_R" },
 277    { R200_SE_VTX_ST_CLR_6_G, "R200_SE_VTX_ST_CLR_6_G" },
 278    { R200_SE_VTX_ST_CLR_6_B, "R200_SE_VTX_ST_CLR_6_B" },
 279    { R200_SE_VTX_ST_CLR_6_A, "R200_SE_VTX_ST_CLR_6_A" },
 280    { R200_SE_VTX_ST_CLR_7_R, "R200_SE_VTX_ST_CLR_7_R" },
 281    { R200_SE_VTX_ST_CLR_7_G, "R200_SE_VTX_ST_CLR_7_G" },
 282    { R200_SE_VTX_ST_CLR_7_B, "R200_SE_VTX_ST_CLR_7_B" },
 283    { R200_SE_VTX_ST_CLR_7_A, "R200_SE_VTX_ST_CLR_7_A" },
 284    { R200_SE_VTX_ST_TEX_0_S, "R200_SE_VTX_ST_TEX_0_S" },
 285    { R200_SE_VTX_ST_TEX_0_T, "R200_SE_VTX_ST_TEX_0_T" },
 286    { R200_SE_VTX_ST_TEX_0_R, "R200_SE_VTX_ST_TEX_0_R" },
 287    { R200_SE_VTX_ST_TEX_0_Q, "R200_SE_VTX_ST_TEX_0_Q" },
 288    { R200_SE_VTX_ST_TEX_1_S, "R200_SE_VTX_ST_TEX_1_S" },
 289    { R200_SE_VTX_ST_TEX_1_T, "R200_SE_VTX_ST_TEX_1_T" },
 290    { R200_SE_VTX_ST_TEX_1_R, "R200_SE_VTX_ST_TEX_1_R" },
 291    { R200_SE_VTX_ST_TEX_1_Q, "R200_SE_VTX_ST_TEX_1_Q" },
 292    { R200_SE_VTX_ST_TEX_2_S, "R200_SE_VTX_ST_TEX_2_S" },
 293    { R200_SE_VTX_ST_TEX_2_T, "R200_SE_VTX_ST_TEX_2_T" },
 294    { R200_SE_VTX_ST_TEX_2_R, "R200_SE_VTX_ST_TEX_2_R" },
 295    { R200_SE_VTX_ST_TEX_2_Q, "R200_SE_VTX_ST_TEX_2_Q" },
 296    { R200_SE_VTX_ST_TEX_3_S, "R200_SE_VTX_ST_TEX_3_S" },
 297    { R200_SE_VTX_ST_TEX_3_T, "R200_SE_VTX_ST_TEX_3_T" },
 298    { R200_SE_VTX_ST_TEX_3_R, "R200_SE_VTX_ST_TEX_3_R" },
 299    { R200_SE_VTX_ST_TEX_3_Q, "R200_SE_VTX_ST_TEX_3_Q" },
 300    { R200_SE_VTX_ST_TEX_4_S, "R200_SE_VTX_ST_TEX_4_S" },
 301    { R200_SE_VTX_ST_TEX_4_T, "R200_SE_VTX_ST_TEX_4_T" },
 302    { R200_SE_VTX_ST_TEX_4_R, "R200_SE_VTX_ST_TEX_4_R" },
 303    { R200_SE_VTX_ST_TEX_4_Q, "R200_SE_VTX_ST_TEX_4_Q" },
 304    { R200_SE_VTX_ST_TEX_5_S, "R200_SE_VTX_ST_TEX_5_S" },
 305    { R200_SE_VTX_ST_TEX_5_T, "R200_SE_VTX_ST_TEX_5_T" },
 306    { R200_SE_VTX_ST_TEX_5_R, "R200_SE_VTX_ST_TEX_5_R" },
 307    { R200_SE_VTX_ST_TEX_5_Q, "R200_SE_VTX_ST_TEX_5_Q" },
 308    { R200_SE_VTX_ST_PNT_SPRT_SZ, "R200_SE_VTX_ST_PNT_SPRT_SZ" },
 309    { R200_SE_VTX_ST_DISC_FOG, "R200_SE_VTX_ST_DISC_FOG" },
 310    { R200_SE_VTX_ST_SHININESS_0, "R200_SE_VTX_ST_SHININESS_0" },
 311    { R200_SE_VTX_ST_SHININESS_1, "R200_SE_VTX_ST_SHININESS_1" },
 312    { R200_SE_VTX_ST_BLND_WT_0, "R200_SE_VTX_ST_BLND_WT_0" },
 313    { R200_SE_VTX_ST_BLND_WT_1, "R200_SE_VTX_ST_BLND_WT_1" },
 314    { R200_SE_VTX_ST_BLND_WT_2, "R200_SE_VTX_ST_BLND_WT_2" },
 315    { R200_SE_VTX_ST_BLND_WT_3, "R200_SE_VTX_ST_BLND_WT_3" },
 316    { R200_SE_VTX_ST_POS_1_X, "R200_SE_VTX_ST_POS_1_X" },
 317    { R200_SE_VTX_ST_POS_1_Y, "R200_SE_VTX_ST_POS_1_Y" },
 318    { R200_SE_VTX_ST_POS_1_Z, "R200_SE_VTX_ST_POS_1_Z" },
 319    { R200_SE_VTX_ST_POS_1_W, "R200_SE_VTX_ST_POS_1_W" },
 320    { R200_SE_VTX_ST_NORM_1_X, "R200_SE_VTX_ST_NORM_1_X" },
 321    { R200_SE_VTX_ST_NORM_1_Y, "R200_SE_VTX_ST_NORM_1_Y" },
 322    { R200_SE_VTX_ST_NORM_1_Z, "R200_SE_VTX_ST_NORM_1_Z" },
 323    { R200_SE_VTX_ST_USR_CLR_0_R, "R200_SE_VTX_ST_USR_CLR_0_R" },
 324    { R200_SE_VTX_ST_USR_CLR_0_G, "R200_SE_VTX_ST_USR_CLR_0_G" },
 325    { R200_SE_VTX_ST_USR_CLR_0_B, "R200_SE_VTX_ST_USR_CLR_0_B" },
 326    { R200_SE_VTX_ST_USR_CLR_0_A, "R200_SE_VTX_ST_USR_CLR_0_A" },
 327    { R200_SE_VTX_ST_USR_CLR_1_R, "R200_SE_VTX_ST_USR_CLR_1_R" },
 328    { R200_SE_VTX_ST_USR_CLR_1_G, "R200_SE_VTX_ST_USR_CLR_1_G" },
 329    { R200_SE_VTX_ST_USR_CLR_1_B, "R200_SE_VTX_ST_USR_CLR_1_B" },
 330    { R200_SE_VTX_ST_USR_CLR_1_A, "R200_SE_VTX_ST_USR_CLR_1_A" },
 331    { R200_SE_VTX_ST_CLR_0_PKD, "R200_SE_VTX_ST_CLR_0_PKD" },
 332    { R200_SE_VTX_ST_CLR_1_PKD, "R200_SE_VTX_ST_CLR_1_PKD" },
 333    { R200_SE_VTX_ST_CLR_2_PKD, "R200_SE_VTX_ST_CLR_2_PKD" },
 334    { R200_SE_VTX_ST_CLR_3_PKD, "R200_SE_VTX_ST_CLR_3_PKD" },
 335    { R200_SE_VTX_ST_CLR_4_PKD, "R200_SE_VTX_ST_CLR_4_PKD" },
 336    { R200_SE_VTX_ST_CLR_5_PKD, "R200_SE_VTX_ST_CLR_5_PKD" },
 337    { R200_SE_VTX_ST_CLR_6_PKD, "R200_SE_VTX_ST_CLR_6_PKD" },
 338    { R200_SE_VTX_ST_CLR_7_PKD, "R200_SE_VTX_ST_CLR_7_PKD" },
 339    { R200_SE_VTX_ST_POS_0_X_2, "R200_SE_VTX_ST_POS_0_X_2" },
 340    { R200_SE_VTX_ST_POS_0_Y_2, "R200_SE_VTX_ST_POS_0_Y_2" },
 341    { R200_SE_VTX_ST_PAR_CLR_LD, "R200_SE_VTX_ST_PAR_CLR_LD" },
 342    { R200_SE_VTX_ST_USR_CLR_PKD, "R200_SE_VTX_ST_USR_CLR_PKD" },
 343    { R200_SE_VTX_ST_POS_0_X_3, "R200_SE_VTX_ST_POS_0_X_3" },
 344    { R200_SE_VTX_ST_POS_0_Y_3, "R200_SE_VTX_ST_POS_0_Y_3" },
 345    { R200_SE_VTX_ST_POS_0_Z_3, "R200_SE_VTX_ST_POS_0_Z_3" },
 346    { R200_SE_VTX_ST_END_OF_PKT, "R200_SE_VTX_ST_END_OF_PKT" },
 347    { R200_RE_POINTSIZE, "R200_RE_POINTSIZE" },
 348    { R200_RE_TOP_LEFT, "R200_RE_TOP_LEFT" },
 349    { R200_RE_AUX_SCISSOR_CNTL, "R200_RE_AUX_SCISSOR_CNTL" },
 350    { R200_PP_TXFILTER_0, "R200_PP_TXFILTER_0" },
 351    { R200_PP_TXFORMAT_0, "R200_PP_TXFORMAT_0" },
 352    { R200_PP_TXSIZE_0, "R200_PP_TXSIZE_0" },
 353    { R200_PP_TXFORMAT_X_0, "R200_PP_TXFORMAT_X_0" },
 354    { R200_PP_TXPITCH_0, "R200_PP_TXPITCH_0" },
 355    { R200_PP_BORDER_COLOR_0, "R200_PP_BORDER_COLOR_0" },
 356    { R200_PP_CUBIC_FACES_0, "R200_PP_CUBIC_FACES_0" },
 357    { R200_PP_TXFILTER_1, "R200_PP_TXFILTER_1" },
 358    { R200_PP_TXFORMAT_1, "R200_PP_TXFORMAT_1" },
 359    { R200_PP_TXSIZE_1, "R200_PP_TXSIZE_1" },
 360    { R200_PP_TXFORMAT_X_1, "R200_PP_TXFORMAT_X_1" },
 361    { R200_PP_TXPITCH_1, "R200_PP_TXPITCH_1" },
 362    { R200_PP_BORDER_COLOR_1, "R200_PP_BORDER_COLOR_1" },
 363    { R200_PP_CUBIC_FACES_1, "R200_PP_CUBIC_FACES_1" },
 364    { R200_PP_TXFILTER_2, "R200_PP_TXFILTER_2" },
 365    { R200_PP_TXFORMAT_2, "R200_PP_TXFORMAT_2" },
 366    { R200_PP_TXSIZE_2, "R200_PP_TXSIZE_2" },
 367    { R200_PP_TXFORMAT_X_2, "R200_PP_TXFORMAT_X_2" },
 368    { R200_PP_TXPITCH_2, "R200_PP_TXPITCH_2" },
 369    { R200_PP_BORDER_COLOR_2, "R200_PP_BORDER_COLOR_2" },
 370    { R200_PP_CUBIC_FACES_2, "R200_PP_CUBIC_FACES_2" },
 371    { R200_PP_TXFILTER_3, "R200_PP_TXFILTER_3" },
 372    { R200_PP_TXFORMAT_3, "R200_PP_TXFORMAT_3" },
 373    { R200_PP_TXSIZE_3, "R200_PP_TXSIZE_3" },
 374    { R200_PP_TXFORMAT_X_3, "R200_PP_TXFORMAT_X_3" },
 375    { R200_PP_TXPITCH_3, "R200_PP_TXPITCH_3" },
 376    { R200_PP_BORDER_COLOR_3, "R200_PP_BORDER_COLOR_3" },
 377    { R200_PP_CUBIC_FACES_3, "R200_PP_CUBIC_FACES_3" },
 378    { R200_PP_TXFILTER_4, "R200_PP_TXFILTER_4" },
 379    { R200_PP_TXFORMAT_4, "R200_PP_TXFORMAT_4" },
 380    { R200_PP_TXSIZE_4, "R200_PP_TXSIZE_4" },
 381    { R200_PP_TXFORMAT_X_4, "R200_PP_TXFORMAT_X_4" },
 382    { R200_PP_TXPITCH_4, "R200_PP_TXPITCH_4" },
 383    { R200_PP_BORDER_COLOR_4, "R200_PP_BORDER_COLOR_4" },
 384    { R200_PP_CUBIC_FACES_4, "R200_PP_CUBIC_FACES_4" },
 385    { R200_PP_TXFILTER_5, "R200_PP_TXFILTER_5" },
 386    { R200_PP_TXFORMAT_5, "R200_PP_TXFORMAT_5" },
 387    { R200_PP_TXSIZE_5, "R200_PP_TXSIZE_5" },
 388    { R200_PP_TXFORMAT_X_5, "R200_PP_TXFORMAT_X_5" },
 389    { R200_PP_TXPITCH_5, "R200_PP_TXPITCH_5" },
 390    { R200_PP_BORDER_COLOR_5, "R200_PP_BORDER_COLOR_5" },
 391    { R200_PP_CUBIC_FACES_5, "R200_PP_CUBIC_FACES_5" },
 392    { R200_PP_TXOFFSET_0, "R200_PP_TXOFFSET_0" },
 393    { R200_PP_CUBIC_OFFSET_F1_0, "R200_PP_CUBIC_OFFSET_F1_0" },
 394    { R200_PP_CUBIC_OFFSET_F2_0, "R200_PP_CUBIC_OFFSET_F2_0" },
 395    { R200_PP_CUBIC_OFFSET_F3_0, "R200_PP_CUBIC_OFFSET_F3_0" },
 396    { R200_PP_CUBIC_OFFSET_F4_0, "R200_PP_CUBIC_OFFSET_F4_0" },
 397    { R200_PP_CUBIC_OFFSET_F5_0, "R200_PP_CUBIC_OFFSET_F5_0" },
 398    { R200_PP_TXOFFSET_1, "R200_PP_TXOFFSET_1" },
 399    { R200_PP_CUBIC_OFFSET_F1_1, "R200_PP_CUBIC_OFFSET_F1_1" },
 400    { R200_PP_CUBIC_OFFSET_F2_1, "R200_PP_CUBIC_OFFSET_F2_1" },
 401    { R200_PP_CUBIC_OFFSET_F3_1, "R200_PP_CUBIC_OFFSET_F3_1" },
 402    { R200_PP_CUBIC_OFFSET_F4_1, "R200_PP_CUBIC_OFFSET_F4_1" },
 403    { R200_PP_CUBIC_OFFSET_F5_1, "R200_PP_CUBIC_OFFSET_F5_1" },
 404    { R200_PP_TXOFFSET_2, "R200_PP_TXOFFSET_2" },
 405    { R200_PP_CUBIC_OFFSET_F1_2, "R200_PP_CUBIC_OFFSET_F1_2" },
 406    { R200_PP_CUBIC_OFFSET_F2_2, "R200_PP_CUBIC_OFFSET_F2_2" },
 407    { R200_PP_CUBIC_OFFSET_F3_2, "R200_PP_CUBIC_OFFSET_F3_2" },
 408    { R200_PP_CUBIC_OFFSET_F4_2, "R200_PP_CUBIC_OFFSET_F4_2" },
 409    { R200_PP_CUBIC_OFFSET_F5_2, "R200_PP_CUBIC_OFFSET_F5_2" },
 410    { R200_PP_TXOFFSET_3, "R200_PP_TXOFFSET_3" },
 411    { R200_PP_CUBIC_OFFSET_F1_3, "R200_PP_CUBIC_OFFSET_F1_3" },
 412    { R200_PP_CUBIC_OFFSET_F2_3, "R200_PP_CUBIC_OFFSET_F2_3" },
 413    { R200_PP_CUBIC_OFFSET_F3_3, "R200_PP_CUBIC_OFFSET_F3_3" },
 414    { R200_PP_CUBIC_OFFSET_F4_3, "R200_PP_CUBIC_OFFSET_F4_3" },
 415    { R200_PP_CUBIC_OFFSET_F5_3, "R200_PP_CUBIC_OFFSET_F5_3" },
 416    { R200_PP_TXOFFSET_4, "R200_PP_TXOFFSET_4" },
 417    { R200_PP_CUBIC_OFFSET_F1_4, "R200_PP_CUBIC_OFFSET_F1_4" },
 418    { R200_PP_CUBIC_OFFSET_F2_4, "R200_PP_CUBIC_OFFSET_F2_4" },
 419    { R200_PP_CUBIC_OFFSET_F3_4, "R200_PP_CUBIC_OFFSET_F3_4" },
 420    { R200_PP_CUBIC_OFFSET_F4_4, "R200_PP_CUBIC_OFFSET_F4_4" },
 421    { R200_PP_CUBIC_OFFSET_F5_4, "R200_PP_CUBIC_OFFSET_F5_4" },
 422    { R200_PP_TXOFFSET_5, "R200_PP_TXOFFSET_5" },
 423    { R200_PP_CUBIC_OFFSET_F1_5, "R200_PP_CUBIC_OFFSET_F1_5" },
 424    { R200_PP_CUBIC_OFFSET_F2_5, "R200_PP_CUBIC_OFFSET_F2_5" },
 425    { R200_PP_CUBIC_OFFSET_F3_5, "R200_PP_CUBIC_OFFSET_F3_5" },
 426    { R200_PP_CUBIC_OFFSET_F4_5, "R200_PP_CUBIC_OFFSET_F4_5" },
 427    { R200_PP_CUBIC_OFFSET_F5_5, "R200_PP_CUBIC_OFFSET_F5_5" },
 428    { R200_PP_TAM_DEBUG3, "R200_PP_TAM_DEBUG3" },
 429    { R200_PP_TFACTOR_0, "R200_PP_TFACTOR_0" },
 430    { R200_PP_TFACTOR_1, "R200_PP_TFACTOR_1" },
 431    { R200_PP_TFACTOR_2, "R200_PP_TFACTOR_2" },
 432    { R200_PP_TFACTOR_3, "R200_PP_TFACTOR_3" },
 433    { R200_PP_TFACTOR_4, "R200_PP_TFACTOR_4" },
 434    { R200_PP_TFACTOR_5, "R200_PP_TFACTOR_5" },
 435    { R200_PP_TXCBLEND_0, "R200_PP_TXCBLEND_0" },
 436    { R200_PP_TXCBLEND2_0, "R200_PP_TXCBLEND2_0" },
 437    { R200_PP_TXABLEND_0, "R200_PP_TXABLEND_0" },
 438    { R200_PP_TXABLEND2_0, "R200_PP_TXABLEND2_0" },
 439    { R200_PP_TXCBLEND_1, "R200_PP_TXCBLEND_1" },
 440    { R200_PP_TXCBLEND2_1, "R200_PP_TXCBLEND2_1" },
 441    { R200_PP_TXABLEND_1, "R200_PP_TXABLEND_1" },
 442    { R200_PP_TXABLEND2_1, "R200_PP_TXABLEND2_1" },
 443    { R200_PP_TXCBLEND_2, "R200_PP_TXCBLEND_2" },
 444    { R200_PP_TXCBLEND2_2, "R200_PP_TXCBLEND2_2" },
 445    { R200_PP_TXABLEND_2, "R200_PP_TXABLEND_2" },
 446    { R200_PP_TXABLEND2_2, "R200_PP_TXABLEND2_2" },
 447    { R200_PP_TXCBLEND_3, "R200_PP_TXCBLEND_3" },
 448    { R200_PP_TXCBLEND2_3, "R200_PP_TXCBLEND2_3" },
 449    { R200_PP_TXABLEND_3, "R200_PP_TXABLEND_3" },
 450    { R200_PP_TXABLEND2_3, "R200_PP_TXABLEND2_3" },
 451    { R200_PP_TXCBLEND_4, "R200_PP_TXCBLEND_4" },
 452    { R200_PP_TXCBLEND2_4, "R200_PP_TXCBLEND2_4" },
 453    { R200_PP_TXABLEND_4, "R200_PP_TXABLEND_4" },
 454    { R200_PP_TXABLEND2_4, "R200_PP_TXABLEND2_4" },
 455    { R200_PP_TXCBLEND_5, "R200_PP_TXCBLEND_5" },
 456    { R200_PP_TXCBLEND2_5, "R200_PP_TXCBLEND2_5" },
 457    { R200_PP_TXABLEND_5, "R200_PP_TXABLEND_5" },
 458    { R200_PP_TXABLEND2_5, "R200_PP_TXABLEND2_5" },
 459    { R200_PP_TXCBLEND_6, "R200_PP_TXCBLEND_6" },
 460    { R200_PP_TXCBLEND2_6, "R200_PP_TXCBLEND2_6" },
 461    { R200_PP_TXABLEND_6, "R200_PP_TXABLEND_6" },
 462    { R200_PP_TXABLEND2_6, "R200_PP_TXABLEND2_6" },
 463    { R200_PP_TXCBLEND_7, "R200_PP_TXCBLEND_7" },
 464    { R200_PP_TXCBLEND2_7, "R200_PP_TXCBLEND2_7" },
 465    { R200_PP_TXABLEND_7, "R200_PP_TXABLEND_7" },
 466    { R200_PP_TXABLEND2_7, "R200_PP_TXABLEND2_7" },
 467    { R200_RB3D_BLENDCOLOR, "R200_RB3D_BLENDCOLOR" },
 468    { R200_RB3D_ABLENDCNTL, "R200_RB3D_ABLENDCNTL" },
 469    { R200_RB3D_CBLENDCNTL, "R200_RB3D_CBLENDCNTL" },
 470    { R200_SE_TCL_OUTPUT_VTX_COMP_SEL, "R200_SE_TCL_OUTPUT_VTX_COMP_SEL" },
 471    { R200_PP_CNTL_X, "R200_PP_CNTL_X" },
 472    { R200_SE_VAP_CNTL_STATUS, "R200_SE_VAP_CNTL_STATUS" },
 473    { R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0, "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0" },
 474    { R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_1, "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_1" },
 475    { R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_2, "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_2" },
 476    { R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_3, "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_3" },
 477 };
 478
 479 static struct reg_names scalar_names[] = {
 480    { R200_SS_LIGHT_DCD_ADDR, "R200_SS_LIGHT_DCD_ADDR" },
 481    { R200_SS_LIGHT_DCM_ADDR, "R200_SS_LIGHT_DCM_ADDR" },
 482    { R200_SS_LIGHT_SPOT_EXPONENT_ADDR, "R200_SS_LIGHT_SPOT_EXPONENT_ADDR" },
 483    { R200_SS_LIGHT_SPOT_CUTOFF_ADDR, "R200_SS_LIGHT_SPOT_CUTOFF_ADDR" },
 484    { R200_SS_LIGHT_SPECULAR_THRESH_ADDR, "R200_SS_LIGHT_SPECULAR_THRESH_ADDR" },
 485    { R200_SS_LIGHT_RANGE_CUTOFF_SQRD, "R200_SS_LIGHT_RANGE_CUTOFF_SQRD" },
 486    { R200_SS_LIGHT_RANGE_ATT_CONST, "R200_SS_LIGHT_RANGE_ATT_CONST" },
 487    { R200_SS_VERT_GUARD_CLIP_ADJ_ADDR, "R200_SS_VERT_GUARD_CLIP_ADJ_ADDR" },
 488    { R200_SS_VERT_GUARD_DISCARD_ADJ_ADDR, "R200_SS_VERT_GUARD_DISCARD_ADJ_ADDR" },
 489    { R200_SS_HORZ_GUARD_CLIP_ADJ_ADDR, "R200_SS_HORZ_GUARD_CLIP_ADJ_ADDR" },
 490    { R200_SS_HORZ_GUARD_DISCARD_ADJ_ADDR, "R200_SS_HORZ_GUARD_DISCARD_ADJ_ADDR" },
 491    { R200_SS_MAT_0_SHININESS, "R200_SS_MAT_0_SHININESS" },
 492    { R200_SS_MAT_1_SHININESS, "R200_SS_MAT_1_SHININESS" },
 493    { 1000, "" },
 494 };
 495
 496 /* Puff these out to make them look like normal (dword) registers.
 497  */
 498 static struct reg_names vector_names[] = {
 499    { 0, "start" },
 500    { R200_VS_LIGHT_AMBIENT_ADDR, "R200_VS_LIGHT_AMBIENT_ADDR" },
 501    { R200_VS_LIGHT_DIFFUSE_ADDR, "R200_VS_LIGHT_DIFFUSE_ADDR" },
 502    { R200_VS_LIGHT_SPECULAR_ADDR, "R200_VS_LIGHT_SPECULAR_ADDR" },
 503    { R200_VS_LIGHT_DIRPOS_ADDR, "R200_VS_LIGHT_DIRPOS_ADDR" },
 504    { R200_VS_LIGHT_HWVSPOT_ADDR, "R200_VS_LIGHT_HWVSPOT_ADDR" },
 505    { R200_VS_LIGHT_ATTENUATION_ADDR, "R200_VS_LIGHT_ATTENUATION_ADDR" },
 506    { R200_VS_SPOT_DUAL_CONE, "R200_VS_SPOT_DUAL_CONE" },
 507    { R200_VS_GLOBAL_AMBIENT_ADDR, "R200_VS_GLOBAL_AMBIENT_ADDR" },
 508    { R200_VS_FOG_PARAM_ADDR, "R200_VS_FOG_PARAM_ADDR" },
 509    { R200_VS_EYE_VECTOR_ADDR, "R200_VS_EYE_VECTOR_ADDR" },
 510    { R200_VS_UCP_ADDR, "R200_VS_UCP_ADDR" },
 511    { R200_VS_PNT_SPRITE_VPORT_SCALE, "R200_VS_PNT_SPRITE_VPORT_SCALE" },
 512    { R200_VS_MATRIX_0_MV, "R200_VS_MATRIX_0_MV" },
 513    { R200_VS_MATRIX_1_INV_MV, "R200_VS_MATRIX_1_INV_MV" },
 514    { R200_VS_MATRIX_2_MVP, "R200_VS_MATRIX_2_MVP" },
 515    { R200_VS_MATRIX_3_TEX0, "R200_VS_MATRIX_3_TEX0" },
 516    { R200_VS_MATRIX_4_TEX1, "R200_VS_MATRIX_4_TEX1" },
 517    { R200_VS_MATRIX_5_TEX2, "R200_VS_MATRIX_5_TEX2" },
 518    { R200_VS_MATRIX_6_TEX3, "R200_VS_MATRIX_6_TEX3" },
 519    { R200_VS_MATRIX_7_TEX4, "R200_VS_MATRIX_7_TEX4" },
 520    { R200_VS_MATRIX_8_TEX5, "R200_VS_MATRIX_8_TEX5" },
 521    { R200_VS_MAT_0_EMISS, "R200_VS_MAT_0_EMISS" },
 522    { R200_VS_MAT_0_AMB, "R200_VS_MAT_0_AMB" },
 523    { R200_VS_MAT_0_DIF, "R200_VS_MAT_0_DIF" },
 524    { R200_VS_MAT_0_SPEC, "R200_VS_MAT_0_SPEC" },
 525    { R200_VS_MAT_1_EMISS, "R200_VS_MAT_1_EMISS" },
 526    { R200_VS_MAT_1_AMB, "R200_VS_MAT_1_AMB" },
 527    { R200_VS_MAT_1_DIF, "R200_VS_MAT_1_DIF" },
 528    { R200_VS_MAT_1_SPEC, "R200_VS_MAT_1_SPEC" },
 529    { R200_VS_EYE2CLIP_MTX, "R200_VS_EYE2CLIP_MTX" },
 530    { R200_VS_PNT_SPRITE_ATT_CONST, "R200_VS_PNT_SPRITE_ATT_CONST" },
 531    { R200_VS_PNT_SPRITE_EYE_IN_MODEL, "R200_VS_PNT_SPRITE_EYE_IN_MODEL" },
 532    { R200_VS_PNT_SPRITE_CLAMP, "R200_VS_PNT_SPRITE_CLAMP" },
 533    { R200_VS_MAX, "R200_VS_MAX" },
 534    { 1000, "" },
 535 };
 536
 537 union fi { float f; int i; };
 538
 539 #define ISVEC   1
 540 #define ISFLOAT 2
 541 #define TOUCHED 4
 542
 543 struct reg {
 544    int idx;
 545    struct reg_names *closest;
 546    int flags;
 547    union fi current;
 548    union fi *values;
 549    int nvalues;
 550    int nalloc;
 551    float vmin, vmax;
 552 };
 553
 554
 555 static struct reg regs[Elements(reg_names)+1];
 556 static struct reg scalars[512+1];
 557 static struct reg vectors[512*4+1];
 558
 559 static int total, total_changed, bufs;
 560
 561 static void init_regs( void )
 562 {
 563    struct reg_names *tmp;
 564    int i;
 565
 566    for (i = 0 ; i < Elements(regs) ; i++) {
 567       regs[i].idx = reg_names[i].idx;
 568       regs[i].closest = &reg_names[i];
 569       regs[i].flags = 0;
 570    }
 571
 572    for (i = 0, tmp = scalar_names ; i < Elements(scalars) ; i++) {
 573       if (tmp[1].idx == i) tmp++;
 574       scalars[i].idx = i;
 575       scalars[i].closest = tmp;
 576       scalars[i].flags = ISFLOAT;
 577    }
 578
 579    for (i = 0, tmp = vector_names ; i < Elements(vectors) ; i++) {
 580       if (tmp[1].idx*4 == i) tmp++;
 581       vectors[i].idx = i;
 582       vectors[i].closest = tmp;
 583       vectors[i].flags = ISFLOAT|ISVEC;
 584    }
 585
 586    regs[Elements(regs)-1].idx = -1;
 587    scalars[Elements(scalars)-1].idx = -1;
 588    vectors[Elements(vectors)-1].idx = -1;
 589 }
 590
 591 static int find_or_add_value( struct reg *reg, int val )
 592 {
 593    int j;
 594
 595    for ( j = 0 ; j < reg->nvalues ; j++)
 596       if ( val == reg->values[j].i )
 597          return 1;
 598
 599    if (j == reg->nalloc) {
 600       reg->nalloc += 5;
 601       reg->nalloc *= 2;
 602       reg->values = (union fi *) realloc( reg->values,
 603                                           reg->nalloc * sizeof(union fi) );
 604    }
 605
 606    reg->values[reg->nvalues++].i = val;
 607    return 0;
 608 }
 609
 610 static struct reg *lookup_reg( struct reg *tab, int reg )
 611 {
 612    int i;
 613
 614    for (i = 0 ; tab[i].idx != -1 ; i++) {
 615       if (tab[i].idx == reg)
 616          return &tab[i];
 617    }
 618
 619    fprintf(stderr, "*** unknown reg 0x%x\n", reg);
 620    return 0;
 621 }
 622
 623
 624 static const char *get_reg_name( struct reg *reg )
 625 {
 626    static char tmp[80];
 627
 628    if (reg->idx == reg->closest->idx)
 629       return reg->closest->name;
 630
 631
 632    if (reg->flags & ISVEC) {
 633       if (reg->idx/4 != reg->closest->idx)
 634          sprintf(tmp, "%s+%d[%d]",
 635                  reg->closest->name,
 636                  (reg->idx/4) - reg->closest->idx,
 637                  reg->idx%4);
 638       else
 639          sprintf(tmp, "%s[%d]", reg->closest->name, reg->idx%4);
 640    }
 641    else {
 642       if (reg->idx != reg->closest->idx)
 643          sprintf(tmp, "%s+%d", reg->closest->name, reg->idx - reg->closest->idx);
 644       else
 645          sprintf(tmp, "%s", reg->closest->name);
 646    }
 647
 648    return tmp;
 649 }
 650
 651 static int print_int_reg_assignment( struct reg *reg, int data )
 652 {
 653    int changed = (reg->current.i != data);
 654    int ever_seen = find_or_add_value( reg, data );
 655
 656    if (VERBOSE || (NORMAL && (changed || !ever_seen)))
 657        fprintf(stderr, "   %s <-- 0x%x", get_reg_name(reg), data);
 658
 659    if (NORMAL) {
 660       if (!ever_seen)
 661          fprintf(stderr, " *** BRAND NEW VALUE");
 662       else if (changed)
 663          fprintf(stderr, " *** CHANGED");
 664    }
 665
 666    reg->current.i = data;
 667
 668    if (VERBOSE || (NORMAL && (changed || !ever_seen)))
 669       fprintf(stderr, "\n");
 670
 671    return changed;
 672 }
 673
 674
 675 static int print_float_reg_assignment( struct reg *reg, float data )
 676 {
 677    int changed = (reg->current.f != data);
 678    int newmin = (data < reg->vmin);
 679    int newmax = (data > reg->vmax);
 680
 681    if (VERBOSE || (NORMAL && (newmin || newmax || changed)))
 682       fprintf(stderr, "   %s <-- %.3f", get_reg_name(reg), data);
 683
 684    if (NORMAL) {
 685       if (newmin) {
 686          fprintf(stderr, " *** NEW MIN (prev %.3f)", reg->vmin);
 687          reg->vmin = data;
 688       }
 689       else if (newmax) {
 690          fprintf(stderr, " *** NEW MAX (prev %.3f)", reg->vmax);
 691          reg->vmax = data;
 692       }
 693       else if (changed) {
 694          fprintf(stderr, " *** CHANGED");
 695       }
 696    }
 697
 698    reg->current.f = data;
 699
 700    if (VERBOSE || (NORMAL && (newmin || newmax || changed)))
 701       fprintf(stderr, "\n");
 702
 703    return changed;
 704 }
 705
 706 static int print_reg_assignment( struct reg *reg, int data )
 707 {
 708    reg->flags |= TOUCHED;
 709    if (reg->flags & ISFLOAT)
 710       return print_float_reg_assignment( reg, *(float *)&data );
 711    else
 712       return print_int_reg_assignment( reg, data );
 713 }
 714
 715 static void print_reg( struct reg *reg )
 716 {
 717    if (reg->flags & TOUCHED) {
 718       if (reg->flags & ISFLOAT) {
 719          fprintf(stderr, "   %s == %f\n", get_reg_name(reg), reg->current.f);
 720       } else {
 721          fprintf(stderr, "   %s == 0x%x\n", get_reg_name(reg), reg->current.i);
 722       }
 723    }
 724 }
 725
 726
 727 static void dump_state( void )
 728 {
 729    int i;
 730
 731    for (i = 0 ; i < Elements(regs) ; i++)
 732       print_reg( &regs[i] );
 733
 734    for (i = 0 ; i < Elements(scalars) ; i++)
 735       print_reg( &scalars[i] );
 736
 737    for (i = 0 ; i < Elements(vectors) ; i++)
 738       print_reg( &vectors[i] );
 739 }
 740
 741
 742
 743 static int radeon_emit_packets(
 744    drm_radeon_cmd_header_t header,
 745    drm_radeon_cmd_buffer_t *cmdbuf )
 746 {
 747    int id = (int)header.packet.packet_id;
 748    int sz = packet[id].len;
 749    int *data = (int *)cmdbuf->buf;
 750    int i;
 751
 752    if (sz * sizeof(int) > cmdbuf->bufsz) {
 753       fprintf(stderr, "Packet overflows cmdbuf\n");
 754       return -EINVAL;
 755    }
 756
 757    if (!packet[id].name) {
 758       fprintf(stderr, "*** Unknown packet 0 nr %d\n", id );
 759       return -EINVAL;
 760    }
 761
 762
 763    if (VERBOSE)
 764       fprintf(stderr, "Packet 0 reg %s nr %d\n", packet[id].name, sz );
 765
 766    for ( i = 0 ; i < sz ; i++) {
 767       struct reg *reg = lookup_reg( regs, packet[id].start + i*4 );
 768       if (print_reg_assignment( reg, data[i] ))
 769          total_changed++;
 770       total++;
 771    }
 772
 773    cmdbuf->buf += sz * sizeof(int);
 774    cmdbuf->bufsz -= sz * sizeof(int);
 775    return 0;
 776 }
 777
 778
 779 static int radeon_emit_scalars(
 780    drm_radeon_cmd_header_t header,
 781    drm_radeon_cmd_buffer_t *cmdbuf )
 782 {
 783    int sz = header.scalars.count;
 784    int *data = (int *)cmdbuf->buf;
 785    int start = header.scalars.offset;
 786    int stride = header.scalars.stride;
 787    int i;
 788
 789    if (VERBOSE)
 790       fprintf(stderr, "emit scalars, start %d stride %d nr %d (end %d)\n",
 791               start, stride, sz, start + stride * sz);
 792
 793
 794    for (i = 0 ; i < sz ; i++, start += stride) {
 795       struct reg *reg = lookup_reg( scalars, start );
 796       if (print_reg_assignment( reg, data[i] ))
 797          total_changed++;
 798       total++;
 799    }
 800
 801    cmdbuf->buf += sz * sizeof(int);
 802    cmdbuf->bufsz -= sz * sizeof(int);
 803    return 0;
 804 }
 805
 806
 807 static int radeon_emit_scalars2(
 808    drm_radeon_cmd_header_t header,
 809    drm_radeon_cmd_buffer_t *cmdbuf )
 810 {
 811    int sz = header.scalars.count;
 812    int *data = (int *)cmdbuf->buf;
 813    int start = header.scalars.offset + 0x100;
 814    int stride = header.scalars.stride;
 815    int i;
 816
 817    if (VERBOSE)
 818       fprintf(stderr, "emit scalars2, start %d stride %d nr %d (end %d)\n",
 819               start, stride, sz, start + stride * sz);
 820
 821    if (start + stride * sz > 258) {
 822       fprintf(stderr, "emit scalars OVERFLOW %d/%d/%d\n", start, stride, sz);
 823       return -1;
 824    }
 825
 826    for (i = 0 ; i < sz ; i++, start += stride) {
 827       struct reg *reg = lookup_reg( scalars, start );
 828       if (print_reg_assignment( reg, data[i] ))
 829          total_changed++;
 830       total++;
 831    }
 832
 833    cmdbuf->buf += sz * sizeof(int);
 834    cmdbuf->bufsz -= sz * sizeof(int);
 835    return 0;
 836 }
 837
 838 /* Check: inf/nan/extreme-size?
 839  * Check: table start, end, nr, etc.
 840  */
 841 static int radeon_emit_vectors(
 842    drm_radeon_cmd_header_t header,
 843    drm_radeon_cmd_buffer_t *cmdbuf )
 844 {
 845    int sz = header.vectors.count;
 846    int *data = (int *)cmdbuf->buf;
 847    int start = header.vectors.offset;
 848    int stride = header.vectors.stride;
 849    int i,j;
 850
 851    if (VERBOSE)
 852       fprintf(stderr, "emit vectors, start %d stride %d nr %d (end %d) (0x%x)\n",
 853               start, stride, sz, start + stride * sz, header.i);
 854
 855 /*    if (start + stride * (sz/4) > 128) { */
 856 /*       fprintf(stderr, "emit vectors OVERFLOW %d/%d/%d\n", start, stride, sz); */
 857 /*       return -1; */
 858 /*    } */
 859
 860    for (i = 0 ; i < sz ;  start += stride) {
 861       int changed = 0;
 862       for (j = 0 ; j < 4 ; i++,j++) {
 863          struct reg *reg = lookup_reg( vectors, start*4+j );
 864          if (print_reg_assignment( reg, data[i] ))
 865             changed = 1;
 866       }
 867       if (changed)
 868          total_changed += 4;
 869       total += 4;
 870    }
 871
 872
 873    cmdbuf->buf += sz * sizeof(int);
 874    cmdbuf->bufsz -= sz * sizeof(int);
 875    return 0;
 876 }
 877
 878 #if 0
 879 static int print_vertex_format( int vfmt )
 880 {
 881    if (NORMAL) {
 882       fprintf(stderr, "   %s(%x): %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
 883               "vertex format",
 884               vfmt,
 885               "xy,",
 886               (vfmt & R200_VTX_Z0) ? "z," : "",
 887               (vfmt & R200_VTX_W0) ? "w0," : "",
 888               (vfmt & R200_VTX_FPCOLOR) ? "fpcolor," : "",
 889               (vfmt & R200_VTX_FPALPHA) ? "fpalpha," : "",
 890               (vfmt & R200_VTX_PKCOLOR) ? "pkcolor," : "",
 891               (vfmt & R200_VTX_FPSPEC) ? "fpspec," : "",
 892               (vfmt & R200_VTX_FPFOG) ? "fpfog," : "",
 893               (vfmt & R200_VTX_PKSPEC) ? "pkspec," : "",
 894               (vfmt & R200_VTX_ST0) ? "st0," : "",
 895               (vfmt & R200_VTX_ST1) ? "st1," : "",
 896               (vfmt & R200_VTX_Q1) ? "q1," : "",
 897               (vfmt & R200_VTX_ST2) ? "st2," : "",
 898               (vfmt & R200_VTX_Q2) ? "q2," : "",
 899               (vfmt & R200_VTX_ST3) ? "st3," : "",
 900               (vfmt & R200_VTX_Q3) ? "q3," : "",
 901               (vfmt & R200_VTX_Q0) ? "q0," : "",
 902               (vfmt & R200_VTX_N0) ? "n0," : "",
 903               (vfmt & R200_VTX_XY1) ? "xy1," : "",
 904               (vfmt & R200_VTX_Z1) ? "z1," : "",
 905               (vfmt & R200_VTX_W1) ? "w1," : "",
 906               (vfmt & R200_VTX_N1) ? "n1," : "");
 907
 908
 909       if (!find_or_add_value( &others[V_VTXFMT], vfmt ))
 910          fprintf(stderr, " *** NEW VALUE");
 911
 912       fprintf(stderr, "\n");
 913    }
 914
 915    return 0;
 916 }
 917 #endif
 918
 919 static char *primname[0x10] = {
 920    "NONE",
 921    "POINTS",
 922    "LINES",
 923    "LINE_STRIP",
 924    "TRIANGLES",
 925    "TRIANGLE_FAN",
 926    "TRIANGLE_STRIP",
 927    "RECT_LIST",
 928    0,
 929    "3VRT_POINTS",
 930    "3VRT_LINES",
 931    "POINT_SPRITES",
 932    "LINE_LOOP",
 933    "QUADS",
 934    "QUAD_STRIP",
 935    "POLYGON",
 936 };
 937
 938 static int print_prim_and_flags( int prim )
 939 {
 940    int numverts;
 941
 942    if (NORMAL)
 943       fprintf(stderr, "   %s(%x): %s%s%s%s%s%s\n",
 944               "prim flags",
 945               prim,
 946               ((prim & 0x30) == R200_VF_PRIM_WALK_IND) ? "IND," : "",
 947               ((prim & 0x30) == R200_VF_PRIM_WALK_LIST) ? "LIST," : "",
 948               ((prim & 0x30) == R200_VF_PRIM_WALK_RING) ? "RING," : "",
 949               (prim & R200_VF_COLOR_ORDER_RGBA) ? "RGBA," : "BGRA, ",
 950               (prim & R200_VF_INDEX_SZ_4) ? "INDX-32," : "",
 951               (prim & R200_VF_TCL_OUTPUT_VTX_ENABLE) ? "TCL_OUT_VTX," : "");
 952
 953    numverts = prim>>16;
 954
 955    if (NORMAL)
 956       fprintf(stderr, "   prim: %s numverts %d\n", primname[prim&0xf], numverts);
 957
 958    switch (prim & 0xf) {
 959    case R200_VF_PRIM_NONE:
 960    case R200_VF_PRIM_POINTS:
 961       if (numverts < 1) {
 962          fprintf(stderr, "Bad nr verts for line %d\n", numverts);
 963          return -1;
 964       }
 965       break;
 966    case R200_VF_PRIM_LINES:
 967    case R200_VF_PRIM_POINT_SPRITES:
 968       if ((numverts & 1) || numverts == 0) {
 969          fprintf(stderr, "Bad nr verts for line %d\n", numverts);
 970          return -1;
 971       }
 972       break;
 973    case R200_VF_PRIM_LINE_STRIP:
 974    case R200_VF_PRIM_LINE_LOOP:
 975       if (numverts < 2) {
 976          fprintf(stderr, "Bad nr verts for line_strip %d\n", numverts);
 977          return -1;
 978       }
 979       break;
 980    case R200_VF_PRIM_TRIANGLES:
 981    case R200_VF_PRIM_3VRT_POINTS:
 982    case R200_VF_PRIM_3VRT_LINES:
 983    case R200_VF_PRIM_RECT_LIST:
 984       if (numverts % 3 || numverts == 0) {
 985          fprintf(stderr, "Bad nr verts for tri %d\n", numverts);
 986          return -1;
 987       }
 988       break;
 989    case R200_VF_PRIM_TRIANGLE_FAN:
 990    case R200_VF_PRIM_TRIANGLE_STRIP:
 991    case R200_VF_PRIM_POLYGON:
 992       if (numverts < 3) {
 993          fprintf(stderr, "Bad nr verts for strip/fan %d\n", numverts);
 994          return -1;
 995       }
 996       break;
 997    case R200_VF_PRIM_QUADS:
 998       if (numverts % 4 || numverts == 0) {
 999          fprintf(stderr, "Bad nr verts for quad %d\n", numverts);
1000          return -1;
1001       }
1002       break;
1003    case R200_VF_PRIM_QUAD_STRIP:
1004       if (numverts % 2 || numverts < 4) {
1005          fprintf(stderr, "Bad nr verts for quadstrip %d\n", numverts);
1006          return -1;
1007       }
1008       break;
1009    default:
1010       fprintf(stderr, "Bad primitive\n");
1011       return -1;
1012    }
1013    return 0;
1014 }
1015
1016 /* build in knowledge about each packet type
1017  */
1018 static int radeon_emit_packet3( drm_radeon_cmd_buffer_t *cmdbuf )
1019 {
1020    int cmdsz;
1021    int *cmd = (int *)cmdbuf->buf;
1022    int *tmp;
1023    int i, stride, size, start;
1024
1025    cmdsz = 2 + ((cmd[0] & RADEON_CP_PACKET_COUNT_MASK) >> 16);
1026
1027    if ((cmd[0] & RADEON_CP_PACKET_MASK) != RADEON_CP_PACKET3 ||
1028        cmdsz * 4 > cmdbuf->bufsz ||
1029        cmdsz > RADEON_CP_PACKET_MAX_DWORDS) {
1030       fprintf(stderr, "Bad packet\n");
1031       return -EINVAL;
1032    }
1033
1034    switch( cmd[0] & ~RADEON_CP_PACKET_COUNT_MASK ) {
1035    case R200_CP_CMD_NOP:
1036       if (NORMAL)
1037          fprintf(stderr, "PACKET3_NOP, %d dwords\n", cmdsz);
1038       break;
1039    case R200_CP_CMD_NEXT_CHAR:
1040       if (NORMAL)
1041          fprintf(stderr, "PACKET3_NEXT_CHAR, %d dwords\n", cmdsz);
1042       break;
1043    case R200_CP_CMD_PLY_NEXTSCAN:
1044       if (NORMAL)
1045          fprintf(stderr, "PACKET3_PLY_NEXTSCAN, %d dwords\n", cmdsz);
1046       break;
1047    case R200_CP_CMD_SET_SCISSORS:
1048       if (NORMAL)
1049          fprintf(stderr, "PACKET3_SET_SCISSORS, %d dwords\n", cmdsz);
1050       break;
1051    case R200_CP_CMD_LOAD_MICROCODE:
1052       if (NORMAL)
1053          fprintf(stderr, "PACKET3_LOAD_MICROCODE, %d dwords\n", cmdsz);
1054       break;
1055    case R200_CP_CMD_WAIT_FOR_IDLE:
1056       if (NORMAL)
1057          fprintf(stderr, "PACKET3_WAIT_FOR_IDLE, %d dwords\n", cmdsz);
1058       break;
1059
1060    case R200_CP_CMD_3D_DRAW_VBUF:
1061       if (NORMAL)
1062          fprintf(stderr, "PACKET3_3D_DRAW_VBUF, %d dwords\n", cmdsz);
1063 /*       print_vertex_format(cmd[1]); */
1064       if (print_prim_and_flags(cmd[2]))
1065          return -EINVAL;
1066       break;
1067
1068    case R200_CP_CMD_3D_DRAW_IMMD:
1069       if (NORMAL)
1070          fprintf(stderr, "PACKET3_3D_DRAW_IMMD, %d dwords\n", cmdsz);
1071       break;
1072    case R200_CP_CMD_3D_DRAW_INDX: {
1073       int neltdwords;
1074       if (NORMAL)
1075          fprintf(stderr, "PACKET3_3D_DRAW_INDX, %d dwords\n", cmdsz);
1076 /*       print_vertex_format(cmd[1]); */
1077       if (print_prim_and_flags(cmd[2]))
1078          return -EINVAL;
1079       neltdwords = cmd[2]>>16;
1080       neltdwords += neltdwords & 1;
1081       neltdwords /= 2;
1082       if (neltdwords + 3 != cmdsz)
1083          fprintf(stderr, "Mismatch in DRAW_INDX, %d vs cmdsz %d\n",
1084                  neltdwords, cmdsz);
1085       break;
1086    }
1087    case R200_CP_CMD_LOAD_PALETTE:
1088       if (NORMAL)
1089          fprintf(stderr, "PACKET3_LOAD_PALETTE, %d dwords\n", cmdsz);
1090       break;
1091    case R200_CP_CMD_3D_LOAD_VBPNTR:
1092       if (NORMAL) {
1093          fprintf(stderr, "PACKET3_3D_LOAD_VBPNTR, %d dwords\n", cmdsz);
1094          fprintf(stderr, "   nr arrays: %d\n", cmd[1]);
1095       }
1096
1097       if (((cmd[1]/2)*3) + ((cmd[1]%2)*2) != cmdsz - 2) {
1098          fprintf(stderr, "  ****** MISMATCH %d/%d *******\n",
1099                  ((cmd[1]/2)*3) + ((cmd[1]%2)*2) + 2, cmdsz);
1100          return -EINVAL;
1101       }
1102
1103       if (NORMAL) {
1104          tmp = cmd+2;
1105          for (i = 0 ; i < cmd[1] ; i++) {
1106             if (i & 1) {
1107                stride = (tmp[0]>>24) & 0xff;
1108                size = (tmp[0]>>16) & 0xff;
1109                start = tmp[2];
1110                tmp += 3;
1111             }
1112             else {
1113                stride = (tmp[0]>>8) & 0xff;
1114                size = (tmp[0]) & 0xff;
1115                start = tmp[1];
1116             }
1117             fprintf(stderr, "   array %d: start 0x%x vsize %d vstride %d\n",
1118                     i, start, size, stride );
1119          }
1120       }
1121       break;
1122    case R200_CP_CMD_PAINT:
1123       if (NORMAL)
1124          fprintf(stderr, "PACKET3_CNTL_PAINT, %d dwords\n", cmdsz);
1125       break;
1126    case R200_CP_CMD_BITBLT:
1127       if (NORMAL)
1128          fprintf(stderr, "PACKET3_CNTL_BITBLT, %d dwords\n", cmdsz);
1129       break;
1130    case R200_CP_CMD_SMALLTEXT:
1131       if (NORMAL)
1132          fprintf(stderr, "PACKET3_CNTL_SMALLTEXT, %d dwords\n", cmdsz);
1133       break;
1134    case R200_CP_CMD_HOSTDATA_BLT:
1135       if (NORMAL)
1136          fprintf(stderr, "PACKET3_CNTL_HOSTDATA_BLT, %d dwords\n",
1137               cmdsz);
1138       break;
1139    case R200_CP_CMD_POLYLINE:
1140       if (NORMAL)
1141          fprintf(stderr, "PACKET3_CNTL_POLYLINE, %d dwords\n", cmdsz);
1142       break;
1143    case R200_CP_CMD_POLYSCANLINES:
1144       if (NORMAL)
1145          fprintf(stderr, "PACKET3_CNTL_POLYSCANLINES, %d dwords\n",
1146               cmdsz);
1147       break;
1148    case R200_CP_CMD_PAINT_MULTI:
1149       if (NORMAL)
1150          fprintf(stderr, "PACKET3_CNTL_PAINT_MULTI, %d dwords\n",
1151               cmdsz);
1152       break;
1153    case R200_CP_CMD_BITBLT_MULTI:
1154       if (NORMAL)
1155          fprintf(stderr, "PACKET3_CNTL_BITBLT_MULTI, %d dwords\n",
1156               cmdsz);
1157       break;
1158    case R200_CP_CMD_TRANS_BITBLT:
1159       if (NORMAL)
1160          fprintf(stderr, "PACKET3_CNTL_TRANS_BITBLT, %d dwords\n",
1161               cmdsz);
1162       break;
1163    case R200_CP_CMD_3D_DRAW_VBUF_2:
1164       if (NORMAL)
1165          fprintf(stderr, "R200_CP_CMD_3D_DRAW_VBUF_2, %d dwords\n",
1166               cmdsz);
1167       if (print_prim_and_flags(cmd[1]))
1168          return -EINVAL;
1169       break;
1170    case R200_CP_CMD_3D_DRAW_IMMD_2:
1171       if (NORMAL)
1172          fprintf(stderr, "R200_CP_CMD_3D_DRAW_IMMD_2, %d dwords\n",
1173               cmdsz);
1174       if (print_prim_and_flags(cmd[1]))
1175          return -EINVAL;
1176       break;
1177    case R200_CP_CMD_3D_DRAW_INDX_2:
1178       if (NORMAL)
1179          fprintf(stderr, "R200_CP_CMD_3D_DRAW_INDX_2, %d dwords\n",
1180               cmdsz);
1181       if (print_prim_and_flags(cmd[1]))
1182          return -EINVAL;
1183       break;
1184    default:
1185       fprintf(stderr, "UNKNOWN PACKET, %d dwords\n", cmdsz);
1186       break;
1187    }
1188
1189    cmdbuf->buf += cmdsz * 4;
1190    cmdbuf->bufsz -= cmdsz * 4;
1191    return 0;
1192 }
1193
1194
1195 /* Check cliprects for bounds, then pass on to above:
1196  */
1197 static int radeon_emit_packet3_cliprect( drm_radeon_cmd_buffer_t *cmdbuf )
1198 {
1199    drm_clip_rect_t *boxes = (drm_clip_rect_t *)cmdbuf->boxes;
1200    int i = 0;
1201
1202    if (VERBOSE && total_changed) {
1203       dump_state();
1204       total_changed = 0;
1205    }
1206
1207    if (NORMAL) {
1208       do {
1209          if ( i < cmdbuf->nbox ) {
1210             fprintf(stderr, "Emit box %d/%d %d,%d %d,%d\n",
1211                     i, cmdbuf->nbox,
1212                     boxes[i].x1, boxes[i].y1, boxes[i].x2, boxes[i].y2);
1213          }
1214       } while ( ++i < cmdbuf->nbox );
1215    }
1216
1217    if (cmdbuf->nbox == 1)
1218       cmdbuf->nbox = 0;
1219
1220    return radeon_emit_packet3( cmdbuf );
1221 }
1222
1223
1224 int r200SanityCmdBuffer( r200ContextPtr rmesa,
1225                            int nbox,
1226                            drm_clip_rect_t *boxes )
1227 {
1228    int idx;
1229    drm_radeon_cmd_buffer_t cmdbuf;
1230    drm_radeon_cmd_header_t header;
1231    static int inited = 0;
1232
1233    if (!inited) {
1234       init_regs();
1235       inited = 1;
1236    }
1237
1238
1239    cmdbuf.buf = rmesa->store.cmd_buf;
1240    cmdbuf.bufsz = rmesa->store.cmd_used;
1241    cmdbuf.boxes = (drm_clip_rect_t *)boxes;
1242    cmdbuf.nbox = nbox;
1243
1244    while ( cmdbuf.bufsz >= sizeof(header) ) {
1245
1246       header.i = *(int *)cmdbuf.buf;
1247       cmdbuf.buf += sizeof(header);
1248       cmdbuf.bufsz -= sizeof(header);
1249
1250       switch (header.header.cmd_type) {
1251       case RADEON_CMD_PACKET:
1252          if (radeon_emit_packets( header, &cmdbuf )) {
1253             fprintf(stderr,"radeon_emit_packets failed\n");
1254             return -EINVAL;
1255          }
1256          break;
1257
1258       case RADEON_CMD_SCALARS:
1259          if (radeon_emit_scalars( header, &cmdbuf )) {
1260             fprintf(stderr,"radeon_emit_scalars failed\n");
1261             return -EINVAL;
1262          }
1263          break;
1264
1265       case RADEON_CMD_SCALARS2:
1266          if (radeon_emit_scalars2( header, &cmdbuf )) {
1267             fprintf(stderr,"radeon_emit_scalars failed\n");
1268             return -EINVAL;
1269          }
1270          break;
1271
1272       case RADEON_CMD_VECTORS:
1273          if (radeon_emit_vectors( header, &cmdbuf )) {
1274             fprintf(stderr,"radeon_emit_vectors failed\n");
1275             return -EINVAL;
1276          }
1277          break;
1278
1279       case RADEON_CMD_DMA_DISCARD:
1280          idx = header.dma.buf_idx;
1281          if (NORMAL)
1282             fprintf(stderr, "RADEON_CMD_DMA_DISCARD buf %d\n", idx);
1283          bufs++;
1284          break;
1285
1286       case RADEON_CMD_PACKET3:
1287          if (radeon_emit_packet3( &cmdbuf )) {
1288             fprintf(stderr,"radeon_emit_packet3 failed\n");
1289             return -EINVAL;
1290          }
1291          break;
1292
1293       case RADEON_CMD_PACKET3_CLIP:
1294          if (radeon_emit_packet3_cliprect( &cmdbuf )) {
1295             fprintf(stderr,"radeon_emit_packet3_clip failed\n");
1296             return -EINVAL;
1297          }
1298          break;
1299
1300       case RADEON_CMD_WAIT:
1301          break;
1302
1303       default:
1304          fprintf(stderr,"bad cmd_type %d at %p\n",
1305                    header.header.cmd_type,
1306                    cmdbuf.buf - sizeof(header));
1307          return -EINVAL;
1308       }
1309    }
1310
1311    if (0)
1312    {
1313       static int n = 0;
1314       n++;
1315       if (n == 10) {
1316          fprintf(stderr, "Bufs %d Total emitted %d real changes %d (%.2f%%)\n",
1317                  bufs,
1318                  total, total_changed,
1319                  ((float)total_changed/(float)total*100.0));
1320          fprintf(stderr, "Total emitted per buf: %.2f\n",
1321                  (float)total/(float)bufs);
1322          fprintf(stderr, "Real changes per buf: %.2f\n",
1323                  (float)total_changed/(float)bufs);
1324
1325          bufs = n = total = total_changed = 0;
1326       }
1327    }
1328
1329    fprintf(stderr, "leaving %s\n\n\n", __FUNCTION__);
1330
1331    return 0;
1332 }