src/mesa/drivers/dri/r200/r200_sanity.c

   1 /**************************************************************************
   2
   3 Copyright 2002 ATI Technologies Inc., Ontario, Canada, and
   4                      VMware, Inc.
   5
   6 All Rights Reserved.
   7
   8 Permission is hereby granted, free of charge, to any person obtaining a
   9 copy of this software and associated documentation files (the "Software"),
  10 to deal in the Software without restriction, including without limitation
  11 on the rights to use, copy, modify, merge, publish, distribute, sub
  12 license, and/or sell copies of the Software, and to permit persons to whom
  13 the Software is furnished to do so, subject to the following conditions:
  14
  15 The above copyright notice and this permission notice (including the next
  16 paragraph) shall be included in all copies or substantial portions of the
  17 Software.
  18
  19 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21 FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  22 ATI, VMWARE AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  23 DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  24 OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  25 USE OR OTHER DEALINGS IN THE SOFTWARE.
  26
  27 **************************************************************************/
  28
  29 /*
  30  * Authors:
  31  *   Keith Whitwell <keithw@vmware.com>
  32  *
  33  */
  34
  35 #include <errno.h>
  36
  37 #include "main/glheader.h"
  38 #include "main/imports.h"
  39
  40 #include "r200_context.h"
  41 #include "r200_sanity.h"
  42 #include "radeon_reg.h"
  43 #include "r200_reg.h"
  44
  45 /* Set this '1' to get more verbiage.
  46  */
  47 #define MORE_VERBOSE 1
  48
  49 #if MORE_VERBOSE
  50 #define VERBOSE (R200_DEBUG & RADEON_VERBOSE)
  51 #define NORMAL  (1)
  52 #else
  53 #define VERBOSE 0
  54 #define NORMAL  (R200_DEBUG & RADEON_VERBOSE)
  55 #endif
  56
  57
  58 /* New (1.3) state mechanism.  3 commands (packet, scalar, vector) in
  59  * 1.3 cmdbuffers allow all previous state to be updated as well as
  60  * the tcl scalar and vector areas.
  61  */
  62 static struct {
  63    int start;
  64    int len;
  65    const char *name;
  66 } packet[RADEON_MAX_STATE_PACKETS] = {
  67    { RADEON_PP_MISC,7,"RADEON_PP_MISC" },
  68    { RADEON_PP_CNTL,3,"RADEON_PP_CNTL" },
  69    { RADEON_RB3D_COLORPITCH,1,"RADEON_RB3D_COLORPITCH" },
  70    { RADEON_RE_LINE_PATTERN,2,"RADEON_RE_LINE_PATTERN" },
  71    { RADEON_SE_LINE_WIDTH,1,"RADEON_SE_LINE_WIDTH" },
  72    { RADEON_PP_LUM_MATRIX,1,"RADEON_PP_LUM_MATRIX" },
  73    { RADEON_PP_ROT_MATRIX_0,2,"RADEON_PP_ROT_MATRIX_0" },
  74    { RADEON_RB3D_STENCILREFMASK,3,"RADEON_RB3D_STENCILREFMASK" },
  75    { RADEON_SE_VPORT_XSCALE,6,"RADEON_SE_VPORT_XSCALE" },
  76    { RADEON_SE_CNTL,2,"RADEON_SE_CNTL" },
  77    { RADEON_SE_CNTL_STATUS,1,"RADEON_SE_CNTL_STATUS" },
  78    { RADEON_RE_MISC,1,"RADEON_RE_MISC" },
  79    { RADEON_PP_TXFILTER_0,6,"RADEON_PP_TXFILTER_0" },
  80    { RADEON_PP_BORDER_COLOR_0,1,"RADEON_PP_BORDER_COLOR_0" },
  81    { RADEON_PP_TXFILTER_1,6,"RADEON_PP_TXFILTER_1" },
  82    { RADEON_PP_BORDER_COLOR_1,1,"RADEON_PP_BORDER_COLOR_1" },
  83    { RADEON_PP_TXFILTER_2,6,"RADEON_PP_TXFILTER_2" },
  84    { RADEON_PP_BORDER_COLOR_2,1,"RADEON_PP_BORDER_COLOR_2" },
  85    { RADEON_SE_ZBIAS_FACTOR,2,"RADEON_SE_ZBIAS_FACTOR" },
  86    { RADEON_SE_TCL_OUTPUT_VTX_FMT,11,"RADEON_SE_TCL_OUTPUT_VTX_FMT" },
  87    { RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED,17,"RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED" },
  88    { R200_PP_TXCBLEND_0, 4, "R200_EMIT_PP_TXCBLEND_0" },
  89    { R200_PP_TXCBLEND_1, 4, "R200_PP_TXCBLEND_1" },
  90    { R200_PP_TXCBLEND_2, 4, "R200_PP_TXCBLEND_2" },
  91    { R200_PP_TXCBLEND_3, 4, "R200_PP_TXCBLEND_3" },
  92    { R200_PP_TXCBLEND_4, 4, "R200_PP_TXCBLEND_4" },
  93    { R200_PP_TXCBLEND_5, 4, "R200_PP_TXCBLEND_5" },
  94    { R200_PP_TXCBLEND_6, 4, "R200_PP_TXCBLEND_6" },
  95    { R200_PP_TXCBLEND_7, 4, "R200_PP_TXCBLEND_7" },
  96    { R200_SE_TCL_LIGHT_MODEL_CTL_0, 6, "R200_SE_TCL_LIGHT_MODEL_CTL_0" },
  97    { R200_PP_TFACTOR_0, 6, "R200_PP_TFACTOR_0" },
  98    { R200_SE_VTX_FMT_0, 4, "R200_SE_VTX_FMT_0" },
  99    { R200_SE_VAP_CNTL, 1, "R200_SE_VAP_CNTL" },
 100    { R200_SE_TCL_MATRIX_SEL_0, 5, "R200_SE_TCL_MATRIX_SEL_0" },
 101    { R200_SE_TCL_TEX_PROC_CTL_2, 5, "R200_SE_TCL_TEX_PROC_CTL_2" },
 102    { R200_SE_TCL_UCP_VERT_BLEND_CTL, 1, "R200_SE_TCL_UCP_VERT_BLEND_CTL" },
 103    { R200_PP_TXFILTER_0, 6, "R200_PP_TXFILTER_0" },
 104    { R200_PP_TXFILTER_1, 6, "R200_PP_TXFILTER_1" },
 105    { R200_PP_TXFILTER_2, 6, "R200_PP_TXFILTER_2" },
 106    { R200_PP_TXFILTER_3, 6, "R200_PP_TXFILTER_3" },
 107    { R200_PP_TXFILTER_4, 6, "R200_PP_TXFILTER_4" },
 108    { R200_PP_TXFILTER_5, 6, "R200_PP_TXFILTER_5" },
 109    { R200_PP_TXOFFSET_0, 1, "R200_PP_TXOFFSET_0" },
 110    { R200_PP_TXOFFSET_1, 1, "R200_PP_TXOFFSET_1" },
 111    { R200_PP_TXOFFSET_2, 1, "R200_PP_TXOFFSET_2" },
 112    { R200_PP_TXOFFSET_3, 1, "R200_PP_TXOFFSET_3" },
 113    { R200_PP_TXOFFSET_4, 1, "R200_PP_TXOFFSET_4" },
 114    { R200_PP_TXOFFSET_5, 1, "R200_PP_TXOFFSET_5" },
 115    { R200_SE_VTE_CNTL, 1, "R200_SE_VTE_CNTL" },
 116    { R200_SE_TCL_OUTPUT_VTX_COMP_SEL, 1, "R200_SE_TCL_OUTPUT_VTX_COMP_SEL" },
 117    { R200_PP_TAM_DEBUG3, 1, "R200_PP_TAM_DEBUG3" },
 118    { R200_PP_CNTL_X, 1, "R200_PP_CNTL_X" },
 119    { R200_RB3D_DEPTHXY_OFFSET, 1, "R200_RB3D_DEPTHXY_OFFSET" },
 120    { R200_RE_AUX_SCISSOR_CNTL, 1, "R200_RE_AUX_SCISSOR_CNTL" },
 121    { R200_RE_SCISSOR_TL_0, 2, "R200_RE_SCISSOR_TL_0" },
 122    { R200_RE_SCISSOR_TL_1, 2, "R200_RE_SCISSOR_TL_1" },
 123    { R200_RE_SCISSOR_TL_2, 2, "R200_RE_SCISSOR_TL_2" },
 124    { R200_SE_VAP_CNTL_STATUS, 1, "R200_SE_VAP_CNTL_STATUS" },
 125    { R200_SE_VTX_STATE_CNTL, 1, "R200_SE_VTX_STATE_CNTL" },
 126    { R200_RE_POINTSIZE, 1, "R200_RE_POINTSIZE" },
 127    { R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0, 4, "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0" },
 128    { R200_PP_CUBIC_FACES_0, 1, "R200_PP_CUBIC_FACES_0" }, /* 61 */
 129    { R200_PP_CUBIC_OFFSET_F1_0, 5, "R200_PP_CUBIC_OFFSET_F1_0" }, /* 62 */
 130    { R200_PP_CUBIC_FACES_1, 1, "R200_PP_CUBIC_FACES_1" },
 131    { R200_PP_CUBIC_OFFSET_F1_1, 5, "R200_PP_CUBIC_OFFSET_F1_1" },
 132    { R200_PP_CUBIC_FACES_2, 1, "R200_PP_CUBIC_FACES_2" },
 133    { R200_PP_CUBIC_OFFSET_F1_2, 5, "R200_PP_CUBIC_OFFSET_F1_2" },
 134    { R200_PP_CUBIC_FACES_3, 1, "R200_PP_CUBIC_FACES_3" },
 135    { R200_PP_CUBIC_OFFSET_F1_3, 5, "R200_PP_CUBIC_OFFSET_F1_3" },
 136    { R200_PP_CUBIC_FACES_4, 1, "R200_PP_CUBIC_FACES_4" },
 137    { R200_PP_CUBIC_OFFSET_F1_4, 5, "R200_PP_CUBIC_OFFSET_F1_4" },
 138    { R200_PP_CUBIC_FACES_5, 1, "R200_PP_CUBIC_FACES_5" },
 139    { R200_PP_CUBIC_OFFSET_F1_5, 5, "R200_PP_CUBIC_OFFSET_F1_5" },
 140    { RADEON_PP_TEX_SIZE_0, 2, "RADEON_PP_TEX_SIZE_0" },
 141    { RADEON_PP_TEX_SIZE_1, 2, "RADEON_PP_TEX_SIZE_1" },
 142    { RADEON_PP_TEX_SIZE_2, 2, "RADEON_PP_TEX_SIZE_2" },
 143    { R200_RB3D_BLENDCOLOR, 3, "R200_RB3D_BLENDCOLOR" },
 144    { R200_SE_TCL_POINT_SPRITE_CNTL, 1, "R200_SE_TCL_POINT_SPRITE_CNTL" },
 145    { RADEON_PP_CUBIC_FACES_0, 1, "RADEON_PP_CUBIC_FACES_0" },
 146    { RADEON_PP_CUBIC_OFFSET_T0_0, 5, "RADEON_PP_CUBIC_OFFSET_T0_0" },
 147    { RADEON_PP_CUBIC_FACES_1, 1, "RADEON_PP_CUBIC_FACES_1" },
 148    { RADEON_PP_CUBIC_OFFSET_T1_0, 5, "RADEON_PP_CUBIC_OFFSET_T1_0" },
 149    { RADEON_PP_CUBIC_FACES_2, 1, "RADEON_PP_CUBIC_FACES_2" },
 150    { RADEON_PP_CUBIC_OFFSET_T2_0, 5, "RADEON_PP_CUBIC_OFFSET_T2_0" },
 151    { R200_PP_TRI_PERF, 2, "R200_PP_TRI_PERF" },
 152    { R200_PP_TXCBLEND_8, 32, "R200_PP_AFS_0"},   /* 85 */
 153    { R200_PP_TXCBLEND_0, 32, "R200_PP_AFS_1"},
 154    { R200_PP_TFACTOR_0, 8, "R200_ATF_TFACTOR"},
 155    { R200_PP_TXFILTER_0, 8, "R200_PP_TXCTLALL_0"},
 156    { R200_PP_TXFILTER_1, 8, "R200_PP_TXCTLALL_1"},
 157    { R200_PP_TXFILTER_2, 8, "R200_PP_TXCTLALL_2"},
 158    { R200_PP_TXFILTER_3, 8, "R200_PP_TXCTLALL_3"},
 159    { R200_PP_TXFILTER_4, 8, "R200_PP_TXCTLALL_4"},
 160    { R200_PP_TXFILTER_5, 8, "R200_PP_TXCTLALL_5"},
 161    { R200_VAP_PVS_CNTL_1, 2, "R200_VAP_PVS_CNTL"},
 162 };
 163
 164 struct reg_names {
 165    int idx;
 166    const char *name;
 167 };
 168
 169 static struct reg_names reg_names[] = {
 170    { R200_PP_MISC, "R200_PP_MISC" },
 171    { R200_PP_FOG_COLOR, "R200_PP_FOG_COLOR" },
 172    { R200_RE_SOLID_COLOR, "R200_RE_SOLID_COLOR" },
 173    { R200_RB3D_BLENDCNTL, "R200_RB3D_BLENDCNTL" },
 174    { R200_RB3D_DEPTHOFFSET, "R200_RB3D_DEPTHOFFSET" },
 175    { R200_RB3D_DEPTHPITCH, "R200_RB3D_DEPTHPITCH" },
 176    { R200_RB3D_ZSTENCILCNTL, "R200_RB3D_ZSTENCILCNTL" },
 177    { R200_PP_CNTL, "R200_PP_CNTL" },
 178    { R200_RB3D_CNTL, "R200_RB3D_CNTL" },
 179    { R200_RB3D_COLOROFFSET, "R200_RB3D_COLOROFFSET" },
 180    { R200_RE_WIDTH_HEIGHT, "R200_RE_WIDTH_HEIGHT" },
 181    { R200_RB3D_COLORPITCH, "R200_RB3D_COLORPITCH" },
 182    { R200_SE_CNTL, "R200_SE_CNTL" },
 183    { R200_RE_CNTL, "R200_RE_CNTL" },
 184    { R200_RE_MISC, "R200_RE_MISC" },
 185    { R200_RE_STIPPLE_ADDR, "R200_RE_STIPPLE_ADDR" },
 186    { R200_RE_STIPPLE_DATA, "R200_RE_STIPPLE_DATA" },
 187    { R200_RE_LINE_PATTERN, "R200_RE_LINE_PATTERN" },
 188    { R200_RE_LINE_STATE, "R200_RE_LINE_STATE" },
 189    { R200_RE_SCISSOR_TL_0, "R200_RE_SCISSOR_TL_0" },
 190    { R200_RE_SCISSOR_BR_0, "R200_RE_SCISSOR_BR_0" },
 191    { R200_RE_SCISSOR_TL_1, "R200_RE_SCISSOR_TL_1" },
 192    { R200_RE_SCISSOR_BR_1, "R200_RE_SCISSOR_BR_1" },
 193    { R200_RE_SCISSOR_TL_2, "R200_RE_SCISSOR_TL_2" },
 194    { R200_RE_SCISSOR_BR_2, "R200_RE_SCISSOR_BR_2" },
 195    { R200_RB3D_DEPTHXY_OFFSET, "R200_RB3D_DEPTHXY_OFFSET" },
 196    { R200_RB3D_STENCILREFMASK, "R200_RB3D_STENCILREFMASK" },
 197    { R200_RB3D_ROPCNTL, "R200_RB3D_ROPCNTL" },
 198    { R200_RB3D_PLANEMASK, "R200_RB3D_PLANEMASK" },
 199    { R200_SE_VPORT_XSCALE, "R200_SE_VPORT_XSCALE" },
 200    { R200_SE_VPORT_XOFFSET, "R200_SE_VPORT_XOFFSET" },
 201    { R200_SE_VPORT_YSCALE, "R200_SE_VPORT_YSCALE" },
 202    { R200_SE_VPORT_YOFFSET, "R200_SE_VPORT_YOFFSET" },
 203    { R200_SE_VPORT_ZSCALE, "R200_SE_VPORT_ZSCALE" },
 204    { R200_SE_VPORT_ZOFFSET, "R200_SE_VPORT_ZOFFSET" },
 205    { R200_SE_ZBIAS_FACTOR, "R200_SE_ZBIAS_FACTOR" },
 206    { R200_SE_ZBIAS_CONSTANT, "R200_SE_ZBIAS_CONSTANT" },
 207    { R200_SE_LINE_WIDTH, "R200_SE_LINE_WIDTH" },
 208    { R200_SE_VAP_CNTL, "R200_SE_VAP_CNTL" },
 209    { R200_SE_VF_CNTL, "R200_SE_VF_CNTL" },
 210    { R200_SE_VTX_FMT_0, "R200_SE_VTX_FMT_0" },
 211    { R200_SE_VTX_FMT_1, "R200_SE_VTX_FMT_1" },
 212    { R200_SE_TCL_OUTPUT_VTX_FMT_0, "R200_SE_TCL_OUTPUT_VTX_FMT_0" },
 213    { R200_SE_TCL_OUTPUT_VTX_FMT_1, "R200_SE_TCL_OUTPUT_VTX_FMT_1" },
 214    { R200_SE_VTE_CNTL, "R200_SE_VTE_CNTL" },
 215    { R200_SE_VTX_NUM_ARRAYS, "R200_SE_VTX_NUM_ARRAYS" },
 216    { R200_SE_VTX_AOS_ATTR01, "R200_SE_VTX_AOS_ATTR01" },
 217    { R200_SE_VTX_AOS_ADDR0, "R200_SE_VTX_AOS_ADDR0" },
 218    { R200_SE_VTX_AOS_ADDR1, "R200_SE_VTX_AOS_ADDR1" },
 219    { R200_SE_VTX_AOS_ATTR23, "R200_SE_VTX_AOS_ATTR23" },
 220    { R200_SE_VTX_AOS_ADDR2, "R200_SE_VTX_AOS_ADDR2" },
 221    { R200_SE_VTX_AOS_ADDR3, "R200_SE_VTX_AOS_ADDR3" },
 222    { R200_SE_VTX_AOS_ATTR45, "R200_SE_VTX_AOS_ATTR45" },
 223    { R200_SE_VTX_AOS_ADDR4, "R200_SE_VTX_AOS_ADDR4" },
 224    { R200_SE_VTX_AOS_ADDR5, "R200_SE_VTX_AOS_ADDR5" },
 225    { R200_SE_VTX_AOS_ATTR67, "R200_SE_VTX_AOS_ATTR67" },
 226    { R200_SE_VTX_AOS_ADDR6, "R200_SE_VTX_AOS_ADDR6" },
 227    { R200_SE_VTX_AOS_ADDR7, "R200_SE_VTX_AOS_ADDR7" },
 228    { R200_SE_VTX_AOS_ATTR89, "R200_SE_VTX_AOS_ATTR89" },
 229    { R200_SE_VTX_AOS_ADDR8, "R200_SE_VTX_AOS_ADDR8" },
 230    { R200_SE_VTX_AOS_ADDR9, "R200_SE_VTX_AOS_ADDR9" },
 231    { R200_SE_VTX_AOS_ATTR1011, "R200_SE_VTX_AOS_ATTR1011" },
 232    { R200_SE_VTX_AOS_ADDR10, "R200_SE_VTX_AOS_ADDR10" },
 233    { R200_SE_VTX_AOS_ADDR11, "R200_SE_VTX_AOS_ADDR11" },
 234    { R200_SE_VF_MAX_VTX_INDX, "R200_SE_VF_MAX_VTX_INDX" },
 235    { R200_SE_VF_MIN_VTX_INDX, "R200_SE_VF_MIN_VTX_INDX" },
 236    { R200_SE_VTX_STATE_CNTL, "R200_SE_VTX_STATE_CNTL" },
 237    { R200_SE_TCL_VECTOR_INDX_REG, "R200_SE_TCL_VECTOR_INDX_REG" },
 238    { R200_SE_TCL_VECTOR_DATA_REG, "R200_SE_TCL_VECTOR_DATA_REG" },
 239    { R200_SE_TCL_SCALAR_INDX_REG, "R200_SE_TCL_SCALAR_INDX_REG" },
 240    { R200_SE_TCL_SCALAR_DATA_REG, "R200_SE_TCL_SCALAR_DATA_REG" },
 241    { R200_SE_TCL_MATRIX_SEL_0, "R200_SE_TCL_MATRIX_SEL_0" },
 242    { R200_SE_TCL_MATRIX_SEL_1, "R200_SE_TCL_MATRIX_SEL_1" },
 243    { R200_SE_TCL_MATRIX_SEL_2, "R200_SE_TCL_MATRIX_SEL_2" },
 244    { R200_SE_TCL_MATRIX_SEL_3, "R200_SE_TCL_MATRIX_SEL_3" },
 245    { R200_SE_TCL_MATRIX_SEL_4, "R200_SE_TCL_MATRIX_SEL_4" },
 246    { R200_SE_TCL_LIGHT_MODEL_CTL_0, "R200_SE_TCL_LIGHT_MODEL_CTL_0" },
 247    { R200_SE_TCL_LIGHT_MODEL_CTL_1, "R200_SE_TCL_LIGHT_MODEL_CTL_1" },
 248    { R200_SE_TCL_PER_LIGHT_CTL_0, "R200_SE_TCL_PER_LIGHT_CTL_0" },
 249    { R200_SE_TCL_PER_LIGHT_CTL_1, "R200_SE_TCL_PER_LIGHT_CTL_1" },
 250    { R200_SE_TCL_PER_LIGHT_CTL_2, "R200_SE_TCL_PER_LIGHT_CTL_2" },
 251    { R200_SE_TCL_PER_LIGHT_CTL_3, "R200_SE_TCL_PER_LIGHT_CTL_3" },
 252    { R200_SE_TCL_TEX_PROC_CTL_2, "R200_SE_TCL_TEX_PROC_CTL_2" },
 253    { R200_SE_TCL_TEX_PROC_CTL_3, "R200_SE_TCL_TEX_PROC_CTL_3" },
 254    { R200_SE_TCL_TEX_PROC_CTL_0, "R200_SE_TCL_TEX_PROC_CTL_0" },
 255    { R200_SE_TCL_TEX_PROC_CTL_1, "R200_SE_TCL_TEX_PROC_CTL_1" },
 256    { R200_SE_TC_TEX_CYL_WRAP_CTL, "R200_SE_TC_TEX_CYL_WRAP_CTL" },
 257    { R200_SE_TCL_UCP_VERT_BLEND_CTL, "R200_SE_TCL_UCP_VERT_BLEND_CTL" },
 258    { R200_SE_TCL_POINT_SPRITE_CNTL, "R200_SE_TCL_POINT_SPRITE_CNTL" },
 259    { R200_SE_VTX_ST_POS_0_X_4, "R200_SE_VTX_ST_POS_0_X_4" },
 260    { R200_SE_VTX_ST_POS_0_Y_4, "R200_SE_VTX_ST_POS_0_Y_4" },
 261    { R200_SE_VTX_ST_POS_0_Z_4, "R200_SE_VTX_ST_POS_0_Z_4" },
 262    { R200_SE_VTX_ST_POS_0_W_4, "R200_SE_VTX_ST_POS_0_W_4" },
 263    { R200_SE_VTX_ST_NORM_0_X, "R200_SE_VTX_ST_NORM_0_X" },
 264    { R200_SE_VTX_ST_NORM_0_Y, "R200_SE_VTX_ST_NORM_0_Y" },
 265    { R200_SE_VTX_ST_NORM_0_Z, "R200_SE_VTX_ST_NORM_0_Z" },
 266    { R200_SE_VTX_ST_PVMS, "R200_SE_VTX_ST_PVMS" },
 267    { R200_SE_VTX_ST_CLR_0_R, "R200_SE_VTX_ST_CLR_0_R" },
 268    { R200_SE_VTX_ST_CLR_0_G, "R200_SE_VTX_ST_CLR_0_G" },
 269    { R200_SE_VTX_ST_CLR_0_B, "R200_SE_VTX_ST_CLR_0_B" },
 270    { R200_SE_VTX_ST_CLR_0_A, "R200_SE_VTX_ST_CLR_0_A" },
 271    { R200_SE_VTX_ST_CLR_1_R, "R200_SE_VTX_ST_CLR_1_R" },
 272    { R200_SE_VTX_ST_CLR_1_G, "R200_SE_VTX_ST_CLR_1_G" },
 273    { R200_SE_VTX_ST_CLR_1_B, "R200_SE_VTX_ST_CLR_1_B" },
 274    { R200_SE_VTX_ST_CLR_1_A, "R200_SE_VTX_ST_CLR_1_A" },
 275    { R200_SE_VTX_ST_CLR_2_R, "R200_SE_VTX_ST_CLR_2_R" },
 276    { R200_SE_VTX_ST_CLR_2_G, "R200_SE_VTX_ST_CLR_2_G" },
 277    { R200_SE_VTX_ST_CLR_2_B, "R200_SE_VTX_ST_CLR_2_B" },
 278    { R200_SE_VTX_ST_CLR_2_A, "R200_SE_VTX_ST_CLR_2_A" },
 279    { R200_SE_VTX_ST_CLR_3_R, "R200_SE_VTX_ST_CLR_3_R" },
 280    { R200_SE_VTX_ST_CLR_3_G, "R200_SE_VTX_ST_CLR_3_G" },
 281    { R200_SE_VTX_ST_CLR_3_B, "R200_SE_VTX_ST_CLR_3_B" },
 282    { R200_SE_VTX_ST_CLR_3_A, "R200_SE_VTX_ST_CLR_3_A" },
 283    { R200_SE_VTX_ST_CLR_4_R, "R200_SE_VTX_ST_CLR_4_R" },
 284    { R200_SE_VTX_ST_CLR_4_G, "R200_SE_VTX_ST_CLR_4_G" },
 285    { R200_SE_VTX_ST_CLR_4_B, "R200_SE_VTX_ST_CLR_4_B" },
 286    { R200_SE_VTX_ST_CLR_4_A, "R200_SE_VTX_ST_CLR_4_A" },
 287    { R200_SE_VTX_ST_CLR_5_R, "R200_SE_VTX_ST_CLR_5_R" },
 288    { R200_SE_VTX_ST_CLR_5_G, "R200_SE_VTX_ST_CLR_5_G" },
 289    { R200_SE_VTX_ST_CLR_5_B, "R200_SE_VTX_ST_CLR_5_B" },
 290    { R200_SE_VTX_ST_CLR_5_A, "R200_SE_VTX_ST_CLR_5_A" },
 291    { R200_SE_VTX_ST_CLR_6_R, "R200_SE_VTX_ST_CLR_6_R" },
 292    { R200_SE_VTX_ST_CLR_6_G, "R200_SE_VTX_ST_CLR_6_G" },
 293    { R200_SE_VTX_ST_CLR_6_B, "R200_SE_VTX_ST_CLR_6_B" },
 294    { R200_SE_VTX_ST_CLR_6_A, "R200_SE_VTX_ST_CLR_6_A" },
 295    { R200_SE_VTX_ST_CLR_7_R, "R200_SE_VTX_ST_CLR_7_R" },
 296    { R200_SE_VTX_ST_CLR_7_G, "R200_SE_VTX_ST_CLR_7_G" },
 297    { R200_SE_VTX_ST_CLR_7_B, "R200_SE_VTX_ST_CLR_7_B" },
 298    { R200_SE_VTX_ST_CLR_7_A, "R200_SE_VTX_ST_CLR_7_A" },
 299    { R200_SE_VTX_ST_TEX_0_S, "R200_SE_VTX_ST_TEX_0_S" },
 300    { R200_SE_VTX_ST_TEX_0_T, "R200_SE_VTX_ST_TEX_0_T" },
 301    { R200_SE_VTX_ST_TEX_0_R, "R200_SE_VTX_ST_TEX_0_R" },
 302    { R200_SE_VTX_ST_TEX_0_Q, "R200_SE_VTX_ST_TEX_0_Q" },
 303    { R200_SE_VTX_ST_TEX_1_S, "R200_SE_VTX_ST_TEX_1_S" },
 304    { R200_SE_VTX_ST_TEX_1_T, "R200_SE_VTX_ST_TEX_1_T" },
 305    { R200_SE_VTX_ST_TEX_1_R, "R200_SE_VTX_ST_TEX_1_R" },
 306    { R200_SE_VTX_ST_TEX_1_Q, "R200_SE_VTX_ST_TEX_1_Q" },
 307    { R200_SE_VTX_ST_TEX_2_S, "R200_SE_VTX_ST_TEX_2_S" },
 308    { R200_SE_VTX_ST_TEX_2_T, "R200_SE_VTX_ST_TEX_2_T" },
 309    { R200_SE_VTX_ST_TEX_2_R, "R200_SE_VTX_ST_TEX_2_R" },
 310    { R200_SE_VTX_ST_TEX_2_Q, "R200_SE_VTX_ST_TEX_2_Q" },
 311    { R200_SE_VTX_ST_TEX_3_S, "R200_SE_VTX_ST_TEX_3_S" },
 312    { R200_SE_VTX_ST_TEX_3_T, "R200_SE_VTX_ST_TEX_3_T" },
 313    { R200_SE_VTX_ST_TEX_3_R, "R200_SE_VTX_ST_TEX_3_R" },
 314    { R200_SE_VTX_ST_TEX_3_Q, "R200_SE_VTX_ST_TEX_3_Q" },
 315    { R200_SE_VTX_ST_TEX_4_S, "R200_SE_VTX_ST_TEX_4_S" },
 316    { R200_SE_VTX_ST_TEX_4_T, "R200_SE_VTX_ST_TEX_4_T" },
 317    { R200_SE_VTX_ST_TEX_4_R, "R200_SE_VTX_ST_TEX_4_R" },
 318    { R200_SE_VTX_ST_TEX_4_Q, "R200_SE_VTX_ST_TEX_4_Q" },
 319    { R200_SE_VTX_ST_TEX_5_S, "R200_SE_VTX_ST_TEX_5_S" },
 320    { R200_SE_VTX_ST_TEX_5_T, "R200_SE_VTX_ST_TEX_5_T" },
 321    { R200_SE_VTX_ST_TEX_5_R, "R200_SE_VTX_ST_TEX_5_R" },
 322    { R200_SE_VTX_ST_TEX_5_Q, "R200_SE_VTX_ST_TEX_5_Q" },
 323    { R200_SE_VTX_ST_PNT_SPRT_SZ, "R200_SE_VTX_ST_PNT_SPRT_SZ" },
 324    { R200_SE_VTX_ST_DISC_FOG, "R200_SE_VTX_ST_DISC_FOG" },
 325    { R200_SE_VTX_ST_SHININESS_0, "R200_SE_VTX_ST_SHININESS_0" },
 326    { R200_SE_VTX_ST_SHININESS_1, "R200_SE_VTX_ST_SHININESS_1" },
 327    { R200_SE_VTX_ST_BLND_WT_0, "R200_SE_VTX_ST_BLND_WT_0" },
 328    { R200_SE_VTX_ST_BLND_WT_1, "R200_SE_VTX_ST_BLND_WT_1" },
 329    { R200_SE_VTX_ST_BLND_WT_2, "R200_SE_VTX_ST_BLND_WT_2" },
 330    { R200_SE_VTX_ST_BLND_WT_3, "R200_SE_VTX_ST_BLND_WT_3" },
 331    { R200_SE_VTX_ST_POS_1_X, "R200_SE_VTX_ST_POS_1_X" },
 332    { R200_SE_VTX_ST_POS_1_Y, "R200_SE_VTX_ST_POS_1_Y" },
 333    { R200_SE_VTX_ST_POS_1_Z, "R200_SE_VTX_ST_POS_1_Z" },
 334    { R200_SE_VTX_ST_POS_1_W, "R200_SE_VTX_ST_POS_1_W" },
 335    { R200_SE_VTX_ST_NORM_1_X, "R200_SE_VTX_ST_NORM_1_X" },
 336    { R200_SE_VTX_ST_NORM_1_Y, "R200_SE_VTX_ST_NORM_1_Y" },
 337    { R200_SE_VTX_ST_NORM_1_Z, "R200_SE_VTX_ST_NORM_1_Z" },
 338    { R200_SE_VTX_ST_USR_CLR_0_R, "R200_SE_VTX_ST_USR_CLR_0_R" },
 339    { R200_SE_VTX_ST_USR_CLR_0_G, "R200_SE_VTX_ST_USR_CLR_0_G" },
 340    { R200_SE_VTX_ST_USR_CLR_0_B, "R200_SE_VTX_ST_USR_CLR_0_B" },
 341    { R200_SE_VTX_ST_USR_CLR_0_A, "R200_SE_VTX_ST_USR_CLR_0_A" },
 342    { R200_SE_VTX_ST_USR_CLR_1_R, "R200_SE_VTX_ST_USR_CLR_1_R" },
 343    { R200_SE_VTX_ST_USR_CLR_1_G, "R200_SE_VTX_ST_USR_CLR_1_G" },
 344    { R200_SE_VTX_ST_USR_CLR_1_B, "R200_SE_VTX_ST_USR_CLR_1_B" },
 345    { R200_SE_VTX_ST_USR_CLR_1_A, "R200_SE_VTX_ST_USR_CLR_1_A" },
 346    { R200_SE_VTX_ST_CLR_0_PKD, "R200_SE_VTX_ST_CLR_0_PKD" },
 347    { R200_SE_VTX_ST_CLR_1_PKD, "R200_SE_VTX_ST_CLR_1_PKD" },
 348    { R200_SE_VTX_ST_CLR_2_PKD, "R200_SE_VTX_ST_CLR_2_PKD" },
 349    { R200_SE_VTX_ST_CLR_3_PKD, "R200_SE_VTX_ST_CLR_3_PKD" },
 350    { R200_SE_VTX_ST_CLR_4_PKD, "R200_SE_VTX_ST_CLR_4_PKD" },
 351    { R200_SE_VTX_ST_CLR_5_PKD, "R200_SE_VTX_ST_CLR_5_PKD" },
 352    { R200_SE_VTX_ST_CLR_6_PKD, "R200_SE_VTX_ST_CLR_6_PKD" },
 353    { R200_SE_VTX_ST_CLR_7_PKD, "R200_SE_VTX_ST_CLR_7_PKD" },
 354    { R200_SE_VTX_ST_POS_0_X_2, "R200_SE_VTX_ST_POS_0_X_2" },
 355    { R200_SE_VTX_ST_POS_0_Y_2, "R200_SE_VTX_ST_POS_0_Y_2" },
 356    { R200_SE_VTX_ST_PAR_CLR_LD, "R200_SE_VTX_ST_PAR_CLR_LD" },
 357    { R200_SE_VTX_ST_USR_CLR_PKD, "R200_SE_VTX_ST_USR_CLR_PKD" },
 358    { R200_SE_VTX_ST_POS_0_X_3, "R200_SE_VTX_ST_POS_0_X_3" },
 359    { R200_SE_VTX_ST_POS_0_Y_3, "R200_SE_VTX_ST_POS_0_Y_3" },
 360    { R200_SE_VTX_ST_POS_0_Z_3, "R200_SE_VTX_ST_POS_0_Z_3" },
 361    { R200_SE_VTX_ST_END_OF_PKT, "R200_SE_VTX_ST_END_OF_PKT" },
 362    { R200_RE_POINTSIZE, "R200_RE_POINTSIZE" },
 363    { R200_RE_TOP_LEFT, "R200_RE_TOP_LEFT" },
 364    { R200_RE_AUX_SCISSOR_CNTL, "R200_RE_AUX_SCISSOR_CNTL" },
 365    { R200_PP_TXFILTER_0, "R200_PP_TXFILTER_0" },
 366    { R200_PP_TXFORMAT_0, "R200_PP_TXFORMAT_0" },
 367    { R200_PP_TXSIZE_0, "R200_PP_TXSIZE_0" },
 368    { R200_PP_TXFORMAT_X_0, "R200_PP_TXFORMAT_X_0" },
 369    { R200_PP_TXPITCH_0, "R200_PP_TXPITCH_0" },
 370    { R200_PP_BORDER_COLOR_0, "R200_PP_BORDER_COLOR_0" },
 371    { R200_PP_CUBIC_FACES_0, "R200_PP_CUBIC_FACES_0" },
 372    { R200_PP_TXMULTI_CTL_0, "R200_PP_TXMULTI_CTL_0" },
 373    { R200_PP_TXFILTER_1, "R200_PP_TXFILTER_1" },
 374    { R200_PP_TXFORMAT_1, "R200_PP_TXFORMAT_1" },
 375    { R200_PP_TXSIZE_1, "R200_PP_TXSIZE_1" },
 376    { R200_PP_TXFORMAT_X_1, "R200_PP_TXFORMAT_X_1" },
 377    { R200_PP_TXPITCH_1, "R200_PP_TXPITCH_1" },
 378    { R200_PP_BORDER_COLOR_1, "R200_PP_BORDER_COLOR_1" },
 379    { R200_PP_CUBIC_FACES_1, "R200_PP_CUBIC_FACES_1" },
 380    { R200_PP_TXMULTI_CTL_1, "R200_PP_TXMULTI_CTL_1" },
 381    { R200_PP_TXFILTER_2, "R200_PP_TXFILTER_2" },
 382    { R200_PP_TXFORMAT_2, "R200_PP_TXFORMAT_2" },
 383    { R200_PP_TXSIZE_2, "R200_PP_TXSIZE_2" },
 384    { R200_PP_TXFORMAT_X_2, "R200_PP_TXFORMAT_X_2" },
 385    { R200_PP_TXPITCH_2, "R200_PP_TXPITCH_2" },
 386    { R200_PP_BORDER_COLOR_2, "R200_PP_BORDER_COLOR_2" },
 387    { R200_PP_CUBIC_FACES_2, "R200_PP_CUBIC_FACES_2" },
 388    { R200_PP_TXMULTI_CTL_2, "R200_PP_TXMULTI_CTL_2" },
 389    { R200_PP_TXFILTER_3, "R200_PP_TXFILTER_3" },
 390    { R200_PP_TXFORMAT_3, "R200_PP_TXFORMAT_3" },
 391    { R200_PP_TXSIZE_3, "R200_PP_TXSIZE_3" },
 392    { R200_PP_TXFORMAT_X_3, "R200_PP_TXFORMAT_X_3" },
 393    { R200_PP_TXPITCH_3, "R200_PP_TXPITCH_3" },
 394    { R200_PP_BORDER_COLOR_3, "R200_PP_BORDER_COLOR_3" },
 395    { R200_PP_CUBIC_FACES_3, "R200_PP_CUBIC_FACES_3" },
 396    { R200_PP_TXMULTI_CTL_3, "R200_PP_TXMULTI_CTL_3" },
 397    { R200_PP_TXFILTER_4, "R200_PP_TXFILTER_4" },
 398    { R200_PP_TXFORMAT_4, "R200_PP_TXFORMAT_4" },
 399    { R200_PP_TXSIZE_4, "R200_PP_TXSIZE_4" },
 400    { R200_PP_TXFORMAT_X_4, "R200_PP_TXFORMAT_X_4" },
 401    { R200_PP_TXPITCH_4, "R200_PP_TXPITCH_4" },
 402    { R200_PP_BORDER_COLOR_4, "R200_PP_BORDER_COLOR_4" },
 403    { R200_PP_CUBIC_FACES_4, "R200_PP_CUBIC_FACES_4" },
 404    { R200_PP_TXMULTI_CTL_4, "R200_PP_TXMULTI_CTL_4" },
 405    { R200_PP_TXFILTER_5, "R200_PP_TXFILTER_5" },
 406    { R200_PP_TXFORMAT_5, "R200_PP_TXFORMAT_5" },
 407    { R200_PP_TXSIZE_5, "R200_PP_TXSIZE_5" },
 408    { R200_PP_TXFORMAT_X_5, "R200_PP_TXFORMAT_X_5" },
 409    { R200_PP_TXPITCH_5, "R200_PP_TXPITCH_5" },
 410    { R200_PP_BORDER_COLOR_5, "R200_PP_BORDER_COLOR_5" },
 411    { R200_PP_CUBIC_FACES_5, "R200_PP_CUBIC_FACES_5" },
 412    { R200_PP_TXMULTI_CTL_5, "R200_PP_TXMULTI_CTL_5" },
 413    { R200_PP_TXOFFSET_0, "R200_PP_TXOFFSET_0" },
 414    { R200_PP_CUBIC_OFFSET_F1_0, "R200_PP_CUBIC_OFFSET_F1_0" },
 415    { R200_PP_CUBIC_OFFSET_F2_0, "R200_PP_CUBIC_OFFSET_F2_0" },
 416    { R200_PP_CUBIC_OFFSET_F3_0, "R200_PP_CUBIC_OFFSET_F3_0" },
 417    { R200_PP_CUBIC_OFFSET_F4_0, "R200_PP_CUBIC_OFFSET_F4_0" },
 418    { R200_PP_CUBIC_OFFSET_F5_0, "R200_PP_CUBIC_OFFSET_F5_0" },
 419    { R200_PP_TXOFFSET_1, "R200_PP_TXOFFSET_1" },
 420    { R200_PP_CUBIC_OFFSET_F1_1, "R200_PP_CUBIC_OFFSET_F1_1" },
 421    { R200_PP_CUBIC_OFFSET_F2_1, "R200_PP_CUBIC_OFFSET_F2_1" },
 422    { R200_PP_CUBIC_OFFSET_F3_1, "R200_PP_CUBIC_OFFSET_F3_1" },
 423    { R200_PP_CUBIC_OFFSET_F4_1, "R200_PP_CUBIC_OFFSET_F4_1" },
 424    { R200_PP_CUBIC_OFFSET_F5_1, "R200_PP_CUBIC_OFFSET_F5_1" },
 425    { R200_PP_TXOFFSET_2, "R200_PP_TXOFFSET_2" },
 426    { R200_PP_CUBIC_OFFSET_F1_2, "R200_PP_CUBIC_OFFSET_F1_2" },
 427    { R200_PP_CUBIC_OFFSET_F2_2, "R200_PP_CUBIC_OFFSET_F2_2" },
 428    { R200_PP_CUBIC_OFFSET_F3_2, "R200_PP_CUBIC_OFFSET_F3_2" },
 429    { R200_PP_CUBIC_OFFSET_F4_2, "R200_PP_CUBIC_OFFSET_F4_2" },
 430    { R200_PP_CUBIC_OFFSET_F5_2, "R200_PP_CUBIC_OFFSET_F5_2" },
 431    { R200_PP_TXOFFSET_3, "R200_PP_TXOFFSET_3" },
 432    { R200_PP_CUBIC_OFFSET_F1_3, "R200_PP_CUBIC_OFFSET_F1_3" },
 433    { R200_PP_CUBIC_OFFSET_F2_3, "R200_PP_CUBIC_OFFSET_F2_3" },
 434    { R200_PP_CUBIC_OFFSET_F3_3, "R200_PP_CUBIC_OFFSET_F3_3" },
 435    { R200_PP_CUBIC_OFFSET_F4_3, "R200_PP_CUBIC_OFFSET_F4_3" },
 436    { R200_PP_CUBIC_OFFSET_F5_3, "R200_PP_CUBIC_OFFSET_F5_3" },
 437    { R200_PP_TXOFFSET_4, "R200_PP_TXOFFSET_4" },
 438    { R200_PP_CUBIC_OFFSET_F1_4, "R200_PP_CUBIC_OFFSET_F1_4" },
 439    { R200_PP_CUBIC_OFFSET_F2_4, "R200_PP_CUBIC_OFFSET_F2_4" },
 440    { R200_PP_CUBIC_OFFSET_F3_4, "R200_PP_CUBIC_OFFSET_F3_4" },
 441    { R200_PP_CUBIC_OFFSET_F4_4, "R200_PP_CUBIC_OFFSET_F4_4" },
 442    { R200_PP_CUBIC_OFFSET_F5_4, "R200_PP_CUBIC_OFFSET_F5_4" },
 443    { R200_PP_TXOFFSET_5, "R200_PP_TXOFFSET_5" },
 444    { R200_PP_CUBIC_OFFSET_F1_5, "R200_PP_CUBIC_OFFSET_F1_5" },
 445    { R200_PP_CUBIC_OFFSET_F2_5, "R200_PP_CUBIC_OFFSET_F2_5" },
 446    { R200_PP_CUBIC_OFFSET_F3_5, "R200_PP_CUBIC_OFFSET_F3_5" },
 447    { R200_PP_CUBIC_OFFSET_F4_5, "R200_PP_CUBIC_OFFSET_F4_5" },
 448    { R200_PP_CUBIC_OFFSET_F5_5, "R200_PP_CUBIC_OFFSET_F5_5" },
 449    { R200_PP_TAM_DEBUG3, "R200_PP_TAM_DEBUG3" },
 450    { R200_PP_TFACTOR_0, "R200_PP_TFACTOR_0" },
 451    { R200_PP_TFACTOR_1, "R200_PP_TFACTOR_1" },
 452    { R200_PP_TFACTOR_2, "R200_PP_TFACTOR_2" },
 453    { R200_PP_TFACTOR_3, "R200_PP_TFACTOR_3" },
 454    { R200_PP_TFACTOR_4, "R200_PP_TFACTOR_4" },
 455    { R200_PP_TFACTOR_5, "R200_PP_TFACTOR_5" },
 456    { R200_PP_TFACTOR_6, "R200_PP_TFACTOR_6" },
 457    { R200_PP_TFACTOR_7, "R200_PP_TFACTOR_7" },
 458    { R200_PP_TXCBLEND_0, "R200_PP_TXCBLEND_0" },
 459    { R200_PP_TXCBLEND2_0, "R200_PP_TXCBLEND2_0" },
 460    { R200_PP_TXABLEND_0, "R200_PP_TXABLEND_0" },
 461    { R200_PP_TXABLEND2_0, "R200_PP_TXABLEND2_0" },
 462    { R200_PP_TXCBLEND_1, "R200_PP_TXCBLEND_1" },
 463    { R200_PP_TXCBLEND2_1, "R200_PP_TXCBLEND2_1" },
 464    { R200_PP_TXABLEND_1, "R200_PP_TXABLEND_1" },
 465    { R200_PP_TXABLEND2_1, "R200_PP_TXABLEND2_1" },
 466    { R200_PP_TXCBLEND_2, "R200_PP_TXCBLEND_2" },
 467    { R200_PP_TXCBLEND2_2, "R200_PP_TXCBLEND2_2" },
 468    { R200_PP_TXABLEND_2, "R200_PP_TXABLEND_2" },
 469    { R200_PP_TXABLEND2_2, "R200_PP_TXABLEND2_2" },
 470    { R200_PP_TXCBLEND_3, "R200_PP_TXCBLEND_3" },
 471    { R200_PP_TXCBLEND2_3, "R200_PP_TXCBLEND2_3" },
 472    { R200_PP_TXABLEND_3, "R200_PP_TXABLEND_3" },
 473    { R200_PP_TXABLEND2_3, "R200_PP_TXABLEND2_3" },
 474    { R200_PP_TXCBLEND_4, "R200_PP_TXCBLEND_4" },
 475    { R200_PP_TXCBLEND2_4, "R200_PP_TXCBLEND2_4" },
 476    { R200_PP_TXABLEND_4, "R200_PP_TXABLEND_4" },
 477    { R200_PP_TXABLEND2_4, "R200_PP_TXABLEND2_4" },
 478    { R200_PP_TXCBLEND_5, "R200_PP_TXCBLEND_5" },
 479    { R200_PP_TXCBLEND2_5, "R200_PP_TXCBLEND2_5" },
 480    { R200_PP_TXABLEND_5, "R200_PP_TXABLEND_5" },
 481    { R200_PP_TXABLEND2_5, "R200_PP_TXABLEND2_5" },
 482    { R200_PP_TXCBLEND_6, "R200_PP_TXCBLEND_6" },
 483    { R200_PP_TXCBLEND2_6, "R200_PP_TXCBLEND2_6" },
 484    { R200_PP_TXABLEND_6, "R200_PP_TXABLEND_6" },
 485    { R200_PP_TXABLEND2_6, "R200_PP_TXABLEND2_6" },
 486    { R200_PP_TXCBLEND_7, "R200_PP_TXCBLEND_7" },
 487    { R200_PP_TXCBLEND2_7, "R200_PP_TXCBLEND2_7" },
 488    { R200_PP_TXABLEND_7, "R200_PP_TXABLEND_7" },
 489    { R200_PP_TXABLEND2_7, "R200_PP_TXABLEND2_7" },
 490    { R200_RB3D_BLENDCOLOR, "R200_RB3D_BLENDCOLOR" },
 491    { R200_RB3D_ABLENDCNTL, "R200_RB3D_ABLENDCNTL" },
 492    { R200_RB3D_CBLENDCNTL, "R200_RB3D_CBLENDCNTL" },
 493    { R200_SE_TCL_OUTPUT_VTX_COMP_SEL, "R200_SE_TCL_OUTPUT_VTX_COMP_SEL" },
 494    { R200_PP_CNTL_X, "R200_PP_CNTL_X" },
 495    { R200_SE_VAP_CNTL_STATUS, "R200_SE_VAP_CNTL_STATUS" },
 496    { R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0, "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0" },
 497    { R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_1, "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_1" },
 498    { R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_2, "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_2" },
 499    { R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_3, "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_3" },
 500    { R200_PP_TRI_PERF, "R200_PP_TRI_PERF" },
 501    { R200_PP_PERF_CNTL, "R200_PP_PERF_CNTL" },
 502    { R200_PP_TXCBLEND_8, "R200_PP_TXCBLEND_8" },
 503    { R200_PP_TXCBLEND2_8, "R200_PP_TXCBLEND2_8" },
 504    { R200_PP_TXABLEND_8, "R200_PP_TXABLEND_8" },
 505    { R200_PP_TXABLEND2_8, "R200_PP_TXABLEND2_8" },
 506    { R200_PP_TXCBLEND_9, "R200_PP_TXCBLEND_9" },
 507    { R200_PP_TXCBLEND2_9, "R200_PP_TXCBLEND2_9" },
 508    { R200_PP_TXABLEND_9, "R200_PP_TXABLEND_9" },
 509    { R200_PP_TXABLEND2_9, "R200_PP_TXABLEND2_9" },
 510    { R200_PP_TXCBLEND_10, "R200_PP_TXCBLEND_10" },
 511    { R200_PP_TXCBLEND2_10, "R200_PP_TXCBLEND2_10" },
 512    { R200_PP_TXABLEND_10, "R200_PP_TXABLEND_10" },
 513    { R200_PP_TXABLEND2_10, "R200_PP_TXABLEND2_10" },
 514    { R200_PP_TXCBLEND_11, "R200_PP_TXCBLEND_11" },
 515    { R200_PP_TXCBLEND2_11, "R200_PP_TXCBLEND2_11" },
 516    { R200_PP_TXABLEND_11, "R200_PP_TXABLEND_11" },
 517    { R200_PP_TXABLEND2_11, "R200_PP_TXABLEND2_11" },
 518    { R200_PP_TXCBLEND_12, "R200_PP_TXCBLEND_12" },
 519    { R200_PP_TXCBLEND2_12, "R200_PP_TXCBLEND2_12" },
 520    { R200_PP_TXABLEND_12, "R200_PP_TXABLEND_12" },
 521    { R200_PP_TXABLEND2_12, "R200_PP_TXABLEND2_12" },
 522    { R200_PP_TXCBLEND_13, "R200_PP_TXCBLEND_13" },
 523    { R200_PP_TXCBLEND2_13, "R200_PP_TXCBLEND2_13" },
 524    { R200_PP_TXABLEND_13, "R200_PP_TXABLEND_13" },
 525    { R200_PP_TXABLEND2_13, "R200_PP_TXABLEND2_13" },
 526    { R200_PP_TXCBLEND_14, "R200_PP_TXCBLEND_14" },
 527    { R200_PP_TXCBLEND2_14, "R200_PP_TXCBLEND2_14" },
 528    { R200_PP_TXABLEND_14, "R200_PP_TXABLEND_14" },
 529    { R200_PP_TXABLEND2_14, "R200_PP_TXABLEND2_14" },
 530    { R200_PP_TXCBLEND_15, "R200_PP_TXCBLEND_15" },
 531    { R200_PP_TXCBLEND2_15, "R200_PP_TXCBLEND2_15" },
 532    { R200_PP_TXABLEND_15, "R200_PP_TXABLEND_15" },
 533    { R200_PP_TXABLEND2_15, "R200_PP_TXABLEND2_15" },
 534    { R200_VAP_PVS_CNTL_1, "R200_VAP_PVS_CNTL_1" },
 535    { R200_VAP_PVS_CNTL_2, "R200_VAP_PVS_CNTL_2" },
 536 };
 537
 538 static struct reg_names scalar_names[] = {
 539    { R200_SS_LIGHT_DCD_ADDR, "R200_SS_LIGHT_DCD_ADDR" },
 540    { R200_SS_LIGHT_DCM_ADDR, "R200_SS_LIGHT_DCM_ADDR" },
 541    { R200_SS_LIGHT_SPOT_EXPONENT_ADDR, "R200_SS_LIGHT_SPOT_EXPONENT_ADDR" },
 542    { R200_SS_LIGHT_SPOT_CUTOFF_ADDR, "R200_SS_LIGHT_SPOT_CUTOFF_ADDR" },
 543    { R200_SS_LIGHT_SPECULAR_THRESH_ADDR, "R200_SS_LIGHT_SPECULAR_THRESH_ADDR" },
 544    { R200_SS_LIGHT_RANGE_CUTOFF_SQRD, "R200_SS_LIGHT_RANGE_CUTOFF_SQRD" },
 545    { R200_SS_LIGHT_RANGE_ATT_CONST, "R200_SS_LIGHT_RANGE_ATT_CONST" },
 546    { R200_SS_VERT_GUARD_CLIP_ADJ_ADDR, "R200_SS_VERT_GUARD_CLIP_ADJ_ADDR" },
 547    { R200_SS_VERT_GUARD_DISCARD_ADJ_ADDR, "R200_SS_VERT_GUARD_DISCARD_ADJ_ADDR" },
 548    { R200_SS_HORZ_GUARD_CLIP_ADJ_ADDR, "R200_SS_HORZ_GUARD_CLIP_ADJ_ADDR" },
 549    { R200_SS_HORZ_GUARD_DISCARD_ADJ_ADDR, "R200_SS_HORZ_GUARD_DISCARD_ADJ_ADDR" },
 550    { R200_SS_MAT_0_SHININESS, "R200_SS_MAT_0_SHININESS" },
 551    { R200_SS_MAT_1_SHININESS, "R200_SS_MAT_1_SHININESS" },
 552    { 1000, "" },
 553 };
 554
 555 /* Puff these out to make them look like normal (dword) registers.
 556  */
 557 static struct reg_names vector_names[] = {
 558    { 0, "start" },
 559    { R200_VS_LIGHT_AMBIENT_ADDR, "R200_VS_LIGHT_AMBIENT_ADDR" },
 560    { R200_VS_LIGHT_DIFFUSE_ADDR, "R200_VS_LIGHT_DIFFUSE_ADDR" },
 561    { R200_VS_LIGHT_SPECULAR_ADDR, "R200_VS_LIGHT_SPECULAR_ADDR" },
 562    { R200_VS_LIGHT_DIRPOS_ADDR, "R200_VS_LIGHT_DIRPOS_ADDR" },
 563    { R200_VS_LIGHT_HWVSPOT_ADDR, "R200_VS_LIGHT_HWVSPOT_ADDR" },
 564    { R200_VS_LIGHT_ATTENUATION_ADDR, "R200_VS_LIGHT_ATTENUATION_ADDR" },
 565    { R200_VS_SPOT_DUAL_CONE, "R200_VS_SPOT_DUAL_CONE" },
 566    { R200_VS_GLOBAL_AMBIENT_ADDR, "R200_VS_GLOBAL_AMBIENT_ADDR" },
 567    { R200_VS_FOG_PARAM_ADDR, "R200_VS_FOG_PARAM_ADDR" },
 568    { R200_VS_EYE_VECTOR_ADDR, "R200_VS_EYE_VECTOR_ADDR" },
 569    { R200_VS_UCP_ADDR, "R200_VS_UCP_ADDR" },
 570    { R200_VS_PNT_SPRITE_VPORT_SCALE, "R200_VS_PNT_SPRITE_VPORT_SCALE" },
 571    { R200_VS_MATRIX_0_MV, "R200_VS_MATRIX_0_MV" },
 572    { R200_VS_MATRIX_1_INV_MV, "R200_VS_MATRIX_1_INV_MV" },
 573    { R200_VS_MATRIX_2_MVP, "R200_VS_MATRIX_2_MVP" },
 574    { R200_VS_MATRIX_3_TEX0, "R200_VS_MATRIX_3_TEX0" },
 575    { R200_VS_MATRIX_4_TEX1, "R200_VS_MATRIX_4_TEX1" },
 576    { R200_VS_MATRIX_5_TEX2, "R200_VS_MATRIX_5_TEX2" },
 577    { R200_VS_MATRIX_6_TEX3, "R200_VS_MATRIX_6_TEX3" },
 578    { R200_VS_MATRIX_7_TEX4, "R200_VS_MATRIX_7_TEX4" },
 579    { R200_VS_MATRIX_8_TEX5, "R200_VS_MATRIX_8_TEX5" },
 580    { R200_VS_MAT_0_EMISS, "R200_VS_MAT_0_EMISS" },
 581    { R200_VS_MAT_0_AMB, "R200_VS_MAT_0_AMB" },
 582    { R200_VS_MAT_0_DIF, "R200_VS_MAT_0_DIF" },
 583    { R200_VS_MAT_0_SPEC, "R200_VS_MAT_0_SPEC" },
 584    { R200_VS_MAT_1_EMISS, "R200_VS_MAT_1_EMISS" },
 585    { R200_VS_MAT_1_AMB, "R200_VS_MAT_1_AMB" },
 586    { R200_VS_MAT_1_DIF, "R200_VS_MAT_1_DIF" },
 587    { R200_VS_MAT_1_SPEC, "R200_VS_MAT_1_SPEC" },
 588    { R200_VS_EYE2CLIP_MTX, "R200_VS_EYE2CLIP_MTX" },
 589    { R200_VS_PNT_SPRITE_ATT_CONST, "R200_VS_PNT_SPRITE_ATT_CONST" },
 590    { R200_VS_PNT_SPRITE_EYE_IN_MODEL, "R200_VS_PNT_SPRITE_EYE_IN_MODEL" },
 591    { R200_VS_PNT_SPRITE_CLAMP, "R200_VS_PNT_SPRITE_CLAMP" },
 592    { R200_VS_MAX, "R200_VS_MAX" },
 593    { 1000, "" },
 594 };
 595
 596 union fi { float f; int i; };
 597
 598 #define ISVEC   1
 599 #define ISFLOAT 2
 600 #define TOUCHED 4
 601
 602 struct reg {
 603    int idx;
 604    struct reg_names *closest;
 605    int flags;
 606    union fi current;
 607    union fi *values;
 608    int nvalues;
 609    int nalloc;
 610    float vmin, vmax;
 611 };
 612
 613
 614 static struct reg regs[Elements(reg_names)+1];
 615 static struct reg scalars[512+1];
 616 static struct reg vectors[512*4+1];
 617
 618 static int total, total_changed, bufs;
 619
 620 static void init_regs( void )
 621 {
 622    struct reg_names *tmp;
 623    int i;
 624
 625    for (i = 0 ; i < Elements(regs) ; i++) {
 626       regs[i].idx = reg_names[i].idx;
 627       regs[i].closest = &reg_names[i];
 628       regs[i].flags = 0;
 629    }
 630
 631    for (i = 0, tmp = scalar_names ; i < Elements(scalars) ; i++) {
 632       if (tmp[1].idx == i) tmp++;
 633       scalars[i].idx = i;
 634       scalars[i].closest = tmp;
 635       scalars[i].flags = ISFLOAT;
 636    }
 637
 638    for (i = 0, tmp = vector_names ; i < Elements(vectors) ; i++) {
 639       if (tmp[1].idx*4 == i) tmp++;
 640       vectors[i].idx = i;
 641       vectors[i].closest = tmp;
 642       vectors[i].flags = ISFLOAT|ISVEC;
 643    }
 644
 645    regs[Elements(regs)-1].idx = -1;
 646    scalars[Elements(scalars)-1].idx = -1;
 647    vectors[Elements(vectors)-1].idx = -1;
 648 }
 649
 650 static int find_or_add_value( struct reg *reg, int val )
 651 {
 652    int j;
 653
 654    for ( j = 0 ; j < reg->nvalues ; j++)
 655       if ( val == reg->values[j].i )
 656          return 1;
 657
 658    if (j == reg->nalloc) {
 659       reg->nalloc += 5;
 660       reg->nalloc *= 2;
 661       reg->values = realloc( reg->values, reg->nalloc * sizeof(union fi) );
 662    }
 663
 664    reg->values[reg->nvalues++].i = val;
 665    return 0;
 666 }
 667
 668 static struct reg *lookup_reg( struct reg *tab, int reg )
 669 {
 670    int i;
 671
 672    for (i = 0 ; tab[i].idx != -1 ; i++) {
 673       if (tab[i].idx == reg)
 674          return &tab[i];
 675    }
 676
 677    fprintf(stderr, "*** unknown reg 0x%x\n", reg);
 678    return NULL;
 679 }
 680
 681
 682 static const char *get_reg_name( struct reg *reg )
 683 {
 684    static char tmp[80];
 685
 686    if (reg->idx == reg->closest->idx)
 687       return reg->closest->name;
 688
 689
 690    if (reg->flags & ISVEC) {
 691       if (reg->idx/4 != reg->closest->idx)
 692          sprintf(tmp, "%s+%d[%d]",
 693                  reg->closest->name,
 694                  (reg->idx/4) - reg->closest->idx,
 695                  reg->idx%4);
 696       else
 697          sprintf(tmp, "%s[%d]", reg->closest->name, reg->idx%4);
 698    }
 699    else {
 700       if (reg->idx != reg->closest->idx)
 701          sprintf(tmp, "%s+%d", reg->closest->name, reg->idx - reg->closest->idx);
 702       else
 703          sprintf(tmp, "%s", reg->closest->name);
 704    }
 705
 706    return tmp;
 707 }
 708
 709 static int print_int_reg_assignment( struct reg *reg, int data )
 710 {
 711    int changed = (reg->current.i != data);
 712    int ever_seen = find_or_add_value( reg, data );
 713
 714    if (VERBOSE || (NORMAL && (changed || !ever_seen)))
 715        fprintf(stderr, "   %s <-- 0x%x", get_reg_name(reg), data);
 716
 717    if (NORMAL) {
 718       if (!ever_seen)
 719          fprintf(stderr, " *** BRAND NEW VALUE");
 720       else if (changed)
 721          fprintf(stderr, " *** CHANGED");
 722    }
 723
 724    reg->current.i = data;
 725
 726    if (VERBOSE || (NORMAL && (changed || !ever_seen)))
 727       fprintf(stderr, "\n");
 728
 729    return changed;
 730 }
 731
 732
 733 static int print_float_reg_assignment( struct reg *reg, float data )
 734 {
 735    int changed = (reg->current.f != data);
 736    int newmin = (data < reg->vmin);
 737    int newmax = (data > reg->vmax);
 738
 739    if (VERBOSE || (NORMAL && (newmin || newmax || changed)))
 740       fprintf(stderr, "   %s <-- %.3f", get_reg_name(reg), data);
 741
 742    if (NORMAL) {
 743       if (newmin) {
 744          fprintf(stderr, " *** NEW MIN (prev %.3f)", reg->vmin);
 745          reg->vmin = data;
 746       }
 747       else if (newmax) {
 748          fprintf(stderr, " *** NEW MAX (prev %.3f)", reg->vmax);
 749          reg->vmax = data;
 750       }
 751       else if (changed) {
 752          fprintf(stderr, " *** CHANGED");
 753       }
 754    }
 755
 756    reg->current.f = data;
 757
 758    if (VERBOSE || (NORMAL && (newmin || newmax || changed)))
 759       fprintf(stderr, "\n");
 760
 761    return changed;
 762 }
 763
 764 static int print_reg_assignment( struct reg *reg, int data )
 765 {
 766    float_ui32_type datau;
 767    datau.ui32 = data;
 768    reg->flags |= TOUCHED;
 769    if (reg->flags & ISFLOAT)
 770       return print_float_reg_assignment( reg, datau.f );
 771    else
 772       return print_int_reg_assignment( reg, data );
 773 }
 774
 775 static void print_reg( struct reg *reg )
 776 {
 777    if (reg->flags & TOUCHED) {
 778       if (reg->flags & ISFLOAT) {
 779          fprintf(stderr, "   %s == %f\n", get_reg_name(reg), reg->current.f);
 780       } else {
 781          fprintf(stderr, "   %s == 0x%x\n", get_reg_name(reg), reg->current.i);
 782       }
 783    }
 784 }
 785
 786
 787 static void dump_state( void )
 788 {
 789    int i;
 790
 791    for (i = 0 ; i < Elements(regs) ; i++)
 792       print_reg( &regs[i] );
 793
 794    for (i = 0 ; i < Elements(scalars) ; i++)
 795       print_reg( &scalars[i] );
 796
 797    for (i = 0 ; i < Elements(vectors) ; i++)
 798       print_reg( &vectors[i] );
 799 }
 800
 801
 802
 803 static int radeon_emit_packets(
 804    drm_radeon_cmd_header_t header,
 805    drm_radeon_cmd_buffer_t *cmdbuf )
 806 {
 807    int id = (int)header.packet.packet_id;
 808    int sz = packet[id].len;
 809    int *data = (int *)cmdbuf->buf;
 810    int i;
 811
 812    if (sz * sizeof(int) > cmdbuf->bufsz) {
 813       fprintf(stderr, "Packet overflows cmdbuf\n");
 814       return -EINVAL;
 815    }
 816
 817    if (!packet[id].name) {
 818       fprintf(stderr, "*** Unknown packet 0 nr %d\n", id );
 819       return -EINVAL;
 820    }
 821
 822
 823    if (VERBOSE)
 824       fprintf(stderr, "Packet 0 reg %s nr %d\n", packet[id].name, sz );
 825
 826    for ( i = 0 ; i < sz ; i++) {
 827       struct reg *reg = lookup_reg( regs, packet[id].start + i*4 );
 828       if (print_reg_assignment( reg, data[i] ))
 829          total_changed++;
 830       total++;
 831    }
 832
 833    cmdbuf->buf += sz * sizeof(int);
 834    cmdbuf->bufsz -= sz * sizeof(int);
 835    return 0;
 836 }
 837
 838
 839 static int radeon_emit_scalars(
 840    drm_radeon_cmd_header_t header,
 841    drm_radeon_cmd_buffer_t *cmdbuf )
 842 {
 843    int sz = header.scalars.count;
 844    int *data = (int *)cmdbuf->buf;
 845    int start = header.scalars.offset;
 846    int stride = header.scalars.stride;
 847    int i;
 848
 849    if (VERBOSE)
 850       fprintf(stderr, "emit scalars, start %d stride %d nr %d (end %d)\n",
 851               start, stride, sz, start + stride * sz);
 852
 853
 854    for (i = 0 ; i < sz ; i++, start += stride) {
 855       struct reg *reg = lookup_reg( scalars, start );
 856       if (print_reg_assignment( reg, data[i] ))
 857          total_changed++;
 858       total++;
 859    }
 860
 861    cmdbuf->buf += sz * sizeof(int);
 862    cmdbuf->bufsz -= sz * sizeof(int);
 863    return 0;
 864 }
 865
 866
 867 static int radeon_emit_scalars2(
 868    drm_radeon_cmd_header_t header,
 869    drm_radeon_cmd_buffer_t *cmdbuf )
 870 {
 871    int sz = header.scalars.count;
 872    int *data = (int *)cmdbuf->buf;
 873    int start = header.scalars.offset + 0x100;
 874    int stride = header.scalars.stride;
 875    int i;
 876
 877    if (VERBOSE)
 878       fprintf(stderr, "emit scalars2, start %d stride %d nr %d (end %d)\n",
 879               start, stride, sz, start + stride * sz);
 880
 881    if (start + stride * sz > 258) {
 882       fprintf(stderr, "emit scalars OVERFLOW %d/%d/%d\n", start, stride, sz);
 883       return -1;
 884    }
 885
 886    for (i = 0 ; i < sz ; i++, start += stride) {
 887       struct reg *reg = lookup_reg( scalars, start );
 888       if (print_reg_assignment( reg, data[i] ))
 889          total_changed++;
 890       total++;
 891    }
 892
 893    cmdbuf->buf += sz * sizeof(int);
 894    cmdbuf->bufsz -= sz * sizeof(int);
 895    return 0;
 896 }
 897
 898 /* Check: inf/nan/extreme-size?
 899  * Check: table start, end, nr, etc.
 900  */
 901 static int radeon_emit_vectors(
 902    drm_radeon_cmd_header_t header,
 903    drm_radeon_cmd_buffer_t *cmdbuf )
 904 {
 905    int sz = header.vectors.count;
 906    int *data = (int *)cmdbuf->buf;
 907    int start = header.vectors.offset;
 908    int stride = header.vectors.stride;
 909    int i,j;
 910
 911    if (VERBOSE)
 912       fprintf(stderr, "emit vectors, start %d stride %d nr %d (end %d) (0x%x)\n",
 913               start, stride, sz, start + stride * sz, header.i);
 914
 915 /*    if (start + stride * (sz/4) > 128) { */
 916 /*       fprintf(stderr, "emit vectors OVERFLOW %d/%d/%d\n", start, stride, sz); */
 917 /*       return -1; */
 918 /*    } */
 919
 920    for (i = 0 ; i < sz ;  start += stride) {
 921       int changed = 0;
 922       for (j = 0 ; j < 4 ; i++,j++) {
 923          struct reg *reg = lookup_reg( vectors, start*4+j );
 924          if (print_reg_assignment( reg, data[i] ))
 925             changed = 1;
 926       }
 927       if (changed)
 928          total_changed += 4;
 929       total += 4;
 930    }
 931
 932
 933    cmdbuf->buf += sz * sizeof(int);
 934    cmdbuf->bufsz -= sz * sizeof(int);
 935    return 0;
 936 }
 937
 938 static int radeon_emit_veclinear(
 939    drm_radeon_cmd_header_t header,
 940    drm_radeon_cmd_buffer_t *cmdbuf )
 941 {
 942    int sz = header.veclinear.count * 4;
 943    int *data = (int *)cmdbuf->buf;
 944    float *fdata =(float *)cmdbuf->buf;
 945    int start = header.veclinear.addr_lo | (header.veclinear.addr_hi << 8);
 946    int i;
 947
 948    if (1||VERBOSE)
 949       fprintf(stderr, "emit vectors linear, start %d nr %d (end %d) (0x%x)\n",
 950               start, sz >> 2, start + (sz >> 2), header.i);
 951
 952
 953    if (start < 0x60) {
 954       for (i = 0 ; i < sz ;  i += 4) {
 955          fprintf(stderr, "R200_VS_PARAM %d 0 %f\n", (i >> 2) + start, fdata[i]);
 956          fprintf(stderr, "R200_VS_PARAM %d 1 %f\n", (i >> 2) + start, fdata[i+1]);
 957          fprintf(stderr, "R200_VS_PARAM %d 2 %f\n", (i >> 2) + start, fdata[i+2]);
 958          fprintf(stderr, "R200_VS_PARAM %d 3 %f\n", (i >> 2) + start, fdata[i+3]);
 959       }
 960    }
 961    else if ((start >= 0x100) && (start < 0x160)) {
 962       for (i = 0 ; i < sz ;  i += 4) {
 963          fprintf(stderr, "R200_VS_PARAM %d 0 %f\n", (i >> 2) + start - 0x100 + 0x60, fdata[i]);
 964          fprintf(stderr, "R200_VS_PARAM %d 1 %f\n", (i >> 2) + start - 0x100 + 0x60, fdata[i+1]);
 965          fprintf(stderr, "R200_VS_PARAM %d 2 %f\n", (i >> 2) + start - 0x100 + 0x60, fdata[i+2]);
 966          fprintf(stderr, "R200_VS_PARAM %d 3 %f\n", (i >> 2) + start - 0x100 + 0x60, fdata[i+3]);
 967       }
 968    }
 969    else if ((start >= 0x80) && (start < 0xc0)) {
 970       for (i = 0 ; i < sz ;  i += 4) {
 971          fprintf(stderr, "R200_VS_PROG %d OPDST %08x\n", (i >> 2) + start - 0x80, data[i]);
 972          fprintf(stderr, "R200_VS_PROG %d SRC1  %08x\n", (i >> 2) + start - 0x80, data[i+1]);
 973          fprintf(stderr, "R200_VS_PROG %d SRC2  %08x\n", (i >> 2) + start - 0x80, data[i+2]);
 974          fprintf(stderr, "R200_VS_PROG %d SRC3  %08x\n", (i >> 2) + start - 0x80, data[i+3]);
 975       }
 976    }
 977    else if ((start >= 0x180) && (start < 0x1c0)) {
 978       for (i = 0 ; i < sz ;  i += 4) {
 979          fprintf(stderr, "R200_VS_PROG %d OPDST %08x\n", (i >> 2) + start - 0x180 + 0x40, data[i]);
 980          fprintf(stderr, "R200_VS_PROG %d SRC1  %08x\n", (i >> 2) + start - 0x180 + 0x40, data[i+1]);
 981          fprintf(stderr, "R200_VS_PROG %d SRC2  %08x\n", (i >> 2) + start - 0x180 + 0x40, data[i+2]);
 982          fprintf(stderr, "R200_VS_PROG %d SRC3  %08x\n", (i >> 2) + start - 0x180 + 0x40, data[i+3]);
 983       }
 984    }
 985    else {
 986       fprintf(stderr, "write to unknown vector area\n");
 987    }
 988
 989    cmdbuf->buf += sz * sizeof(int);
 990    cmdbuf->bufsz -= sz * sizeof(int);
 991    return 0;
 992 }
 993
 994 #if 0
 995 static int print_vertex_format( int vfmt )
 996 {
 997    if (NORMAL) {
 998       fprintf(stderr, "   %s(%x): %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
 999               "vertex format",
1000               vfmt,
1001               "xy,",
1002               (vfmt & R200_VTX_Z0) ? "z," : "",
1003               (vfmt & R200_VTX_W0) ? "w0," : "",
1004               (vfmt & R200_VTX_FPCOLOR) ? "fpcolor," : "",
1005               (vfmt & R200_VTX_FPALPHA) ? "fpalpha," : "",
1006               (vfmt & R200_VTX_PKCOLOR) ? "pkcolor," : "",
1007               (vfmt & R200_VTX_FPSPEC) ? "fpspec," : "",
1008               (vfmt & R200_VTX_FPFOG) ? "fpfog," : "",
1009               (vfmt & R200_VTX_PKSPEC) ? "pkspec," : "",
1010               (vfmt & R200_VTX_ST0) ? "st0," : "",
1011               (vfmt & R200_VTX_ST1) ? "st1," : "",
1012               (vfmt & R200_VTX_Q1) ? "q1," : "",
1013               (vfmt & R200_VTX_ST2) ? "st2," : "",
1014               (vfmt & R200_VTX_Q2) ? "q2," : "",
1015               (vfmt & R200_VTX_ST3) ? "st3," : "",
1016               (vfmt & R200_VTX_Q3) ? "q3," : "",
1017               (vfmt & R200_VTX_Q0) ? "q0," : "",
1018               (vfmt & R200_VTX_N0) ? "n0," : "",
1019               (vfmt & R200_VTX_XY1) ? "xy1," : "",
1020               (vfmt & R200_VTX_Z1) ? "z1," : "",
1021               (vfmt & R200_VTX_W1) ? "w1," : "",
1022               (vfmt & R200_VTX_N1) ? "n1," : "");
1023
1024
1025       if (!find_or_add_value( &others[V_VTXFMT], vfmt ))
1026          fprintf(stderr, " *** NEW VALUE");
1027
1028       fprintf(stderr, "\n");
1029    }
1030
1031    return 0;
1032 }
1033 #endif
1034
1035 static char *primname[0x10] = {
1036    "NONE",
1037    "POINTS",
1038    "LINES",
1039    "LINE_STRIP",
1040    "TRIANGLES",
1041    "TRIANGLE_FAN",
1042    "TRIANGLE_STRIP",
1043    "RECT_LIST",
1044    NULL,
1045    "3VRT_POINTS",
1046    "3VRT_LINES",
1047    "POINT_SPRITES",
1048    "LINE_LOOP",
1049    "QUADS",
1050    "QUAD_STRIP",
1051    "POLYGON",
1052 };
1053
1054 static int print_prim_and_flags( int prim )
1055 {
1056    int numverts;
1057
1058    if (NORMAL)
1059       fprintf(stderr, "   %s(%x): %s%s%s%s%s%s\n",
1060               "prim flags",
1061               prim,
1062               ((prim & 0x30) == R200_VF_PRIM_WALK_IND) ? "IND," : "",
1063               ((prim & 0x30) == R200_VF_PRIM_WALK_LIST) ? "LIST," : "",
1064               ((prim & 0x30) == R200_VF_PRIM_WALK_RING) ? "RING," : "",
1065               (prim & R200_VF_COLOR_ORDER_RGBA) ? "RGBA," : "BGRA, ",
1066               (prim & R200_VF_INDEX_SZ_4) ? "INDX-32," : "",
1067               (prim & R200_VF_TCL_OUTPUT_VTX_ENABLE) ? "TCL_OUT_VTX," : "");
1068
1069    numverts = prim>>16;
1070
1071    if (NORMAL)
1072       fprintf(stderr, "   prim: %s numverts %d\n", primname[prim&0xf], numverts);
1073
1074    switch (prim & 0xf) {
1075    case R200_VF_PRIM_NONE:
1076    case R200_VF_PRIM_POINTS:
1077       if (numverts < 1) {
1078          fprintf(stderr, "Bad nr verts for line %d\n", numverts);
1079          return -1;
1080       }
1081       break;
1082    case R200_VF_PRIM_LINES:
1083    case R200_VF_PRIM_POINT_SPRITES:
1084       if ((numverts & 1) || numverts == 0) {
1085          fprintf(stderr, "Bad nr verts for line %d\n", numverts);
1086          return -1;
1087       }
1088       break;
1089    case R200_VF_PRIM_LINE_STRIP:
1090    case R200_VF_PRIM_LINE_LOOP:
1091       if (numverts < 2) {
1092          fprintf(stderr, "Bad nr verts for line_strip %d\n", numverts);
1093          return -1;
1094       }
1095       break;
1096    case R200_VF_PRIM_TRIANGLES:
1097    case R200_VF_PRIM_3VRT_POINTS:
1098    case R200_VF_PRIM_3VRT_LINES:
1099    case R200_VF_PRIM_RECT_LIST:
1100       if (numverts % 3 || numverts == 0) {
1101          fprintf(stderr, "Bad nr verts for tri %d\n", numverts);
1102          return -1;
1103       }
1104       break;
1105    case R200_VF_PRIM_TRIANGLE_FAN:
1106    case R200_VF_PRIM_TRIANGLE_STRIP:
1107    case R200_VF_PRIM_POLYGON:
1108       if (numverts < 3) {
1109          fprintf(stderr, "Bad nr verts for strip/fan %d\n", numverts);
1110          return -1;
1111       }
1112       break;
1113    case R200_VF_PRIM_QUADS:
1114       if (numverts % 4 || numverts == 0) {
1115          fprintf(stderr, "Bad nr verts for quad %d\n", numverts);
1116          return -1;
1117       }
1118       break;
1119    case R200_VF_PRIM_QUAD_STRIP:
1120       if (numverts % 2 || numverts < 4) {
1121          fprintf(stderr, "Bad nr verts for quadstrip %d\n", numverts);
1122          return -1;
1123       }
1124       break;
1125    default:
1126       fprintf(stderr, "Bad primitive\n");
1127       return -1;
1128    }
1129    return 0;
1130 }
1131
1132 /* build in knowledge about each packet type
1133  */
1134 static int radeon_emit_packet3( drm_radeon_cmd_buffer_t *cmdbuf )
1135 {
1136    int cmdsz;
1137    int *cmd = (int *)cmdbuf->buf;
1138    int *tmp;
1139    int i, stride, size, start;
1140
1141    cmdsz = 2 + ((cmd[0] & RADEON_CP_PACKET_COUNT_MASK) >> 16);
1142
1143    if ((cmd[0] & RADEON_CP_PACKET_MASK) != RADEON_CP_PACKET3 ||
1144        cmdsz * 4 > cmdbuf->bufsz ||
1145        cmdsz > RADEON_CP_PACKET_MAX_DWORDS) {
1146       fprintf(stderr, "Bad packet\n");
1147       return -EINVAL;
1148    }
1149
1150    switch( cmd[0] & ~RADEON_CP_PACKET_COUNT_MASK ) {
1151    case R200_CP_CMD_NOP:
1152       if (NORMAL)
1153          fprintf(stderr, "PACKET3_NOP, %d dwords\n", cmdsz);
1154       break;
1155    case R200_CP_CMD_NEXT_CHAR:
1156       if (NORMAL)
1157          fprintf(stderr, "PACKET3_NEXT_CHAR, %d dwords\n", cmdsz);
1158       break;
1159    case R200_CP_CMD_PLY_NEXTSCAN:
1160       if (NORMAL)
1161          fprintf(stderr, "PACKET3_PLY_NEXTSCAN, %d dwords\n", cmdsz);
1162       break;
1163    case R200_CP_CMD_SET_SCISSORS:
1164       if (NORMAL)
1165          fprintf(stderr, "PACKET3_SET_SCISSORS, %d dwords\n", cmdsz);
1166       break;
1167    case R200_CP_CMD_LOAD_MICROCODE:
1168       if (NORMAL)
1169          fprintf(stderr, "PACKET3_LOAD_MICROCODE, %d dwords\n", cmdsz);
1170       break;
1171    case R200_CP_CMD_WAIT_FOR_IDLE:
1172       if (NORMAL)
1173          fprintf(stderr, "PACKET3_WAIT_FOR_IDLE, %d dwords\n", cmdsz);
1174       break;
1175
1176    case R200_CP_CMD_3D_DRAW_VBUF:
1177       if (NORMAL)
1178          fprintf(stderr, "PACKET3_3D_DRAW_VBUF, %d dwords\n", cmdsz);
1179 /*       print_vertex_format(cmd[1]); */
1180       if (print_prim_and_flags(cmd[2]))
1181          return -EINVAL;
1182       break;
1183
1184    case R200_CP_CMD_3D_DRAW_IMMD:
1185       if (NORMAL)
1186          fprintf(stderr, "PACKET3_3D_DRAW_IMMD, %d dwords\n", cmdsz);
1187       break;
1188    case R200_CP_CMD_3D_DRAW_INDX: {
1189       int neltdwords;
1190       if (NORMAL)
1191          fprintf(stderr, "PACKET3_3D_DRAW_INDX, %d dwords\n", cmdsz);
1192 /*       print_vertex_format(cmd[1]); */
1193       if (print_prim_and_flags(cmd[2]))
1194          return -EINVAL;
1195       neltdwords = cmd[2]>>16;
1196       neltdwords += neltdwords & 1;
1197       neltdwords /= 2;
1198       if (neltdwords + 3 != cmdsz)
1199          fprintf(stderr, "Mismatch in DRAW_INDX, %d vs cmdsz %d\n",
1200                  neltdwords, cmdsz);
1201       break;
1202    }
1203    case R200_CP_CMD_LOAD_PALETTE:
1204       if (NORMAL)
1205          fprintf(stderr, "PACKET3_LOAD_PALETTE, %d dwords\n", cmdsz);
1206       break;
1207    case R200_CP_CMD_3D_LOAD_VBPNTR:
1208       if (NORMAL) {
1209          fprintf(stderr, "PACKET3_3D_LOAD_VBPNTR, %d dwords\n", cmdsz);
1210          fprintf(stderr, "   nr arrays: %d\n", cmd[1]);
1211       }
1212
1213       if (((cmd[1]/2)*3) + ((cmd[1]%2)*2) != cmdsz - 2) {
1214          fprintf(stderr, "  ****** MISMATCH %d/%d *******\n",
1215                  ((cmd[1]/2)*3) + ((cmd[1]%2)*2) + 2, cmdsz);
1216          return -EINVAL;
1217       }
1218
1219       if (NORMAL) {
1220          tmp = cmd+2;
1221          for (i = 0 ; i < cmd[1] ; i++) {
1222             if (i & 1) {
1223                stride = (tmp[0]>>24) & 0xff;
1224                size = (tmp[0]>>16) & 0xff;
1225                start = tmp[2];
1226                tmp += 3;
1227             }
1228             else {
1229                stride = (tmp[0]>>8) & 0xff;
1230                size = (tmp[0]) & 0xff;
1231                start = tmp[1];
1232             }
1233             fprintf(stderr, "   array %d: start 0x%x vsize %d vstride %d\n",
1234                     i, start, size, stride );
1235          }
1236       }
1237       break;
1238    case R200_CP_CMD_PAINT:
1239       if (NORMAL)
1240          fprintf(stderr, "PACKET3_CNTL_PAINT, %d dwords\n", cmdsz);
1241       break;
1242    case R200_CP_CMD_BITBLT:
1243       if (NORMAL)
1244          fprintf(stderr, "PACKET3_CNTL_BITBLT, %d dwords\n", cmdsz);
1245       break;
1246    case R200_CP_CMD_SMALLTEXT:
1247       if (NORMAL)
1248          fprintf(stderr, "PACKET3_CNTL_SMALLTEXT, %d dwords\n", cmdsz);
1249       break;
1250    case R200_CP_CMD_HOSTDATA_BLT:
1251       if (NORMAL)
1252          fprintf(stderr, "PACKET3_CNTL_HOSTDATA_BLT, %d dwords\n",
1253               cmdsz);
1254       break;
1255    case R200_CP_CMD_POLYLINE:
1256       if (NORMAL)
1257          fprintf(stderr, "PACKET3_CNTL_POLYLINE, %d dwords\n", cmdsz);
1258       break;
1259    case R200_CP_CMD_POLYSCANLINES:
1260       if (NORMAL)
1261          fprintf(stderr, "PACKET3_CNTL_POLYSCANLINES, %d dwords\n",
1262               cmdsz);
1263       break;
1264    case R200_CP_CMD_PAINT_MULTI:
1265       if (NORMAL)
1266          fprintf(stderr, "PACKET3_CNTL_PAINT_MULTI, %d dwords\n",
1267               cmdsz);
1268       break;
1269    case R200_CP_CMD_BITBLT_MULTI:
1270       if (NORMAL)
1271          fprintf(stderr, "PACKET3_CNTL_BITBLT_MULTI, %d dwords\n",
1272               cmdsz);
1273       break;
1274    case R200_CP_CMD_TRANS_BITBLT:
1275       if (NORMAL)
1276          fprintf(stderr, "PACKET3_CNTL_TRANS_BITBLT, %d dwords\n",
1277               cmdsz);
1278       break;
1279    case R200_CP_CMD_3D_DRAW_VBUF_2:
1280       if (NORMAL)
1281          fprintf(stderr, "R200_CP_CMD_3D_DRAW_VBUF_2, %d dwords\n",
1282               cmdsz);
1283       if (print_prim_and_flags(cmd[1]))
1284          return -EINVAL;
1285       break;
1286    case R200_CP_CMD_3D_DRAW_IMMD_2:
1287       if (NORMAL)
1288          fprintf(stderr, "R200_CP_CMD_3D_DRAW_IMMD_2, %d dwords\n",
1289               cmdsz);
1290       if (print_prim_and_flags(cmd[1]))
1291          return -EINVAL;
1292       break;
1293    case R200_CP_CMD_3D_DRAW_INDX_2:
1294       if (NORMAL)
1295          fprintf(stderr, "R200_CP_CMD_3D_DRAW_INDX_2, %d dwords\n",
1296               cmdsz);
1297       if (print_prim_and_flags(cmd[1]))
1298          return -EINVAL;
1299       break;
1300    default:
1301       fprintf(stderr, "UNKNOWN PACKET, %d dwords\n", cmdsz);
1302       break;
1303    }
1304
1305    cmdbuf->buf += cmdsz * 4;
1306    cmdbuf->bufsz -= cmdsz * 4;
1307    return 0;
1308 }
1309
1310
1311 /* Check cliprects for bounds, then pass on to above:
1312  */
1313 static int radeon_emit_packet3_cliprect( drm_radeon_cmd_buffer_t *cmdbuf )
1314 {
1315    drm_clip_rect_t *boxes = (drm_clip_rect_t *)cmdbuf->boxes;
1316    int i = 0;
1317
1318    if (VERBOSE && total_changed) {
1319       dump_state();
1320       total_changed = 0;
1321    }
1322
1323    if (NORMAL) {
1324       do {
1325          if ( i < cmdbuf->nbox ) {
1326             fprintf(stderr, "Emit box %d/%d %d,%d %d,%d\n",
1327                     i, cmdbuf->nbox,
1328                     boxes[i].x1, boxes[i].y1, boxes[i].x2, boxes[i].y2);
1329          }
1330       } while ( ++i < cmdbuf->nbox );
1331    }
1332
1333    if (cmdbuf->nbox == 1)
1334       cmdbuf->nbox = 0;
1335
1336    return radeon_emit_packet3( cmdbuf );
1337 }
1338
1339
1340 int r200SanityCmdBuffer( r200ContextPtr rmesa,
1341                            int nbox,
1342                            drm_clip_rect_t *boxes )
1343 {
1344    int idx;
1345    drm_radeon_cmd_buffer_t cmdbuf;
1346    drm_radeon_cmd_header_t header;
1347    static int inited = 0;
1348
1349    if (!inited) {
1350       init_regs();
1351       inited = 1;
1352    }
1353
1354
1355    cmdbuf.buf = rmesa->store.cmd_buf;
1356    cmdbuf.bufsz = rmesa->store.cmd_used;
1357    cmdbuf.boxes = (drm_clip_rect_t *)boxes;
1358    cmdbuf.nbox = nbox;
1359
1360    while ( cmdbuf.bufsz >= sizeof(header) ) {
1361
1362       header.i = *(int *)cmdbuf.buf;
1363       cmdbuf.buf += sizeof(header);
1364       cmdbuf.bufsz -= sizeof(header);
1365
1366       switch (header.header.cmd_type) {
1367       case RADEON_CMD_PACKET:
1368          if (radeon_emit_packets( header, &cmdbuf )) {
1369             fprintf(stderr,"radeon_emit_packets failed\n");
1370             return -EINVAL;
1371          }
1372          break;
1373
1374       case RADEON_CMD_SCALARS:
1375          if (radeon_emit_scalars( header, &cmdbuf )) {
1376             fprintf(stderr,"radeon_emit_scalars failed\n");
1377             return -EINVAL;
1378          }
1379          break;
1380
1381       case RADEON_CMD_SCALARS2:
1382          if (radeon_emit_scalars2( header, &cmdbuf )) {
1383             fprintf(stderr,"radeon_emit_scalars failed\n");
1384             return -EINVAL;
1385          }
1386          break;
1387
1388       case RADEON_CMD_VECTORS:
1389          if (radeon_emit_vectors( header, &cmdbuf )) {
1390             fprintf(stderr,"radeon_emit_vectors failed\n");
1391             return -EINVAL;
1392          }
1393          break;
1394
1395       case RADEON_CMD_DMA_DISCARD:
1396          idx = header.dma.buf_idx;
1397          if (NORMAL)
1398             fprintf(stderr, "RADEON_CMD_DMA_DISCARD buf %d\n", idx);
1399          bufs++;
1400          break;
1401
1402       case RADEON_CMD_PACKET3:
1403          if (radeon_emit_packet3( &cmdbuf )) {
1404             fprintf(stderr,"radeon_emit_packet3 failed\n");
1405             return -EINVAL;
1406          }
1407          break;
1408
1409       case RADEON_CMD_PACKET3_CLIP:
1410          if (radeon_emit_packet3_cliprect( &cmdbuf )) {
1411             fprintf(stderr,"radeon_emit_packet3_clip failed\n");
1412             return -EINVAL;
1413          }
1414          break;
1415
1416       case RADEON_CMD_WAIT:
1417          break;
1418
1419       case RADEON_CMD_VECLINEAR:
1420          if (radeon_emit_veclinear( header, &cmdbuf )) {
1421             fprintf(stderr,"radeon_emit_veclinear failed\n");
1422             return -EINVAL;
1423          }
1424          break;
1425
1426       default:
1427          fprintf(stderr,"bad cmd_type %d at %p\n",
1428                    header.header.cmd_type,
1429                    cmdbuf.buf - sizeof(header));
1430          return -EINVAL;
1431       }
1432    }
1433
1434    if (0)
1435    {
1436       static int n = 0;
1437       n++;
1438       if (n == 10) {
1439          fprintf(stderr, "Bufs %d Total emitted %d real changes %d (%.2f%%)\n",
1440                  bufs,
1441                  total, total_changed,
1442                  ((float)total_changed/(float)total*100.0));
1443          fprintf(stderr, "Total emitted per buf: %.2f\n",
1444                  (float)total/(float)bufs);
1445          fprintf(stderr, "Real changes per buf: %.2f\n",
1446                  (float)total_changed/(float)bufs);
1447
1448          bufs = n = total = total_changed = 0;
1449       }
1450    }
1451
1452    fprintf(stderr, "leaving %s\n\n\n", __FUNCTION__);
1453
1454    return 0;
1455 }