1 /* $XFree86: xc/lib/GL/mesa/src/drv/r200/r200_sanity.c,v 1.1 2002/10/30 12:51:52 alanh Exp $ */
2 /**************************************************************************
4 Copyright 2002 ATI Technologies Inc., Ontario, Canada, and
5 Tungsten Graphics Inc, Cedar Park, TX.
9 Permission is hereby granted, free of charge, to any person obtaining a
10 copy of this software and associated documentation files (the "Software"),
11 to deal in the Software without restriction, including without limitation
12 on the rights to use, copy, modify, merge, publish, distribute, sub
13 license, and/or sell copies of the Software, and to permit persons to whom
14 the Software is furnished to do so, subject to the following conditions:
16 The above copyright notice and this permission notice (including the next
17 paragraph) shall be included in all copies or substantial portions of the
20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
21 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
22 FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
23 ATI, TUNGSTEN GRAPHICS AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
24 DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
25 OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
26 USE OR OTHER DEALINGS IN THE SOFTWARE.
28 **************************************************************************/
32 * Keith Whitwell <keith@tungstengraphics.com>
41 #include "r200_context.h"
42 #include "r200_ioctl.h"
43 #include "r200_sanity.h"
44 #include "radeon_reg.h"
47 /* Set this '1' to get more verbiage.
49 #define MORE_VERBOSE 1
52 #define VERBOSE (R200_DEBUG & DEBUG_VERBOSE)
56 #define NORMAL (R200_DEBUG & DEBUG_VERBOSE)
60 /* New (1.3) state mechanism. 3 commands (packet, scalar, vector) in
61 * 1.3 cmdbuffers allow all previous state to be updated as well as
62 * the tcl scalar and vector areas.
68 } packet
[RADEON_MAX_STATE_PACKETS
] = {
69 { RADEON_PP_MISC
,7,"RADEON_PP_MISC" },
70 { RADEON_PP_CNTL
,3,"RADEON_PP_CNTL" },
71 { RADEON_RB3D_COLORPITCH
,1,"RADEON_RB3D_COLORPITCH" },
72 { RADEON_RE_LINE_PATTERN
,2,"RADEON_RE_LINE_PATTERN" },
73 { RADEON_SE_LINE_WIDTH
,1,"RADEON_SE_LINE_WIDTH" },
74 { RADEON_PP_LUM_MATRIX
,1,"RADEON_PP_LUM_MATRIX" },
75 { RADEON_PP_ROT_MATRIX_0
,2,"RADEON_PP_ROT_MATRIX_0" },
76 { RADEON_RB3D_STENCILREFMASK
,3,"RADEON_RB3D_STENCILREFMASK" },
77 { RADEON_SE_VPORT_XSCALE
,6,"RADEON_SE_VPORT_XSCALE" },
78 { RADEON_SE_CNTL
,2,"RADEON_SE_CNTL" },
79 { RADEON_SE_CNTL_STATUS
,1,"RADEON_SE_CNTL_STATUS" },
80 { RADEON_RE_MISC
,1,"RADEON_RE_MISC" },
81 { RADEON_PP_TXFILTER_0
,6,"RADEON_PP_TXFILTER_0" },
82 { RADEON_PP_BORDER_COLOR_0
,1,"RADEON_PP_BORDER_COLOR_0" },
83 { RADEON_PP_TXFILTER_1
,6,"RADEON_PP_TXFILTER_1" },
84 { RADEON_PP_BORDER_COLOR_1
,1,"RADEON_PP_BORDER_COLOR_1" },
85 { RADEON_PP_TXFILTER_2
,6,"RADEON_PP_TXFILTER_2" },
86 { RADEON_PP_BORDER_COLOR_2
,1,"RADEON_PP_BORDER_COLOR_2" },
87 { RADEON_SE_ZBIAS_FACTOR
,2,"RADEON_SE_ZBIAS_FACTOR" },
88 { RADEON_SE_TCL_OUTPUT_VTX_FMT
,11,"RADEON_SE_TCL_OUTPUT_VTX_FMT" },
89 { RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED
,17,"RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED" },
90 { R200_PP_TXCBLEND_0
, 4, "R200_EMIT_PP_TXCBLEND_0" },
91 { R200_PP_TXCBLEND_1
, 4, "R200_PP_TXCBLEND_1" },
92 { R200_PP_TXCBLEND_2
, 4, "R200_PP_TXCBLEND_2" },
93 { R200_PP_TXCBLEND_3
, 4, "R200_PP_TXCBLEND_3" },
94 { R200_PP_TXCBLEND_4
, 4, "R200_PP_TXCBLEND_4" },
95 { R200_PP_TXCBLEND_5
, 4, "R200_PP_TXCBLEND_5" },
96 { R200_PP_TXCBLEND_6
, 4, "R200_PP_TXCBLEND_6" },
97 { R200_PP_TXCBLEND_7
, 4, "R200_PP_TXCBLEND_7" },
98 { R200_SE_TCL_LIGHT_MODEL_CTL_0
, 6, "R200_SE_TCL_LIGHT_MODEL_CTL_0" },
99 { R200_PP_TFACTOR_0
, 6, "R200_PP_TFACTOR_0" },
100 { R200_SE_VTX_FMT_0
, 4, "R200_SE_VTX_FMT_0" },
101 { R200_SE_VAP_CNTL
, 1, "R200_SE_VAP_CNTL" },
102 { R200_SE_TCL_MATRIX_SEL_0
, 5, "R200_SE_TCL_MATRIX_SEL_0" },
103 { R200_SE_TCL_TEX_PROC_CTL_2
, 5, "R200_SE_TCL_TEX_PROC_CTL_2" },
104 { R200_SE_TCL_UCP_VERT_BLEND_CTL
, 1, "R200_SE_TCL_UCP_VERT_BLEND_CTL" },
105 { R200_PP_TXFILTER_0
, 6, "R200_PP_TXFILTER_0" },
106 { R200_PP_TXFILTER_1
, 6, "R200_PP_TXFILTER_1" },
107 { R200_PP_TXFILTER_2
, 6, "R200_PP_TXFILTER_2" },
108 { R200_PP_TXFILTER_3
, 6, "R200_PP_TXFILTER_3" },
109 { R200_PP_TXFILTER_4
, 6, "R200_PP_TXFILTER_4" },
110 { R200_PP_TXFILTER_5
, 6, "R200_PP_TXFILTER_5" },
111 { R200_PP_TXOFFSET_0
, 1, "R200_PP_TXOFFSET_0" },
112 { R200_PP_TXOFFSET_1
, 1, "R200_PP_TXOFFSET_1" },
113 { R200_PP_TXOFFSET_2
, 1, "R200_PP_TXOFFSET_2" },
114 { R200_PP_TXOFFSET_3
, 1, "R200_PP_TXOFFSET_3" },
115 { R200_PP_TXOFFSET_4
, 1, "R200_PP_TXOFFSET_4" },
116 { R200_PP_TXOFFSET_5
, 1, "R200_PP_TXOFFSET_5" },
117 { R200_SE_VTE_CNTL
, 1, "R200_SE_VTE_CNTL" },
118 { R200_SE_TCL_OUTPUT_VTX_COMP_SEL
, 1, "R200_SE_TCL_OUTPUT_VTX_COMP_SEL" },
119 { R200_PP_TAM_DEBUG3
, 1, "R200_PP_TAM_DEBUG3" },
120 { R200_PP_CNTL_X
, 1, "R200_PP_CNTL_X" },
121 { R200_RB3D_DEPTHXY_OFFSET
, 1, "R200_RB3D_DEPTHXY_OFFSET" },
122 { R200_RE_AUX_SCISSOR_CNTL
, 1, "R200_RE_AUX_SCISSOR_CNTL" },
123 { R200_RE_SCISSOR_TL_0
, 2, "R200_RE_SCISSOR_TL_0" },
124 { R200_RE_SCISSOR_TL_1
, 2, "R200_RE_SCISSOR_TL_1" },
125 { R200_RE_SCISSOR_TL_2
, 2, "R200_RE_SCISSOR_TL_2" },
126 { R200_SE_VAP_CNTL_STATUS
, 1, "R200_SE_VAP_CNTL_STATUS" },
127 { R200_SE_VTX_STATE_CNTL
, 1, "R200_SE_VTX_STATE_CNTL" },
128 { R200_RE_POINTSIZE
, 1, "R200_RE_POINTSIZE" },
129 { R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0
, 4, "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0" },
130 { R200_PP_CUBIC_FACES_0
, 1, "R200_PP_CUBIC_FACES_0" }, /* 61 */
131 { R200_PP_CUBIC_OFFSET_F1_0
, 5, "R200_PP_CUBIC_OFFSET_F1_0" }, /* 62 */
132 { R200_PP_CUBIC_FACES_1
, 1, "R200_PP_CUBIC_FACES_1" },
133 { R200_PP_CUBIC_OFFSET_F1_1
, 5, "R200_PP_CUBIC_OFFSET_F1_1" },
134 { R200_PP_CUBIC_FACES_2
, 1, "R200_PP_CUBIC_FACES_2" },
135 { R200_PP_CUBIC_OFFSET_F1_2
, 5, "R200_PP_CUBIC_OFFSET_F1_2" },
136 { R200_PP_CUBIC_FACES_3
, 1, "R200_PP_CUBIC_FACES_3" },
137 { R200_PP_CUBIC_OFFSET_F1_3
, 5, "R200_PP_CUBIC_OFFSET_F1_3" },
138 { R200_PP_CUBIC_FACES_4
, 1, "R200_PP_CUBIC_FACES_4" },
139 { R200_PP_CUBIC_OFFSET_F1_4
, 5, "R200_PP_CUBIC_OFFSET_F1_4" },
140 { R200_PP_CUBIC_FACES_5
, 1, "R200_PP_CUBIC_FACES_5" },
141 { R200_PP_CUBIC_OFFSET_F1_5
, 5, "R200_PP_CUBIC_OFFSET_F1_5" },
142 { RADEON_PP_TEX_SIZE_0
, 2, "RADEON_PP_TEX_SIZE_0" },
143 { RADEON_PP_TEX_SIZE_1
, 2, "RADEON_PP_TEX_SIZE_1" },
144 { RADEON_PP_TEX_SIZE_2
, 2, "RADEON_PP_TEX_SIZE_2" },
145 { R200_RB3D_BLENDCOLOR
, 3, "R200_RB3D_BLENDCOLOR" },
146 { R200_SE_TCL_POINT_SPRITE_CNTL
, 1, "R200_SE_TCL_POINT_SPRITE_CNTL" },
147 { RADEON_PP_CUBIC_FACES_0
, 1, "RADEON_PP_CUBIC_FACES_0" },
148 { RADEON_PP_CUBIC_OFFSET_T0_0
, 5, "RADEON_PP_CUBIC_OFFSET_T0_0" },
149 { RADEON_PP_CUBIC_FACES_1
, 1, "RADEON_PP_CUBIC_FACES_1" },
150 { RADEON_PP_CUBIC_OFFSET_T1_0
, 5, "RADEON_PP_CUBIC_OFFSET_T1_0" },
151 { RADEON_PP_CUBIC_FACES_2
, 1, "RADEON_PP_CUBIC_FACES_2" },
152 { RADEON_PP_CUBIC_OFFSET_T2_0
, 5, "RADEON_PP_CUBIC_OFFSET_T2_0" },
153 { R200_PP_TRI_PERF
, 2, "R200_PP_TRI_PERF" },
154 { R200_PP_TXCBLEND_8
, 32, "R200_PP_AFS_0"}, /* 85 */
155 { R200_PP_TXCBLEND_0
, 32, "R200_PP_AFS_1"},
156 { R200_PP_TFACTOR_0
, 8, "R200_ATF_TFACTOR"},
157 { R200_PP_TXFILTER_0
, 8, "R200_PP_TXCTLALL_0"},
158 { R200_PP_TXFILTER_1
, 8, "R200_PP_TXCTLALL_1"},
159 { R200_PP_TXFILTER_2
, 8, "R200_PP_TXCTLALL_2"},
160 { R200_PP_TXFILTER_3
, 8, "R200_PP_TXCTLALL_3"},
161 { R200_PP_TXFILTER_4
, 8, "R200_PP_TXCTLALL_4"},
162 { R200_PP_TXFILTER_5
, 8, "R200_PP_TXCTLALL_5"},
163 { R200_VAP_PVS_CNTL_1
, 2, "R200_VAP_PVS_CNTL"},
171 static struct reg_names reg_names
[] = {
172 { R200_PP_MISC
, "R200_PP_MISC" },
173 { R200_PP_FOG_COLOR
, "R200_PP_FOG_COLOR" },
174 { R200_RE_SOLID_COLOR
, "R200_RE_SOLID_COLOR" },
175 { R200_RB3D_BLENDCNTL
, "R200_RB3D_BLENDCNTL" },
176 { R200_RB3D_DEPTHOFFSET
, "R200_RB3D_DEPTHOFFSET" },
177 { R200_RB3D_DEPTHPITCH
, "R200_RB3D_DEPTHPITCH" },
178 { R200_RB3D_ZSTENCILCNTL
, "R200_RB3D_ZSTENCILCNTL" },
179 { R200_PP_CNTL
, "R200_PP_CNTL" },
180 { R200_RB3D_CNTL
, "R200_RB3D_CNTL" },
181 { R200_RB3D_COLOROFFSET
, "R200_RB3D_COLOROFFSET" },
182 { R200_RE_WIDTH_HEIGHT
, "R200_RE_WIDTH_HEIGHT" },
183 { R200_RB3D_COLORPITCH
, "R200_RB3D_COLORPITCH" },
184 { R200_SE_CNTL
, "R200_SE_CNTL" },
185 { R200_RE_CNTL
, "R200_RE_CNTL" },
186 { R200_RE_MISC
, "R200_RE_MISC" },
187 { R200_RE_STIPPLE_ADDR
, "R200_RE_STIPPLE_ADDR" },
188 { R200_RE_STIPPLE_DATA
, "R200_RE_STIPPLE_DATA" },
189 { R200_RE_LINE_PATTERN
, "R200_RE_LINE_PATTERN" },
190 { R200_RE_LINE_STATE
, "R200_RE_LINE_STATE" },
191 { R200_RE_SCISSOR_TL_0
, "R200_RE_SCISSOR_TL_0" },
192 { R200_RE_SCISSOR_BR_0
, "R200_RE_SCISSOR_BR_0" },
193 { R200_RE_SCISSOR_TL_1
, "R200_RE_SCISSOR_TL_1" },
194 { R200_RE_SCISSOR_BR_1
, "R200_RE_SCISSOR_BR_1" },
195 { R200_RE_SCISSOR_TL_2
, "R200_RE_SCISSOR_TL_2" },
196 { R200_RE_SCISSOR_BR_2
, "R200_RE_SCISSOR_BR_2" },
197 { R200_RB3D_DEPTHXY_OFFSET
, "R200_RB3D_DEPTHXY_OFFSET" },
198 { R200_RB3D_STENCILREFMASK
, "R200_RB3D_STENCILREFMASK" },
199 { R200_RB3D_ROPCNTL
, "R200_RB3D_ROPCNTL" },
200 { R200_RB3D_PLANEMASK
, "R200_RB3D_PLANEMASK" },
201 { R200_SE_VPORT_XSCALE
, "R200_SE_VPORT_XSCALE" },
202 { R200_SE_VPORT_XOFFSET
, "R200_SE_VPORT_XOFFSET" },
203 { R200_SE_VPORT_YSCALE
, "R200_SE_VPORT_YSCALE" },
204 { R200_SE_VPORT_YOFFSET
, "R200_SE_VPORT_YOFFSET" },
205 { R200_SE_VPORT_ZSCALE
, "R200_SE_VPORT_ZSCALE" },
206 { R200_SE_VPORT_ZOFFSET
, "R200_SE_VPORT_ZOFFSET" },
207 { R200_SE_ZBIAS_FACTOR
, "R200_SE_ZBIAS_FACTOR" },
208 { R200_SE_ZBIAS_CONSTANT
, "R200_SE_ZBIAS_CONSTANT" },
209 { R200_SE_LINE_WIDTH
, "R200_SE_LINE_WIDTH" },
210 { R200_SE_VAP_CNTL
, "R200_SE_VAP_CNTL" },
211 { R200_SE_VF_CNTL
, "R200_SE_VF_CNTL" },
212 { R200_SE_VTX_FMT_0
, "R200_SE_VTX_FMT_0" },
213 { R200_SE_VTX_FMT_1
, "R200_SE_VTX_FMT_1" },
214 { R200_SE_TCL_OUTPUT_VTX_FMT_0
, "R200_SE_TCL_OUTPUT_VTX_FMT_0" },
215 { R200_SE_TCL_OUTPUT_VTX_FMT_1
, "R200_SE_TCL_OUTPUT_VTX_FMT_1" },
216 { R200_SE_VTE_CNTL
, "R200_SE_VTE_CNTL" },
217 { R200_SE_VTX_NUM_ARRAYS
, "R200_SE_VTX_NUM_ARRAYS" },
218 { R200_SE_VTX_AOS_ATTR01
, "R200_SE_VTX_AOS_ATTR01" },
219 { R200_SE_VTX_AOS_ADDR0
, "R200_SE_VTX_AOS_ADDR0" },
220 { R200_SE_VTX_AOS_ADDR1
, "R200_SE_VTX_AOS_ADDR1" },
221 { R200_SE_VTX_AOS_ATTR23
, "R200_SE_VTX_AOS_ATTR23" },
222 { R200_SE_VTX_AOS_ADDR2
, "R200_SE_VTX_AOS_ADDR2" },
223 { R200_SE_VTX_AOS_ADDR3
, "R200_SE_VTX_AOS_ADDR3" },
224 { R200_SE_VTX_AOS_ATTR45
, "R200_SE_VTX_AOS_ATTR45" },
225 { R200_SE_VTX_AOS_ADDR4
, "R200_SE_VTX_AOS_ADDR4" },
226 { R200_SE_VTX_AOS_ADDR5
, "R200_SE_VTX_AOS_ADDR5" },
227 { R200_SE_VTX_AOS_ATTR67
, "R200_SE_VTX_AOS_ATTR67" },
228 { R200_SE_VTX_AOS_ADDR6
, "R200_SE_VTX_AOS_ADDR6" },
229 { R200_SE_VTX_AOS_ADDR7
, "R200_SE_VTX_AOS_ADDR7" },
230 { R200_SE_VTX_AOS_ATTR89
, "R200_SE_VTX_AOS_ATTR89" },
231 { R200_SE_VTX_AOS_ADDR8
, "R200_SE_VTX_AOS_ADDR8" },
232 { R200_SE_VTX_AOS_ADDR9
, "R200_SE_VTX_AOS_ADDR9" },
233 { R200_SE_VTX_AOS_ATTR1011
, "R200_SE_VTX_AOS_ATTR1011" },
234 { R200_SE_VTX_AOS_ADDR10
, "R200_SE_VTX_AOS_ADDR10" },
235 { R200_SE_VTX_AOS_ADDR11
, "R200_SE_VTX_AOS_ADDR11" },
236 { R200_SE_VF_MAX_VTX_INDX
, "R200_SE_VF_MAX_VTX_INDX" },
237 { R200_SE_VF_MIN_VTX_INDX
, "R200_SE_VF_MIN_VTX_INDX" },
238 { R200_SE_VTX_STATE_CNTL
, "R200_SE_VTX_STATE_CNTL" },
239 { R200_SE_TCL_VECTOR_INDX_REG
, "R200_SE_TCL_VECTOR_INDX_REG" },
240 { R200_SE_TCL_VECTOR_DATA_REG
, "R200_SE_TCL_VECTOR_DATA_REG" },
241 { R200_SE_TCL_SCALAR_INDX_REG
, "R200_SE_TCL_SCALAR_INDX_REG" },
242 { R200_SE_TCL_SCALAR_DATA_REG
, "R200_SE_TCL_SCALAR_DATA_REG" },
243 { R200_SE_TCL_MATRIX_SEL_0
, "R200_SE_TCL_MATRIX_SEL_0" },
244 { R200_SE_TCL_MATRIX_SEL_1
, "R200_SE_TCL_MATRIX_SEL_1" },
245 { R200_SE_TCL_MATRIX_SEL_2
, "R200_SE_TCL_MATRIX_SEL_2" },
246 { R200_SE_TCL_MATRIX_SEL_3
, "R200_SE_TCL_MATRIX_SEL_3" },
247 { R200_SE_TCL_MATRIX_SEL_4
, "R200_SE_TCL_MATRIX_SEL_4" },
248 { R200_SE_TCL_LIGHT_MODEL_CTL_0
, "R200_SE_TCL_LIGHT_MODEL_CTL_0" },
249 { R200_SE_TCL_LIGHT_MODEL_CTL_1
, "R200_SE_TCL_LIGHT_MODEL_CTL_1" },
250 { R200_SE_TCL_PER_LIGHT_CTL_0
, "R200_SE_TCL_PER_LIGHT_CTL_0" },
251 { R200_SE_TCL_PER_LIGHT_CTL_1
, "R200_SE_TCL_PER_LIGHT_CTL_1" },
252 { R200_SE_TCL_PER_LIGHT_CTL_2
, "R200_SE_TCL_PER_LIGHT_CTL_2" },
253 { R200_SE_TCL_PER_LIGHT_CTL_3
, "R200_SE_TCL_PER_LIGHT_CTL_3" },
254 { R200_SE_TCL_TEX_PROC_CTL_2
, "R200_SE_TCL_TEX_PROC_CTL_2" },
255 { R200_SE_TCL_TEX_PROC_CTL_3
, "R200_SE_TCL_TEX_PROC_CTL_3" },
256 { R200_SE_TCL_TEX_PROC_CTL_0
, "R200_SE_TCL_TEX_PROC_CTL_0" },
257 { R200_SE_TCL_TEX_PROC_CTL_1
, "R200_SE_TCL_TEX_PROC_CTL_1" },
258 { R200_SE_TC_TEX_CYL_WRAP_CTL
, "R200_SE_TC_TEX_CYL_WRAP_CTL" },
259 { R200_SE_TCL_UCP_VERT_BLEND_CTL
, "R200_SE_TCL_UCP_VERT_BLEND_CTL" },
260 { R200_SE_TCL_POINT_SPRITE_CNTL
, "R200_SE_TCL_POINT_SPRITE_CNTL" },
261 { R200_SE_VTX_ST_POS_0_X_4
, "R200_SE_VTX_ST_POS_0_X_4" },
262 { R200_SE_VTX_ST_POS_0_Y_4
, "R200_SE_VTX_ST_POS_0_Y_4" },
263 { R200_SE_VTX_ST_POS_0_Z_4
, "R200_SE_VTX_ST_POS_0_Z_4" },
264 { R200_SE_VTX_ST_POS_0_W_4
, "R200_SE_VTX_ST_POS_0_W_4" },
265 { R200_SE_VTX_ST_NORM_0_X
, "R200_SE_VTX_ST_NORM_0_X" },
266 { R200_SE_VTX_ST_NORM_0_Y
, "R200_SE_VTX_ST_NORM_0_Y" },
267 { R200_SE_VTX_ST_NORM_0_Z
, "R200_SE_VTX_ST_NORM_0_Z" },
268 { R200_SE_VTX_ST_PVMS
, "R200_SE_VTX_ST_PVMS" },
269 { R200_SE_VTX_ST_CLR_0_R
, "R200_SE_VTX_ST_CLR_0_R" },
270 { R200_SE_VTX_ST_CLR_0_G
, "R200_SE_VTX_ST_CLR_0_G" },
271 { R200_SE_VTX_ST_CLR_0_B
, "R200_SE_VTX_ST_CLR_0_B" },
272 { R200_SE_VTX_ST_CLR_0_A
, "R200_SE_VTX_ST_CLR_0_A" },
273 { R200_SE_VTX_ST_CLR_1_R
, "R200_SE_VTX_ST_CLR_1_R" },
274 { R200_SE_VTX_ST_CLR_1_G
, "R200_SE_VTX_ST_CLR_1_G" },
275 { R200_SE_VTX_ST_CLR_1_B
, "R200_SE_VTX_ST_CLR_1_B" },
276 { R200_SE_VTX_ST_CLR_1_A
, "R200_SE_VTX_ST_CLR_1_A" },
277 { R200_SE_VTX_ST_CLR_2_R
, "R200_SE_VTX_ST_CLR_2_R" },
278 { R200_SE_VTX_ST_CLR_2_G
, "R200_SE_VTX_ST_CLR_2_G" },
279 { R200_SE_VTX_ST_CLR_2_B
, "R200_SE_VTX_ST_CLR_2_B" },
280 { R200_SE_VTX_ST_CLR_2_A
, "R200_SE_VTX_ST_CLR_2_A" },
281 { R200_SE_VTX_ST_CLR_3_R
, "R200_SE_VTX_ST_CLR_3_R" },
282 { R200_SE_VTX_ST_CLR_3_G
, "R200_SE_VTX_ST_CLR_3_G" },
283 { R200_SE_VTX_ST_CLR_3_B
, "R200_SE_VTX_ST_CLR_3_B" },
284 { R200_SE_VTX_ST_CLR_3_A
, "R200_SE_VTX_ST_CLR_3_A" },
285 { R200_SE_VTX_ST_CLR_4_R
, "R200_SE_VTX_ST_CLR_4_R" },
286 { R200_SE_VTX_ST_CLR_4_G
, "R200_SE_VTX_ST_CLR_4_G" },
287 { R200_SE_VTX_ST_CLR_4_B
, "R200_SE_VTX_ST_CLR_4_B" },
288 { R200_SE_VTX_ST_CLR_4_A
, "R200_SE_VTX_ST_CLR_4_A" },
289 { R200_SE_VTX_ST_CLR_5_R
, "R200_SE_VTX_ST_CLR_5_R" },
290 { R200_SE_VTX_ST_CLR_5_G
, "R200_SE_VTX_ST_CLR_5_G" },
291 { R200_SE_VTX_ST_CLR_5_B
, "R200_SE_VTX_ST_CLR_5_B" },
292 { R200_SE_VTX_ST_CLR_5_A
, "R200_SE_VTX_ST_CLR_5_A" },
293 { R200_SE_VTX_ST_CLR_6_R
, "R200_SE_VTX_ST_CLR_6_R" },
294 { R200_SE_VTX_ST_CLR_6_G
, "R200_SE_VTX_ST_CLR_6_G" },
295 { R200_SE_VTX_ST_CLR_6_B
, "R200_SE_VTX_ST_CLR_6_B" },
296 { R200_SE_VTX_ST_CLR_6_A
, "R200_SE_VTX_ST_CLR_6_A" },
297 { R200_SE_VTX_ST_CLR_7_R
, "R200_SE_VTX_ST_CLR_7_R" },
298 { R200_SE_VTX_ST_CLR_7_G
, "R200_SE_VTX_ST_CLR_7_G" },
299 { R200_SE_VTX_ST_CLR_7_B
, "R200_SE_VTX_ST_CLR_7_B" },
300 { R200_SE_VTX_ST_CLR_7_A
, "R200_SE_VTX_ST_CLR_7_A" },
301 { R200_SE_VTX_ST_TEX_0_S
, "R200_SE_VTX_ST_TEX_0_S" },
302 { R200_SE_VTX_ST_TEX_0_T
, "R200_SE_VTX_ST_TEX_0_T" },
303 { R200_SE_VTX_ST_TEX_0_R
, "R200_SE_VTX_ST_TEX_0_R" },
304 { R200_SE_VTX_ST_TEX_0_Q
, "R200_SE_VTX_ST_TEX_0_Q" },
305 { R200_SE_VTX_ST_TEX_1_S
, "R200_SE_VTX_ST_TEX_1_S" },
306 { R200_SE_VTX_ST_TEX_1_T
, "R200_SE_VTX_ST_TEX_1_T" },
307 { R200_SE_VTX_ST_TEX_1_R
, "R200_SE_VTX_ST_TEX_1_R" },
308 { R200_SE_VTX_ST_TEX_1_Q
, "R200_SE_VTX_ST_TEX_1_Q" },
309 { R200_SE_VTX_ST_TEX_2_S
, "R200_SE_VTX_ST_TEX_2_S" },
310 { R200_SE_VTX_ST_TEX_2_T
, "R200_SE_VTX_ST_TEX_2_T" },
311 { R200_SE_VTX_ST_TEX_2_R
, "R200_SE_VTX_ST_TEX_2_R" },
312 { R200_SE_VTX_ST_TEX_2_Q
, "R200_SE_VTX_ST_TEX_2_Q" },
313 { R200_SE_VTX_ST_TEX_3_S
, "R200_SE_VTX_ST_TEX_3_S" },
314 { R200_SE_VTX_ST_TEX_3_T
, "R200_SE_VTX_ST_TEX_3_T" },
315 { R200_SE_VTX_ST_TEX_3_R
, "R200_SE_VTX_ST_TEX_3_R" },
316 { R200_SE_VTX_ST_TEX_3_Q
, "R200_SE_VTX_ST_TEX_3_Q" },
317 { R200_SE_VTX_ST_TEX_4_S
, "R200_SE_VTX_ST_TEX_4_S" },
318 { R200_SE_VTX_ST_TEX_4_T
, "R200_SE_VTX_ST_TEX_4_T" },
319 { R200_SE_VTX_ST_TEX_4_R
, "R200_SE_VTX_ST_TEX_4_R" },
320 { R200_SE_VTX_ST_TEX_4_Q
, "R200_SE_VTX_ST_TEX_4_Q" },
321 { R200_SE_VTX_ST_TEX_5_S
, "R200_SE_VTX_ST_TEX_5_S" },
322 { R200_SE_VTX_ST_TEX_5_T
, "R200_SE_VTX_ST_TEX_5_T" },
323 { R200_SE_VTX_ST_TEX_5_R
, "R200_SE_VTX_ST_TEX_5_R" },
324 { R200_SE_VTX_ST_TEX_5_Q
, "R200_SE_VTX_ST_TEX_5_Q" },
325 { R200_SE_VTX_ST_PNT_SPRT_SZ
, "R200_SE_VTX_ST_PNT_SPRT_SZ" },
326 { R200_SE_VTX_ST_DISC_FOG
, "R200_SE_VTX_ST_DISC_FOG" },
327 { R200_SE_VTX_ST_SHININESS_0
, "R200_SE_VTX_ST_SHININESS_0" },
328 { R200_SE_VTX_ST_SHININESS_1
, "R200_SE_VTX_ST_SHININESS_1" },
329 { R200_SE_VTX_ST_BLND_WT_0
, "R200_SE_VTX_ST_BLND_WT_0" },
330 { R200_SE_VTX_ST_BLND_WT_1
, "R200_SE_VTX_ST_BLND_WT_1" },
331 { R200_SE_VTX_ST_BLND_WT_2
, "R200_SE_VTX_ST_BLND_WT_2" },
332 { R200_SE_VTX_ST_BLND_WT_3
, "R200_SE_VTX_ST_BLND_WT_3" },
333 { R200_SE_VTX_ST_POS_1_X
, "R200_SE_VTX_ST_POS_1_X" },
334 { R200_SE_VTX_ST_POS_1_Y
, "R200_SE_VTX_ST_POS_1_Y" },
335 { R200_SE_VTX_ST_POS_1_Z
, "R200_SE_VTX_ST_POS_1_Z" },
336 { R200_SE_VTX_ST_POS_1_W
, "R200_SE_VTX_ST_POS_1_W" },
337 { R200_SE_VTX_ST_NORM_1_X
, "R200_SE_VTX_ST_NORM_1_X" },
338 { R200_SE_VTX_ST_NORM_1_Y
, "R200_SE_VTX_ST_NORM_1_Y" },
339 { R200_SE_VTX_ST_NORM_1_Z
, "R200_SE_VTX_ST_NORM_1_Z" },
340 { R200_SE_VTX_ST_USR_CLR_0_R
, "R200_SE_VTX_ST_USR_CLR_0_R" },
341 { R200_SE_VTX_ST_USR_CLR_0_G
, "R200_SE_VTX_ST_USR_CLR_0_G" },
342 { R200_SE_VTX_ST_USR_CLR_0_B
, "R200_SE_VTX_ST_USR_CLR_0_B" },
343 { R200_SE_VTX_ST_USR_CLR_0_A
, "R200_SE_VTX_ST_USR_CLR_0_A" },
344 { R200_SE_VTX_ST_USR_CLR_1_R
, "R200_SE_VTX_ST_USR_CLR_1_R" },
345 { R200_SE_VTX_ST_USR_CLR_1_G
, "R200_SE_VTX_ST_USR_CLR_1_G" },
346 { R200_SE_VTX_ST_USR_CLR_1_B
, "R200_SE_VTX_ST_USR_CLR_1_B" },
347 { R200_SE_VTX_ST_USR_CLR_1_A
, "R200_SE_VTX_ST_USR_CLR_1_A" },
348 { R200_SE_VTX_ST_CLR_0_PKD
, "R200_SE_VTX_ST_CLR_0_PKD" },
349 { R200_SE_VTX_ST_CLR_1_PKD
, "R200_SE_VTX_ST_CLR_1_PKD" },
350 { R200_SE_VTX_ST_CLR_2_PKD
, "R200_SE_VTX_ST_CLR_2_PKD" },
351 { R200_SE_VTX_ST_CLR_3_PKD
, "R200_SE_VTX_ST_CLR_3_PKD" },
352 { R200_SE_VTX_ST_CLR_4_PKD
, "R200_SE_VTX_ST_CLR_4_PKD" },
353 { R200_SE_VTX_ST_CLR_5_PKD
, "R200_SE_VTX_ST_CLR_5_PKD" },
354 { R200_SE_VTX_ST_CLR_6_PKD
, "R200_SE_VTX_ST_CLR_6_PKD" },
355 { R200_SE_VTX_ST_CLR_7_PKD
, "R200_SE_VTX_ST_CLR_7_PKD" },
356 { R200_SE_VTX_ST_POS_0_X_2
, "R200_SE_VTX_ST_POS_0_X_2" },
357 { R200_SE_VTX_ST_POS_0_Y_2
, "R200_SE_VTX_ST_POS_0_Y_2" },
358 { R200_SE_VTX_ST_PAR_CLR_LD
, "R200_SE_VTX_ST_PAR_CLR_LD" },
359 { R200_SE_VTX_ST_USR_CLR_PKD
, "R200_SE_VTX_ST_USR_CLR_PKD" },
360 { R200_SE_VTX_ST_POS_0_X_3
, "R200_SE_VTX_ST_POS_0_X_3" },
361 { R200_SE_VTX_ST_POS_0_Y_3
, "R200_SE_VTX_ST_POS_0_Y_3" },
362 { R200_SE_VTX_ST_POS_0_Z_3
, "R200_SE_VTX_ST_POS_0_Z_3" },
363 { R200_SE_VTX_ST_END_OF_PKT
, "R200_SE_VTX_ST_END_OF_PKT" },
364 { R200_RE_POINTSIZE
, "R200_RE_POINTSIZE" },
365 { R200_RE_TOP_LEFT
, "R200_RE_TOP_LEFT" },
366 { R200_RE_AUX_SCISSOR_CNTL
, "R200_RE_AUX_SCISSOR_CNTL" },
367 { R200_PP_TXFILTER_0
, "R200_PP_TXFILTER_0" },
368 { R200_PP_TXFORMAT_0
, "R200_PP_TXFORMAT_0" },
369 { R200_PP_TXSIZE_0
, "R200_PP_TXSIZE_0" },
370 { R200_PP_TXFORMAT_X_0
, "R200_PP_TXFORMAT_X_0" },
371 { R200_PP_TXPITCH_0
, "R200_PP_TXPITCH_0" },
372 { R200_PP_BORDER_COLOR_0
, "R200_PP_BORDER_COLOR_0" },
373 { R200_PP_CUBIC_FACES_0
, "R200_PP_CUBIC_FACES_0" },
374 { R200_PP_TXMULTI_CTL_0
, "R200_PP_TXMULTI_CTL_0" },
375 { R200_PP_TXFILTER_1
, "R200_PP_TXFILTER_1" },
376 { R200_PP_TXFORMAT_1
, "R200_PP_TXFORMAT_1" },
377 { R200_PP_TXSIZE_1
, "R200_PP_TXSIZE_1" },
378 { R200_PP_TXFORMAT_X_1
, "R200_PP_TXFORMAT_X_1" },
379 { R200_PP_TXPITCH_1
, "R200_PP_TXPITCH_1" },
380 { R200_PP_BORDER_COLOR_1
, "R200_PP_BORDER_COLOR_1" },
381 { R200_PP_CUBIC_FACES_1
, "R200_PP_CUBIC_FACES_1" },
382 { R200_PP_TXMULTI_CTL_1
, "R200_PP_TXMULTI_CTL_1" },
383 { R200_PP_TXFILTER_2
, "R200_PP_TXFILTER_2" },
384 { R200_PP_TXFORMAT_2
, "R200_PP_TXFORMAT_2" },
385 { R200_PP_TXSIZE_2
, "R200_PP_TXSIZE_2" },
386 { R200_PP_TXFORMAT_X_2
, "R200_PP_TXFORMAT_X_2" },
387 { R200_PP_TXPITCH_2
, "R200_PP_TXPITCH_2" },
388 { R200_PP_BORDER_COLOR_2
, "R200_PP_BORDER_COLOR_2" },
389 { R200_PP_CUBIC_FACES_2
, "R200_PP_CUBIC_FACES_2" },
390 { R200_PP_TXMULTI_CTL_2
, "R200_PP_TXMULTI_CTL_2" },
391 { R200_PP_TXFILTER_3
, "R200_PP_TXFILTER_3" },
392 { R200_PP_TXFORMAT_3
, "R200_PP_TXFORMAT_3" },
393 { R200_PP_TXSIZE_3
, "R200_PP_TXSIZE_3" },
394 { R200_PP_TXFORMAT_X_3
, "R200_PP_TXFORMAT_X_3" },
395 { R200_PP_TXPITCH_3
, "R200_PP_TXPITCH_3" },
396 { R200_PP_BORDER_COLOR_3
, "R200_PP_BORDER_COLOR_3" },
397 { R200_PP_CUBIC_FACES_3
, "R200_PP_CUBIC_FACES_3" },
398 { R200_PP_TXMULTI_CTL_3
, "R200_PP_TXMULTI_CTL_3" },
399 { R200_PP_TXFILTER_4
, "R200_PP_TXFILTER_4" },
400 { R200_PP_TXFORMAT_4
, "R200_PP_TXFORMAT_4" },
401 { R200_PP_TXSIZE_4
, "R200_PP_TXSIZE_4" },
402 { R200_PP_TXFORMAT_X_4
, "R200_PP_TXFORMAT_X_4" },
403 { R200_PP_TXPITCH_4
, "R200_PP_TXPITCH_4" },
404 { R200_PP_BORDER_COLOR_4
, "R200_PP_BORDER_COLOR_4" },
405 { R200_PP_CUBIC_FACES_4
, "R200_PP_CUBIC_FACES_4" },
406 { R200_PP_TXMULTI_CTL_4
, "R200_PP_TXMULTI_CTL_4" },
407 { R200_PP_TXFILTER_5
, "R200_PP_TXFILTER_5" },
408 { R200_PP_TXFORMAT_5
, "R200_PP_TXFORMAT_5" },
409 { R200_PP_TXSIZE_5
, "R200_PP_TXSIZE_5" },
410 { R200_PP_TXFORMAT_X_5
, "R200_PP_TXFORMAT_X_5" },
411 { R200_PP_TXPITCH_5
, "R200_PP_TXPITCH_5" },
412 { R200_PP_BORDER_COLOR_5
, "R200_PP_BORDER_COLOR_5" },
413 { R200_PP_CUBIC_FACES_5
, "R200_PP_CUBIC_FACES_5" },
414 { R200_PP_TXMULTI_CTL_5
, "R200_PP_TXMULTI_CTL_5" },
415 { R200_PP_TXOFFSET_0
, "R200_PP_TXOFFSET_0" },
416 { R200_PP_CUBIC_OFFSET_F1_0
, "R200_PP_CUBIC_OFFSET_F1_0" },
417 { R200_PP_CUBIC_OFFSET_F2_0
, "R200_PP_CUBIC_OFFSET_F2_0" },
418 { R200_PP_CUBIC_OFFSET_F3_0
, "R200_PP_CUBIC_OFFSET_F3_0" },
419 { R200_PP_CUBIC_OFFSET_F4_0
, "R200_PP_CUBIC_OFFSET_F4_0" },
420 { R200_PP_CUBIC_OFFSET_F5_0
, "R200_PP_CUBIC_OFFSET_F5_0" },
421 { R200_PP_TXOFFSET_1
, "R200_PP_TXOFFSET_1" },
422 { R200_PP_CUBIC_OFFSET_F1_1
, "R200_PP_CUBIC_OFFSET_F1_1" },
423 { R200_PP_CUBIC_OFFSET_F2_1
, "R200_PP_CUBIC_OFFSET_F2_1" },
424 { R200_PP_CUBIC_OFFSET_F3_1
, "R200_PP_CUBIC_OFFSET_F3_1" },
425 { R200_PP_CUBIC_OFFSET_F4_1
, "R200_PP_CUBIC_OFFSET_F4_1" },
426 { R200_PP_CUBIC_OFFSET_F5_1
, "R200_PP_CUBIC_OFFSET_F5_1" },
427 { R200_PP_TXOFFSET_2
, "R200_PP_TXOFFSET_2" },
428 { R200_PP_CUBIC_OFFSET_F1_2
, "R200_PP_CUBIC_OFFSET_F1_2" },
429 { R200_PP_CUBIC_OFFSET_F2_2
, "R200_PP_CUBIC_OFFSET_F2_2" },
430 { R200_PP_CUBIC_OFFSET_F3_2
, "R200_PP_CUBIC_OFFSET_F3_2" },
431 { R200_PP_CUBIC_OFFSET_F4_2
, "R200_PP_CUBIC_OFFSET_F4_2" },
432 { R200_PP_CUBIC_OFFSET_F5_2
, "R200_PP_CUBIC_OFFSET_F5_2" },
433 { R200_PP_TXOFFSET_3
, "R200_PP_TXOFFSET_3" },
434 { R200_PP_CUBIC_OFFSET_F1_3
, "R200_PP_CUBIC_OFFSET_F1_3" },
435 { R200_PP_CUBIC_OFFSET_F2_3
, "R200_PP_CUBIC_OFFSET_F2_3" },
436 { R200_PP_CUBIC_OFFSET_F3_3
, "R200_PP_CUBIC_OFFSET_F3_3" },
437 { R200_PP_CUBIC_OFFSET_F4_3
, "R200_PP_CUBIC_OFFSET_F4_3" },
438 { R200_PP_CUBIC_OFFSET_F5_3
, "R200_PP_CUBIC_OFFSET_F5_3" },
439 { R200_PP_TXOFFSET_4
, "R200_PP_TXOFFSET_4" },
440 { R200_PP_CUBIC_OFFSET_F1_4
, "R200_PP_CUBIC_OFFSET_F1_4" },
441 { R200_PP_CUBIC_OFFSET_F2_4
, "R200_PP_CUBIC_OFFSET_F2_4" },
442 { R200_PP_CUBIC_OFFSET_F3_4
, "R200_PP_CUBIC_OFFSET_F3_4" },
443 { R200_PP_CUBIC_OFFSET_F4_4
, "R200_PP_CUBIC_OFFSET_F4_4" },
444 { R200_PP_CUBIC_OFFSET_F5_4
, "R200_PP_CUBIC_OFFSET_F5_4" },
445 { R200_PP_TXOFFSET_5
, "R200_PP_TXOFFSET_5" },
446 { R200_PP_CUBIC_OFFSET_F1_5
, "R200_PP_CUBIC_OFFSET_F1_5" },
447 { R200_PP_CUBIC_OFFSET_F2_5
, "R200_PP_CUBIC_OFFSET_F2_5" },
448 { R200_PP_CUBIC_OFFSET_F3_5
, "R200_PP_CUBIC_OFFSET_F3_5" },
449 { R200_PP_CUBIC_OFFSET_F4_5
, "R200_PP_CUBIC_OFFSET_F4_5" },
450 { R200_PP_CUBIC_OFFSET_F5_5
, "R200_PP_CUBIC_OFFSET_F5_5" },
451 { R200_PP_TAM_DEBUG3
, "R200_PP_TAM_DEBUG3" },
452 { R200_PP_TFACTOR_0
, "R200_PP_TFACTOR_0" },
453 { R200_PP_TFACTOR_1
, "R200_PP_TFACTOR_1" },
454 { R200_PP_TFACTOR_2
, "R200_PP_TFACTOR_2" },
455 { R200_PP_TFACTOR_3
, "R200_PP_TFACTOR_3" },
456 { R200_PP_TFACTOR_4
, "R200_PP_TFACTOR_4" },
457 { R200_PP_TFACTOR_5
, "R200_PP_TFACTOR_5" },
458 { R200_PP_TFACTOR_6
, "R200_PP_TFACTOR_6" },
459 { R200_PP_TFACTOR_7
, "R200_PP_TFACTOR_7" },
460 { R200_PP_TXCBLEND_0
, "R200_PP_TXCBLEND_0" },
461 { R200_PP_TXCBLEND2_0
, "R200_PP_TXCBLEND2_0" },
462 { R200_PP_TXABLEND_0
, "R200_PP_TXABLEND_0" },
463 { R200_PP_TXABLEND2_0
, "R200_PP_TXABLEND2_0" },
464 { R200_PP_TXCBLEND_1
, "R200_PP_TXCBLEND_1" },
465 { R200_PP_TXCBLEND2_1
, "R200_PP_TXCBLEND2_1" },
466 { R200_PP_TXABLEND_1
, "R200_PP_TXABLEND_1" },
467 { R200_PP_TXABLEND2_1
, "R200_PP_TXABLEND2_1" },
468 { R200_PP_TXCBLEND_2
, "R200_PP_TXCBLEND_2" },
469 { R200_PP_TXCBLEND2_2
, "R200_PP_TXCBLEND2_2" },
470 { R200_PP_TXABLEND_2
, "R200_PP_TXABLEND_2" },
471 { R200_PP_TXABLEND2_2
, "R200_PP_TXABLEND2_2" },
472 { R200_PP_TXCBLEND_3
, "R200_PP_TXCBLEND_3" },
473 { R200_PP_TXCBLEND2_3
, "R200_PP_TXCBLEND2_3" },
474 { R200_PP_TXABLEND_3
, "R200_PP_TXABLEND_3" },
475 { R200_PP_TXABLEND2_3
, "R200_PP_TXABLEND2_3" },
476 { R200_PP_TXCBLEND_4
, "R200_PP_TXCBLEND_4" },
477 { R200_PP_TXCBLEND2_4
, "R200_PP_TXCBLEND2_4" },
478 { R200_PP_TXABLEND_4
, "R200_PP_TXABLEND_4" },
479 { R200_PP_TXABLEND2_4
, "R200_PP_TXABLEND2_4" },
480 { R200_PP_TXCBLEND_5
, "R200_PP_TXCBLEND_5" },
481 { R200_PP_TXCBLEND2_5
, "R200_PP_TXCBLEND2_5" },
482 { R200_PP_TXABLEND_5
, "R200_PP_TXABLEND_5" },
483 { R200_PP_TXABLEND2_5
, "R200_PP_TXABLEND2_5" },
484 { R200_PP_TXCBLEND_6
, "R200_PP_TXCBLEND_6" },
485 { R200_PP_TXCBLEND2_6
, "R200_PP_TXCBLEND2_6" },
486 { R200_PP_TXABLEND_6
, "R200_PP_TXABLEND_6" },
487 { R200_PP_TXABLEND2_6
, "R200_PP_TXABLEND2_6" },
488 { R200_PP_TXCBLEND_7
, "R200_PP_TXCBLEND_7" },
489 { R200_PP_TXCBLEND2_7
, "R200_PP_TXCBLEND2_7" },
490 { R200_PP_TXABLEND_7
, "R200_PP_TXABLEND_7" },
491 { R200_PP_TXABLEND2_7
, "R200_PP_TXABLEND2_7" },
492 { R200_RB3D_BLENDCOLOR
, "R200_RB3D_BLENDCOLOR" },
493 { R200_RB3D_ABLENDCNTL
, "R200_RB3D_ABLENDCNTL" },
494 { R200_RB3D_CBLENDCNTL
, "R200_RB3D_CBLENDCNTL" },
495 { R200_SE_TCL_OUTPUT_VTX_COMP_SEL
, "R200_SE_TCL_OUTPUT_VTX_COMP_SEL" },
496 { R200_PP_CNTL_X
, "R200_PP_CNTL_X" },
497 { R200_SE_VAP_CNTL_STATUS
, "R200_SE_VAP_CNTL_STATUS" },
498 { R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0
, "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0" },
499 { R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_1
, "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_1" },
500 { R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_2
, "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_2" },
501 { R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_3
, "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_3" },
502 { R200_PP_TRI_PERF
, "R200_PP_TRI_PERF" },
503 { R200_PP_PERF_CNTL
, "R200_PP_PERF_CNTL" },
504 { R200_PP_TXCBLEND_8
, "R200_PP_TXCBLEND_8" },
505 { R200_PP_TXCBLEND2_8
, "R200_PP_TXCBLEND2_8" },
506 { R200_PP_TXABLEND_8
, "R200_PP_TXABLEND_8" },
507 { R200_PP_TXABLEND2_8
, "R200_PP_TXABLEND2_8" },
508 { R200_PP_TXCBLEND_9
, "R200_PP_TXCBLEND_9" },
509 { R200_PP_TXCBLEND2_9
, "R200_PP_TXCBLEND2_9" },
510 { R200_PP_TXABLEND_9
, "R200_PP_TXABLEND_9" },
511 { R200_PP_TXABLEND2_9
, "R200_PP_TXABLEND2_9" },
512 { R200_PP_TXCBLEND_10
, "R200_PP_TXCBLEND_10" },
513 { R200_PP_TXCBLEND2_10
, "R200_PP_TXCBLEND2_10" },
514 { R200_PP_TXABLEND_10
, "R200_PP_TXABLEND_10" },
515 { R200_PP_TXABLEND2_10
, "R200_PP_TXABLEND2_10" },
516 { R200_PP_TXCBLEND_11
, "R200_PP_TXCBLEND_11" },
517 { R200_PP_TXCBLEND2_11
, "R200_PP_TXCBLEND2_11" },
518 { R200_PP_TXABLEND_11
, "R200_PP_TXABLEND_11" },
519 { R200_PP_TXABLEND2_11
, "R200_PP_TXABLEND2_11" },
520 { R200_PP_TXCBLEND_12
, "R200_PP_TXCBLEND_12" },
521 { R200_PP_TXCBLEND2_12
, "R200_PP_TXCBLEND2_12" },
522 { R200_PP_TXABLEND_12
, "R200_PP_TXABLEND_12" },
523 { R200_PP_TXABLEND2_12
, "R200_PP_TXABLEND2_12" },
524 { R200_PP_TXCBLEND_13
, "R200_PP_TXCBLEND_13" },
525 { R200_PP_TXCBLEND2_13
, "R200_PP_TXCBLEND2_13" },
526 { R200_PP_TXABLEND_13
, "R200_PP_TXABLEND_13" },
527 { R200_PP_TXABLEND2_13
, "R200_PP_TXABLEND2_13" },
528 { R200_PP_TXCBLEND_14
, "R200_PP_TXCBLEND_14" },
529 { R200_PP_TXCBLEND2_14
, "R200_PP_TXCBLEND2_14" },
530 { R200_PP_TXABLEND_14
, "R200_PP_TXABLEND_14" },
531 { R200_PP_TXABLEND2_14
, "R200_PP_TXABLEND2_14" },
532 { R200_PP_TXCBLEND_15
, "R200_PP_TXCBLEND_15" },
533 { R200_PP_TXCBLEND2_15
, "R200_PP_TXCBLEND2_15" },
534 { R200_PP_TXABLEND_15
, "R200_PP_TXABLEND_15" },
535 { R200_PP_TXABLEND2_15
, "R200_PP_TXABLEND2_15" },
536 { R200_VAP_PVS_CNTL_1
, "R200_VAP_PVS_CNTL_1" },
537 { R200_VAP_PVS_CNTL_2
, "R200_VAP_PVS_CNTL_2" },
540 static struct reg_names scalar_names
[] = {
541 { R200_SS_LIGHT_DCD_ADDR
, "R200_SS_LIGHT_DCD_ADDR" },
542 { R200_SS_LIGHT_DCM_ADDR
, "R200_SS_LIGHT_DCM_ADDR" },
543 { R200_SS_LIGHT_SPOT_EXPONENT_ADDR
, "R200_SS_LIGHT_SPOT_EXPONENT_ADDR" },
544 { R200_SS_LIGHT_SPOT_CUTOFF_ADDR
, "R200_SS_LIGHT_SPOT_CUTOFF_ADDR" },
545 { R200_SS_LIGHT_SPECULAR_THRESH_ADDR
, "R200_SS_LIGHT_SPECULAR_THRESH_ADDR" },
546 { R200_SS_LIGHT_RANGE_CUTOFF_SQRD
, "R200_SS_LIGHT_RANGE_CUTOFF_SQRD" },
547 { R200_SS_LIGHT_RANGE_ATT_CONST
, "R200_SS_LIGHT_RANGE_ATT_CONST" },
548 { R200_SS_VERT_GUARD_CLIP_ADJ_ADDR
, "R200_SS_VERT_GUARD_CLIP_ADJ_ADDR" },
549 { R200_SS_VERT_GUARD_DISCARD_ADJ_ADDR
, "R200_SS_VERT_GUARD_DISCARD_ADJ_ADDR" },
550 { R200_SS_HORZ_GUARD_CLIP_ADJ_ADDR
, "R200_SS_HORZ_GUARD_CLIP_ADJ_ADDR" },
551 { R200_SS_HORZ_GUARD_DISCARD_ADJ_ADDR
, "R200_SS_HORZ_GUARD_DISCARD_ADJ_ADDR" },
552 { R200_SS_MAT_0_SHININESS
, "R200_SS_MAT_0_SHININESS" },
553 { R200_SS_MAT_1_SHININESS
, "R200_SS_MAT_1_SHININESS" },
557 /* Puff these out to make them look like normal (dword) registers.
559 static struct reg_names vector_names
[] = {
561 { R200_VS_LIGHT_AMBIENT_ADDR
, "R200_VS_LIGHT_AMBIENT_ADDR" },
562 { R200_VS_LIGHT_DIFFUSE_ADDR
, "R200_VS_LIGHT_DIFFUSE_ADDR" },
563 { R200_VS_LIGHT_SPECULAR_ADDR
, "R200_VS_LIGHT_SPECULAR_ADDR" },
564 { R200_VS_LIGHT_DIRPOS_ADDR
, "R200_VS_LIGHT_DIRPOS_ADDR" },
565 { R200_VS_LIGHT_HWVSPOT_ADDR
, "R200_VS_LIGHT_HWVSPOT_ADDR" },
566 { R200_VS_LIGHT_ATTENUATION_ADDR
, "R200_VS_LIGHT_ATTENUATION_ADDR" },
567 { R200_VS_SPOT_DUAL_CONE
, "R200_VS_SPOT_DUAL_CONE" },
568 { R200_VS_GLOBAL_AMBIENT_ADDR
, "R200_VS_GLOBAL_AMBIENT_ADDR" },
569 { R200_VS_FOG_PARAM_ADDR
, "R200_VS_FOG_PARAM_ADDR" },
570 { R200_VS_EYE_VECTOR_ADDR
, "R200_VS_EYE_VECTOR_ADDR" },
571 { R200_VS_UCP_ADDR
, "R200_VS_UCP_ADDR" },
572 { R200_VS_PNT_SPRITE_VPORT_SCALE
, "R200_VS_PNT_SPRITE_VPORT_SCALE" },
573 { R200_VS_MATRIX_0_MV
, "R200_VS_MATRIX_0_MV" },
574 { R200_VS_MATRIX_1_INV_MV
, "R200_VS_MATRIX_1_INV_MV" },
575 { R200_VS_MATRIX_2_MVP
, "R200_VS_MATRIX_2_MVP" },
576 { R200_VS_MATRIX_3_TEX0
, "R200_VS_MATRIX_3_TEX0" },
577 { R200_VS_MATRIX_4_TEX1
, "R200_VS_MATRIX_4_TEX1" },
578 { R200_VS_MATRIX_5_TEX2
, "R200_VS_MATRIX_5_TEX2" },
579 { R200_VS_MATRIX_6_TEX3
, "R200_VS_MATRIX_6_TEX3" },
580 { R200_VS_MATRIX_7_TEX4
, "R200_VS_MATRIX_7_TEX4" },
581 { R200_VS_MATRIX_8_TEX5
, "R200_VS_MATRIX_8_TEX5" },
582 { R200_VS_MAT_0_EMISS
, "R200_VS_MAT_0_EMISS" },
583 { R200_VS_MAT_0_AMB
, "R200_VS_MAT_0_AMB" },
584 { R200_VS_MAT_0_DIF
, "R200_VS_MAT_0_DIF" },
585 { R200_VS_MAT_0_SPEC
, "R200_VS_MAT_0_SPEC" },
586 { R200_VS_MAT_1_EMISS
, "R200_VS_MAT_1_EMISS" },
587 { R200_VS_MAT_1_AMB
, "R200_VS_MAT_1_AMB" },
588 { R200_VS_MAT_1_DIF
, "R200_VS_MAT_1_DIF" },
589 { R200_VS_MAT_1_SPEC
, "R200_VS_MAT_1_SPEC" },
590 { R200_VS_EYE2CLIP_MTX
, "R200_VS_EYE2CLIP_MTX" },
591 { R200_VS_PNT_SPRITE_ATT_CONST
, "R200_VS_PNT_SPRITE_ATT_CONST" },
592 { R200_VS_PNT_SPRITE_EYE_IN_MODEL
, "R200_VS_PNT_SPRITE_EYE_IN_MODEL" },
593 { R200_VS_PNT_SPRITE_CLAMP
, "R200_VS_PNT_SPRITE_CLAMP" },
594 { R200_VS_MAX
, "R200_VS_MAX" },
598 union fi
{ float f
; int i
; };
606 struct reg_names
*closest
;
616 static struct reg regs
[Elements(reg_names
)+1];
617 static struct reg scalars
[512+1];
618 static struct reg vectors
[512*4+1];
620 static int total
, total_changed
, bufs
;
622 static void init_regs( void )
624 struct reg_names
*tmp
;
627 for (i
= 0 ; i
< Elements(regs
) ; i
++) {
628 regs
[i
].idx
= reg_names
[i
].idx
;
629 regs
[i
].closest
= ®_names
[i
];
633 for (i
= 0, tmp
= scalar_names
; i
< Elements(scalars
) ; i
++) {
634 if (tmp
[1].idx
== i
) tmp
++;
636 scalars
[i
].closest
= tmp
;
637 scalars
[i
].flags
= ISFLOAT
;
640 for (i
= 0, tmp
= vector_names
; i
< Elements(vectors
) ; i
++) {
641 if (tmp
[1].idx
*4 == i
) tmp
++;
643 vectors
[i
].closest
= tmp
;
644 vectors
[i
].flags
= ISFLOAT
|ISVEC
;
647 regs
[Elements(regs
)-1].idx
= -1;
648 scalars
[Elements(scalars
)-1].idx
= -1;
649 vectors
[Elements(vectors
)-1].idx
= -1;
652 static int find_or_add_value( struct reg
*reg
, int val
)
656 for ( j
= 0 ; j
< reg
->nvalues
; j
++)
657 if ( val
== reg
->values
[j
].i
)
660 if (j
== reg
->nalloc
) {
663 reg
->values
= (union fi
*) realloc( reg
->values
,
664 reg
->nalloc
* sizeof(union fi
) );
667 reg
->values
[reg
->nvalues
++].i
= val
;
671 static struct reg
*lookup_reg( struct reg
*tab
, int reg
)
675 for (i
= 0 ; tab
[i
].idx
!= -1 ; i
++) {
676 if (tab
[i
].idx
== reg
)
680 fprintf(stderr
, "*** unknown reg 0x%x\n", reg
);
685 static const char *get_reg_name( struct reg
*reg
)
689 if (reg
->idx
== reg
->closest
->idx
)
690 return reg
->closest
->name
;
693 if (reg
->flags
& ISVEC
) {
694 if (reg
->idx
/4 != reg
->closest
->idx
)
695 sprintf(tmp
, "%s+%d[%d]",
697 (reg
->idx
/4) - reg
->closest
->idx
,
700 sprintf(tmp
, "%s[%d]", reg
->closest
->name
, reg
->idx
%4);
703 if (reg
->idx
!= reg
->closest
->idx
)
704 sprintf(tmp
, "%s+%d", reg
->closest
->name
, reg
->idx
- reg
->closest
->idx
);
706 sprintf(tmp
, "%s", reg
->closest
->name
);
712 static int print_int_reg_assignment( struct reg
*reg
, int data
)
714 int changed
= (reg
->current
.i
!= data
);
715 int ever_seen
= find_or_add_value( reg
, data
);
717 if (VERBOSE
|| (NORMAL
&& (changed
|| !ever_seen
)))
718 fprintf(stderr
, " %s <-- 0x%x", get_reg_name(reg
), data
);
722 fprintf(stderr
, " *** BRAND NEW VALUE");
724 fprintf(stderr
, " *** CHANGED");
727 reg
->current
.i
= data
;
729 if (VERBOSE
|| (NORMAL
&& (changed
|| !ever_seen
)))
730 fprintf(stderr
, "\n");
736 static int print_float_reg_assignment( struct reg
*reg
, float data
)
738 int changed
= (reg
->current
.f
!= data
);
739 int newmin
= (data
< reg
->vmin
);
740 int newmax
= (data
> reg
->vmax
);
742 if (VERBOSE
|| (NORMAL
&& (newmin
|| newmax
|| changed
)))
743 fprintf(stderr
, " %s <-- %.3f", get_reg_name(reg
), data
);
747 fprintf(stderr
, " *** NEW MIN (prev %.3f)", reg
->vmin
);
751 fprintf(stderr
, " *** NEW MAX (prev %.3f)", reg
->vmax
);
755 fprintf(stderr
, " *** CHANGED");
759 reg
->current
.f
= data
;
761 if (VERBOSE
|| (NORMAL
&& (newmin
|| newmax
|| changed
)))
762 fprintf(stderr
, "\n");
767 static int print_reg_assignment( struct reg
*reg
, int data
)
769 float_ui32_type datau
;
771 reg
->flags
|= TOUCHED
;
772 if (reg
->flags
& ISFLOAT
)
773 return print_float_reg_assignment( reg
, datau
.f
);
775 return print_int_reg_assignment( reg
, data
);
778 static void print_reg( struct reg
*reg
)
780 if (reg
->flags
& TOUCHED
) {
781 if (reg
->flags
& ISFLOAT
) {
782 fprintf(stderr
, " %s == %f\n", get_reg_name(reg
), reg
->current
.f
);
784 fprintf(stderr
, " %s == 0x%x\n", get_reg_name(reg
), reg
->current
.i
);
790 static void dump_state( void )
794 for (i
= 0 ; i
< Elements(regs
) ; i
++)
795 print_reg( ®s
[i
] );
797 for (i
= 0 ; i
< Elements(scalars
) ; i
++)
798 print_reg( &scalars
[i
] );
800 for (i
= 0 ; i
< Elements(vectors
) ; i
++)
801 print_reg( &vectors
[i
] );
806 static int radeon_emit_packets(
807 drm_radeon_cmd_header_t header
,
808 drm_radeon_cmd_buffer_t
*cmdbuf
)
810 int id
= (int)header
.packet
.packet_id
;
811 int sz
= packet
[id
].len
;
812 int *data
= (int *)cmdbuf
->buf
;
815 if (sz
* sizeof(int) > cmdbuf
->bufsz
) {
816 fprintf(stderr
, "Packet overflows cmdbuf\n");
820 if (!packet
[id
].name
) {
821 fprintf(stderr
, "*** Unknown packet 0 nr %d\n", id
);
827 fprintf(stderr
, "Packet 0 reg %s nr %d\n", packet
[id
].name
, sz
);
829 for ( i
= 0 ; i
< sz
; i
++) {
830 struct reg
*reg
= lookup_reg( regs
, packet
[id
].start
+ i
*4 );
831 if (print_reg_assignment( reg
, data
[i
] ))
836 cmdbuf
->buf
+= sz
* sizeof(int);
837 cmdbuf
->bufsz
-= sz
* sizeof(int);
842 static int radeon_emit_scalars(
843 drm_radeon_cmd_header_t header
,
844 drm_radeon_cmd_buffer_t
*cmdbuf
)
846 int sz
= header
.scalars
.count
;
847 int *data
= (int *)cmdbuf
->buf
;
848 int start
= header
.scalars
.offset
;
849 int stride
= header
.scalars
.stride
;
853 fprintf(stderr
, "emit scalars, start %d stride %d nr %d (end %d)\n",
854 start
, stride
, sz
, start
+ stride
* sz
);
857 for (i
= 0 ; i
< sz
; i
++, start
+= stride
) {
858 struct reg
*reg
= lookup_reg( scalars
, start
);
859 if (print_reg_assignment( reg
, data
[i
] ))
864 cmdbuf
->buf
+= sz
* sizeof(int);
865 cmdbuf
->bufsz
-= sz
* sizeof(int);
870 static int radeon_emit_scalars2(
871 drm_radeon_cmd_header_t header
,
872 drm_radeon_cmd_buffer_t
*cmdbuf
)
874 int sz
= header
.scalars
.count
;
875 int *data
= (int *)cmdbuf
->buf
;
876 int start
= header
.scalars
.offset
+ 0x100;
877 int stride
= header
.scalars
.stride
;
881 fprintf(stderr
, "emit scalars2, start %d stride %d nr %d (end %d)\n",
882 start
, stride
, sz
, start
+ stride
* sz
);
884 if (start
+ stride
* sz
> 258) {
885 fprintf(stderr
, "emit scalars OVERFLOW %d/%d/%d\n", start
, stride
, sz
);
889 for (i
= 0 ; i
< sz
; i
++, start
+= stride
) {
890 struct reg
*reg
= lookup_reg( scalars
, start
);
891 if (print_reg_assignment( reg
, data
[i
] ))
896 cmdbuf
->buf
+= sz
* sizeof(int);
897 cmdbuf
->bufsz
-= sz
* sizeof(int);
901 /* Check: inf/nan/extreme-size?
902 * Check: table start, end, nr, etc.
904 static int radeon_emit_vectors(
905 drm_radeon_cmd_header_t header
,
906 drm_radeon_cmd_buffer_t
*cmdbuf
)
908 int sz
= header
.vectors
.count
;
909 int *data
= (int *)cmdbuf
->buf
;
910 int start
= header
.vectors
.offset
;
911 int stride
= header
.vectors
.stride
;
915 fprintf(stderr
, "emit vectors, start %d stride %d nr %d (end %d) (0x%x)\n",
916 start
, stride
, sz
, start
+ stride
* sz
, header
.i
);
918 /* if (start + stride * (sz/4) > 128) { */
919 /* fprintf(stderr, "emit vectors OVERFLOW %d/%d/%d\n", start, stride, sz); */
923 for (i
= 0 ; i
< sz
; start
+= stride
) {
925 for (j
= 0 ; j
< 4 ; i
++,j
++) {
926 struct reg
*reg
= lookup_reg( vectors
, start
*4+j
);
927 if (print_reg_assignment( reg
, data
[i
] ))
936 cmdbuf
->buf
+= sz
* sizeof(int);
937 cmdbuf
->bufsz
-= sz
* sizeof(int);
941 static int radeon_emit_veclinear(
942 drm_radeon_cmd_header_t header
,
943 drm_radeon_cmd_buffer_t
*cmdbuf
)
945 int sz
= header
.veclinear
.count
* 4;
946 int *data
= (int *)cmdbuf
->buf
;
947 float *fdata
=(float *)cmdbuf
->buf
;
948 int start
= header
.veclinear
.addr_lo
| (header
.veclinear
.addr_hi
<< 8);
952 fprintf(stderr
, "emit vectors linear, start %d nr %d (end %d) (0x%x)\n",
953 start
, sz
>> 2, start
+ (sz
>> 2), header
.i
);
957 for (i
= 0 ; i
< sz
; i
+= 4) {
958 fprintf(stderr
, "R200_VS_PARAM %d 0 %f\n", (i
>> 2) + start
, fdata
[i
]);
959 fprintf(stderr
, "R200_VS_PARAM %d 1 %f\n", (i
>> 2) + start
, fdata
[i
+1]);
960 fprintf(stderr
, "R200_VS_PARAM %d 2 %f\n", (i
>> 2) + start
, fdata
[i
+2]);
961 fprintf(stderr
, "R200_VS_PARAM %d 3 %f\n", (i
>> 2) + start
, fdata
[i
+3]);
964 else if ((start
>= 0x100) && (start
< 0x160)) {
965 for (i
= 0 ; i
< sz
; i
+= 4) {
966 fprintf(stderr
, "R200_VS_PARAM %d 0 %f\n", (i
>> 2) + start
- 0x100 + 0x60, fdata
[i
]);
967 fprintf(stderr
, "R200_VS_PARAM %d 1 %f\n", (i
>> 2) + start
- 0x100 + 0x60, fdata
[i
+1]);
968 fprintf(stderr
, "R200_VS_PARAM %d 2 %f\n", (i
>> 2) + start
- 0x100 + 0x60, fdata
[i
+2]);
969 fprintf(stderr
, "R200_VS_PARAM %d 3 %f\n", (i
>> 2) + start
- 0x100 + 0x60, fdata
[i
+3]);
972 else if ((start
>= 0x80) && (start
< 0xc0)) {
973 for (i
= 0 ; i
< sz
; i
+= 4) {
974 fprintf(stderr
, "R200_VS_PROG %d OPDST %08x\n", (i
>> 2) + start
- 0x80, data
[i
]);
975 fprintf(stderr
, "R200_VS_PROG %d SRC1 %08x\n", (i
>> 2) + start
- 0x80, data
[i
+1]);
976 fprintf(stderr
, "R200_VS_PROG %d SRC2 %08x\n", (i
>> 2) + start
- 0x80, data
[i
+2]);
977 fprintf(stderr
, "R200_VS_PROG %d SRC3 %08x\n", (i
>> 2) + start
- 0x80, data
[i
+3]);
980 else if ((start
>= 0x180) && (start
< 0x1c0)) {
981 for (i
= 0 ; i
< sz
; i
+= 4) {
982 fprintf(stderr
, "R200_VS_PROG %d OPDST %08x\n", (i
>> 2) + start
- 0x180 + 0x40, data
[i
]);
983 fprintf(stderr
, "R200_VS_PROG %d SRC1 %08x\n", (i
>> 2) + start
- 0x180 + 0x40, data
[i
+1]);
984 fprintf(stderr
, "R200_VS_PROG %d SRC2 %08x\n", (i
>> 2) + start
- 0x180 + 0x40, data
[i
+2]);
985 fprintf(stderr
, "R200_VS_PROG %d SRC3 %08x\n", (i
>> 2) + start
- 0x180 + 0x40, data
[i
+3]);
989 fprintf(stderr
, "write to unknown vector area\n");
992 cmdbuf
->buf
+= sz
* sizeof(int);
993 cmdbuf
->bufsz
-= sz
* sizeof(int);
998 static int print_vertex_format( int vfmt
)
1001 fprintf(stderr
, " %s(%x): %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
1005 (vfmt
& R200_VTX_Z0
) ? "z," : "",
1006 (vfmt
& R200_VTX_W0
) ? "w0," : "",
1007 (vfmt
& R200_VTX_FPCOLOR
) ? "fpcolor," : "",
1008 (vfmt
& R200_VTX_FPALPHA
) ? "fpalpha," : "",
1009 (vfmt
& R200_VTX_PKCOLOR
) ? "pkcolor," : "",
1010 (vfmt
& R200_VTX_FPSPEC
) ? "fpspec," : "",
1011 (vfmt
& R200_VTX_FPFOG
) ? "fpfog," : "",
1012 (vfmt
& R200_VTX_PKSPEC
) ? "pkspec," : "",
1013 (vfmt
& R200_VTX_ST0
) ? "st0," : "",
1014 (vfmt
& R200_VTX_ST1
) ? "st1," : "",
1015 (vfmt
& R200_VTX_Q1
) ? "q1," : "",
1016 (vfmt
& R200_VTX_ST2
) ? "st2," : "",
1017 (vfmt
& R200_VTX_Q2
) ? "q2," : "",
1018 (vfmt
& R200_VTX_ST3
) ? "st3," : "",
1019 (vfmt
& R200_VTX_Q3
) ? "q3," : "",
1020 (vfmt
& R200_VTX_Q0
) ? "q0," : "",
1021 (vfmt
& R200_VTX_N0
) ? "n0," : "",
1022 (vfmt
& R200_VTX_XY1
) ? "xy1," : "",
1023 (vfmt
& R200_VTX_Z1
) ? "z1," : "",
1024 (vfmt
& R200_VTX_W1
) ? "w1," : "",
1025 (vfmt
& R200_VTX_N1
) ? "n1," : "");
1028 if (!find_or_add_value( &others
[V_VTXFMT
], vfmt
))
1029 fprintf(stderr
, " *** NEW VALUE");
1031 fprintf(stderr
, "\n");
1038 static char *primname
[0x10] = {
1057 static int print_prim_and_flags( int prim
)
1062 fprintf(stderr
, " %s(%x): %s%s%s%s%s%s\n",
1065 ((prim
& 0x30) == R200_VF_PRIM_WALK_IND
) ? "IND," : "",
1066 ((prim
& 0x30) == R200_VF_PRIM_WALK_LIST
) ? "LIST," : "",
1067 ((prim
& 0x30) == R200_VF_PRIM_WALK_RING
) ? "RING," : "",
1068 (prim
& R200_VF_COLOR_ORDER_RGBA
) ? "RGBA," : "BGRA, ",
1069 (prim
& R200_VF_INDEX_SZ_4
) ? "INDX-32," : "",
1070 (prim
& R200_VF_TCL_OUTPUT_VTX_ENABLE
) ? "TCL_OUT_VTX," : "");
1072 numverts
= prim
>>16;
1075 fprintf(stderr
, " prim: %s numverts %d\n", primname
[prim
&0xf], numverts
);
1077 switch (prim
& 0xf) {
1078 case R200_VF_PRIM_NONE
:
1079 case R200_VF_PRIM_POINTS
:
1081 fprintf(stderr
, "Bad nr verts for line %d\n", numverts
);
1085 case R200_VF_PRIM_LINES
:
1086 case R200_VF_PRIM_POINT_SPRITES
:
1087 if ((numverts
& 1) || numverts
== 0) {
1088 fprintf(stderr
, "Bad nr verts for line %d\n", numverts
);
1092 case R200_VF_PRIM_LINE_STRIP
:
1093 case R200_VF_PRIM_LINE_LOOP
:
1095 fprintf(stderr
, "Bad nr verts for line_strip %d\n", numverts
);
1099 case R200_VF_PRIM_TRIANGLES
:
1100 case R200_VF_PRIM_3VRT_POINTS
:
1101 case R200_VF_PRIM_3VRT_LINES
:
1102 case R200_VF_PRIM_RECT_LIST
:
1103 if (numverts
% 3 || numverts
== 0) {
1104 fprintf(stderr
, "Bad nr verts for tri %d\n", numverts
);
1108 case R200_VF_PRIM_TRIANGLE_FAN
:
1109 case R200_VF_PRIM_TRIANGLE_STRIP
:
1110 case R200_VF_PRIM_POLYGON
:
1112 fprintf(stderr
, "Bad nr verts for strip/fan %d\n", numverts
);
1116 case R200_VF_PRIM_QUADS
:
1117 if (numverts
% 4 || numverts
== 0) {
1118 fprintf(stderr
, "Bad nr verts for quad %d\n", numverts
);
1122 case R200_VF_PRIM_QUAD_STRIP
:
1123 if (numverts
% 2 || numverts
< 4) {
1124 fprintf(stderr
, "Bad nr verts for quadstrip %d\n", numverts
);
1129 fprintf(stderr
, "Bad primitive\n");
1135 /* build in knowledge about each packet type
1137 static int radeon_emit_packet3( drm_radeon_cmd_buffer_t
*cmdbuf
)
1140 int *cmd
= (int *)cmdbuf
->buf
;
1142 int i
, stride
, size
, start
;
1144 cmdsz
= 2 + ((cmd
[0] & RADEON_CP_PACKET_COUNT_MASK
) >> 16);
1146 if ((cmd
[0] & RADEON_CP_PACKET_MASK
) != RADEON_CP_PACKET3
||
1147 cmdsz
* 4 > cmdbuf
->bufsz
||
1148 cmdsz
> RADEON_CP_PACKET_MAX_DWORDS
) {
1149 fprintf(stderr
, "Bad packet\n");
1153 switch( cmd
[0] & ~RADEON_CP_PACKET_COUNT_MASK
) {
1154 case R200_CP_CMD_NOP
:
1156 fprintf(stderr
, "PACKET3_NOP, %d dwords\n", cmdsz
);
1158 case R200_CP_CMD_NEXT_CHAR
:
1160 fprintf(stderr
, "PACKET3_NEXT_CHAR, %d dwords\n", cmdsz
);
1162 case R200_CP_CMD_PLY_NEXTSCAN
:
1164 fprintf(stderr
, "PACKET3_PLY_NEXTSCAN, %d dwords\n", cmdsz
);
1166 case R200_CP_CMD_SET_SCISSORS
:
1168 fprintf(stderr
, "PACKET3_SET_SCISSORS, %d dwords\n", cmdsz
);
1170 case R200_CP_CMD_LOAD_MICROCODE
:
1172 fprintf(stderr
, "PACKET3_LOAD_MICROCODE, %d dwords\n", cmdsz
);
1174 case R200_CP_CMD_WAIT_FOR_IDLE
:
1176 fprintf(stderr
, "PACKET3_WAIT_FOR_IDLE, %d dwords\n", cmdsz
);
1179 case R200_CP_CMD_3D_DRAW_VBUF
:
1181 fprintf(stderr
, "PACKET3_3D_DRAW_VBUF, %d dwords\n", cmdsz
);
1182 /* print_vertex_format(cmd[1]); */
1183 if (print_prim_and_flags(cmd
[2]))
1187 case R200_CP_CMD_3D_DRAW_IMMD
:
1189 fprintf(stderr
, "PACKET3_3D_DRAW_IMMD, %d dwords\n", cmdsz
);
1191 case R200_CP_CMD_3D_DRAW_INDX
: {
1194 fprintf(stderr
, "PACKET3_3D_DRAW_INDX, %d dwords\n", cmdsz
);
1195 /* print_vertex_format(cmd[1]); */
1196 if (print_prim_and_flags(cmd
[2]))
1198 neltdwords
= cmd
[2]>>16;
1199 neltdwords
+= neltdwords
& 1;
1201 if (neltdwords
+ 3 != cmdsz
)
1202 fprintf(stderr
, "Mismatch in DRAW_INDX, %d vs cmdsz %d\n",
1206 case R200_CP_CMD_LOAD_PALETTE
:
1208 fprintf(stderr
, "PACKET3_LOAD_PALETTE, %d dwords\n", cmdsz
);
1210 case R200_CP_CMD_3D_LOAD_VBPNTR
:
1212 fprintf(stderr
, "PACKET3_3D_LOAD_VBPNTR, %d dwords\n", cmdsz
);
1213 fprintf(stderr
, " nr arrays: %d\n", cmd
[1]);
1216 if (((cmd
[1]/2)*3) + ((cmd
[1]%2)*2) != cmdsz
- 2) {
1217 fprintf(stderr
, " ****** MISMATCH %d/%d *******\n",
1218 ((cmd
[1]/2)*3) + ((cmd
[1]%2)*2) + 2, cmdsz
);
1224 for (i
= 0 ; i
< cmd
[1] ; i
++) {
1226 stride
= (tmp
[0]>>24) & 0xff;
1227 size
= (tmp
[0]>>16) & 0xff;
1232 stride
= (tmp
[0]>>8) & 0xff;
1233 size
= (tmp
[0]) & 0xff;
1236 fprintf(stderr
, " array %d: start 0x%x vsize %d vstride %d\n",
1237 i
, start
, size
, stride
);
1241 case R200_CP_CMD_PAINT
:
1243 fprintf(stderr
, "PACKET3_CNTL_PAINT, %d dwords\n", cmdsz
);
1245 case R200_CP_CMD_BITBLT
:
1247 fprintf(stderr
, "PACKET3_CNTL_BITBLT, %d dwords\n", cmdsz
);
1249 case R200_CP_CMD_SMALLTEXT
:
1251 fprintf(stderr
, "PACKET3_CNTL_SMALLTEXT, %d dwords\n", cmdsz
);
1253 case R200_CP_CMD_HOSTDATA_BLT
:
1255 fprintf(stderr
, "PACKET3_CNTL_HOSTDATA_BLT, %d dwords\n",
1258 case R200_CP_CMD_POLYLINE
:
1260 fprintf(stderr
, "PACKET3_CNTL_POLYLINE, %d dwords\n", cmdsz
);
1262 case R200_CP_CMD_POLYSCANLINES
:
1264 fprintf(stderr
, "PACKET3_CNTL_POLYSCANLINES, %d dwords\n",
1267 case R200_CP_CMD_PAINT_MULTI
:
1269 fprintf(stderr
, "PACKET3_CNTL_PAINT_MULTI, %d dwords\n",
1272 case R200_CP_CMD_BITBLT_MULTI
:
1274 fprintf(stderr
, "PACKET3_CNTL_BITBLT_MULTI, %d dwords\n",
1277 case R200_CP_CMD_TRANS_BITBLT
:
1279 fprintf(stderr
, "PACKET3_CNTL_TRANS_BITBLT, %d dwords\n",
1282 case R200_CP_CMD_3D_DRAW_VBUF_2
:
1284 fprintf(stderr
, "R200_CP_CMD_3D_DRAW_VBUF_2, %d dwords\n",
1286 if (print_prim_and_flags(cmd
[1]))
1289 case R200_CP_CMD_3D_DRAW_IMMD_2
:
1291 fprintf(stderr
, "R200_CP_CMD_3D_DRAW_IMMD_2, %d dwords\n",
1293 if (print_prim_and_flags(cmd
[1]))
1296 case R200_CP_CMD_3D_DRAW_INDX_2
:
1298 fprintf(stderr
, "R200_CP_CMD_3D_DRAW_INDX_2, %d dwords\n",
1300 if (print_prim_and_flags(cmd
[1]))
1304 fprintf(stderr
, "UNKNOWN PACKET, %d dwords\n", cmdsz
);
1308 cmdbuf
->buf
+= cmdsz
* 4;
1309 cmdbuf
->bufsz
-= cmdsz
* 4;
1314 /* Check cliprects for bounds, then pass on to above:
1316 static int radeon_emit_packet3_cliprect( drm_radeon_cmd_buffer_t
*cmdbuf
)
1318 drm_clip_rect_t
*boxes
= (drm_clip_rect_t
*)cmdbuf
->boxes
;
1321 if (VERBOSE
&& total_changed
) {
1328 if ( i
< cmdbuf
->nbox
) {
1329 fprintf(stderr
, "Emit box %d/%d %d,%d %d,%d\n",
1331 boxes
[i
].x1
, boxes
[i
].y1
, boxes
[i
].x2
, boxes
[i
].y2
);
1333 } while ( ++i
< cmdbuf
->nbox
);
1336 if (cmdbuf
->nbox
== 1)
1339 return radeon_emit_packet3( cmdbuf
);
1343 int r200SanityCmdBuffer( r200ContextPtr rmesa
,
1345 drm_clip_rect_t
*boxes
)
1348 drm_radeon_cmd_buffer_t cmdbuf
;
1349 drm_radeon_cmd_header_t header
;
1350 static int inited
= 0;
1358 cmdbuf
.buf
= rmesa
->store
.cmd_buf
;
1359 cmdbuf
.bufsz
= rmesa
->store
.cmd_used
;
1360 cmdbuf
.boxes
= (drm_clip_rect_t
*)boxes
;
1363 while ( cmdbuf
.bufsz
>= sizeof(header
) ) {
1365 header
.i
= *(int *)cmdbuf
.buf
;
1366 cmdbuf
.buf
+= sizeof(header
);
1367 cmdbuf
.bufsz
-= sizeof(header
);
1369 switch (header
.header
.cmd_type
) {
1370 case RADEON_CMD_PACKET
:
1371 if (radeon_emit_packets( header
, &cmdbuf
)) {
1372 fprintf(stderr
,"radeon_emit_packets failed\n");
1377 case RADEON_CMD_SCALARS
:
1378 if (radeon_emit_scalars( header
, &cmdbuf
)) {
1379 fprintf(stderr
,"radeon_emit_scalars failed\n");
1384 case RADEON_CMD_SCALARS2
:
1385 if (radeon_emit_scalars2( header
, &cmdbuf
)) {
1386 fprintf(stderr
,"radeon_emit_scalars failed\n");
1391 case RADEON_CMD_VECTORS
:
1392 if (radeon_emit_vectors( header
, &cmdbuf
)) {
1393 fprintf(stderr
,"radeon_emit_vectors failed\n");
1398 case RADEON_CMD_DMA_DISCARD
:
1399 idx
= header
.dma
.buf_idx
;
1401 fprintf(stderr
, "RADEON_CMD_DMA_DISCARD buf %d\n", idx
);
1405 case RADEON_CMD_PACKET3
:
1406 if (radeon_emit_packet3( &cmdbuf
)) {
1407 fprintf(stderr
,"radeon_emit_packet3 failed\n");
1412 case RADEON_CMD_PACKET3_CLIP
:
1413 if (radeon_emit_packet3_cliprect( &cmdbuf
)) {
1414 fprintf(stderr
,"radeon_emit_packet3_clip failed\n");
1419 case RADEON_CMD_WAIT
:
1422 case RADEON_CMD_VECLINEAR
:
1423 if (radeon_emit_veclinear( header
, &cmdbuf
)) {
1424 fprintf(stderr
,"radeon_emit_veclinear failed\n");
1430 fprintf(stderr
,"bad cmd_type %d at %p\n",
1431 header
.header
.cmd_type
,
1432 cmdbuf
.buf
- sizeof(header
));
1442 fprintf(stderr
, "Bufs %d Total emitted %d real changes %d (%.2f%%)\n",
1444 total
, total_changed
,
1445 ((float)total_changed
/(float)total
*100.0));
1446 fprintf(stderr
, "Total emitted per buf: %.2f\n",
1447 (float)total
/(float)bufs
);
1448 fprintf(stderr
, "Real changes per buf: %.2f\n",
1449 (float)total_changed
/(float)bufs
);
1451 bufs
= n
= total
= total_changed
= 0;
1455 fprintf(stderr
, "leaving %s\n\n\n", __FUNCTION__
);