src/mesa/drivers/dri/r200/r200_span.c

   1 /*
   2 Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
   3
   4 The Weather Channel (TM) funded Tungsten Graphics to develop the
   5 initial release of the Radeon 8500 driver under the XFree86 license.
   6 This notice must be preserved.
   7
   8 Permission is hereby granted, free of charge, to any person obtaining
   9 a copy of this software and associated documentation files (the
  10 "Software"), to deal in the Software without restriction, including
  11 without limitation the rights to use, copy, modify, merge, publish,
  12 distribute, sublicense, and/or sell copies of the Software, and to
  13 permit persons to whom the Software is furnished to do so, subject to
  14 the following conditions:
  15
  16 The above copyright notice and this permission notice (including the
  17 next paragraph) shall be included in all copies or substantial
  18 portions of the Software.
  19
  20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27
  28 **************************************************************************/
  29
  30 /*
  31  * Authors:
  32  *   Keith Whitwell <keith@tungstengraphics.com>
  33  */
  34
  35 #include "main/glheader.h"
  36 #include "main/imports.h"
  37 #include "main/colormac.h"
  38 #include "swrast/swrast.h"
  39
  40 #include "r200_context.h"
  41 #include "radeon_buffer.h"
  42 #include "r200_ioctl.h"
  43 #include "r200_state.h"
  44 #include "r200_span.h"
  45 #include "r200_tex.h"
  46
  47 #define DBG 0
  48
  49 /*
  50  * Note that all information needed to access pixels in a renderbuffer
  51  * should be obtained through the gl_renderbuffer parameter, not per-context
  52  * information.
  53  */
  54 #define LOCAL_VARS                                              \
  55    struct radeon_renderbuffer *rrb = (void *) rb;               \
  56    const __DRIdrawablePrivate *dPriv = rrb->dPriv;              \
  57    const GLuint bottom = dPriv->h - 1;                          \
  58    GLuint p;                                                    \
  59    (void) p;
  60
  61 #define LOCAL_DEPTH_VARS                                \
  62    struct radeon_renderbuffer *rrb = (void *) rb;               \
  63    const __DRIdrawablePrivate *dPriv = rrb->dPriv;      \
  64    const GLuint bottom = dPriv->h - 1;                  \
  65    GLuint xo = dPriv->x;                                \
  66    GLuint yo = dPriv->y;
  67
  68 #define LOCAL_STENCIL_VARS LOCAL_DEPTH_VARS
  69
  70 #define Y_FLIP(Y) (bottom - (Y))
  71
  72 #define HW_LOCK()
  73
  74 #define HW_UNLOCK()
  75
  76
  77
  78 /* ================================================================
  79  * Color buffer
  80  */
  81
  82 /* 16 bit, RGB565 color spanline and pixel functions
  83  */
  84 #define SPANTMP_PIXEL_FMT GL_RGB
  85 #define SPANTMP_PIXEL_TYPE GL_UNSIGNED_SHORT_5_6_5
  86
  87 #define TAG(x)    radeon##x##_RGB565
  88 #define TAG2(x,y) radeon##x##_RGB565##y
  89 #define GET_PTR(X,Y) radeon_ptr16(rrb, (X), (Y))
  90 #include "spantmp2.h"
  91
  92 /* 32 bit, ARGB8888 color spanline and pixel functions
  93  */
  94 #define SPANTMP_PIXEL_FMT GL_BGRA
  95 #define SPANTMP_PIXEL_TYPE GL_UNSIGNED_INT_8_8_8_8_REV
  96
  97 #define TAG(x)    radeon##x##_ARGB8888
  98 #define TAG2(x,y) radeon##x##_ARGB8888##y
  99 #define GET_PTR(X,Y) radeon_ptr32(rrb, (X), (Y))
 100 #include "spantmp2.h"
 101
 102
 103 /* ================================================================
 104  * Depth buffer
 105  */
 106
 107 /* The Radeon family has depth tiling on all the time, so we have to convert
 108  * the x,y coordinates into the memory bus address (mba) in the same
 109  * manner as the engine.  In each case, the linear block address (ba)
 110  * is calculated, and then wired with x and y to produce the final
 111  * memory address.
 112  * The chip will do address translation on its own if the surface registers
 113  * are set up correctly. It is not quite enough to get it working with hyperz too...
 114  */
 115
 116 /* 16-bit depth buffer functions
 117  */
 118 #define VALUE_TYPE GLushort
 119
 120 #define WRITE_DEPTH( _x, _y, d )                                        \
 121    *(GLushort *)radeon_ptr(rrb, _x + xo, _y + yo) = d
 122
 123 #define READ_DEPTH( d, _x, _y )                                         \
 124    d = *(GLushort *)radeon_ptr(rrb, _x + xo, _y + yo)
 125
 126 #define TAG(x) radeon##x##_z16
 127 #include "depthtmp.h"
 128
 129
 130 /* 24 bit depth, 8 bit stencil depthbuffer functions
 131  */
 132 #define VALUE_TYPE GLuint
 133
 134 #define WRITE_DEPTH( _x, _y, d )                                        \
 135 do {                                                                    \
 136    GLuint *_ptr = (GLuint*)radeon_ptr32(rrb, _x + xo, _y + yo);         \
 137    GLuint tmp = *_ptr;                                                  \
 138    tmp &= 0xff000000;                                                   \
 139    tmp |= ((d) & 0x00ffffff);                                           \
 140    *_ptr = tmp;                                 \
 141 } while (0)
 142
 143 #define READ_DEPTH( d, _x, _y )                                         \
 144    do {                                                                 \
 145       d = (*(GLuint*)(radeon_ptr32(rrb, _x + xo, _y + yo)) & 0x00ffffff); \
 146    }while(0)
 147
 148 #define TAG(x) radeon##x##_z24_s8
 149 #include "depthtmp.h"
 150
 151
 152 /* ================================================================
 153  * Stencil buffer
 154  */
 155
 156 /* 24 bit depth, 8 bit stencil depthbuffer functions
 157  */
 158 #define WRITE_STENCIL( _x, _y, d )                                      \
 159 do {                                                                    \
 160    GLuint *_ptr = (GLuint*)radeon_ptr32(rrb, _x + xo, _y + yo);         \
 161    GLuint tmp = *_ptr;                          \
 162    tmp &= 0x00ffffff;                                                   \
 163    tmp |= (((d) & 0xff) << 24);                                         \
 164    *_ptr = tmp;                                 \
 165 } while (0)
 166
 167 #define READ_STENCIL( d, _x, _y )                                       \
 168 do {                                                                    \
 169    GLuint *_ptr = (GLuint*)radeon_ptr32(rrb, _x + xo, _y + yo);         \
 170    GLuint tmp = *_ptr;                                                  \
 171    tmp &= 0xff000000;                                                   \
 172    d = tmp >> 24;                                                       \
 173 } while (0)
 174
 175 #define TAG(x) radeon##x##_z24_s8
 176 #include "stenciltmp.h"
 177
 178
 179 void r200InitSpanFuncs( GLcontext *ctx )
 180 {
 181    struct swrast_device_driver *swdd = _swrast_GetDeviceDriverReference(ctx);
 182    swdd->SpanRenderStart          = radeonSpanRenderStart;
 183    swdd->SpanRenderFinish         = radeonSpanRenderFinish;
 184 }
 185
 186
 187
 188 /**
 189  * Plug in the Get/Put routines for the given driRenderbuffer.
 190  */
 191 void radeonSetSpanFunctions(struct radeon_renderbuffer *rrb)
 192 {
 193         if (rrb->base.InternalFormat == GL_RGB5) {
 194                 radeonInitPointers_RGB565(&rrb->base);
 195         } else if (rrb->base.InternalFormat == GL_RGBA8) {
 196                 radeonInitPointers_ARGB8888(&rrb->base);
 197         } else if (rrb->base.InternalFormat == GL_DEPTH_COMPONENT16) {
 198                 radeonInitDepthPointers_z16(&rrb->base);
 199         } else if (rrb->base.InternalFormat == GL_DEPTH_COMPONENT24) {
 200                 radeonInitDepthPointers_z24_s8(&rrb->base);
 201         } else if (rrb->base.InternalFormat == GL_STENCIL_INDEX8_EXT) {
 202                 radeonInitStencilPointers_z24_s8(&rrb->base);
 203         }
 204 }