src/mesa/drivers/dri/r200/r200_span.c

   1 /*
   2 Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
   3
   4 The Weather Channel (TM) funded Tungsten Graphics to develop the
   5 initial release of the Radeon 8500 driver under the XFree86 license.
   6 This notice must be preserved.
   7
   8 Permission is hereby granted, free of charge, to any person obtaining
   9 a copy of this software and associated documentation files (the
  10 "Software"), to deal in the Software without restriction, including
  11 without limitation the rights to use, copy, modify, merge, publish,
  12 distribute, sublicense, and/or sell copies of the Software, and to
  13 permit persons to whom the Software is furnished to do so, subject to
  14 the following conditions:
  15
  16 The above copyright notice and this permission notice (including the
  17 next paragraph) shall be included in all copies or substantial
  18 portions of the Software.
  19
  20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27
  28 **************************************************************************/
  29
  30 /*
  31  * Authors:
  32  *   Keith Whitwell <keith@tungstengraphics.com>
  33  */
  34
  35 #include "main/glheader.h"
  36 #include "main/imports.h"
  37 #include "main/colormac.h"
  38 #include "swrast/swrast.h"
  39
  40 #include "r200_context.h"
  41 #include "radeon_buffer.h"
  42 #include "r200_ioctl.h"
  43 #include "r200_state.h"
  44 #include "r200_span.h"
  45 #include "r200_tex.h"
  46
  47 #define DBG 0
  48
  49 /*
  50  * Note that all information needed to access pixels in a renderbuffer
  51  * should be obtained through the gl_renderbuffer parameter, not per-context
  52  * information.
  53  */
  54 #define LOCAL_VARS                                              \
  55    driRenderbuffer *drb = (driRenderbuffer *) rb;               \
  56    const __DRIdrawablePrivate *dPriv = drb->dPriv;              \
  57    const GLuint bottom = dPriv->h - 1;                          \
  58    GLubyte *buf = (GLubyte *) drb->flippedData                  \
  59       + (dPriv->y * drb->flippedPitch + dPriv->x) * drb->cpp;   \
  60    GLuint p;                                                    \
  61    (void) p;
  62
  63 #define LOCAL_DEPTH_VARS                                \
  64    driRenderbuffer *drb = (driRenderbuffer *) rb;       \
  65    const __DRIdrawablePrivate *dPriv = drb->dPriv;      \
  66    const GLuint bottom = dPriv->h - 1;                  \
  67    GLuint xo = dPriv->x;                                \
  68    GLuint yo = dPriv->y;                                \
  69    GLubyte *buf = (GLubyte *) drb->Base.Data;
  70
  71 #define LOCAL_STENCIL_VARS LOCAL_DEPTH_VARS
  72
  73 #define Y_FLIP(Y) (bottom - (Y))
  74
  75 #define HW_LOCK()
  76
  77 #define HW_UNLOCK()
  78
  79
  80
  81 /* ================================================================
  82  * Color buffer
  83  */
  84
  85 /* 16 bit, RGB565 color spanline and pixel functions
  86  */
  87 #define SPANTMP_PIXEL_FMT GL_RGB
  88 #define SPANTMP_PIXEL_TYPE GL_UNSIGNED_SHORT_5_6_5
  89
  90 #define TAG(x)    radeon##x##_RGB565
  91 #define TAG2(x,y) radeon##x##_RGB565##y
  92 #define GET_PTR(X,Y) (buf + ((Y) * drb->flippedPitch + (X)) * 2)
  93 #include "spantmp2.h"
  94
  95 /* 32 bit, ARGB8888 color spanline and pixel functions
  96  */
  97 #define SPANTMP_PIXEL_FMT GL_BGRA
  98 #define SPANTMP_PIXEL_TYPE GL_UNSIGNED_INT_8_8_8_8_REV
  99
 100 #define TAG(x)    radeon##x##_ARGB8888
 101 #define TAG2(x,y) radeon##x##_ARGB8888##y
 102 #define GET_PTR(X,Y) (buf + ((Y) * drb->flippedPitch + (X)) * 4)
 103 #include "spantmp2.h"
 104
 105
 106 /* ================================================================
 107  * Depth buffer
 108  */
 109
 110 /* The Radeon family has depth tiling on all the time, so we have to convert
 111  * the x,y coordinates into the memory bus address (mba) in the same
 112  * manner as the engine.  In each case, the linear block address (ba)
 113  * is calculated, and then wired with x and y to produce the final
 114  * memory address.
 115  * The chip will do address translation on its own if the surface registers
 116  * are set up correctly. It is not quite enough to get it working with hyperz too...
 117  */
 118
 119 /* extract bit 'b' of x, result is zero or one */
 120 #define BIT(x,b) ((x & (1<<b))>>b)
 121
 122 static GLuint
 123 r200_mba_z32( driRenderbuffer *drb, GLint x, GLint y )
 124 {
 125    GLuint pitch = drb->pitch;
 126    if (drb->depthHasSurface) {
 127       return 4 * (x + y * pitch);
 128    }
 129    else {
 130       GLuint b = ((y & 0x7FF) >> 4) * ((pitch & 0xFFF) >> 5) + ((x & 0x7FF) >> 5);
 131       GLuint a =
 132          (BIT(x,0) << 2) |
 133          (BIT(y,0) << 3) |
 134          (BIT(x,1) << 4) |
 135          (BIT(y,1) << 5) |
 136          (BIT(x,3) << 6) |
 137          (BIT(x,4) << 7) |
 138          (BIT(x,2) << 8) |
 139          (BIT(y,2) << 9) |
 140          (BIT(y,3) << 10) |
 141          (((pitch & 0x20) ? (b & 0x01) : ((b & 0x01) ^ (BIT(y,4)))) << 11) |
 142          ((b >> 1) << 12);
 143       return a;
 144    }
 145 }
 146
 147 static GLuint
 148 r200_mba_z16( driRenderbuffer *drb, GLint x, GLint y )
 149 {
 150    GLuint pitch = drb->pitch;
 151    if (drb->depthHasSurface) {
 152       return 2 * (x + y * pitch);
 153    }
 154    else {
 155       GLuint b = ((y & 0x7FF) >> 4) * ((pitch & 0xFFF) >> 6) + ((x & 0x7FF) >> 6);
 156       GLuint a =
 157          (BIT(x,0) << 1) |
 158          (BIT(y,0) << 2) |
 159          (BIT(x,1) << 3) |
 160          (BIT(y,1) << 4) |
 161          (BIT(x,2) << 5) |
 162          (BIT(x,4) << 6) |
 163          (BIT(x,5) << 7) |
 164          (BIT(x,3) << 8) |
 165          (BIT(y,2) << 9) |
 166          (BIT(y,3) << 10) |
 167          (((pitch & 0x40) ? (b & 0x01) : ((b & 0x01) ^ (BIT(y,4)))) << 11) |
 168          ((b >> 1) << 12);
 169       return a;
 170    }
 171 }
 172
 173
 174 /* 16-bit depth buffer functions
 175  */
 176 #define VALUE_TYPE GLushort
 177
 178 #define WRITE_DEPTH( _x, _y, d )                                        \
 179    *(GLushort *)(buf + r200_mba_z16( drb, _x + xo, _y + yo )) = d;
 180
 181 #define READ_DEPTH( d, _x, _y )                                         \
 182    d = *(GLushort *)(buf + r200_mba_z16( drb, _x + xo, _y + yo ));
 183
 184 #define TAG(x) radeon##x##_z16
 185 #include "depthtmp.h"
 186
 187
 188 /* 24 bit depth, 8 bit stencil depthbuffer functions
 189  */
 190 #define VALUE_TYPE GLuint
 191
 192 #define WRITE_DEPTH( _x, _y, d )                                        \
 193 do {                                                                    \
 194    GLuint offset = r200_mba_z32( drb, _x + xo, _y + yo );               \
 195    GLuint tmp = *(GLuint *)(buf + offset);                              \
 196    tmp &= 0xff000000;                                                   \
 197    tmp |= ((d) & 0x00ffffff);                                           \
 198    *(GLuint *)(buf + offset) = tmp;                                     \
 199 } while (0)
 200
 201 #define READ_DEPTH( d, _x, _y )                                         \
 202    d = *(GLuint *)(buf + r200_mba_z32( drb, _x + xo,                    \
 203                                          _y + yo )) & 0x00ffffff;
 204
 205 #define TAG(x) radeon##x##_z24_s8
 206 #include "depthtmp.h"
 207
 208
 209 /* ================================================================
 210  * Stencil buffer
 211  */
 212
 213 /* 24 bit depth, 8 bit stencil depthbuffer functions
 214  */
 215 #define WRITE_STENCIL( _x, _y, d )                                      \
 216 do {                                                                    \
 217    GLuint offset = r200_mba_z32( drb, _x + xo, _y + yo );               \
 218    GLuint tmp = *(GLuint *)(buf + offset);                              \
 219    tmp &= 0x00ffffff;                                                   \
 220    tmp |= (((d) & 0xff) << 24);                                         \
 221    *(GLuint *)(buf + offset) = tmp;                                     \
 222 } while (0)
 223
 224 #define READ_STENCIL( d, _x, _y )                                       \
 225 do {                                                                    \
 226    GLuint offset = r200_mba_z32( drb, _x + xo, _y + yo );               \
 227    GLuint tmp = *(GLuint *)(buf + offset);                              \
 228    tmp &= 0xff000000;                                                   \
 229    d = tmp >> 24;                                                       \
 230 } while (0)
 231
 232 #define TAG(x) radeon##x##_z24_s8
 233 #include "stenciltmp.h"
 234
 235
 236 /* Move locking out to get reasonable span performance (10x better
 237  * than doing this in HW_LOCK above).  WaitForIdle() is the main
 238  * culprit.
 239  */
 240
 241 static void r200SpanRenderStart( GLcontext *ctx )
 242 {
 243    r200ContextPtr rmesa = R200_CONTEXT( ctx );
 244
 245    R200_FIREVERTICES( rmesa );
 246    LOCK_HARDWARE( &rmesa->radeon );
 247    radeonWaitForIdleLocked( &rmesa->radeon );
 248
 249    /* Read & rewrite the first pixel in the frame buffer.  This should
 250     * be a noop, right?  In fact without this conform fails as reading
 251     * from the framebuffer sometimes produces old results -- the
 252     * on-card read cache gets mixed up and doesn't notice that the
 253     * framebuffer has been updated.
 254     *
 255     * In the worst case this is buggy too as p might get the wrong
 256     * value first time, so really need a hidden pixel somewhere for this.
 257     */
 258    {
 259       int p;
 260       driRenderbuffer *drb =
 261          (driRenderbuffer *) ctx->WinSysDrawBuffer->_ColorDrawBuffers[0];
 262       volatile int *buf =
 263          (volatile int *)(rmesa->radeon.dri.screen->pFB + drb->offset);
 264       p = *buf;
 265       *buf = p;
 266    }
 267 }
 268
 269 static void r200SpanRenderFinish( GLcontext *ctx )
 270 {
 271    r200ContextPtr rmesa = R200_CONTEXT( ctx );
 272    _swrast_flush( ctx );
 273    UNLOCK_HARDWARE( &rmesa->radeon );
 274 }
 275
 276 void r200InitSpanFuncs( GLcontext *ctx )
 277 {
 278    struct swrast_device_driver *swdd = _swrast_GetDeviceDriverReference(ctx);
 279    swdd->SpanRenderStart          = r200SpanRenderStart;
 280    swdd->SpanRenderFinish         = r200SpanRenderFinish;
 281 }
 282
 283
 284
 285 /**
 286  * Plug in the Get/Put routines for the given driRenderbuffer.
 287  */
 288 void radeonSetSpanFunctions(struct radeon_renderbuffer *rrb)
 289 {
 290         if (rrb->base.InternalFormat == GL_RGB5) {
 291                 radeonInitPointers_RGB565(&rrb->base);
 292         } else if (rrb->base.InternalFormat == GL_RGBA8) {
 293                 radeonInitPointers_ARGB8888(&rrb->base);
 294         } else if (rrb->base.InternalFormat == GL_DEPTH_COMPONENT16) {
 295                 radeonInitDepthPointers_z16(&rrb->base);
 296         } else if (rrb->base.InternalFormat == GL_DEPTH_COMPONENT24) {
 297                 radeonInitDepthPointers_z24_s8(&rrb->base);
 298         } else if (rrb->base.InternalFormat == GL_STENCIL_INDEX8_EXT) {
 299                 radeonInitStencilPointers_z24_s8(&rrb->base);
 300         }
 301 }