1 /* $XFree86: xc/lib/GL/mesa/src/drv/r200/r200_state_init.c,v 1.4 2003/02/22 06:21:11 dawes Exp $ */
3 Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
5 The Weather Channel (TM) funded Tungsten Graphics to develop the
6 initial release of the Radeon 8500 driver under the XFree86 license.
7 This notice must be preserved.
9 Permission is hereby granted, free of charge, to any person obtaining
10 a copy of this software and associated documentation files (the
11 "Software"), to deal in the Software without restriction, including
12 without limitation the rights to use, copy, modify, merge, publish,
13 distribute, sublicense, and/or sell copies of the Software, and to
14 permit persons to whom the Software is furnished to do so, subject to
15 the following conditions:
17 The above copyright notice and this permission notice (including the
18 next paragraph) shall be included in all copies or substantial
19 portions of the Software.
21 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
22 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
23 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
24 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
25 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
26 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
27 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
32 * Keith Whitwell <keith@tungstengraphics.com>
39 #include "api_arrayelt.h"
41 #include "swrast/swrast.h"
42 #include "array_cache/acache.h"
44 #include "tnl/t_pipeline.h"
45 #include "swrast_setup/swrast_setup.h"
47 #include "r200_context.h"
48 #include "r200_ioctl.h"
49 #include "r200_state.h"
52 #include "r200_swtcl.h"
53 #include "r200_vtxfmt.h"
57 /* =============================================================
58 * State initialization
61 void r200PrintDirty( r200ContextPtr rmesa
, const char *msg
)
63 struct r200_state_atom
*l
;
66 fprintf(stderr
, ": ");
68 foreach(l
, &(rmesa
->hw
.dirty
)) {
69 fprintf(stderr
, "%s, ", l
->name
);
72 fprintf(stderr
, "\n");
75 static int cmdpkt( int id
)
77 drm_radeon_cmd_header_t h
;
79 h
.packet
.cmd_type
= RADEON_CMD_PACKET
;
80 h
.packet
.packet_id
= id
;
84 static int cmdvec( int offset
, int stride
, int count
)
86 drm_radeon_cmd_header_t h
;
88 h
.vectors
.cmd_type
= RADEON_CMD_VECTORS
;
89 h
.vectors
.offset
= offset
;
90 h
.vectors
.stride
= stride
;
91 h
.vectors
.count
= count
;
95 static int cmdscl( int offset
, int stride
, int count
)
97 drm_radeon_cmd_header_t h
;
99 h
.scalars
.cmd_type
= RADEON_CMD_SCALARS
;
100 h
.scalars
.offset
= offset
;
101 h
.scalars
.stride
= stride
;
102 h
.scalars
.count
= count
;
106 static int cmdscl2( int offset
, int stride
, int count
)
108 drm_radeon_cmd_header_t h
;
110 h
.scalars
.cmd_type
= RADEON_CMD_SCALARS2
;
111 h
.scalars
.offset
= offset
- 0x100;
112 h
.scalars
.stride
= stride
;
113 h
.scalars
.count
= count
;
117 #define CHECK( NM, FLAG ) \
118 static GLboolean check_##NM( GLcontext *ctx, int idx ) \
124 #define TCL_CHECK( NM, FLAG ) \
125 static GLboolean check_##NM( GLcontext *ctx, int idx ) \
127 r200ContextPtr rmesa = R200_CONTEXT(ctx); \
129 return !rmesa->TclFallback && (FLAG); \
134 CHECK( always
, GL_TRUE
)
135 CHECK( never
, GL_FALSE
)
136 CHECK( tex_any
, ctx
->Texture
._EnabledUnits
)
137 CHECK( tex
, ctx
->Texture
.Unit
[idx
]._ReallyEnabled
)
138 CHECK( fog
, ctx
->Fog
.Enabled
)
139 TCL_CHECK( tcl
, GL_TRUE
)
140 TCL_CHECK( tcl_tex
, ctx
->Texture
.Unit
[idx
]._ReallyEnabled
)
141 TCL_CHECK( tcl_lighting
, ctx
->Light
.Enabled
)
142 TCL_CHECK( tcl_light
, ctx
->Light
.Enabled
&& ctx
->Light
.Light
[idx
].Enabled
)
143 TCL_CHECK( tcl_ucp
, (ctx
->Transform
.ClipPlanesEnabled
& (1 << idx
)) )
146 /* Initialize the context's hardware state.
148 void r200InitState( r200ContextPtr rmesa
)
150 GLcontext
*ctx
= rmesa
->glCtx
;
151 GLuint color_fmt
, depth_fmt
, i
;
153 switch ( rmesa
->r200Screen
->cpp
) {
155 color_fmt
= R200_COLOR_FORMAT_RGB565
;
158 color_fmt
= R200_COLOR_FORMAT_ARGB8888
;
161 fprintf( stderr
, "Error: Unsupported pixel depth... exiting\n" );
165 rmesa
->state
.color
.clear
= 0x00000000;
167 switch ( ctx
->Visual
.depthBits
) {
169 rmesa
->state
.depth
.scale
= 1.0 / (GLfloat
)0xffff;
170 depth_fmt
= R200_DEPTH_FORMAT_16BIT_INT_Z
;
171 rmesa
->state
.stencil
.clear
= 0x00000000;
174 rmesa
->state
.depth
.scale
= 1.0 / (GLfloat
)0xffffff;
175 depth_fmt
= R200_DEPTH_FORMAT_24BIT_INT_Z
;
176 rmesa
->state
.stencil
.clear
= 0xff000000;
179 fprintf( stderr
, "Error: Unsupported depth %d... exiting\n",
180 ctx
->Visual
.depthBits
);
184 /* Only have hw stencil when depth buffer is 24 bits deep */
185 rmesa
->state
.stencil
.hwBuffer
= ( ctx
->Visual
.stencilBits
> 0 &&
186 ctx
->Visual
.depthBits
== 24 );
190 if ( ctx
->Visual
.doubleBufferMode
&& rmesa
->sarea
->pfCurrentPage
== 0 ) {
191 rmesa
->state
.color
.drawOffset
= rmesa
->r200Screen
->backOffset
;
192 rmesa
->state
.color
.drawPitch
= rmesa
->r200Screen
->backPitch
;
194 rmesa
->state
.color
.drawOffset
= rmesa
->r200Screen
->frontOffset
;
195 rmesa
->state
.color
.drawPitch
= rmesa
->r200Screen
->frontPitch
;
198 rmesa
->state
.pixel
.readOffset
= rmesa
->state
.color
.drawOffset
;
199 rmesa
->state
.pixel
.readPitch
= rmesa
->state
.color
.drawPitch
;
203 make_empty_list(&(rmesa
->hw
.dirty
)); rmesa
->hw
.dirty
.name
= "DIRTY";
204 make_empty_list(&(rmesa
->hw
.clean
)); rmesa
->hw
.clean
.name
= "CLEAN";
207 #define ALLOC_STATE( ATOM, CHK, SZ, NM, IDX ) \
209 rmesa->hw.ATOM.cmd_size = SZ; \
210 rmesa->hw.ATOM.cmd = (int *)CALLOC(SZ * sizeof(int)); \
211 rmesa->hw.ATOM.lastcmd = (int *)CALLOC(SZ * sizeof(int)); \
212 rmesa->hw.ATOM.name = NM; \
213 rmesa->hw.ATOM.idx = IDX; \
214 rmesa->hw.ATOM.check = check_##CHK; \
215 insert_at_head(&(rmesa->hw.dirty), &(rmesa->hw.ATOM)); \
219 /* Allocate state buffers:
221 if (rmesa
->r200Screen
->drmSupportsBlendColor
)
222 ALLOC_STATE( ctx
, always
, CTX_STATE_SIZE_NEWDRM
, "CTX/context", 0 );
224 ALLOC_STATE( ctx
, always
, CTX_STATE_SIZE_OLDDRM
, "CTX/context", 0 );
225 ALLOC_STATE( set
, always
, SET_STATE_SIZE
, "SET/setup", 0 );
226 ALLOC_STATE( lin
, always
, LIN_STATE_SIZE
, "LIN/line", 0 );
227 ALLOC_STATE( msk
, always
, MSK_STATE_SIZE
, "MSK/mask", 0 );
228 ALLOC_STATE( vpt
, always
, VPT_STATE_SIZE
, "VPT/viewport", 0 );
229 ALLOC_STATE( vtx
, always
, VTX_STATE_SIZE
, "VTX/vertex", 0 );
230 ALLOC_STATE( vap
, always
, VAP_STATE_SIZE
, "VAP/vap", 0 );
231 ALLOC_STATE( vte
, always
, VTE_STATE_SIZE
, "VTE/vte", 0 );
232 ALLOC_STATE( msc
, always
, MSC_STATE_SIZE
, "MSC/misc", 0 );
233 ALLOC_STATE( cst
, always
, CST_STATE_SIZE
, "CST/constant", 0 );
234 ALLOC_STATE( zbs
, always
, ZBS_STATE_SIZE
, "ZBS/zbias", 0 );
235 ALLOC_STATE( tam
, tex_any
, TAM_STATE_SIZE
, "TAM/tam", 0 );
236 ALLOC_STATE( tf
, tex_any
, TF_STATE_SIZE
, "TF/tfactor", 0 );
237 ALLOC_STATE( tex
[0], tex_any
, TEX_STATE_SIZE
, "TEX/tex-0", 0 );
238 ALLOC_STATE( tex
[1], tex_any
, TEX_STATE_SIZE
, "TEX/tex-1", 1 );
240 if (rmesa
->r200Screen
->drmSupportsCubeMaps
) {
241 ALLOC_STATE( cube
[0], tex_any
, CUBE_STATE_SIZE
, "CUBE/tex-0", 0 );
242 ALLOC_STATE( cube
[1], tex_any
, CUBE_STATE_SIZE
, "CUBE/tex-1", 1 );
245 ALLOC_STATE( cube
[0], never
, CUBE_STATE_SIZE
, "CUBE/tex-0", 0 );
246 ALLOC_STATE( cube
[1], never
, CUBE_STATE_SIZE
, "CUBE/tex-1", 1 );
249 ALLOC_STATE( tcl
, tcl
, TCL_STATE_SIZE
, "TCL/tcl", 0 );
250 ALLOC_STATE( msl
, tcl
, MSL_STATE_SIZE
, "MSL/matrix-select", 0 );
251 ALLOC_STATE( tcg
, tcl
, TCG_STATE_SIZE
, "TCG/texcoordgen", 0 );
252 ALLOC_STATE( mtl
[0], tcl_lighting
, MTL_STATE_SIZE
, "MTL0/material0", 0 );
253 ALLOC_STATE( mtl
[1], tcl_lighting
, MTL_STATE_SIZE
, "MTL1/material1", 1 );
254 ALLOC_STATE( grd
, tcl
, GRD_STATE_SIZE
, "GRD/guard-band", 0 );
255 ALLOC_STATE( fog
, fog
, FOG_STATE_SIZE
, "FOG/fog", 0 );
256 ALLOC_STATE( glt
, tcl_lighting
, GLT_STATE_SIZE
, "GLT/light-global", 0 );
257 ALLOC_STATE( eye
, tcl_lighting
, EYE_STATE_SIZE
, "EYE/eye-vector", 0 );
258 ALLOC_STATE( mat
[R200_MTX_MV
], tcl
, MAT_STATE_SIZE
, "MAT/modelview", 0 );
259 ALLOC_STATE( mat
[R200_MTX_IMV
], tcl
, MAT_STATE_SIZE
, "MAT/it-modelview", 0 );
260 ALLOC_STATE( mat
[R200_MTX_MVP
], tcl
, MAT_STATE_SIZE
, "MAT/modelproject", 0 );
261 ALLOC_STATE( mat
[R200_MTX_TEX0
], tcl_tex
, MAT_STATE_SIZE
, "MAT/texmat0", 0 );
262 ALLOC_STATE( mat
[R200_MTX_TEX1
], tcl_tex
, MAT_STATE_SIZE
, "MAT/texmat1", 1 );
263 ALLOC_STATE( ucp
[0], tcl_ucp
, UCP_STATE_SIZE
, "UCP/userclip-0", 0 );
264 ALLOC_STATE( ucp
[1], tcl_ucp
, UCP_STATE_SIZE
, "UCP/userclip-1", 1 );
265 ALLOC_STATE( ucp
[2], tcl_ucp
, UCP_STATE_SIZE
, "UCP/userclip-2", 2 );
266 ALLOC_STATE( ucp
[3], tcl_ucp
, UCP_STATE_SIZE
, "UCP/userclip-3", 3 );
267 ALLOC_STATE( ucp
[4], tcl_ucp
, UCP_STATE_SIZE
, "UCP/userclip-4", 4 );
268 ALLOC_STATE( ucp
[5], tcl_ucp
, UCP_STATE_SIZE
, "UCP/userclip-5", 5 );
269 ALLOC_STATE( lit
[0], tcl_light
, LIT_STATE_SIZE
, "LIT/light-0", 0 );
270 ALLOC_STATE( lit
[1], tcl_light
, LIT_STATE_SIZE
, "LIT/light-1", 1 );
271 ALLOC_STATE( lit
[2], tcl_light
, LIT_STATE_SIZE
, "LIT/light-2", 2 );
272 ALLOC_STATE( lit
[3], tcl_light
, LIT_STATE_SIZE
, "LIT/light-3", 3 );
273 ALLOC_STATE( lit
[4], tcl_light
, LIT_STATE_SIZE
, "LIT/light-4", 4 );
274 ALLOC_STATE( lit
[5], tcl_light
, LIT_STATE_SIZE
, "LIT/light-5", 5 );
275 ALLOC_STATE( lit
[6], tcl_light
, LIT_STATE_SIZE
, "LIT/light-6", 6 );
276 ALLOC_STATE( lit
[7], tcl_light
, LIT_STATE_SIZE
, "LIT/light-7", 7 );
277 ALLOC_STATE( pix
[0], always
, PIX_STATE_SIZE
, "PIX/pixstage-0", 0 );
278 ALLOC_STATE( pix
[1], tex
, PIX_STATE_SIZE
, "PIX/pixstage-1", 1 );
281 /* Fill in the packet headers:
283 rmesa
->hw
.ctx
.cmd
[CTX_CMD_0
] = cmdpkt(RADEON_EMIT_PP_MISC
);
284 rmesa
->hw
.ctx
.cmd
[CTX_CMD_1
] = cmdpkt(RADEON_EMIT_PP_CNTL
);
285 rmesa
->hw
.ctx
.cmd
[CTX_CMD_2
] = cmdpkt(RADEON_EMIT_RB3D_COLORPITCH
);
286 if (rmesa
->r200Screen
->drmSupportsBlendColor
)
287 rmesa
->hw
.ctx
.cmd
[CTX_CMD_3
] = cmdpkt(R200_EMIT_RB3D_BLENDCOLOR
);
288 rmesa
->hw
.lin
.cmd
[LIN_CMD_0
] = cmdpkt(RADEON_EMIT_RE_LINE_PATTERN
);
289 rmesa
->hw
.lin
.cmd
[LIN_CMD_1
] = cmdpkt(RADEON_EMIT_SE_LINE_WIDTH
);
290 rmesa
->hw
.msk
.cmd
[MSK_CMD_0
] = cmdpkt(RADEON_EMIT_RB3D_STENCILREFMASK
);
291 rmesa
->hw
.vpt
.cmd
[VPT_CMD_0
] = cmdpkt(RADEON_EMIT_SE_VPORT_XSCALE
);
292 rmesa
->hw
.set
.cmd
[SET_CMD_0
] = cmdpkt(RADEON_EMIT_SE_CNTL
);
293 rmesa
->hw
.msc
.cmd
[MSC_CMD_0
] = cmdpkt(RADEON_EMIT_RE_MISC
);
294 rmesa
->hw
.cst
.cmd
[CST_CMD_0
] = cmdpkt(R200_EMIT_PP_CNTL_X
);
295 rmesa
->hw
.cst
.cmd
[CST_CMD_1
] = cmdpkt(R200_EMIT_RB3D_DEPTHXY_OFFSET
);
296 rmesa
->hw
.cst
.cmd
[CST_CMD_2
] = cmdpkt(R200_EMIT_RE_AUX_SCISSOR_CNTL
);
297 rmesa
->hw
.cst
.cmd
[CST_CMD_3
] = cmdpkt(R200_EMIT_RE_SCISSOR_TL_0
);
298 rmesa
->hw
.cst
.cmd
[CST_CMD_4
] = cmdpkt(R200_EMIT_SE_VAP_CNTL_STATUS
);
299 rmesa
->hw
.cst
.cmd
[CST_CMD_5
] = cmdpkt(R200_EMIT_RE_POINTSIZE
);
300 rmesa
->hw
.cst
.cmd
[CST_CMD_6
] = cmdpkt(R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0
);
301 rmesa
->hw
.tam
.cmd
[TAM_CMD_0
] = cmdpkt(R200_EMIT_PP_TAM_DEBUG3
);
302 rmesa
->hw
.tf
.cmd
[TF_CMD_0
] = cmdpkt(R200_EMIT_TFACTOR_0
);
303 rmesa
->hw
.tex
[0].cmd
[TEX_CMD_0
] = cmdpkt(R200_EMIT_PP_TXFILTER_0
);
304 rmesa
->hw
.tex
[0].cmd
[TEX_CMD_1
] = cmdpkt(R200_EMIT_PP_TXOFFSET_0
);
305 rmesa
->hw
.tex
[1].cmd
[TEX_CMD_0
] = cmdpkt(R200_EMIT_PP_TXFILTER_1
);
306 rmesa
->hw
.tex
[1].cmd
[TEX_CMD_1
] = cmdpkt(R200_EMIT_PP_TXOFFSET_1
);
307 rmesa
->hw
.cube
[0].cmd
[CUBE_CMD_0
] = cmdpkt(R200_EMIT_PP_CUBIC_FACES_0
);
308 rmesa
->hw
.cube
[0].cmd
[CUBE_CMD_1
] = cmdpkt(R200_EMIT_PP_CUBIC_OFFSETS_0
);
309 rmesa
->hw
.cube
[1].cmd
[CUBE_CMD_0
] = cmdpkt(R200_EMIT_PP_CUBIC_FACES_1
);
310 rmesa
->hw
.cube
[1].cmd
[CUBE_CMD_1
] = cmdpkt(R200_EMIT_PP_CUBIC_OFFSETS_1
);
311 rmesa
->hw
.pix
[0].cmd
[PIX_CMD_0
] = cmdpkt(R200_EMIT_PP_TXCBLEND_0
);
312 rmesa
->hw
.pix
[1].cmd
[PIX_CMD_0
] = cmdpkt(R200_EMIT_PP_TXCBLEND_1
);
313 rmesa
->hw
.zbs
.cmd
[ZBS_CMD_0
] = cmdpkt(RADEON_EMIT_SE_ZBIAS_FACTOR
);
314 rmesa
->hw
.tcl
.cmd
[TCL_CMD_0
] = cmdpkt(R200_EMIT_TCL_LIGHT_MODEL_CTL_0
);
315 rmesa
->hw
.tcl
.cmd
[TCL_CMD_1
] = cmdpkt(R200_EMIT_TCL_UCP_VERT_BLEND_CTL
);
316 rmesa
->hw
.tcg
.cmd
[TCG_CMD_0
] = cmdpkt(R200_EMIT_TEX_PROC_CTL_2
);
317 rmesa
->hw
.msl
.cmd
[MSL_CMD_0
] = cmdpkt(R200_EMIT_MATRIX_SELECT_0
);
318 rmesa
->hw
.vap
.cmd
[VAP_CMD_0
] = cmdpkt(R200_EMIT_VAP_CTL
);
319 rmesa
->hw
.vtx
.cmd
[VTX_CMD_0
] = cmdpkt(R200_EMIT_VTX_FMT_0
);
320 rmesa
->hw
.vtx
.cmd
[VTX_CMD_1
] = cmdpkt(R200_EMIT_OUTPUT_VTX_COMP_SEL
);
321 rmesa
->hw
.vtx
.cmd
[VTX_CMD_2
] = cmdpkt(R200_EMIT_SE_VTX_STATE_CNTL
);
322 rmesa
->hw
.vte
.cmd
[VTE_CMD_0
] = cmdpkt(R200_EMIT_VTE_CNTL
);
323 rmesa
->hw
.mtl
[0].cmd
[MTL_CMD_0
] =
324 cmdvec( R200_VS_MAT_0_EMISS
, 1, 16 );
325 rmesa
->hw
.mtl
[0].cmd
[MTL_CMD_1
] =
326 cmdscl2( R200_SS_MAT_0_SHININESS
, 1, 1 );
327 rmesa
->hw
.mtl
[1].cmd
[MTL_CMD_0
] =
328 cmdvec( R200_VS_MAT_1_EMISS
, 1, 16 );
329 rmesa
->hw
.mtl
[1].cmd
[MTL_CMD_1
] =
330 cmdscl2( R200_SS_MAT_1_SHININESS
, 1, 1 );
332 rmesa
->hw
.grd
.cmd
[GRD_CMD_0
] =
333 cmdscl( R200_SS_VERT_GUARD_CLIP_ADJ_ADDR
, 1, 4 );
334 rmesa
->hw
.fog
.cmd
[FOG_CMD_0
] =
335 cmdvec( R200_VS_FOG_PARAM_ADDR
, 1, 4 );
336 rmesa
->hw
.glt
.cmd
[GLT_CMD_0
] =
337 cmdvec( R200_VS_GLOBAL_AMBIENT_ADDR
, 1, 4 );
338 rmesa
->hw
.eye
.cmd
[EYE_CMD_0
] =
339 cmdvec( R200_VS_EYE_VECTOR_ADDR
, 1, 4 );
341 rmesa
->hw
.mat
[R200_MTX_MV
].cmd
[MAT_CMD_0
] =
342 cmdvec( R200_VS_MATRIX_0_MV
, 1, 16);
343 rmesa
->hw
.mat
[R200_MTX_IMV
].cmd
[MAT_CMD_0
] =
344 cmdvec( R200_VS_MATRIX_1_INV_MV
, 1, 16);
345 rmesa
->hw
.mat
[R200_MTX_MVP
].cmd
[MAT_CMD_0
] =
346 cmdvec( R200_VS_MATRIX_2_MVP
, 1, 16);
347 rmesa
->hw
.mat
[R200_MTX_TEX0
].cmd
[MAT_CMD_0
] =
348 cmdvec( R200_VS_MATRIX_3_TEX0
, 1, 16);
349 rmesa
->hw
.mat
[R200_MTX_TEX1
].cmd
[MAT_CMD_0
] =
350 cmdvec( R200_VS_MATRIX_4_TEX1
, 1, 16);
352 for (i
= 0 ; i
< 8; i
++) {
353 rmesa
->hw
.lit
[i
].cmd
[LIT_CMD_0
] =
354 cmdvec( R200_VS_LIGHT_AMBIENT_ADDR
+ i
, 8, 24 );
355 rmesa
->hw
.lit
[i
].cmd
[LIT_CMD_1
] =
356 cmdscl( R200_SS_LIGHT_DCD_ADDR
+ i
, 8, 7 );
359 for (i
= 0 ; i
< 6; i
++) {
360 rmesa
->hw
.ucp
[i
].cmd
[UCP_CMD_0
] =
361 cmdvec( R200_VS_UCP_ADDR
+ i
, 1, 4 );
364 /* Initial Harware state:
366 rmesa
->hw
.ctx
.cmd
[CTX_PP_MISC
] = (R200_ALPHA_TEST_PASS
367 /* | R200_RIGHT_HAND_CUBE_OGL*/);
369 rmesa
->hw
.ctx
.cmd
[CTX_PP_FOG_COLOR
] = (R200_FOG_VERTEX
|
370 R200_FOG_USE_SPEC_ALPHA
);
372 rmesa
->hw
.ctx
.cmd
[CTX_RE_SOLID_COLOR
] = 0x00000000;
374 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_BLENDCNTL
] = (R200_COMB_FCN_ADD_CLAMP
|
375 (R200_BLEND_GL_ONE
<< R200_SRC_BLEND_SHIFT
) |
376 (R200_BLEND_GL_ZERO
<< R200_DST_BLEND_SHIFT
));
378 if (rmesa
->r200Screen
->drmSupportsBlendColor
) {
379 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_BLENDCOLOR
] = 0x00000000;
380 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ABLENDCNTL
] = (R200_COMB_FCN_ADD_CLAMP
|
381 (R200_BLEND_GL_ONE
<< R200_SRC_BLEND_SHIFT
) |
382 (R200_BLEND_GL_ZERO
<< R200_DST_BLEND_SHIFT
));
383 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_CBLENDCNTL
] = (R200_COMB_FCN_ADD_CLAMP
|
384 (R200_BLEND_GL_ONE
<< R200_SRC_BLEND_SHIFT
) |
385 (R200_BLEND_GL_ZERO
<< R200_DST_BLEND_SHIFT
));
388 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_DEPTHOFFSET
] =
389 rmesa
->r200Screen
->depthOffset
+ rmesa
->r200Screen
->fbLocation
;
391 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_DEPTHPITCH
] =
392 ((rmesa
->r200Screen
->depthPitch
&
393 R200_DEPTHPITCH_MASK
) |
394 R200_DEPTH_ENDIAN_NO_SWAP
);
396 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] = (depth_fmt
|
398 R200_STENCIL_TEST_ALWAYS
|
399 R200_STENCIL_FAIL_KEEP
|
400 R200_STENCIL_ZPASS_KEEP
|
401 R200_STENCIL_ZFAIL_KEEP
|
402 R200_Z_WRITE_ENABLE
);
404 rmesa
->hw
.ctx
.cmd
[CTX_PP_CNTL
] = (R200_ANTI_ALIAS_NONE
405 | R200_TEX_BLEND_0_ENABLE
);
407 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_CNTL
] = color_fmt
;
408 switch ( driQueryOptioni( &rmesa
->optionCache
, "dither_mode" ) ) {
409 case DRI_CONF_DITHER_XERRORDIFFRESET
:
410 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_CNTL
] |= R200_DITHER_INIT
;
412 case DRI_CONF_DITHER_ORDERED
:
413 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_CNTL
] |= R200_SCALE_DITHER_ENABLE
;
416 if ( driQueryOptioni( &rmesa
->optionCache
, "round_mode" ) ==
417 DRI_CONF_ROUND_ROUND
)
418 rmesa
->state
.color
.roundEnable
= R200_ROUND_ENABLE
;
420 rmesa
->state
.color
.roundEnable
= 0;
421 if ( driQueryOptioni (&rmesa
->optionCache
, "color_reduction" ) ==
422 DRI_CONF_COLOR_REDUCTION_DITHER
)
423 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_CNTL
] |= R200_DITHER_ENABLE
;
425 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_CNTL
] |= rmesa
->state
.color
.roundEnable
;
427 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_COLOROFFSET
] = ((rmesa
->state
.color
.drawOffset
+
428 rmesa
->r200Screen
->fbLocation
)
429 & R200_COLOROFFSET_MASK
);
431 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_COLORPITCH
] = ((rmesa
->state
.color
.drawPitch
&
432 R200_COLORPITCH_MASK
) |
433 R200_COLOR_ENDIAN_NO_SWAP
);
435 rmesa
->hw
.set
.cmd
[SET_SE_CNTL
] = (R200_FFACE_CULL_CCW
|
438 R200_FLAT_SHADE_VTX_LAST
|
439 R200_DIFFUSE_SHADE_GOURAUD
|
440 R200_ALPHA_SHADE_GOURAUD
|
441 R200_SPECULAR_SHADE_GOURAUD
|
442 R200_FOG_SHADE_GOURAUD
|
443 R200_VTX_PIX_CENTER_OGL
|
444 R200_ROUND_MODE_TRUNC
|
445 R200_ROUND_PREC_8TH_PIX
);
447 rmesa
->hw
.set
.cmd
[SET_RE_CNTL
] = (R200_PERSPECTIVE_ENABLE
|
448 R200_SCISSOR_ENABLE
);
450 rmesa
->hw
.lin
.cmd
[LIN_RE_LINE_PATTERN
] = ((1 << 16) | 0xffff);
452 rmesa
->hw
.lin
.cmd
[LIN_RE_LINE_STATE
] =
453 ((0 << R200_LINE_CURRENT_PTR_SHIFT
) |
454 (1 << R200_LINE_CURRENT_COUNT_SHIFT
));
456 rmesa
->hw
.lin
.cmd
[LIN_SE_LINE_WIDTH
] = (1 << 4);
458 rmesa
->hw
.msk
.cmd
[MSK_RB3D_STENCILREFMASK
] =
459 ((0x00 << R200_STENCIL_REF_SHIFT
) |
460 (0xff << R200_STENCIL_MASK_SHIFT
) |
461 (0xff << R200_STENCIL_WRITEMASK_SHIFT
));
463 rmesa
->hw
.msk
.cmd
[MSK_RB3D_ROPCNTL
] = R200_ROP_COPY
;
464 rmesa
->hw
.msk
.cmd
[MSK_RB3D_PLANEMASK
] = 0xffffffff;
466 rmesa
->hw
.tam
.cmd
[TAM_DEBUG3
] = 0;
468 rmesa
->hw
.msc
.cmd
[MSC_RE_MISC
] =
469 ((0 << R200_STIPPLE_X_OFFSET_SHIFT
) |
470 (0 << R200_STIPPLE_Y_OFFSET_SHIFT
) |
471 R200_STIPPLE_BIG_BIT_ORDER
);
474 rmesa
->hw
.cst
.cmd
[CST_PP_CNTL_X
] = 0;
475 rmesa
->hw
.cst
.cmd
[CST_RB3D_DEPTHXY_OFFSET
] = 0;
476 rmesa
->hw
.cst
.cmd
[CST_RE_AUX_SCISSOR_CNTL
] = 0x0;
477 rmesa
->hw
.cst
.cmd
[CST_RE_SCISSOR_TL_0
] = 0;
478 rmesa
->hw
.cst
.cmd
[CST_RE_SCISSOR_BR_0
] = 0;
479 rmesa
->hw
.cst
.cmd
[CST_SE_VAP_CNTL_STATUS
] =
480 #ifdef MESA_BIG_ENDIAN
486 if (!(rmesa
->r200Screen
->chipset
& R200_CHIPSET_TCL
)) {
488 rmesa
->hw
.cst
.cmd
[CST_SE_VAP_CNTL_STATUS
] |= (1<<8);
491 rmesa
->hw
.cst
.cmd
[CST_RE_POINTSIZE
] = 0x100010;
492 rmesa
->hw
.cst
.cmd
[CST_SE_TCL_INPUT_VTX_0
] =
493 (0x0 << R200_VERTEX_POSITION_ADDR__SHIFT
);
494 rmesa
->hw
.cst
.cmd
[CST_SE_TCL_INPUT_VTX_1
] =
495 (0x02 << R200_VTX_COLOR_0_ADDR__SHIFT
) |
496 (0x03 << R200_VTX_COLOR_1_ADDR__SHIFT
);
497 rmesa
->hw
.cst
.cmd
[CST_SE_TCL_INPUT_VTX_2
] =
498 (0x06 << R200_VTX_TEX_0_ADDR__SHIFT
) |
499 (0x07 << R200_VTX_TEX_1_ADDR__SHIFT
) |
500 (0x08 << R200_VTX_TEX_2_ADDR__SHIFT
) |
501 (0x09 << R200_VTX_TEX_3_ADDR__SHIFT
);
502 rmesa
->hw
.cst
.cmd
[CST_SE_TCL_INPUT_VTX_3
] =
503 (0x0A << R200_VTX_TEX_4_ADDR__SHIFT
) |
504 (0x0B << R200_VTX_TEX_5_ADDR__SHIFT
);
507 rmesa
->hw
.vpt
.cmd
[VPT_SE_VPORT_XSCALE
] = 0x00000000;
508 rmesa
->hw
.vpt
.cmd
[VPT_SE_VPORT_XOFFSET
] = 0x00000000;
509 rmesa
->hw
.vpt
.cmd
[VPT_SE_VPORT_YSCALE
] = 0x00000000;
510 rmesa
->hw
.vpt
.cmd
[VPT_SE_VPORT_YOFFSET
] = 0x00000000;
511 rmesa
->hw
.vpt
.cmd
[VPT_SE_VPORT_ZSCALE
] = 0x00000000;
512 rmesa
->hw
.vpt
.cmd
[VPT_SE_VPORT_ZOFFSET
] = 0x00000000;
514 for ( i
= 0 ; i
< ctx
->Const
.MaxTextureUnits
; i
++ ) {
515 rmesa
->hw
.tex
[i
].cmd
[TEX_PP_TXFILTER
] = R200_BORDER_MODE_OGL
;
516 rmesa
->hw
.tex
[i
].cmd
[TEX_PP_TXFORMAT
] =
517 ((i
<< R200_TXFORMAT_ST_ROUTE_SHIFT
) | /* <-- note i */
518 (2 << R200_TXFORMAT_WIDTH_SHIFT
) |
519 (2 << R200_TXFORMAT_HEIGHT_SHIFT
));
520 rmesa
->hw
.tex
[i
].cmd
[TEX_PP_TXOFFSET
] =
521 rmesa
->r200Screen
->texOffset
[RADEON_LOCAL_TEX_HEAP
];
522 rmesa
->hw
.tex
[i
].cmd
[TEX_PP_BORDER_COLOR
] = 0;
523 rmesa
->hw
.tex
[i
].cmd
[TEX_PP_TXFORMAT_X
] =
524 (/* R200_TEXCOORD_PROJ | */
525 0x100000); /* Small default bias */
527 rmesa
->hw
.cube
[i
].cmd
[CUBE_PP_CUBIC_FACES
] = 0;
528 rmesa
->hw
.cube
[i
].cmd
[CUBE_PP_CUBIC_OFFSET_F1
] =
529 rmesa
->r200Screen
->texOffset
[RADEON_LOCAL_TEX_HEAP
];
530 rmesa
->hw
.cube
[i
].cmd
[CUBE_PP_CUBIC_OFFSET_F2
] =
531 rmesa
->r200Screen
->texOffset
[RADEON_LOCAL_TEX_HEAP
];
532 rmesa
->hw
.cube
[i
].cmd
[CUBE_PP_CUBIC_OFFSET_F3
] =
533 rmesa
->r200Screen
->texOffset
[RADEON_LOCAL_TEX_HEAP
];
534 rmesa
->hw
.cube
[i
].cmd
[CUBE_PP_CUBIC_OFFSET_F4
] =
535 rmesa
->r200Screen
->texOffset
[RADEON_LOCAL_TEX_HEAP
];
536 rmesa
->hw
.cube
[i
].cmd
[CUBE_PP_CUBIC_OFFSET_F5
] =
537 rmesa
->r200Screen
->texOffset
[RADEON_LOCAL_TEX_HEAP
];
540 rmesa
->hw
.pix
[0].cmd
[PIX_PP_TXCBLEND
] =
541 (R200_TXC_ARG_A_ZERO
|
542 R200_TXC_ARG_B_ZERO
|
543 R200_TXC_ARG_C_DIFFUSE_COLOR
|
546 rmesa
->hw
.pix
[0].cmd
[PIX_PP_TXCBLEND2
] =
547 ((0 << R200_TXC_TFACTOR_SEL_SHIFT
) |
550 R200_TXC_OUTPUT_REG_R0
);
552 rmesa
->hw
.pix
[0].cmd
[PIX_PP_TXABLEND
] =
553 (R200_TXA_ARG_A_ZERO
|
554 R200_TXA_ARG_B_ZERO
|
555 R200_TXA_ARG_C_DIFFUSE_ALPHA
|
558 rmesa
->hw
.pix
[0].cmd
[PIX_PP_TXABLEND2
] =
559 ((0 << R200_TXA_TFACTOR_SEL_SHIFT
) |
562 R200_TXA_OUTPUT_REG_R0
);
564 rmesa
->hw
.pix
[1].cmd
[PIX_PP_TXCBLEND
] =
565 (R200_TXC_ARG_A_ZERO
|
566 R200_TXC_ARG_B_ZERO
|
567 R200_TXC_ARG_C_DIFFUSE_COLOR
|
570 rmesa
->hw
.pix
[1].cmd
[PIX_PP_TXCBLEND2
] =
571 ((0 << R200_TXC_TFACTOR_SEL_SHIFT
) |
574 R200_TXC_OUTPUT_REG_R0
);
576 rmesa
->hw
.pix
[1].cmd
[PIX_PP_TXABLEND
] =
577 (R200_TXA_ARG_A_ZERO
|
578 R200_TXA_ARG_B_ZERO
|
579 R200_TXA_ARG_C_DIFFUSE_ALPHA
|
582 rmesa
->hw
.pix
[1].cmd
[PIX_PP_TXABLEND2
] =
583 ((0 << R200_TXA_TFACTOR_SEL_SHIFT
) |
586 R200_TXA_OUTPUT_REG_R0
);
588 rmesa
->hw
.tf
.cmd
[TF_TFACTOR_0
] = 0;
589 rmesa
->hw
.tf
.cmd
[TF_TFACTOR_1
] = 0;
590 rmesa
->hw
.tf
.cmd
[TF_TFACTOR_2
] = 0;
591 rmesa
->hw
.tf
.cmd
[TF_TFACTOR_3
] = 0;
592 rmesa
->hw
.tf
.cmd
[TF_TFACTOR_4
] = 0;
593 rmesa
->hw
.tf
.cmd
[TF_TFACTOR_5
] = 0;
595 rmesa
->hw
.vap
.cmd
[VAP_SE_VAP_CNTL
] =
596 (R200_VAP_TCL_ENABLE
|
597 (0x9 << R200_VAP_VF_MAX_VTX_NUM__SHIFT
));
599 rmesa
->hw
.vte
.cmd
[VTE_SE_VTE_CNTL
] =
600 (R200_VPORT_X_SCALE_ENA
|
601 R200_VPORT_Y_SCALE_ENA
|
602 R200_VPORT_Z_SCALE_ENA
|
603 R200_VPORT_X_OFFSET_ENA
|
604 R200_VPORT_Y_OFFSET_ENA
|
605 R200_VPORT_Z_OFFSET_ENA
|
606 /* FIXME: Turn on for tex rect only */
607 R200_VTX_ST_DENORMALIZED
|
611 rmesa
->hw
.vtx
.cmd
[VTX_VTXFMT_0
] = 0;
612 rmesa
->hw
.vtx
.cmd
[VTX_VTXFMT_1
] = 0;
613 rmesa
->hw
.vtx
.cmd
[VTX_TCL_OUTPUT_VTXFMT_0
] =
614 ((R200_VTX_Z0
| R200_VTX_W0
|
615 (R200_VTX_FP_RGBA
<< R200_VTX_COLOR_0_SHIFT
)));
616 rmesa
->hw
.vtx
.cmd
[VTX_TCL_OUTPUT_VTXFMT_1
] = 0;
617 rmesa
->hw
.vtx
.cmd
[VTX_TCL_OUTPUT_COMPSEL
] = (R200_OUTPUT_XYZW
);
618 rmesa
->hw
.vtx
.cmd
[VTX_STATE_CNTL
] = R200_VSC_UPDATE_USER_COLOR_0_ENABLE
;
621 /* Matrix selection */
622 rmesa
->hw
.msl
.cmd
[MSL_MATRIX_SELECT_0
] =
623 (R200_MTX_MV
<< R200_MODELVIEW_0_SHIFT
);
625 rmesa
->hw
.msl
.cmd
[MSL_MATRIX_SELECT_1
] =
626 (R200_MTX_IMV
<< R200_IT_MODELVIEW_0_SHIFT
);
628 rmesa
->hw
.msl
.cmd
[MSL_MATRIX_SELECT_2
] =
629 (R200_MTX_MVP
<< R200_MODELPROJECT_0_SHIFT
);
631 rmesa
->hw
.msl
.cmd
[MSL_MATRIX_SELECT_3
] =
632 ((R200_MTX_TEX0
<< R200_TEXMAT_0_SHIFT
) |
633 (R200_MTX_TEX1
<< R200_TEXMAT_1_SHIFT
) |
634 (R200_MTX_TEX2
<< R200_TEXMAT_2_SHIFT
) |
635 (R200_MTX_TEX3
<< R200_TEXMAT_3_SHIFT
));
637 rmesa
->hw
.msl
.cmd
[MSL_MATRIX_SELECT_4
] =
638 ((R200_MTX_TEX4
<< R200_TEXMAT_4_SHIFT
) |
639 (R200_MTX_TEX5
<< R200_TEXMAT_5_SHIFT
));
642 /* General TCL state */
643 rmesa
->hw
.tcl
.cmd
[TCL_LIGHT_MODEL_CTL_0
] =
644 (R200_SPECULAR_LIGHTS
|
645 R200_DIFFUSE_SPECULAR_COMBINE
|
646 R200_LOCAL_LIGHT_VEC_GL
|
647 R200_LM0_SOURCE_MATERIAL_0
<< R200_FRONT_SHININESS_SOURCE_SHIFT
|
648 R200_LM0_SOURCE_MATERIAL_1
<< R200_BACK_SHININESS_SOURCE_SHIFT
);
650 rmesa
->hw
.tcl
.cmd
[TCL_LIGHT_MODEL_CTL_1
] =
651 ((R200_LM1_SOURCE_MATERIAL_0
<< R200_FRONT_EMISSIVE_SOURCE_SHIFT
) |
652 (R200_LM1_SOURCE_MATERIAL_0
<< R200_FRONT_AMBIENT_SOURCE_SHIFT
) |
653 (R200_LM1_SOURCE_MATERIAL_0
<< R200_FRONT_DIFFUSE_SOURCE_SHIFT
) |
654 (R200_LM1_SOURCE_MATERIAL_0
<< R200_FRONT_SPECULAR_SOURCE_SHIFT
) |
655 (R200_LM1_SOURCE_MATERIAL_1
<< R200_BACK_EMISSIVE_SOURCE_SHIFT
) |
656 (R200_LM1_SOURCE_MATERIAL_1
<< R200_BACK_AMBIENT_SOURCE_SHIFT
) |
657 (R200_LM1_SOURCE_MATERIAL_1
<< R200_BACK_DIFFUSE_SOURCE_SHIFT
) |
658 (R200_LM1_SOURCE_MATERIAL_1
<< R200_BACK_SPECULAR_SOURCE_SHIFT
));
660 rmesa
->hw
.tcl
.cmd
[TCL_PER_LIGHT_CTL_0
] = 0; /* filled in via callbacks */
661 rmesa
->hw
.tcl
.cmd
[TCL_PER_LIGHT_CTL_1
] = 0;
662 rmesa
->hw
.tcl
.cmd
[TCL_PER_LIGHT_CTL_2
] = 0;
663 rmesa
->hw
.tcl
.cmd
[TCL_PER_LIGHT_CTL_3
] = 0;
665 rmesa
->hw
.tcl
.cmd
[TCL_UCP_VERT_BLEND_CTL
] =
666 (R200_UCP_IN_CLIP_SPACE
|
667 R200_CULL_FRONT_IS_CCW
);
669 /* Texgen/Texmat state */
670 rmesa
->hw
.tcg
.cmd
[TCG_TEX_PROC_CTL_2
] = 0x0; /* masks??? */
671 rmesa
->hw
.tcg
.cmd
[TCG_TEX_PROC_CTL_3
] =
672 ((0 << R200_TEXGEN_0_INPUT_TEX_SHIFT
) |
673 (1 << R200_TEXGEN_1_INPUT_TEX_SHIFT
) |
674 (2 << R200_TEXGEN_2_INPUT_TEX_SHIFT
) |
675 (3 << R200_TEXGEN_3_INPUT_TEX_SHIFT
) |
676 (4 << R200_TEXGEN_4_INPUT_TEX_SHIFT
) |
677 (5 << R200_TEXGEN_5_INPUT_TEX_SHIFT
));
678 rmesa
->hw
.tcg
.cmd
[TCG_TEX_PROC_CTL_0
] = 0;
679 rmesa
->hw
.tcg
.cmd
[TCG_TEX_PROC_CTL_1
] =
680 ((0 << R200_TEXGEN_0_INPUT_SHIFT
) |
681 (1 << R200_TEXGEN_1_INPUT_SHIFT
) |
682 (2 << R200_TEXGEN_2_INPUT_SHIFT
) |
683 (3 << R200_TEXGEN_3_INPUT_SHIFT
) |
684 (4 << R200_TEXGEN_4_INPUT_SHIFT
) |
685 (5 << R200_TEXGEN_5_INPUT_SHIFT
));
686 rmesa
->hw
.tcg
.cmd
[TCG_TEX_CYL_WRAP_CTL
] = 0;
688 rmesa
->TexGenInputs
= rmesa
->hw
.tcg
.cmd
[TCG_TEX_PROC_CTL_1
];
691 for (i
= 0 ; i
< 8; i
++) {
692 struct gl_light
*l
= &ctx
->Light
.Light
[i
];
693 GLenum p
= GL_LIGHT0
+ i
;
694 *(float *)&(rmesa
->hw
.lit
[i
].cmd
[LIT_RANGE_CUTOFF
]) = FLT_MAX
;
696 ctx
->Driver
.Lightfv( ctx
, p
, GL_AMBIENT
, l
->Ambient
);
697 ctx
->Driver
.Lightfv( ctx
, p
, GL_DIFFUSE
, l
->Diffuse
);
698 ctx
->Driver
.Lightfv( ctx
, p
, GL_SPECULAR
, l
->Specular
);
699 ctx
->Driver
.Lightfv( ctx
, p
, GL_POSITION
, 0 );
700 ctx
->Driver
.Lightfv( ctx
, p
, GL_SPOT_DIRECTION
, 0 );
701 ctx
->Driver
.Lightfv( ctx
, p
, GL_SPOT_EXPONENT
, &l
->SpotExponent
);
702 ctx
->Driver
.Lightfv( ctx
, p
, GL_SPOT_CUTOFF
, &l
->SpotCutoff
);
703 ctx
->Driver
.Lightfv( ctx
, p
, GL_CONSTANT_ATTENUATION
,
704 &l
->ConstantAttenuation
);
705 ctx
->Driver
.Lightfv( ctx
, p
, GL_LINEAR_ATTENUATION
,
706 &l
->LinearAttenuation
);
707 ctx
->Driver
.Lightfv( ctx
, p
, GL_QUADRATIC_ATTENUATION
,
708 &l
->QuadraticAttenuation
);
709 *(float *)&(rmesa
->hw
.lit
[i
].cmd
[LIT_ATTEN_XXX
]) = 0.0;
712 ctx
->Driver
.LightModelfv( ctx
, GL_LIGHT_MODEL_AMBIENT
,
713 ctx
->Light
.Model
.Ambient
);
715 TNL_CONTEXT(ctx
)->Driver
.NotifyMaterialChange( ctx
);
717 for (i
= 0 ; i
< 6; i
++) {
718 ctx
->Driver
.ClipPlane( ctx
, GL_CLIP_PLANE0
+ i
, NULL
);
721 ctx
->Driver
.Fogfv( ctx
, GL_FOG_MODE
, 0 );
722 ctx
->Driver
.Fogfv( ctx
, GL_FOG_DENSITY
, &ctx
->Fog
.Density
);
723 ctx
->Driver
.Fogfv( ctx
, GL_FOG_START
, &ctx
->Fog
.Start
);
724 ctx
->Driver
.Fogfv( ctx
, GL_FOG_END
, &ctx
->Fog
.End
);
725 ctx
->Driver
.Fogfv( ctx
, GL_FOG_COLOR
, ctx
->Fog
.Color
);
726 ctx
->Driver
.Fogfv( ctx
, GL_FOG_COORDINATE_SOURCE_EXT
, 0 );
728 rmesa
->hw
.grd
.cmd
[GRD_VERT_GUARD_CLIP_ADJ
] = IEEE_ONE
;
729 rmesa
->hw
.grd
.cmd
[GRD_VERT_GUARD_DISCARD_ADJ
] = IEEE_ONE
;
730 rmesa
->hw
.grd
.cmd
[GRD_HORZ_GUARD_CLIP_ADJ
] = IEEE_ONE
;
731 rmesa
->hw
.grd
.cmd
[GRD_HORZ_GUARD_DISCARD_ADJ
] = IEEE_ONE
;
733 rmesa
->hw
.eye
.cmd
[EYE_X
] = 0;
734 rmesa
->hw
.eye
.cmd
[EYE_Y
] = 0;
735 rmesa
->hw
.eye
.cmd
[EYE_Z
] = IEEE_ONE
;
736 rmesa
->hw
.eye
.cmd
[EYE_RESCALE_FACTOR
] = IEEE_ONE
;
738 r200LightingSpaceChange( ctx
);
740 rmesa
->lost_context
= 1;