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implement arb_vertex_program in hw for r200. Code contains still some hacks, generic...
[mesa.git] / src / mesa / drivers / dri / r200 / r200_state_init.c
1 /* $XFree86: xc/lib/GL/mesa/src/drv/r200/r200_state_init.c,v 1.4 2003/02/22 06:21:11 dawes Exp $ */
2 /*
3 Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
4
5 The Weather Channel (TM) funded Tungsten Graphics to develop the
6 initial release of the Radeon 8500 driver under the XFree86 license.
7 This notice must be preserved.
8
9 Permission is hereby granted, free of charge, to any person obtaining
10 a copy of this software and associated documentation files (the
11 "Software"), to deal in the Software without restriction, including
12 without limitation the rights to use, copy, modify, merge, publish,
13 distribute, sublicense, and/or sell copies of the Software, and to
14 permit persons to whom the Software is furnished to do so, subject to
15 the following conditions:
16
17 The above copyright notice and this permission notice (including the
18 next paragraph) shall be included in all copies or substantial
19 portions of the Software.
20
21 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
22 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
23 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
24 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
25 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
26 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
27 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
28 */
29
30 /*
31 * Authors:
32 * Keith Whitwell <keith@tungstengraphics.com>
33 */
34
35 #include "glheader.h"
36 #include "imports.h"
37 #include "enums.h"
38 #include "colormac.h"
39 #include "api_arrayelt.h"
40
41 #include "swrast/swrast.h"
42 #include "array_cache/acache.h"
43 #include "tnl/tnl.h"
44 #include "tnl/t_pipeline.h"
45 #include "swrast_setup/swrast_setup.h"
46
47 #include "r200_context.h"
48 #include "r200_ioctl.h"
49 #include "r200_state.h"
50 #include "r200_tcl.h"
51 #include "r200_tex.h"
52 #include "r200_swtcl.h"
53 #include "r200_vtxfmt.h"
54
55 #include "xmlpool.h"
56
57 /* =============================================================
58 * State initialization
59 */
60
61 void r200PrintDirty( r200ContextPtr rmesa, const char *msg )
62 {
63 struct r200_state_atom *l;
64
65 fprintf(stderr, msg);
66 fprintf(stderr, ": ");
67
68 foreach(l, &rmesa->hw.atomlist) {
69 if (l->dirty || rmesa->hw.all_dirty)
70 fprintf(stderr, "%s, ", l->name);
71 }
72
73 fprintf(stderr, "\n");
74 }
75
76 static int cmdpkt( int id )
77 {
78 drm_radeon_cmd_header_t h;
79 h.i = 0;
80 h.packet.cmd_type = RADEON_CMD_PACKET;
81 h.packet.packet_id = id;
82 return h.i;
83 }
84
85 static int cmdvec( int offset, int stride, int count )
86 {
87 drm_radeon_cmd_header_t h;
88 h.i = 0;
89 h.vectors.cmd_type = RADEON_CMD_VECTORS;
90 h.vectors.offset = offset;
91 h.vectors.stride = stride;
92 h.vectors.count = count;
93 return h.i;
94 }
95
96 /* warning: the count here is divided by 4 compared to other cmds
97 (so it doesn't exceed the char size)! */
98 static int cmdveclinear( int offset, int count )
99 {
100 drm_radeon_cmd_header_t h;
101 h.i = 0;
102 h.veclinear.cmd_type = RADEON_CMD_VECLINEAR;
103 h.veclinear.addr_lo = offset & 0xff;
104 h.veclinear.addr_hi = (offset & 0xff00) >> 8;
105 h.veclinear.count = count;
106 return h.i;
107 }
108
109 static int cmdscl( int offset, int stride, int count )
110 {
111 drm_radeon_cmd_header_t h;
112 h.i = 0;
113 h.scalars.cmd_type = RADEON_CMD_SCALARS;
114 h.scalars.offset = offset;
115 h.scalars.stride = stride;
116 h.scalars.count = count;
117 return h.i;
118 }
119
120 static int cmdscl2( int offset, int stride, int count )
121 {
122 drm_radeon_cmd_header_t h;
123 h.i = 0;
124 h.scalars.cmd_type = RADEON_CMD_SCALARS2;
125 h.scalars.offset = offset - 0x100;
126 h.scalars.stride = stride;
127 h.scalars.count = count;
128 return h.i;
129 }
130
131 #define CHECK( NM, FLAG ) \
132 static GLboolean check_##NM( GLcontext *ctx, int idx ) \
133 { \
134 r200ContextPtr rmesa = R200_CONTEXT(ctx); \
135 (void) idx; \
136 (void) rmesa; \
137 return FLAG; \
138 }
139
140 #define TCL_CHECK( NM, FLAG ) \
141 static GLboolean check_##NM( GLcontext *ctx, int idx ) \
142 { \
143 r200ContextPtr rmesa = R200_CONTEXT(ctx); \
144 (void) idx; \
145 return !rmesa->TclFallback && !ctx->VertexProgram._Enabled && (FLAG); \
146 }
147
148 #define TCL_OR_VP_CHECK( NM, FLAG ) \
149 static GLboolean check_##NM( GLcontext *ctx, int idx ) \
150 { \
151 r200ContextPtr rmesa = R200_CONTEXT(ctx); \
152 (void) idx; \
153 return !rmesa->TclFallback && (FLAG); \
154 }
155
156 #define VP_CHECK( NM, FLAG ) \
157 static GLboolean check_##NM( GLcontext *ctx, int idx ) \
158 { \
159 r200ContextPtr rmesa = R200_CONTEXT(ctx); \
160 (void) idx; \
161 return !rmesa->TclFallback && ctx->VertexProgram._Enabled && (FLAG); \
162 }
163
164
165 CHECK( always, GL_TRUE )
166 CHECK( never, GL_FALSE )
167 CHECK( tex_any, ctx->Texture._EnabledUnits )
168 CHECK( tf, (ctx->Texture._EnabledUnits && !ctx->ATIFragmentShader._Enabled) );
169 CHECK( tex_pair, (rmesa->state.texture.unit[idx].unitneeded | rmesa->state.texture.unit[idx & ~1].unitneeded) )
170 CHECK( tex, rmesa->state.texture.unit[idx].unitneeded )
171 CHECK( pix_zero, !ctx->ATIFragmentShader._Enabled )
172 CHECK( texenv, (rmesa->state.envneeded & (1 << idx) && !ctx->ATIFragmentShader._Enabled) )
173 CHECK( afs_pass1, (ctx->ATIFragmentShader._Enabled && (ctx->ATIFragmentShader.Current->NumPasses > 1)) )
174 CHECK( afs, ctx->ATIFragmentShader._Enabled )
175 CHECK( tex_cube, rmesa->state.texture.unit[idx].unitneeded & TEXTURE_CUBE_BIT )
176 CHECK( fog, ctx->Fog.Enabled )
177 TCL_CHECK( tcl, GL_TRUE )
178 TCL_CHECK( tcl_tex, rmesa->state.texture.unit[idx].unitneeded )
179 TCL_CHECK( tcl_lighting, ctx->Light.Enabled )
180 TCL_CHECK( tcl_light, ctx->Light.Enabled && ctx->Light.Light[idx].Enabled )
181 TCL_OR_VP_CHECK( tcl_ucp, (ctx->Transform.ClipPlanesEnabled & (1 << idx)) )
182 TCL_OR_VP_CHECK( tcl_or_vp, GL_TRUE )
183 VP_CHECK( tcl_vp, GL_TRUE )
184 VP_CHECK( tcl_vp_size, ctx->VertexProgram.Current->Base.NumNativeInstructions > 64 )
185 VP_CHECK( tcl_vpp_size, ctx->VertexProgram.Current->Base.NumNativeParameters > 96 )
186
187
188 /* Initialize the context's hardware state.
189 */
190 void r200InitState( r200ContextPtr rmesa )
191 {
192 GLcontext *ctx = rmesa->glCtx;
193 GLuint color_fmt, depth_fmt, i;
194 GLint drawPitch, drawOffset;
195
196 switch ( rmesa->r200Screen->cpp ) {
197 case 2:
198 color_fmt = R200_COLOR_FORMAT_RGB565;
199 break;
200 case 4:
201 color_fmt = R200_COLOR_FORMAT_ARGB8888;
202 break;
203 default:
204 fprintf( stderr, "Error: Unsupported pixel depth... exiting\n" );
205 exit( -1 );
206 }
207
208 rmesa->state.color.clear = 0x00000000;
209
210 switch ( ctx->Visual.depthBits ) {
211 case 16:
212 rmesa->state.depth.clear = 0x0000ffff;
213 rmesa->state.depth.scale = 1.0 / (GLfloat)0xffff;
214 depth_fmt = R200_DEPTH_FORMAT_16BIT_INT_Z;
215 rmesa->state.stencil.clear = 0x00000000;
216 break;
217 case 24:
218 rmesa->state.depth.clear = 0x00ffffff;
219 rmesa->state.depth.scale = 1.0 / (GLfloat)0xffffff;
220 depth_fmt = R200_DEPTH_FORMAT_24BIT_INT_Z;
221 rmesa->state.stencil.clear = 0xffff0000;
222 break;
223 default:
224 fprintf( stderr, "Error: Unsupported depth %d... exiting\n",
225 ctx->Visual.depthBits );
226 exit( -1 );
227 }
228
229 /* Only have hw stencil when depth buffer is 24 bits deep */
230 rmesa->state.stencil.hwBuffer = ( ctx->Visual.stencilBits > 0 &&
231 ctx->Visual.depthBits == 24 );
232
233 rmesa->Fallback = 0;
234
235 if ( ctx->Visual.doubleBufferMode && rmesa->sarea->pfCurrentPage == 0 ) {
236 drawOffset = rmesa->r200Screen->backOffset;
237 drawPitch = rmesa->r200Screen->backPitch;
238 } else {
239 drawOffset = rmesa->r200Screen->frontOffset;
240 drawPitch = rmesa->r200Screen->frontPitch;
241 }
242 #if 000
243 if ( ctx->Visual.doubleBufferMode && rmesa->sarea->pfCurrentPage == 0 ) {
244 rmesa->state.color.drawOffset = rmesa->r200Screen->backOffset;
245 rmesa->state.color.drawPitch = rmesa->r200Screen->backPitch;
246 } else {
247 rmesa->state.color.drawOffset = rmesa->r200Screen->frontOffset;
248 rmesa->state.color.drawPitch = rmesa->r200Screen->frontPitch;
249 }
250
251 rmesa->state.pixel.readOffset = rmesa->state.color.drawOffset;
252 rmesa->state.pixel.readPitch = rmesa->state.color.drawPitch;
253 #endif
254
255 rmesa->hw.max_state_size = 0;
256
257 #define ALLOC_STATE( ATOM, CHK, SZ, NM, IDX ) \
258 do { \
259 rmesa->hw.ATOM.cmd_size = SZ; \
260 rmesa->hw.ATOM.cmd = (int *)CALLOC(SZ * sizeof(int)); \
261 rmesa->hw.ATOM.lastcmd = (int *)CALLOC(SZ * sizeof(int)); \
262 rmesa->hw.ATOM.name = NM; \
263 rmesa->hw.ATOM.idx = IDX; \
264 rmesa->hw.ATOM.check = check_##CHK; \
265 rmesa->hw.ATOM.dirty = GL_FALSE; \
266 rmesa->hw.max_state_size += SZ * sizeof(int); \
267 } while (0)
268
269
270 /* Allocate state buffers:
271 */
272 if (rmesa->r200Screen->drmSupportsBlendColor)
273 ALLOC_STATE( ctx, always, CTX_STATE_SIZE_NEWDRM, "CTX/context", 0 );
274 else
275 ALLOC_STATE( ctx, always, CTX_STATE_SIZE_OLDDRM, "CTX/context", 0 );
276 ALLOC_STATE( set, always, SET_STATE_SIZE, "SET/setup", 0 );
277 ALLOC_STATE( lin, always, LIN_STATE_SIZE, "LIN/line", 0 );
278 ALLOC_STATE( msk, always, MSK_STATE_SIZE, "MSK/mask", 0 );
279 ALLOC_STATE( vpt, always, VPT_STATE_SIZE, "VPT/viewport", 0 );
280 ALLOC_STATE( vtx, always, VTX_STATE_SIZE, "VTX/vertex", 0 );
281 ALLOC_STATE( vap, always, VAP_STATE_SIZE, "VAP/vap", 0 );
282 ALLOC_STATE( vte, always, VTE_STATE_SIZE, "VTE/vte", 0 );
283 ALLOC_STATE( msc, always, MSC_STATE_SIZE, "MSC/misc", 0 );
284 ALLOC_STATE( cst, always, CST_STATE_SIZE, "CST/constant", 0 );
285 ALLOC_STATE( zbs, always, ZBS_STATE_SIZE, "ZBS/zbias", 0 );
286 ALLOC_STATE( tf, tf, TF_STATE_SIZE, "TF/tfactor", 0 );
287 if (rmesa->r200Screen->drmSupportsFragShader) {
288 if (rmesa->r200Screen->chip_family == CHIP_FAMILY_R200) {
289 /* make sure texture units 0/1 are emitted pair-wise for r200 t0 hang workaround */
290 ALLOC_STATE( tex[0], tex_pair, TEX_STATE_SIZE_NEWDRM, "TEX/tex-0", 0 );
291 ALLOC_STATE( tex[1], tex_pair, TEX_STATE_SIZE_NEWDRM, "TEX/tex-1", 1 );
292 ALLOC_STATE( tam, tex_any, TAM_STATE_SIZE, "TAM/tam", 0 );
293 }
294 else {
295 ALLOC_STATE( tex[0], tex, TEX_STATE_SIZE_NEWDRM, "TEX/tex-0", 0 );
296 ALLOC_STATE( tex[1], tex, TEX_STATE_SIZE_NEWDRM, "TEX/tex-1", 1 );
297 ALLOC_STATE( tam, never, TAM_STATE_SIZE, "TAM/tam", 0 );
298 }
299 ALLOC_STATE( tex[2], tex, TEX_STATE_SIZE_NEWDRM, "TEX/tex-2", 2 );
300 ALLOC_STATE( tex[3], tex, TEX_STATE_SIZE_NEWDRM, "TEX/tex-3", 3 );
301 ALLOC_STATE( tex[4], tex, TEX_STATE_SIZE_NEWDRM, "TEX/tex-4", 4 );
302 ALLOC_STATE( tex[5], tex, TEX_STATE_SIZE_NEWDRM, "TEX/tex-5", 5 );
303 ALLOC_STATE( atf, afs, ATF_STATE_SIZE, "ATF/tfactor", 0 );
304 ALLOC_STATE( afs[0], afs_pass1, AFS_STATE_SIZE, "AFS/afsinst-0", 0 );
305 ALLOC_STATE( afs[1], afs, AFS_STATE_SIZE, "AFS/afsinst-1", 1 );
306 }
307 else {
308 if (rmesa->r200Screen->chip_family == CHIP_FAMILY_R200) {
309 ALLOC_STATE( tex[0], tex_pair, TEX_STATE_SIZE_OLDDRM, "TEX/tex-0", 0 );
310 ALLOC_STATE( tex[1], tex_pair, TEX_STATE_SIZE_OLDDRM, "TEX/tex-1", 1 );
311 ALLOC_STATE( tam, tex_any, TAM_STATE_SIZE, "TAM/tam", 0 );
312 }
313 else {
314 ALLOC_STATE( tex[0], tex, TEX_STATE_SIZE_OLDDRM, "TEX/tex-0", 0 );
315 ALLOC_STATE( tex[1], tex, TEX_STATE_SIZE_OLDDRM, "TEX/tex-1", 1 );
316 ALLOC_STATE( tam, never, TAM_STATE_SIZE, "TAM/tam", 0 );
317 }
318 ALLOC_STATE( tex[2], tex, TEX_STATE_SIZE_OLDDRM, "TEX/tex-2", 2 );
319 ALLOC_STATE( tex[3], tex, TEX_STATE_SIZE_OLDDRM, "TEX/tex-3", 3 );
320 ALLOC_STATE( tex[4], tex, TEX_STATE_SIZE_OLDDRM, "TEX/tex-4", 4 );
321 ALLOC_STATE( tex[5], tex, TEX_STATE_SIZE_OLDDRM, "TEX/tex-5", 5 );
322 ALLOC_STATE( atf, never, ATF_STATE_SIZE, "TF/tfactor", 0 );
323 ALLOC_STATE( afs[0], never, AFS_STATE_SIZE, "AFS/afsinst-0", 0 );
324 ALLOC_STATE( afs[1], never, AFS_STATE_SIZE, "AFS/afsinst-1", 1 );
325 }
326 if (rmesa->r200Screen->drmSupportsCubeMapsR200) {
327 ALLOC_STATE( cube[0], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-0", 0 );
328 ALLOC_STATE( cube[1], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-1", 1 );
329 ALLOC_STATE( cube[2], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-2", 2 );
330 ALLOC_STATE( cube[3], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-3", 3 );
331 ALLOC_STATE( cube[4], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-4", 4 );
332 ALLOC_STATE( cube[5], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-5", 5 );
333 }
334 else {
335 ALLOC_STATE( cube[0], never, CUBE_STATE_SIZE, "CUBE/tex-0", 0 );
336 ALLOC_STATE( cube[1], never, CUBE_STATE_SIZE, "CUBE/tex-1", 1 );
337 ALLOC_STATE( cube[2], never, CUBE_STATE_SIZE, "CUBE/tex-2", 2 );
338 ALLOC_STATE( cube[3], never, CUBE_STATE_SIZE, "CUBE/tex-3", 3 );
339 ALLOC_STATE( cube[4], never, CUBE_STATE_SIZE, "CUBE/tex-4", 4 );
340 ALLOC_STATE( cube[5], never, CUBE_STATE_SIZE, "CUBE/tex-5", 5 );
341 }
342 if (rmesa->r200Screen->drmSupportsVertexProgram) {
343 ALLOC_STATE( pvs, tcl_vp, PVS_STATE_SIZE, "PVS/pvscntl", 0 );
344 ALLOC_STATE( vpi[0], tcl_vp, VPI_STATE_SIZE, "VP/vertexprog-0", 0 );
345 ALLOC_STATE( vpi[1], tcl_vp_size, VPI_STATE_SIZE, "VP/vertexprog-1", 1 );
346 ALLOC_STATE( vpp[0], tcl_vp, VPP_STATE_SIZE, "VPP/vertexparam-0", 0 );
347 ALLOC_STATE( vpp[1], tcl_vpp_size, VPP_STATE_SIZE, "VPP/vertexparam-1", 1 );
348 }
349 else {
350 ALLOC_STATE( pvs, never, PVS_STATE_SIZE, "PVS/pvscntl", 0 );
351 ALLOC_STATE( vpi[0], never, VPI_STATE_SIZE, "VP/vertexprog-0", 0 );
352 ALLOC_STATE( vpi[1], never, VPI_STATE_SIZE, "VP/vertexprog-1", 1 );
353 ALLOC_STATE( vpp[0], never, VPP_STATE_SIZE, "VPP/vertexparam-0", 0 );
354 ALLOC_STATE( vpp[1], never, VPP_STATE_SIZE, "VPP/vertexparam-1", 1 );
355 }
356 /* FIXME: this atom has two commands, we need only one (ucp_vert_blend) for vp */
357 ALLOC_STATE( tcl, tcl_or_vp, TCL_STATE_SIZE, "TCL/tcl", 0 );
358 ALLOC_STATE( msl, tcl, MSL_STATE_SIZE, "MSL/matrix-select", 0 );
359 ALLOC_STATE( tcg, tcl, TCG_STATE_SIZE, "TCG/texcoordgen", 0 );
360 ALLOC_STATE( mtl[0], tcl_lighting, MTL_STATE_SIZE, "MTL0/material0", 0 );
361 ALLOC_STATE( mtl[1], tcl_lighting, MTL_STATE_SIZE, "MTL1/material1", 1 );
362 ALLOC_STATE( grd, tcl_or_vp, GRD_STATE_SIZE, "GRD/guard-band", 0 );
363 ALLOC_STATE( fog, fog, FOG_STATE_SIZE, "FOG/fog", 0 );
364 ALLOC_STATE( glt, tcl_lighting, GLT_STATE_SIZE, "GLT/light-global", 0 );
365 ALLOC_STATE( eye, tcl_lighting, EYE_STATE_SIZE, "EYE/eye-vector", 0 );
366 ALLOC_STATE( mat[R200_MTX_MV], tcl, MAT_STATE_SIZE, "MAT/modelview", 0 );
367 ALLOC_STATE( mat[R200_MTX_IMV], tcl, MAT_STATE_SIZE, "MAT/it-modelview", 0 );
368 ALLOC_STATE( mat[R200_MTX_MVP], tcl, MAT_STATE_SIZE, "MAT/modelproject", 0 );
369 ALLOC_STATE( mat[R200_MTX_TEX0], tcl_tex, MAT_STATE_SIZE, "MAT/texmat0", 0 );
370 ALLOC_STATE( mat[R200_MTX_TEX1], tcl_tex, MAT_STATE_SIZE, "MAT/texmat1", 1 );
371 ALLOC_STATE( mat[R200_MTX_TEX2], tcl_tex, MAT_STATE_SIZE, "MAT/texmat2", 2 );
372 ALLOC_STATE( mat[R200_MTX_TEX3], tcl_tex, MAT_STATE_SIZE, "MAT/texmat3", 3 );
373 ALLOC_STATE( mat[R200_MTX_TEX4], tcl_tex, MAT_STATE_SIZE, "MAT/texmat4", 4 );
374 ALLOC_STATE( mat[R200_MTX_TEX5], tcl_tex, MAT_STATE_SIZE, "MAT/texmat5", 5 );
375 ALLOC_STATE( ucp[0], tcl_ucp, UCP_STATE_SIZE, "UCP/userclip-0", 0 );
376 ALLOC_STATE( ucp[1], tcl_ucp, UCP_STATE_SIZE, "UCP/userclip-1", 1 );
377 ALLOC_STATE( ucp[2], tcl_ucp, UCP_STATE_SIZE, "UCP/userclip-2", 2 );
378 ALLOC_STATE( ucp[3], tcl_ucp, UCP_STATE_SIZE, "UCP/userclip-3", 3 );
379 ALLOC_STATE( ucp[4], tcl_ucp, UCP_STATE_SIZE, "UCP/userclip-4", 4 );
380 ALLOC_STATE( ucp[5], tcl_ucp, UCP_STATE_SIZE, "UCP/userclip-5", 5 );
381 ALLOC_STATE( lit[0], tcl_light, LIT_STATE_SIZE, "LIT/light-0", 0 );
382 ALLOC_STATE( lit[1], tcl_light, LIT_STATE_SIZE, "LIT/light-1", 1 );
383 ALLOC_STATE( lit[2], tcl_light, LIT_STATE_SIZE, "LIT/light-2", 2 );
384 ALLOC_STATE( lit[3], tcl_light, LIT_STATE_SIZE, "LIT/light-3", 3 );
385 ALLOC_STATE( lit[4], tcl_light, LIT_STATE_SIZE, "LIT/light-4", 4 );
386 ALLOC_STATE( lit[5], tcl_light, LIT_STATE_SIZE, "LIT/light-5", 5 );
387 ALLOC_STATE( lit[6], tcl_light, LIT_STATE_SIZE, "LIT/light-6", 6 );
388 ALLOC_STATE( lit[7], tcl_light, LIT_STATE_SIZE, "LIT/light-7", 7 );
389 ALLOC_STATE( pix[0], pix_zero, PIX_STATE_SIZE, "PIX/pixstage-0", 0 );
390 ALLOC_STATE( pix[1], texenv, PIX_STATE_SIZE, "PIX/pixstage-1", 1 );
391 ALLOC_STATE( pix[2], texenv, PIX_STATE_SIZE, "PIX/pixstage-2", 2 );
392 ALLOC_STATE( pix[3], texenv, PIX_STATE_SIZE, "PIX/pixstage-3", 3 );
393 ALLOC_STATE( pix[4], texenv, PIX_STATE_SIZE, "PIX/pixstage-4", 4 );
394 ALLOC_STATE( pix[5], texenv, PIX_STATE_SIZE, "PIX/pixstage-5", 5 );
395 if (rmesa->r200Screen->drmSupportsTriPerf) {
396 ALLOC_STATE( prf, always, PRF_STATE_SIZE, "PRF/performance-tri", 0 );
397 }
398 else {
399 ALLOC_STATE( prf, never, PRF_STATE_SIZE, "PRF/performance-tri", 0 );
400 }
401 if (rmesa->r200Screen->drmSupportsPointSprites)
402 ALLOC_STATE( spr, always, SPR_STATE_SIZE, "SPR/pointsprite", 0 );
403 else
404 ALLOC_STATE (spr, never, SPR_STATE_SIZE, "SPR/pointsprite", 0 );
405
406 r200SetUpAtomList( rmesa );
407
408 /* Fill in the packet headers:
409 */
410 rmesa->hw.ctx.cmd[CTX_CMD_0] = cmdpkt(RADEON_EMIT_PP_MISC);
411 rmesa->hw.ctx.cmd[CTX_CMD_1] = cmdpkt(RADEON_EMIT_PP_CNTL);
412 rmesa->hw.ctx.cmd[CTX_CMD_2] = cmdpkt(RADEON_EMIT_RB3D_COLORPITCH);
413 if (rmesa->r200Screen->drmSupportsBlendColor)
414 rmesa->hw.ctx.cmd[CTX_CMD_3] = cmdpkt(R200_EMIT_RB3D_BLENDCOLOR);
415 rmesa->hw.lin.cmd[LIN_CMD_0] = cmdpkt(RADEON_EMIT_RE_LINE_PATTERN);
416 rmesa->hw.lin.cmd[LIN_CMD_1] = cmdpkt(RADEON_EMIT_SE_LINE_WIDTH);
417 rmesa->hw.msk.cmd[MSK_CMD_0] = cmdpkt(RADEON_EMIT_RB3D_STENCILREFMASK);
418 rmesa->hw.vpt.cmd[VPT_CMD_0] = cmdpkt(RADEON_EMIT_SE_VPORT_XSCALE);
419 rmesa->hw.set.cmd[SET_CMD_0] = cmdpkt(RADEON_EMIT_SE_CNTL);
420 rmesa->hw.msc.cmd[MSC_CMD_0] = cmdpkt(RADEON_EMIT_RE_MISC);
421 rmesa->hw.cst.cmd[CST_CMD_0] = cmdpkt(R200_EMIT_PP_CNTL_X);
422 rmesa->hw.cst.cmd[CST_CMD_1] = cmdpkt(R200_EMIT_RB3D_DEPTHXY_OFFSET);
423 rmesa->hw.cst.cmd[CST_CMD_2] = cmdpkt(R200_EMIT_RE_AUX_SCISSOR_CNTL);
424 rmesa->hw.cst.cmd[CST_CMD_3] = cmdpkt(R200_EMIT_RE_SCISSOR_TL_0);
425 rmesa->hw.cst.cmd[CST_CMD_4] = cmdpkt(R200_EMIT_SE_VAP_CNTL_STATUS);
426 rmesa->hw.cst.cmd[CST_CMD_5] = cmdpkt(R200_EMIT_RE_POINTSIZE);
427 rmesa->hw.cst.cmd[CST_CMD_6] = cmdpkt(R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0);
428 rmesa->hw.tam.cmd[TAM_CMD_0] = cmdpkt(R200_EMIT_PP_TAM_DEBUG3);
429 rmesa->hw.tf.cmd[TF_CMD_0] = cmdpkt(R200_EMIT_TFACTOR_0);
430 if (rmesa->r200Screen->drmSupportsFragShader) {
431 rmesa->hw.atf.cmd[ATF_CMD_0] = cmdpkt(R200_EMIT_ATF_TFACTOR);
432 rmesa->hw.tex[0].cmd[TEX_CMD_0] = cmdpkt(R200_EMIT_PP_TXCTLALL_0);
433 rmesa->hw.tex[0].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(R200_EMIT_PP_TXOFFSET_0);
434 rmesa->hw.tex[1].cmd[TEX_CMD_0] = cmdpkt(R200_EMIT_PP_TXCTLALL_1);
435 rmesa->hw.tex[1].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(R200_EMIT_PP_TXOFFSET_1);
436 rmesa->hw.tex[2].cmd[TEX_CMD_0] = cmdpkt(R200_EMIT_PP_TXCTLALL_2);
437 rmesa->hw.tex[2].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(R200_EMIT_PP_TXOFFSET_2);
438 rmesa->hw.tex[3].cmd[TEX_CMD_0] = cmdpkt(R200_EMIT_PP_TXCTLALL_3);
439 rmesa->hw.tex[3].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(R200_EMIT_PP_TXOFFSET_3);
440 rmesa->hw.tex[4].cmd[TEX_CMD_0] = cmdpkt(R200_EMIT_PP_TXCTLALL_4);
441 rmesa->hw.tex[4].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(R200_EMIT_PP_TXOFFSET_4);
442 rmesa->hw.tex[5].cmd[TEX_CMD_0] = cmdpkt(R200_EMIT_PP_TXCTLALL_5);
443 rmesa->hw.tex[5].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(R200_EMIT_PP_TXOFFSET_5);
444 } else {
445 rmesa->hw.tex[0].cmd[TEX_CMD_0] = cmdpkt(R200_EMIT_PP_TXFILTER_0);
446 rmesa->hw.tex[0].cmd[TEX_CMD_1_OLDDRM] = cmdpkt(R200_EMIT_PP_TXOFFSET_0);
447 rmesa->hw.tex[1].cmd[TEX_CMD_0] = cmdpkt(R200_EMIT_PP_TXFILTER_1);
448 rmesa->hw.tex[1].cmd[TEX_CMD_1_OLDDRM] = cmdpkt(R200_EMIT_PP_TXOFFSET_1);
449 rmesa->hw.tex[2].cmd[TEX_CMD_0] = cmdpkt(R200_EMIT_PP_TXFILTER_2);
450 rmesa->hw.tex[2].cmd[TEX_CMD_1_OLDDRM] = cmdpkt(R200_EMIT_PP_TXOFFSET_2);
451 rmesa->hw.tex[3].cmd[TEX_CMD_0] = cmdpkt(R200_EMIT_PP_TXFILTER_3);
452 rmesa->hw.tex[3].cmd[TEX_CMD_1_OLDDRM] = cmdpkt(R200_EMIT_PP_TXOFFSET_3);
453 rmesa->hw.tex[4].cmd[TEX_CMD_0] = cmdpkt(R200_EMIT_PP_TXFILTER_4);
454 rmesa->hw.tex[4].cmd[TEX_CMD_1_OLDDRM] = cmdpkt(R200_EMIT_PP_TXOFFSET_4);
455 rmesa->hw.tex[5].cmd[TEX_CMD_0] = cmdpkt(R200_EMIT_PP_TXFILTER_5);
456 rmesa->hw.tex[5].cmd[TEX_CMD_1_OLDDRM] = cmdpkt(R200_EMIT_PP_TXOFFSET_5);
457 }
458 rmesa->hw.afs[0].cmd[AFS_CMD_0] = cmdpkt(R200_EMIT_PP_AFS_0);
459 rmesa->hw.afs[1].cmd[AFS_CMD_0] = cmdpkt(R200_EMIT_PP_AFS_1);
460 rmesa->hw.pvs.cmd[PVS_CMD_0] = cmdpkt(R200_EMIT_VAP_PVS_CNTL);
461 rmesa->hw.cube[0].cmd[CUBE_CMD_0] = cmdpkt(R200_EMIT_PP_CUBIC_FACES_0);
462 rmesa->hw.cube[0].cmd[CUBE_CMD_1] = cmdpkt(R200_EMIT_PP_CUBIC_OFFSETS_0);
463 rmesa->hw.cube[1].cmd[CUBE_CMD_0] = cmdpkt(R200_EMIT_PP_CUBIC_FACES_1);
464 rmesa->hw.cube[1].cmd[CUBE_CMD_1] = cmdpkt(R200_EMIT_PP_CUBIC_OFFSETS_1);
465 rmesa->hw.cube[2].cmd[CUBE_CMD_0] = cmdpkt(R200_EMIT_PP_CUBIC_FACES_2);
466 rmesa->hw.cube[2].cmd[CUBE_CMD_1] = cmdpkt(R200_EMIT_PP_CUBIC_OFFSETS_2);
467 rmesa->hw.cube[3].cmd[CUBE_CMD_0] = cmdpkt(R200_EMIT_PP_CUBIC_FACES_3);
468 rmesa->hw.cube[3].cmd[CUBE_CMD_1] = cmdpkt(R200_EMIT_PP_CUBIC_OFFSETS_3);
469 rmesa->hw.cube[4].cmd[CUBE_CMD_0] = cmdpkt(R200_EMIT_PP_CUBIC_FACES_4);
470 rmesa->hw.cube[4].cmd[CUBE_CMD_1] = cmdpkt(R200_EMIT_PP_CUBIC_OFFSETS_4);
471 rmesa->hw.cube[5].cmd[CUBE_CMD_0] = cmdpkt(R200_EMIT_PP_CUBIC_FACES_5);
472 rmesa->hw.cube[5].cmd[CUBE_CMD_1] = cmdpkt(R200_EMIT_PP_CUBIC_OFFSETS_5);
473 rmesa->hw.pix[0].cmd[PIX_CMD_0] = cmdpkt(R200_EMIT_PP_TXCBLEND_0);
474 rmesa->hw.pix[1].cmd[PIX_CMD_0] = cmdpkt(R200_EMIT_PP_TXCBLEND_1);
475 rmesa->hw.pix[2].cmd[PIX_CMD_0] = cmdpkt(R200_EMIT_PP_TXCBLEND_2);
476 rmesa->hw.pix[3].cmd[PIX_CMD_0] = cmdpkt(R200_EMIT_PP_TXCBLEND_3);
477 rmesa->hw.pix[4].cmd[PIX_CMD_0] = cmdpkt(R200_EMIT_PP_TXCBLEND_4);
478 rmesa->hw.pix[5].cmd[PIX_CMD_0] = cmdpkt(R200_EMIT_PP_TXCBLEND_5);
479 rmesa->hw.zbs.cmd[ZBS_CMD_0] = cmdpkt(RADEON_EMIT_SE_ZBIAS_FACTOR);
480 rmesa->hw.tcl.cmd[TCL_CMD_0] = cmdpkt(R200_EMIT_TCL_LIGHT_MODEL_CTL_0);
481 rmesa->hw.tcl.cmd[TCL_CMD_1] = cmdpkt(R200_EMIT_TCL_UCP_VERT_BLEND_CTL);
482 rmesa->hw.tcg.cmd[TCG_CMD_0] = cmdpkt(R200_EMIT_TEX_PROC_CTL_2);
483 rmesa->hw.msl.cmd[MSL_CMD_0] = cmdpkt(R200_EMIT_MATRIX_SELECT_0);
484 rmesa->hw.vap.cmd[VAP_CMD_0] = cmdpkt(R200_EMIT_VAP_CTL);
485 rmesa->hw.vtx.cmd[VTX_CMD_0] = cmdpkt(R200_EMIT_VTX_FMT_0);
486 rmesa->hw.vtx.cmd[VTX_CMD_1] = cmdpkt(R200_EMIT_OUTPUT_VTX_COMP_SEL);
487 rmesa->hw.vtx.cmd[VTX_CMD_2] = cmdpkt(R200_EMIT_SE_VTX_STATE_CNTL);
488 rmesa->hw.vte.cmd[VTE_CMD_0] = cmdpkt(R200_EMIT_VTE_CNTL);
489 rmesa->hw.prf.cmd[PRF_CMD_0] = cmdpkt(R200_EMIT_PP_TRI_PERF_CNTL);
490 rmesa->hw.spr.cmd[SPR_CMD_0] = cmdpkt(R200_EMIT_TCL_POINT_SPRITE_CNTL);
491 rmesa->hw.mtl[0].cmd[MTL_CMD_0] =
492 cmdvec( R200_VS_MAT_0_EMISS, 1, 16 );
493 rmesa->hw.mtl[0].cmd[MTL_CMD_1] =
494 cmdscl2( R200_SS_MAT_0_SHININESS, 1, 1 );
495 rmesa->hw.mtl[1].cmd[MTL_CMD_0] =
496 cmdvec( R200_VS_MAT_1_EMISS, 1, 16 );
497 rmesa->hw.mtl[1].cmd[MTL_CMD_1] =
498 cmdscl2( R200_SS_MAT_1_SHININESS, 1, 1 );
499
500 rmesa->hw.vpi[0].cmd[VPI_CMD_0] =
501 cmdveclinear( R200_PVS_PROG0, 64 );
502 rmesa->hw.vpi[1].cmd[VPI_CMD_0] =
503 cmdveclinear( R200_PVS_PROG1, 64 );
504 rmesa->hw.vpp[0].cmd[VPP_CMD_0] =
505 cmdveclinear( R200_PVS_PARAM0, 96 );
506 rmesa->hw.vpp[1].cmd[VPP_CMD_0] =
507 cmdveclinear( R200_PVS_PARAM1, 96 );
508
509 rmesa->hw.grd.cmd[GRD_CMD_0] =
510 cmdscl( R200_SS_VERT_GUARD_CLIP_ADJ_ADDR, 1, 4 );
511 rmesa->hw.fog.cmd[FOG_CMD_0] =
512 cmdvec( R200_VS_FOG_PARAM_ADDR, 1, 4 );
513 rmesa->hw.glt.cmd[GLT_CMD_0] =
514 cmdvec( R200_VS_GLOBAL_AMBIENT_ADDR, 1, 4 );
515 rmesa->hw.eye.cmd[EYE_CMD_0] =
516 cmdvec( R200_VS_EYE_VECTOR_ADDR, 1, 4 );
517
518 rmesa->hw.mat[R200_MTX_MV].cmd[MAT_CMD_0] =
519 cmdvec( R200_VS_MATRIX_0_MV, 1, 16);
520 rmesa->hw.mat[R200_MTX_IMV].cmd[MAT_CMD_0] =
521 cmdvec( R200_VS_MATRIX_1_INV_MV, 1, 16);
522 rmesa->hw.mat[R200_MTX_MVP].cmd[MAT_CMD_0] =
523 cmdvec( R200_VS_MATRIX_2_MVP, 1, 16);
524 rmesa->hw.mat[R200_MTX_TEX0].cmd[MAT_CMD_0] =
525 cmdvec( R200_VS_MATRIX_3_TEX0, 1, 16);
526 rmesa->hw.mat[R200_MTX_TEX1].cmd[MAT_CMD_0] =
527 cmdvec( R200_VS_MATRIX_4_TEX1, 1, 16);
528 rmesa->hw.mat[R200_MTX_TEX2].cmd[MAT_CMD_0] =
529 cmdvec( R200_VS_MATRIX_5_TEX2, 1, 16);
530 rmesa->hw.mat[R200_MTX_TEX3].cmd[MAT_CMD_0] =
531 cmdvec( R200_VS_MATRIX_6_TEX3, 1, 16);
532 rmesa->hw.mat[R200_MTX_TEX4].cmd[MAT_CMD_0] =
533 cmdvec( R200_VS_MATRIX_7_TEX4, 1, 16);
534 rmesa->hw.mat[R200_MTX_TEX5].cmd[MAT_CMD_0] =
535 cmdvec( R200_VS_MATRIX_8_TEX5, 1, 16);
536
537 for (i = 0 ; i < 8; i++) {
538 rmesa->hw.lit[i].cmd[LIT_CMD_0] =
539 cmdvec( R200_VS_LIGHT_AMBIENT_ADDR + i, 8, 24 );
540 rmesa->hw.lit[i].cmd[LIT_CMD_1] =
541 cmdscl( R200_SS_LIGHT_DCD_ADDR + i, 8, 7 );
542 }
543
544 for (i = 0 ; i < 6; i++) {
545 rmesa->hw.ucp[i].cmd[UCP_CMD_0] =
546 cmdvec( R200_VS_UCP_ADDR + i, 1, 4 );
547 }
548
549 /* Initial Harware state:
550 */
551 rmesa->hw.ctx.cmd[CTX_PP_MISC] = (R200_ALPHA_TEST_PASS
552 /* | R200_RIGHT_HAND_CUBE_OGL*/);
553
554 rmesa->hw.ctx.cmd[CTX_PP_FOG_COLOR] = (R200_FOG_VERTEX |
555 R200_FOG_USE_SPEC_ALPHA);
556
557 rmesa->hw.ctx.cmd[CTX_RE_SOLID_COLOR] = 0x00000000;
558
559 rmesa->hw.ctx.cmd[CTX_RB3D_BLENDCNTL] = (R200_COMB_FCN_ADD_CLAMP |
560 (R200_BLEND_GL_ONE << R200_SRC_BLEND_SHIFT) |
561 (R200_BLEND_GL_ZERO << R200_DST_BLEND_SHIFT));
562
563 if (rmesa->r200Screen->drmSupportsBlendColor) {
564 rmesa->hw.ctx.cmd[CTX_RB3D_BLENDCOLOR] = 0x00000000;
565 rmesa->hw.ctx.cmd[CTX_RB3D_ABLENDCNTL] = (R200_COMB_FCN_ADD_CLAMP |
566 (R200_BLEND_GL_ONE << R200_SRC_BLEND_SHIFT) |
567 (R200_BLEND_GL_ZERO << R200_DST_BLEND_SHIFT));
568 rmesa->hw.ctx.cmd[CTX_RB3D_CBLENDCNTL] = (R200_COMB_FCN_ADD_CLAMP |
569 (R200_BLEND_GL_ONE << R200_SRC_BLEND_SHIFT) |
570 (R200_BLEND_GL_ZERO << R200_DST_BLEND_SHIFT));
571 }
572
573 rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHOFFSET] =
574 rmesa->r200Screen->depthOffset + rmesa->r200Screen->fbLocation;
575
576 rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHPITCH] =
577 ((rmesa->r200Screen->depthPitch &
578 R200_DEPTHPITCH_MASK) |
579 R200_DEPTH_ENDIAN_NO_SWAP);
580
581 if (rmesa->using_hyperz)
582 rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHPITCH] |= R200_DEPTH_HYPERZ;
583
584 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] = (depth_fmt |
585 R200_Z_TEST_LESS |
586 R200_STENCIL_TEST_ALWAYS |
587 R200_STENCIL_FAIL_KEEP |
588 R200_STENCIL_ZPASS_KEEP |
589 R200_STENCIL_ZFAIL_KEEP |
590 R200_Z_WRITE_ENABLE);
591
592 if (rmesa->using_hyperz) {
593 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= R200_Z_COMPRESSION_ENABLE |
594 R200_Z_DECOMPRESSION_ENABLE;
595 /* if (rmesa->r200Screen->chip_family == CHIP_FAMILY_R200)
596 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_HIERARCHY_ENABLE;*/
597 }
598
599 rmesa->hw.ctx.cmd[CTX_PP_CNTL] = (R200_ANTI_ALIAS_NONE
600 | R200_TEX_BLEND_0_ENABLE);
601
602 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] = color_fmt;
603 switch ( driQueryOptioni( &rmesa->optionCache, "dither_mode" ) ) {
604 case DRI_CONF_DITHER_XERRORDIFFRESET:
605 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= R200_DITHER_INIT;
606 break;
607 case DRI_CONF_DITHER_ORDERED:
608 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= R200_SCALE_DITHER_ENABLE;
609 break;
610 }
611 if ( driQueryOptioni( &rmesa->optionCache, "round_mode" ) ==
612 DRI_CONF_ROUND_ROUND )
613 rmesa->state.color.roundEnable = R200_ROUND_ENABLE;
614 else
615 rmesa->state.color.roundEnable = 0;
616 if ( driQueryOptioni (&rmesa->optionCache, "color_reduction" ) ==
617 DRI_CONF_COLOR_REDUCTION_DITHER )
618 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= R200_DITHER_ENABLE;
619 else
620 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= rmesa->state.color.roundEnable;
621
622 #if 000
623 rmesa->hw.ctx.cmd[CTX_RB3D_COLOROFFSET] = ((rmesa->state.color.drawOffset +
624 rmesa->r200Screen->fbLocation)
625 & R200_COLOROFFSET_MASK);
626
627 rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] = ((rmesa->state.color.drawPitch &
628 R200_COLORPITCH_MASK) |
629 R200_COLOR_ENDIAN_NO_SWAP);
630 #else
631 rmesa->hw.ctx.cmd[CTX_RB3D_COLOROFFSET] = ((drawOffset +
632 rmesa->r200Screen->fbLocation)
633 & R200_COLOROFFSET_MASK);
634
635 rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] = ((drawPitch &
636 R200_COLORPITCH_MASK) |
637 R200_COLOR_ENDIAN_NO_SWAP);
638 #endif
639 /* (fixed size) sarea is initialized to zero afaics so can omit version check. Phew! */
640 if (rmesa->sarea->tiling_enabled) {
641 rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] |= R200_COLOR_TILE_ENABLE;
642 }
643
644 rmesa->hw.prf.cmd[PRF_PP_TRI_PERF] = R200_TRI_CUTOFF_MASK - R200_TRI_CUTOFF_MASK *
645 driQueryOptionf (&rmesa->optionCache,"texture_blend_quality");
646 rmesa->hw.prf.cmd[PRF_PP_PERF_CNTL] = 0;
647
648 rmesa->hw.set.cmd[SET_SE_CNTL] = (R200_FFACE_CULL_CCW |
649 R200_BFACE_SOLID |
650 R200_FFACE_SOLID |
651 R200_FLAT_SHADE_VTX_LAST |
652 R200_DIFFUSE_SHADE_GOURAUD |
653 R200_ALPHA_SHADE_GOURAUD |
654 R200_SPECULAR_SHADE_GOURAUD |
655 R200_FOG_SHADE_GOURAUD |
656 R200_VTX_PIX_CENTER_OGL |
657 R200_ROUND_MODE_TRUNC |
658 R200_ROUND_PREC_8TH_PIX);
659
660 rmesa->hw.set.cmd[SET_RE_CNTL] = (R200_PERSPECTIVE_ENABLE |
661 R200_SCISSOR_ENABLE);
662
663 rmesa->hw.lin.cmd[LIN_RE_LINE_PATTERN] = ((1 << 16) | 0xffff);
664
665 rmesa->hw.lin.cmd[LIN_RE_LINE_STATE] =
666 ((0 << R200_LINE_CURRENT_PTR_SHIFT) |
667 (1 << R200_LINE_CURRENT_COUNT_SHIFT));
668
669 rmesa->hw.lin.cmd[LIN_SE_LINE_WIDTH] = (1 << 4);
670
671 rmesa->hw.msk.cmd[MSK_RB3D_STENCILREFMASK] =
672 ((0x00 << R200_STENCIL_REF_SHIFT) |
673 (0xff << R200_STENCIL_MASK_SHIFT) |
674 (0xff << R200_STENCIL_WRITEMASK_SHIFT));
675
676 rmesa->hw.msk.cmd[MSK_RB3D_ROPCNTL] = R200_ROP_COPY;
677 rmesa->hw.msk.cmd[MSK_RB3D_PLANEMASK] = 0xffffffff;
678
679 rmesa->hw.tam.cmd[TAM_DEBUG3] = 0;
680
681 rmesa->hw.msc.cmd[MSC_RE_MISC] =
682 ((0 << R200_STIPPLE_X_OFFSET_SHIFT) |
683 (0 << R200_STIPPLE_Y_OFFSET_SHIFT) |
684 R200_STIPPLE_BIG_BIT_ORDER);
685
686
687 rmesa->hw.cst.cmd[CST_PP_CNTL_X] = 0;
688 rmesa->hw.cst.cmd[CST_RB3D_DEPTHXY_OFFSET] = 0;
689 rmesa->hw.cst.cmd[CST_RE_AUX_SCISSOR_CNTL] = 0x0;
690 rmesa->hw.cst.cmd[CST_RE_SCISSOR_TL_0] = 0;
691 rmesa->hw.cst.cmd[CST_RE_SCISSOR_BR_0] = 0;
692 rmesa->hw.cst.cmd[CST_SE_VAP_CNTL_STATUS] =
693 #ifdef MESA_BIG_ENDIAN
694 R200_VC_32BIT_SWAP;
695 #else
696 R200_VC_NO_SWAP;
697 #endif
698
699 if (!(rmesa->r200Screen->chip_flags & RADEON_CHIPSET_TCL)) {
700 /* Bypass TCL */
701 rmesa->hw.cst.cmd[CST_SE_VAP_CNTL_STATUS] |= (1<<8);
702 }
703
704 rmesa->hw.cst.cmd[CST_RE_POINTSIZE] =
705 (((GLuint)(ctx->Const.MaxPointSize * 16.0)) << R200_MAXPOINTSIZE_SHIFT) | 0x10;
706 rmesa->hw.cst.cmd[CST_SE_TCL_INPUT_VTX_0] =
707 (0x0 << R200_VERTEX_POSITION_ADDR__SHIFT);
708 rmesa->hw.cst.cmd[CST_SE_TCL_INPUT_VTX_1] =
709 (0x02 << R200_VTX_COLOR_0_ADDR__SHIFT) |
710 (0x03 << R200_VTX_COLOR_1_ADDR__SHIFT);
711 rmesa->hw.cst.cmd[CST_SE_TCL_INPUT_VTX_2] =
712 (0x06 << R200_VTX_TEX_0_ADDR__SHIFT) |
713 (0x07 << R200_VTX_TEX_1_ADDR__SHIFT) |
714 (0x08 << R200_VTX_TEX_2_ADDR__SHIFT) |
715 (0x09 << R200_VTX_TEX_3_ADDR__SHIFT);
716 rmesa->hw.cst.cmd[CST_SE_TCL_INPUT_VTX_3] =
717 (0x0A << R200_VTX_TEX_4_ADDR__SHIFT) |
718 (0x0B << R200_VTX_TEX_5_ADDR__SHIFT);
719
720
721 rmesa->hw.vpt.cmd[VPT_SE_VPORT_XSCALE] = 0x00000000;
722 rmesa->hw.vpt.cmd[VPT_SE_VPORT_XOFFSET] = 0x00000000;
723 rmesa->hw.vpt.cmd[VPT_SE_VPORT_YSCALE] = 0x00000000;
724 rmesa->hw.vpt.cmd[VPT_SE_VPORT_YOFFSET] = 0x00000000;
725 rmesa->hw.vpt.cmd[VPT_SE_VPORT_ZSCALE] = 0x00000000;
726 rmesa->hw.vpt.cmd[VPT_SE_VPORT_ZOFFSET] = 0x00000000;
727
728 for ( i = 0 ; i < ctx->Const.MaxTextureUnits ; i++ ) {
729 rmesa->hw.tex[i].cmd[TEX_PP_TXFILTER] = R200_BORDER_MODE_OGL;
730 rmesa->hw.tex[i].cmd[TEX_PP_TXFORMAT] =
731 ((i << R200_TXFORMAT_ST_ROUTE_SHIFT) | /* <-- note i */
732 (2 << R200_TXFORMAT_WIDTH_SHIFT) |
733 (2 << R200_TXFORMAT_HEIGHT_SHIFT));
734 rmesa->hw.tex[i].cmd[TEX_PP_BORDER_COLOR] = 0;
735 rmesa->hw.tex[i].cmd[TEX_PP_TXFORMAT_X] =
736 (/* R200_TEXCOORD_PROJ | */
737 0x100000); /* Small default bias */
738 if (rmesa->r200Screen->drmSupportsFragShader) {
739 rmesa->hw.tex[i].cmd[TEX_PP_TXOFFSET_NEWDRM] =
740 rmesa->r200Screen->texOffset[RADEON_LOCAL_TEX_HEAP];
741 rmesa->hw.tex[i].cmd[TEX_PP_CUBIC_FACES] = 0;
742 rmesa->hw.tex[i].cmd[TEX_PP_TXMULTI_CTL] = 0;
743 }
744 else {
745 rmesa->hw.tex[i].cmd[TEX_PP_TXOFFSET_OLDDRM] =
746 rmesa->r200Screen->texOffset[RADEON_LOCAL_TEX_HEAP];
747 }
748
749 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_FACES] = 0;
750 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F1] =
751 rmesa->r200Screen->texOffset[RADEON_LOCAL_TEX_HEAP];
752 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F2] =
753 rmesa->r200Screen->texOffset[RADEON_LOCAL_TEX_HEAP];
754 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F3] =
755 rmesa->r200Screen->texOffset[RADEON_LOCAL_TEX_HEAP];
756 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F4] =
757 rmesa->r200Screen->texOffset[RADEON_LOCAL_TEX_HEAP];
758 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F5] =
759 rmesa->r200Screen->texOffset[RADEON_LOCAL_TEX_HEAP];
760
761 rmesa->hw.pix[i].cmd[PIX_PP_TXCBLEND] =
762 (R200_TXC_ARG_A_ZERO |
763 R200_TXC_ARG_B_ZERO |
764 R200_TXC_ARG_C_DIFFUSE_COLOR |
765 R200_TXC_OP_MADD);
766
767 rmesa->hw.pix[i].cmd[PIX_PP_TXCBLEND2] =
768 ((i << R200_TXC_TFACTOR_SEL_SHIFT) |
769 R200_TXC_SCALE_1X |
770 R200_TXC_CLAMP_0_1 |
771 R200_TXC_OUTPUT_REG_R0);
772
773 rmesa->hw.pix[i].cmd[PIX_PP_TXABLEND] =
774 (R200_TXA_ARG_A_ZERO |
775 R200_TXA_ARG_B_ZERO |
776 R200_TXA_ARG_C_DIFFUSE_ALPHA |
777 R200_TXA_OP_MADD);
778
779 rmesa->hw.pix[i].cmd[PIX_PP_TXABLEND2] =
780 ((i << R200_TXA_TFACTOR_SEL_SHIFT) |
781 R200_TXA_SCALE_1X |
782 R200_TXA_CLAMP_0_1 |
783 R200_TXA_OUTPUT_REG_R0);
784 }
785
786 rmesa->hw.tf.cmd[TF_TFACTOR_0] = 0;
787 rmesa->hw.tf.cmd[TF_TFACTOR_1] = 0;
788 rmesa->hw.tf.cmd[TF_TFACTOR_2] = 0;
789 rmesa->hw.tf.cmd[TF_TFACTOR_3] = 0;
790 rmesa->hw.tf.cmd[TF_TFACTOR_4] = 0;
791 rmesa->hw.tf.cmd[TF_TFACTOR_5] = 0;
792
793 rmesa->hw.vap.cmd[VAP_SE_VAP_CNTL] =
794 (R200_VAP_TCL_ENABLE |
795 (0x9 << R200_VAP_VF_MAX_VTX_NUM__SHIFT));
796
797 rmesa->hw.vte.cmd[VTE_SE_VTE_CNTL] =
798 (R200_VPORT_X_SCALE_ENA |
799 R200_VPORT_Y_SCALE_ENA |
800 R200_VPORT_Z_SCALE_ENA |
801 R200_VPORT_X_OFFSET_ENA |
802 R200_VPORT_Y_OFFSET_ENA |
803 R200_VPORT_Z_OFFSET_ENA |
804 /* FIXME: Turn on for tex rect only */
805 R200_VTX_ST_DENORMALIZED |
806 R200_VTX_W0_FMT);
807
808
809 rmesa->hw.vtx.cmd[VTX_VTXFMT_0] = 0;
810 rmesa->hw.vtx.cmd[VTX_VTXFMT_1] = 0;
811 rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_VTXFMT_0] =
812 ((R200_VTX_Z0 | R200_VTX_W0 |
813 (R200_VTX_FP_RGBA << R200_VTX_COLOR_0_SHIFT)));
814 rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_VTXFMT_1] = 0;
815 rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_COMPSEL] = (R200_OUTPUT_XYZW);
816 rmesa->hw.vtx.cmd[VTX_STATE_CNTL] = R200_VSC_UPDATE_USER_COLOR_0_ENABLE;
817
818
819 /* Matrix selection */
820 rmesa->hw.msl.cmd[MSL_MATRIX_SELECT_0] =
821 (R200_MTX_MV << R200_MODELVIEW_0_SHIFT);
822
823 rmesa->hw.msl.cmd[MSL_MATRIX_SELECT_1] =
824 (R200_MTX_IMV << R200_IT_MODELVIEW_0_SHIFT);
825
826 rmesa->hw.msl.cmd[MSL_MATRIX_SELECT_2] =
827 (R200_MTX_MVP << R200_MODELPROJECT_0_SHIFT);
828
829 rmesa->hw.msl.cmd[MSL_MATRIX_SELECT_3] =
830 ((R200_MTX_TEX0 << R200_TEXMAT_0_SHIFT) |
831 (R200_MTX_TEX1 << R200_TEXMAT_1_SHIFT) |
832 (R200_MTX_TEX2 << R200_TEXMAT_2_SHIFT) |
833 (R200_MTX_TEX3 << R200_TEXMAT_3_SHIFT));
834
835 rmesa->hw.msl.cmd[MSL_MATRIX_SELECT_4] =
836 ((R200_MTX_TEX4 << R200_TEXMAT_4_SHIFT) |
837 (R200_MTX_TEX5 << R200_TEXMAT_5_SHIFT));
838
839
840 /* General TCL state */
841 rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL_0] =
842 (R200_SPECULAR_LIGHTS |
843 R200_DIFFUSE_SPECULAR_COMBINE |
844 R200_LOCAL_LIGHT_VEC_GL |
845 R200_LM0_SOURCE_MATERIAL_0 << R200_FRONT_SHININESS_SOURCE_SHIFT |
846 R200_LM0_SOURCE_MATERIAL_1 << R200_BACK_SHININESS_SOURCE_SHIFT);
847
848 rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL_1] =
849 ((R200_LM1_SOURCE_MATERIAL_0 << R200_FRONT_EMISSIVE_SOURCE_SHIFT) |
850 (R200_LM1_SOURCE_MATERIAL_0 << R200_FRONT_AMBIENT_SOURCE_SHIFT) |
851 (R200_LM1_SOURCE_MATERIAL_0 << R200_FRONT_DIFFUSE_SOURCE_SHIFT) |
852 (R200_LM1_SOURCE_MATERIAL_0 << R200_FRONT_SPECULAR_SOURCE_SHIFT) |
853 (R200_LM1_SOURCE_MATERIAL_1 << R200_BACK_EMISSIVE_SOURCE_SHIFT) |
854 (R200_LM1_SOURCE_MATERIAL_1 << R200_BACK_AMBIENT_SOURCE_SHIFT) |
855 (R200_LM1_SOURCE_MATERIAL_1 << R200_BACK_DIFFUSE_SOURCE_SHIFT) |
856 (R200_LM1_SOURCE_MATERIAL_1 << R200_BACK_SPECULAR_SOURCE_SHIFT));
857
858 rmesa->hw.tcl.cmd[TCL_PER_LIGHT_CTL_0] = 0; /* filled in via callbacks */
859 rmesa->hw.tcl.cmd[TCL_PER_LIGHT_CTL_1] = 0;
860 rmesa->hw.tcl.cmd[TCL_PER_LIGHT_CTL_2] = 0;
861 rmesa->hw.tcl.cmd[TCL_PER_LIGHT_CTL_3] = 0;
862
863 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] =
864 (R200_UCP_IN_CLIP_SPACE |
865 R200_CULL_FRONT_IS_CCW);
866
867 /* Texgen/Texmat state */
868 rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_2] = 0x00ffffff;
869 rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_3] =
870 ((0 << R200_TEXGEN_0_INPUT_TEX_SHIFT) |
871 (1 << R200_TEXGEN_1_INPUT_TEX_SHIFT) |
872 (2 << R200_TEXGEN_2_INPUT_TEX_SHIFT) |
873 (3 << R200_TEXGEN_3_INPUT_TEX_SHIFT) |
874 (4 << R200_TEXGEN_4_INPUT_TEX_SHIFT) |
875 (5 << R200_TEXGEN_5_INPUT_TEX_SHIFT));
876 rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_0] = 0;
877 rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_1] =
878 ((0 << R200_TEXGEN_0_INPUT_SHIFT) |
879 (1 << R200_TEXGEN_1_INPUT_SHIFT) |
880 (2 << R200_TEXGEN_2_INPUT_SHIFT) |
881 (3 << R200_TEXGEN_3_INPUT_SHIFT) |
882 (4 << R200_TEXGEN_4_INPUT_SHIFT) |
883 (5 << R200_TEXGEN_5_INPUT_SHIFT));
884 rmesa->hw.tcg.cmd[TCG_TEX_CYL_WRAP_CTL] = 0;
885
886
887 for (i = 0 ; i < 8; i++) {
888 struct gl_light *l = &ctx->Light.Light[i];
889 GLenum p = GL_LIGHT0 + i;
890 *(float *)&(rmesa->hw.lit[i].cmd[LIT_RANGE_CUTOFF]) = FLT_MAX;
891
892 ctx->Driver.Lightfv( ctx, p, GL_AMBIENT, l->Ambient );
893 ctx->Driver.Lightfv( ctx, p, GL_DIFFUSE, l->Diffuse );
894 ctx->Driver.Lightfv( ctx, p, GL_SPECULAR, l->Specular );
895 ctx->Driver.Lightfv( ctx, p, GL_POSITION, NULL );
896 ctx->Driver.Lightfv( ctx, p, GL_SPOT_DIRECTION, NULL );
897 ctx->Driver.Lightfv( ctx, p, GL_SPOT_EXPONENT, &l->SpotExponent );
898 ctx->Driver.Lightfv( ctx, p, GL_SPOT_CUTOFF, &l->SpotCutoff );
899 ctx->Driver.Lightfv( ctx, p, GL_CONSTANT_ATTENUATION,
900 &l->ConstantAttenuation );
901 ctx->Driver.Lightfv( ctx, p, GL_LINEAR_ATTENUATION,
902 &l->LinearAttenuation );
903 ctx->Driver.Lightfv( ctx, p, GL_QUADRATIC_ATTENUATION,
904 &l->QuadraticAttenuation );
905 *(float *)&(rmesa->hw.lit[i].cmd[LIT_ATTEN_XXX]) = 0.0;
906 }
907
908 ctx->Driver.LightModelfv( ctx, GL_LIGHT_MODEL_AMBIENT,
909 ctx->Light.Model.Ambient );
910
911 TNL_CONTEXT(ctx)->Driver.NotifyMaterialChange( ctx );
912
913 for (i = 0 ; i < 6; i++) {
914 ctx->Driver.ClipPlane( ctx, GL_CLIP_PLANE0 + i, NULL );
915 }
916
917 ctx->Driver.Fogfv( ctx, GL_FOG_MODE, NULL );
918 ctx->Driver.Fogfv( ctx, GL_FOG_DENSITY, &ctx->Fog.Density );
919 ctx->Driver.Fogfv( ctx, GL_FOG_START, &ctx->Fog.Start );
920 ctx->Driver.Fogfv( ctx, GL_FOG_END, &ctx->Fog.End );
921 ctx->Driver.Fogfv( ctx, GL_FOG_COLOR, ctx->Fog.Color );
922 ctx->Driver.Fogfv( ctx, GL_FOG_COORDINATE_SOURCE_EXT, NULL );
923
924 rmesa->hw.grd.cmd[GRD_VERT_GUARD_CLIP_ADJ] = IEEE_ONE;
925 rmesa->hw.grd.cmd[GRD_VERT_GUARD_DISCARD_ADJ] = IEEE_ONE;
926 rmesa->hw.grd.cmd[GRD_HORZ_GUARD_CLIP_ADJ] = IEEE_ONE;
927 rmesa->hw.grd.cmd[GRD_HORZ_GUARD_DISCARD_ADJ] = IEEE_ONE;
928
929 rmesa->hw.eye.cmd[EYE_X] = 0;
930 rmesa->hw.eye.cmd[EYE_Y] = 0;
931 rmesa->hw.eye.cmd[EYE_Z] = IEEE_ONE;
932 rmesa->hw.eye.cmd[EYE_RESCALE_FACTOR] = IEEE_ONE;
933
934 rmesa->hw.spr.cmd[SPR_POINT_SPRITE_CNTL] = R200_POINTSIZE_SEL_STATE;
935
936 r200LightingSpaceChange( ctx );
937
938 rmesa->hw.all_dirty = GL_TRUE;
939 }