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r200: emit elts into a separate ELT bo
[mesa.git] / src / mesa / drivers / dri / r200 / r200_state_init.c
1 /*
2 Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
3
4 The Weather Channel (TM) funded Tungsten Graphics to develop the
5 initial release of the Radeon 8500 driver under the XFree86 license.
6 This notice must be preserved.
7
8 Permission is hereby granted, free of charge, to any person obtaining
9 a copy of this software and associated documentation files (the
10 "Software"), to deal in the Software without restriction, including
11 without limitation the rights to use, copy, modify, merge, publish,
12 distribute, sublicense, and/or sell copies of the Software, and to
13 permit persons to whom the Software is furnished to do so, subject to
14 the following conditions:
15
16 The above copyright notice and this permission notice (including the
17 next paragraph) shall be included in all copies or substantial
18 portions of the Software.
19
20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 */
28
29 /*
30 * Authors:
31 * Keith Whitwell <keith@tungstengraphics.com>
32 */
33
34 #include "main/glheader.h"
35 #include "main/imports.h"
36 #include "main/enums.h"
37 #include "main/colormac.h"
38 #include "main/api_arrayelt.h"
39
40 #include "swrast/swrast.h"
41 #include "vbo/vbo.h"
42 #include "tnl/tnl.h"
43 #include "tnl/t_pipeline.h"
44 #include "swrast_setup/swrast_setup.h"
45
46 #include "radeon_buffer.h"
47 #include "radeon_mipmap_tree.h"
48 #include "radeon_cs.h"
49 #include "common_context.h"
50 #include "common_cmdbuf.h"
51 #include "r200_context.h"
52 #include "r200_ioctl.h"
53 #include "r200_state.h"
54 #include "r200_tcl.h"
55 #include "r200_tex.h"
56 #include "r200_swtcl.h"
57
58 #include "xmlpool.h"
59
60 /* New (1.3) state mechanism. 3 commands (packet, scalar, vector) in
61 * 1.3 cmdbuffers allow all previous state to be updated as well as
62 * the tcl scalar and vector areas.
63 */
64 static struct {
65 int start;
66 int len;
67 const char *name;
68 } packet[RADEON_MAX_STATE_PACKETS] = {
69 {RADEON_PP_MISC, 7, "RADEON_PP_MISC"},
70 {RADEON_PP_CNTL, 3, "RADEON_PP_CNTL"},
71 {RADEON_RB3D_COLORPITCH, 1, "RADEON_RB3D_COLORPITCH"},
72 {RADEON_RE_LINE_PATTERN, 2, "RADEON_RE_LINE_PATTERN"},
73 {RADEON_SE_LINE_WIDTH, 1, "RADEON_SE_LINE_WIDTH"},
74 {RADEON_PP_LUM_MATRIX, 1, "RADEON_PP_LUM_MATRIX"},
75 {RADEON_PP_ROT_MATRIX_0, 2, "RADEON_PP_ROT_MATRIX_0"},
76 {RADEON_RB3D_STENCILREFMASK, 3, "RADEON_RB3D_STENCILREFMASK"},
77 {RADEON_SE_VPORT_XSCALE, 6, "RADEON_SE_VPORT_XSCALE"},
78 {RADEON_SE_CNTL, 2, "RADEON_SE_CNTL"},
79 {RADEON_SE_CNTL_STATUS, 1, "RADEON_SE_CNTL_STATUS"},
80 {RADEON_RE_MISC, 1, "RADEON_RE_MISC"},
81 {RADEON_PP_TXFILTER_0, 6, "RADEON_PP_TXFILTER_0"},
82 {RADEON_PP_BORDER_COLOR_0, 1, "RADEON_PP_BORDER_COLOR_0"},
83 {RADEON_PP_TXFILTER_1, 6, "RADEON_PP_TXFILTER_1"},
84 {RADEON_PP_BORDER_COLOR_1, 1, "RADEON_PP_BORDER_COLOR_1"},
85 {RADEON_PP_TXFILTER_2, 6, "RADEON_PP_TXFILTER_2"},
86 {RADEON_PP_BORDER_COLOR_2, 1, "RADEON_PP_BORDER_COLOR_2"},
87 {RADEON_SE_ZBIAS_FACTOR, 2, "RADEON_SE_ZBIAS_FACTOR"},
88 {RADEON_SE_TCL_OUTPUT_VTX_FMT, 11, "RADEON_SE_TCL_OUTPUT_VTX_FMT"},
89 {RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED, 17,
90 "RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED"},
91 {R200_PP_TXCBLEND_0, 4, "R200_PP_TXCBLEND_0"},
92 {R200_PP_TXCBLEND_1, 4, "R200_PP_TXCBLEND_1"},
93 {R200_PP_TXCBLEND_2, 4, "R200_PP_TXCBLEND_2"},
94 {R200_PP_TXCBLEND_3, 4, "R200_PP_TXCBLEND_3"},
95 {R200_PP_TXCBLEND_4, 4, "R200_PP_TXCBLEND_4"},
96 {R200_PP_TXCBLEND_5, 4, "R200_PP_TXCBLEND_5"},
97 {R200_PP_TXCBLEND_6, 4, "R200_PP_TXCBLEND_6"},
98 {R200_PP_TXCBLEND_7, 4, "R200_PP_TXCBLEND_7"},
99 {R200_SE_TCL_LIGHT_MODEL_CTL_0, 6, "R200_SE_TCL_LIGHT_MODEL_CTL_0"},
100 {R200_PP_TFACTOR_0, 6, "R200_PP_TFACTOR_0"},
101 {R200_SE_VTX_FMT_0, 4, "R200_SE_VTX_FMT_0"},
102 {R200_SE_VAP_CNTL, 1, "R200_SE_VAP_CNTL"},
103 {R200_SE_TCL_MATRIX_SEL_0, 5, "R200_SE_TCL_MATRIX_SEL_0"},
104 {R200_SE_TCL_TEX_PROC_CTL_2, 5, "R200_SE_TCL_TEX_PROC_CTL_2"},
105 {R200_SE_TCL_UCP_VERT_BLEND_CTL, 1, "R200_SE_TCL_UCP_VERT_BLEND_CTL"},
106 {R200_PP_TXFILTER_0, 6, "R200_PP_TXFILTER_0"},
107 {R200_PP_TXFILTER_1, 6, "R200_PP_TXFILTER_1"},
108 {R200_PP_TXFILTER_2, 6, "R200_PP_TXFILTER_2"},
109 {R200_PP_TXFILTER_3, 6, "R200_PP_TXFILTER_3"},
110 {R200_PP_TXFILTER_4, 6, "R200_PP_TXFILTER_4"},
111 {R200_PP_TXFILTER_5, 6, "R200_PP_TXFILTER_5"},
112 {R200_PP_TXOFFSET_0, 1, "R200_PP_TXOFFSET_0"},
113 {R200_PP_TXOFFSET_1, 1, "R200_PP_TXOFFSET_1"},
114 {R200_PP_TXOFFSET_2, 1, "R200_PP_TXOFFSET_2"},
115 {R200_PP_TXOFFSET_3, 1, "R200_PP_TXOFFSET_3"},
116 {R200_PP_TXOFFSET_4, 1, "R200_PP_TXOFFSET_4"},
117 {R200_PP_TXOFFSET_5, 1, "R200_PP_TXOFFSET_5"},
118 {R200_SE_VTE_CNTL, 1, "R200_SE_VTE_CNTL"},
119 {R200_SE_TCL_OUTPUT_VTX_COMP_SEL, 1,
120 "R200_SE_TCL_OUTPUT_VTX_COMP_SEL"},
121 {R200_PP_TAM_DEBUG3, 1, "R200_PP_TAM_DEBUG3"},
122 {R200_PP_CNTL_X, 1, "R200_PP_CNTL_X"},
123 {R200_RB3D_DEPTHXY_OFFSET, 1, "R200_RB3D_DEPTHXY_OFFSET"},
124 {R200_RE_AUX_SCISSOR_CNTL, 1, "R200_RE_AUX_SCISSOR_CNTL"},
125 {R200_RE_SCISSOR_TL_0, 2, "R200_RE_SCISSOR_TL_0"},
126 {R200_RE_SCISSOR_TL_1, 2, "R200_RE_SCISSOR_TL_1"},
127 {R200_RE_SCISSOR_TL_2, 2, "R200_RE_SCISSOR_TL_2"},
128 {R200_SE_VAP_CNTL_STATUS, 1, "R200_SE_VAP_CNTL_STATUS"},
129 {R200_SE_VTX_STATE_CNTL, 1, "R200_SE_VTX_STATE_CNTL"},
130 {R200_RE_POINTSIZE, 1, "R200_RE_POINTSIZE"},
131 {R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0, 4,
132 "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0"},
133 {R200_PP_CUBIC_FACES_0, 1, "R200_PP_CUBIC_FACES_0"}, /* 61 */
134 {R200_PP_CUBIC_OFFSET_F1_0, 5, "R200_PP_CUBIC_OFFSET_F1_0"}, /* 62 */
135 {R200_PP_CUBIC_FACES_1, 1, "R200_PP_CUBIC_FACES_1"},
136 {R200_PP_CUBIC_OFFSET_F1_1, 5, "R200_PP_CUBIC_OFFSET_F1_1"},
137 {R200_PP_CUBIC_FACES_2, 1, "R200_PP_CUBIC_FACES_2"},
138 {R200_PP_CUBIC_OFFSET_F1_2, 5, "R200_PP_CUBIC_OFFSET_F1_2"},
139 {R200_PP_CUBIC_FACES_3, 1, "R200_PP_CUBIC_FACES_3"},
140 {R200_PP_CUBIC_OFFSET_F1_3, 5, "R200_PP_CUBIC_OFFSET_F1_3"},
141 {R200_PP_CUBIC_FACES_4, 1, "R200_PP_CUBIC_FACES_4"},
142 {R200_PP_CUBIC_OFFSET_F1_4, 5, "R200_PP_CUBIC_OFFSET_F1_4"},
143 {R200_PP_CUBIC_FACES_5, 1, "R200_PP_CUBIC_FACES_5"},
144 {R200_PP_CUBIC_OFFSET_F1_5, 5, "R200_PP_CUBIC_OFFSET_F1_5"},
145 {RADEON_PP_TEX_SIZE_0, 2, "RADEON_PP_TEX_SIZE_0"},
146 {RADEON_PP_TEX_SIZE_1, 2, "RADEON_PP_TEX_SIZE_1"},
147 {RADEON_PP_TEX_SIZE_2, 2, "RADEON_PP_TEX_SIZE_2"},
148 {R200_RB3D_BLENDCOLOR, 3, "R200_RB3D_BLENDCOLOR"},
149 {R200_SE_TCL_POINT_SPRITE_CNTL, 1, "R200_SE_TCL_POINT_SPRITE_CNTL"},
150 {RADEON_PP_CUBIC_FACES_0, 1, "RADEON_PP_CUBIC_FACES_0"},
151 {RADEON_PP_CUBIC_OFFSET_T0_0, 5, "RADEON_PP_CUBIC_OFFSET_T0_0"},
152 {RADEON_PP_CUBIC_FACES_1, 1, "RADEON_PP_CUBIC_FACES_1"},
153 {RADEON_PP_CUBIC_OFFSET_T1_0, 5, "RADEON_PP_CUBIC_OFFSET_T1_0"},
154 {RADEON_PP_CUBIC_FACES_2, 1, "RADEON_PP_CUBIC_FACES_2"},
155 {RADEON_PP_CUBIC_OFFSET_T2_0, 5, "RADEON_PP_CUBIC_OFFSET_T2_0"},
156 {R200_PP_TRI_PERF, 2, "R200_PP_TRI_PERF"},
157 {R200_PP_TXCBLEND_8, 32, "R200_PP_AFS_0"}, /* 85 */
158 {R200_PP_TXCBLEND_0, 32, "R200_PP_AFS_1"},
159 {R200_PP_TFACTOR_0, 8, "R200_ATF_TFACTOR"},
160 {R200_PP_TXFILTER_0, 8, "R200_PP_TXCTLALL_0"},
161 {R200_PP_TXFILTER_1, 8, "R200_PP_TXCTLALL_1"},
162 {R200_PP_TXFILTER_2, 8, "R200_PP_TXCTLALL_2"},
163 {R200_PP_TXFILTER_3, 8, "R200_PP_TXCTLALL_3"},
164 {R200_PP_TXFILTER_4, 8, "R200_PP_TXCTLALL_4"},
165 {R200_PP_TXFILTER_5, 8, "R200_PP_TXCTLALL_5"},
166 {R200_VAP_PVS_CNTL_1, 2, "R200_VAP_PVS_CNTL"},
167 };
168
169 /* =============================================================
170 * State initialization
171 */
172
173 void r200PrintDirty( r200ContextPtr rmesa, const char *msg )
174 {
175 struct radeon_state_atom *l;
176
177 fprintf(stderr, msg);
178 fprintf(stderr, ": ");
179
180 foreach(l, &rmesa->hw.atomlist) {
181 if (l->dirty || rmesa->hw.all_dirty)
182 fprintf(stderr, "%s, ", l->name);
183 }
184
185 fprintf(stderr, "\n");
186 }
187
188 static int cmdpkt( int id )
189 {
190 drm_radeon_cmd_header_t h;
191 h.i = 0;
192 h.packet.cmd_type = RADEON_CMD_PACKET;
193 h.packet.packet_id = id;
194 return h.i;
195 }
196
197 static int cmdvec( int offset, int stride, int count )
198 {
199 drm_radeon_cmd_header_t h;
200 h.i = 0;
201 h.vectors.cmd_type = RADEON_CMD_VECTORS;
202 h.vectors.offset = offset;
203 h.vectors.stride = stride;
204 h.vectors.count = count;
205 return h.i;
206 }
207
208 /* warning: the count here is divided by 4 compared to other cmds
209 (so it doesn't exceed the char size)! */
210 static int cmdveclinear( int offset, int count )
211 {
212 drm_radeon_cmd_header_t h;
213 h.i = 0;
214 h.veclinear.cmd_type = RADEON_CMD_VECLINEAR;
215 h.veclinear.addr_lo = offset & 0xff;
216 h.veclinear.addr_hi = (offset & 0xff00) >> 8;
217 h.veclinear.count = count;
218 return h.i;
219 }
220
221 static int cmdscl( int offset, int stride, int count )
222 {
223 drm_radeon_cmd_header_t h;
224 h.i = 0;
225 h.scalars.cmd_type = RADEON_CMD_SCALARS;
226 h.scalars.offset = offset;
227 h.scalars.stride = stride;
228 h.scalars.count = count;
229 return h.i;
230 }
231
232 static int cmdscl2( int offset, int stride, int count )
233 {
234 drm_radeon_cmd_header_t h;
235 h.i = 0;
236 h.scalars.cmd_type = RADEON_CMD_SCALARS2;
237 h.scalars.offset = offset - 0x100;
238 h.scalars.stride = stride;
239 h.scalars.count = count;
240 return h.i;
241 }
242
243 #define CHECK( NM, FLAG ) \
244 static int check_##NM( GLcontext *ctx, struct radeon_state_atom *atom) \
245 { \
246 r200ContextPtr rmesa = R200_CONTEXT(ctx); \
247 (void) rmesa; \
248 return (FLAG) ? atom->cmd_size : 0; \
249 }
250
251 #define TCL_CHECK( NM, FLAG ) \
252 static int check_##NM( GLcontext *ctx, struct radeon_state_atom *atom) \
253 { \
254 r200ContextPtr rmesa = R200_CONTEXT(ctx); \
255 return (!rmesa->radeon.TclFallback && !ctx->VertexProgram._Enabled && (FLAG)) ? atom->cmd_size : 0; \
256 }
257
258 #define TCL_OR_VP_CHECK( NM, FLAG ) \
259 static int check_##NM( GLcontext *ctx, struct radeon_state_atom *atom ) \
260 { \
261 r200ContextPtr rmesa = R200_CONTEXT(ctx); \
262 return (!rmesa->radeon.TclFallback && (FLAG)) ? atom->cmd_size : 0; \
263 }
264
265 #define VP_CHECK( NM, FLAG ) \
266 static int check_##NM( GLcontext *ctx, struct radeon_state_atom *atom ) \
267 { \
268 r200ContextPtr rmesa = R200_CONTEXT(ctx); \
269 (void) atom; \
270 return (!rmesa->radeon.TclFallback && ctx->VertexProgram._Enabled && (FLAG)) ? atom->cmd_size : 0; \
271 }
272
273 CHECK( always, GL_TRUE )
274 CHECK( never, GL_FALSE )
275 CHECK( tex_any, ctx->Texture._EnabledUnits )
276 CHECK( tf, (ctx->Texture._EnabledUnits && !ctx->ATIFragmentShader._Enabled) );
277 CHECK( tex_pair, (rmesa->state.texture.unit[atom->idx].unitneeded | rmesa->state.texture.unit[atom->idx & ~1].unitneeded) )
278 CHECK( tex, rmesa->state.texture.unit[atom->idx].unitneeded )
279 CHECK( pix_zero, !ctx->ATIFragmentShader._Enabled )
280 CHECK( texenv, (rmesa->state.envneeded & (1 << (atom->idx)) && !ctx->ATIFragmentShader._Enabled) )
281 CHECK( afs_pass1, (ctx->ATIFragmentShader._Enabled && (ctx->ATIFragmentShader.Current->NumPasses > 1)) )
282 CHECK( afs, ctx->ATIFragmentShader._Enabled )
283 CHECK( tex_cube, rmesa->state.texture.unit[atom->idx].unitneeded & TEXTURE_CUBE_BIT )
284 TCL_CHECK( tcl_fog, ctx->Fog.Enabled )
285 TCL_CHECK( tcl, GL_TRUE )
286 TCL_CHECK( tcl_tex, rmesa->state.texture.unit[atom->idx].unitneeded )
287 TCL_CHECK( tcl_lighting, ctx->Light.Enabled )
288 TCL_CHECK( tcl_light, ctx->Light.Enabled && ctx->Light.Light[atom->idx].Enabled )
289 TCL_OR_VP_CHECK( tcl_ucp, (ctx->Transform.ClipPlanesEnabled & (1 << (atom->idx))) )
290 TCL_OR_VP_CHECK( tcl_or_vp, GL_TRUE )
291 VP_CHECK( tcl_vp, GL_TRUE )
292 VP_CHECK( tcl_vp_size, ctx->VertexProgram.Current->Base.NumNativeInstructions > 64 )
293 VP_CHECK( tcl_vpp_size, ctx->VertexProgram.Current->Base.NumNativeParameters > 96 )
294
295
296 static void ctx_emit(GLcontext *ctx, struct radeon_state_atom *atom)
297 {
298 r200ContextPtr r200 = R200_CONTEXT(ctx);
299 BATCH_LOCALS(&r200->radeon);
300 struct radeon_renderbuffer *rrb;
301 uint32_t cbpitch;
302 uint32_t zbpitch;
303 uint32_t dwords = atom->cmd_size;
304 GLframebuffer *fb = r200->radeon.dri.drawable->driverPrivate;
305
306 /* output the first 7 bytes of context */
307 BEGIN_BATCH_NO_AUTOSTATE(dwords);
308 OUT_BATCH_TABLE(atom->cmd, 5);
309
310 rrb = r200->radeon.state.depth.rrb;
311 if (!rrb) {
312 OUT_BATCH(atom->cmd[CTX_RB3D_DEPTHOFFSET]);
313 OUT_BATCH(atom->cmd[CTX_RB3D_DEPTHPITCH]);
314 } else {
315 zbpitch = (rrb->pitch / rrb->cpp);
316 OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
317 OUT_BATCH(zbpitch);
318 }
319
320 OUT_BATCH(atom->cmd[CTX_RB3D_ZSTENCILCNTL]);
321 OUT_BATCH(atom->cmd[CTX_CMD_1]);
322 OUT_BATCH(atom->cmd[CTX_PP_CNTL]);
323 OUT_BATCH(atom->cmd[CTX_RB3D_CNTL]);
324
325 rrb = r200->radeon.state.color.rrb;
326 if (r200->radeon.radeonScreen->driScreen->dri2.enabled) {
327 rrb = (struct radeon_renderbuffer *)fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer;
328 }
329 if (!rrb || !rrb->bo) {
330 OUT_BATCH(atom->cmd[CTX_RB3D_COLOROFFSET]);
331 } else {
332 OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
333 }
334
335 OUT_BATCH(atom->cmd[CTX_CMD_2]);
336
337 if (!rrb || !rrb->bo) {
338 OUT_BATCH(atom->cmd[CTX_RB3D_COLORPITCH]);
339 } else {
340 cbpitch = (rrb->pitch / rrb->cpp);
341 if (rrb->cpp == 4)
342 ;
343 else
344 ;
345 if (r200->radeon.sarea->tiling_enabled)
346 cbpitch |= R200_COLOR_TILE_ENABLE;
347 OUT_BATCH(cbpitch);
348 }
349
350 if (atom->cmd_size == CTX_STATE_SIZE_NEWDRM)
351 OUT_BATCH_TABLE((atom->cmd + 14), 4);
352
353 END_BATCH();
354
355 }
356
357 static void tex_emit(GLcontext *ctx, struct radeon_state_atom *atom)
358 {
359 r200ContextPtr r200 = R200_CONTEXT(ctx);
360 BATCH_LOCALS(&r200->radeon);
361 uint32_t dwords = atom->cmd_size;
362 int i = atom->idx;
363 radeonTexObj *t = r200->state.texture.unit[i].texobj;
364
365 BEGIN_BATCH_NO_AUTOSTATE(dwords);
366 fprintf(stderr,"atom state is %x, %x %x %x %x %x\n", atom->cmd[0],
367 atom->cmd[1],
368 atom->cmd[2],
369 atom->cmd[3],
370 atom->cmd[4],
371 atom->cmd[5]);
372 OUT_BATCH_TABLE(atom->cmd, 10);
373 if (t && !t->image_override) {
374 fprintf(stderr,"emitting reloc for %d\n", i);
375 OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, 0,
376 RADEON_GEM_DOMAIN_VRAM, 0, 0);
377 } else if (!t) {
378
379 OUT_BATCH(atom->cmd[10]);
380 }
381
382 END_BATCH();
383 }
384
385 static void cube_emit(GLcontext *ctx, struct radeon_state_atom *atom)
386 {
387 r200ContextPtr r200 = R200_CONTEXT(ctx);
388 BATCH_LOCALS(&r200->radeon);
389 uint32_t dwords = atom->cmd_size;
390 int i = atom->idx;
391 radeonTexObj *t = r200->state.texture.unit[i].texobj;
392 GLuint size;
393
394 BEGIN_BATCH_NO_AUTOSTATE(dwords);
395 OUT_BATCH_TABLE(atom->cmd, 3);
396
397 fprintf(stderr,"total size is %d\n", t->mt->totalsize);
398 if (t && !t->image_override) {
399 size = t->mt->totalsize / 6;
400 OUT_BATCH_RELOC(0, t->mt->bo, size, RADEON_GEM_DOMAIN_VRAM, 0, 0);
401 OUT_BATCH_RELOC(0, t->mt->bo, size * 2, RADEON_GEM_DOMAIN_VRAM, 0, 0);
402 OUT_BATCH_RELOC(0, t->mt->bo, size * 3, RADEON_GEM_DOMAIN_VRAM, 0, 0);
403 OUT_BATCH_RELOC(0, t->mt->bo, size * 4, RADEON_GEM_DOMAIN_VRAM, 0, 0);
404 OUT_BATCH_RELOC(0, t->mt->bo, size * 5, RADEON_GEM_DOMAIN_VRAM, 0, 0);
405 }
406 END_BATCH();
407 }
408
409 /* Initialize the context's hardware state.
410 */
411 void r200InitState( r200ContextPtr rmesa )
412 {
413 GLcontext *ctx = rmesa->radeon.glCtx;
414 GLuint color_fmt, depth_fmt, i;
415 GLint drawPitch, drawOffset;
416
417 switch ( rmesa->radeon.radeonScreen->cpp ) {
418 case 2:
419 color_fmt = R200_COLOR_FORMAT_RGB565;
420 break;
421 case 4:
422 color_fmt = R200_COLOR_FORMAT_ARGB8888;
423 break;
424 default:
425 fprintf( stderr, "Error: Unsupported pixel depth... exiting\n" );
426 exit( -1 );
427 }
428
429 rmesa->radeon.state.color.clear = 0x00000000;
430
431 switch ( ctx->Visual.depthBits ) {
432 case 16:
433 rmesa->radeon.state.depth.clear = 0x0000ffff;
434 rmesa->radeon.state.depth.scale = 1.0 / (GLfloat)0xffff;
435 depth_fmt = R200_DEPTH_FORMAT_16BIT_INT_Z;
436 rmesa->radeon.state.stencil.clear = 0x00000000;
437 break;
438 case 24:
439 rmesa->radeon.state.depth.clear = 0x00ffffff;
440 rmesa->radeon.state.depth.scale = 1.0 / (GLfloat)0xffffff;
441 depth_fmt = R200_DEPTH_FORMAT_24BIT_INT_Z;
442 rmesa->radeon.state.stencil.clear = 0xffff0000;
443 break;
444 default:
445 fprintf( stderr, "Error: Unsupported depth %d... exiting\n",
446 ctx->Visual.depthBits );
447 exit( -1 );
448 }
449
450 /* Only have hw stencil when depth buffer is 24 bits deep */
451 rmesa->radeon.state.stencil.hwBuffer = ( ctx->Visual.stencilBits > 0 &&
452 ctx->Visual.depthBits == 24 );
453
454 rmesa->radeon.Fallback = 0;
455
456 if ( ctx->Visual.doubleBufferMode && rmesa->radeon.sarea->pfCurrentPage == 0 ) {
457 drawOffset = rmesa->radeon.radeonScreen->backOffset;
458 drawPitch = rmesa->radeon.radeonScreen->backPitch;
459 } else {
460 drawOffset = rmesa->radeon.radeonScreen->frontOffset;
461 drawPitch = rmesa->radeon.radeonScreen->frontPitch;
462 }
463 #if 000
464 if ( ctx->Visual.doubleBufferMode && rmesa->sarea->pfCurrentPage == 0 ) {
465 rmesa->radeon.state.color.drawOffset = rmesa->radeon.radeonScreen->backOffset;
466 rmesa->radeon.state.color.drawPitch = rmesa->radeon.radeonScreen->backPitch;
467 } else {
468 rmesa->radeon.state.color.drawOffset = rmesa->radeon.radeonScreen->frontOffset;
469 rmesa->radeon.state.color.drawPitch = rmesa->radeon.radeonScreen->frontPitch;
470 }
471
472 rmesa->state.pixel.readOffset = rmesa->radeon.state.color.drawOffset;
473 rmesa->state.pixel.readPitch = rmesa->radeon.state.color.drawPitch;
474 #endif
475
476 rmesa->hw.max_state_size = 0;
477
478 #define ALLOC_STATE( ATOM, CHK, SZ, NM, IDX ) \
479 do { \
480 rmesa->hw.ATOM.cmd_size = SZ; \
481 rmesa->hw.ATOM.cmd = (GLuint *)CALLOC(SZ * sizeof(int)); \
482 rmesa->hw.ATOM.lastcmd = (GLuint *)CALLOC(SZ * sizeof(int)); \
483 rmesa->hw.ATOM.name = NM; \
484 rmesa->hw.ATOM.idx = IDX; \
485 rmesa->hw.ATOM.check = check_##CHK; \
486 rmesa->hw.ATOM.dirty = GL_FALSE; \
487 rmesa->hw.max_state_size += SZ * sizeof(int); \
488 } while (0)
489
490
491 /* Allocate state buffers:
492 */
493 if (rmesa->radeon.radeonScreen->drmSupportsBlendColor)
494 ALLOC_STATE( ctx, always, CTX_STATE_SIZE_NEWDRM, "CTX/context", 0 );
495 else
496 ALLOC_STATE( ctx, always, CTX_STATE_SIZE_OLDDRM, "CTX/context", 0 );
497
498 rmesa->hw.ctx.emit = ctx_emit;
499 ALLOC_STATE( set, always, SET_STATE_SIZE, "SET/setup", 0 );
500 ALLOC_STATE( lin, always, LIN_STATE_SIZE, "LIN/line", 0 );
501 ALLOC_STATE( msk, always, MSK_STATE_SIZE, "MSK/mask", 0 );
502 ALLOC_STATE( vpt, always, VPT_STATE_SIZE, "VPT/viewport", 0 );
503 ALLOC_STATE( vtx, always, VTX_STATE_SIZE, "VTX/vertex", 0 );
504 ALLOC_STATE( vap, always, VAP_STATE_SIZE, "VAP/vap", 0 );
505 ALLOC_STATE( vte, always, VTE_STATE_SIZE, "VTE/vte", 0 );
506 ALLOC_STATE( msc, always, MSC_STATE_SIZE, "MSC/misc", 0 );
507 ALLOC_STATE( cst, always, CST_STATE_SIZE, "CST/constant", 0 );
508 ALLOC_STATE( zbs, always, ZBS_STATE_SIZE, "ZBS/zbias", 0 );
509 ALLOC_STATE( tf, tf, TF_STATE_SIZE, "TF/tfactor", 0 );
510 if (rmesa->radeon.radeonScreen->drmSupportsFragShader) {
511 if (rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_R200) {
512 /* make sure texture units 0/1 are emitted pair-wise for r200 t0 hang workaround */
513 ALLOC_STATE( tex[0], tex_pair, TEX_STATE_SIZE_NEWDRM, "TEX/tex-0", 0 );
514 ALLOC_STATE( tex[1], tex_pair, TEX_STATE_SIZE_NEWDRM, "TEX/tex-1", 1 );
515 ALLOC_STATE( tam, tex_any, TAM_STATE_SIZE, "TAM/tam", 0 );
516 }
517 else {
518 ALLOC_STATE( tex[0], tex, TEX_STATE_SIZE_NEWDRM, "TEX/tex-0", 0 );
519 ALLOC_STATE( tex[1], tex, TEX_STATE_SIZE_NEWDRM, "TEX/tex-1", 1 );
520 ALLOC_STATE( tam, never, TAM_STATE_SIZE, "TAM/tam", 0 );
521 }
522 ALLOC_STATE( tex[2], tex, TEX_STATE_SIZE_NEWDRM, "TEX/tex-2", 2 );
523 ALLOC_STATE( tex[3], tex, TEX_STATE_SIZE_NEWDRM, "TEX/tex-3", 3 );
524 ALLOC_STATE( tex[4], tex, TEX_STATE_SIZE_NEWDRM, "TEX/tex-4", 4 );
525 ALLOC_STATE( tex[5], tex, TEX_STATE_SIZE_NEWDRM, "TEX/tex-5", 5 );
526 ALLOC_STATE( atf, afs, ATF_STATE_SIZE, "ATF/tfactor", 0 );
527 ALLOC_STATE( afs[0], afs_pass1, AFS_STATE_SIZE, "AFS/afsinst-0", 0 );
528 ALLOC_STATE( afs[1], afs, AFS_STATE_SIZE, "AFS/afsinst-1", 1 );
529 }
530 else {
531 if (rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_R200) {
532 ALLOC_STATE( tex[0], tex_pair, TEX_STATE_SIZE_OLDDRM, "TEX/tex-0", 0 );
533 ALLOC_STATE( tex[1], tex_pair, TEX_STATE_SIZE_OLDDRM, "TEX/tex-1", 1 );
534 ALLOC_STATE( tam, tex_any, TAM_STATE_SIZE, "TAM/tam", 0 );
535 }
536 else {
537 ALLOC_STATE( tex[0], tex, TEX_STATE_SIZE_OLDDRM, "TEX/tex-0", 0 );
538 ALLOC_STATE( tex[1], tex, TEX_STATE_SIZE_OLDDRM, "TEX/tex-1", 1 );
539 ALLOC_STATE( tam, never, TAM_STATE_SIZE, "TAM/tam", 0 );
540 }
541 ALLOC_STATE( tex[2], tex, TEX_STATE_SIZE_OLDDRM, "TEX/tex-2", 2 );
542 ALLOC_STATE( tex[3], tex, TEX_STATE_SIZE_OLDDRM, "TEX/tex-3", 3 );
543 ALLOC_STATE( tex[4], tex, TEX_STATE_SIZE_OLDDRM, "TEX/tex-4", 4 );
544 ALLOC_STATE( tex[5], tex, TEX_STATE_SIZE_OLDDRM, "TEX/tex-5", 5 );
545 ALLOC_STATE( atf, never, ATF_STATE_SIZE, "TF/tfactor", 0 );
546 ALLOC_STATE( afs[0], never, AFS_STATE_SIZE, "AFS/afsinst-0", 0 );
547 ALLOC_STATE( afs[1], never, AFS_STATE_SIZE, "AFS/afsinst-1", 1 );
548 }
549
550 for (i = 0; i < 5; i++)
551 rmesa->hw.tex[i].emit = tex_emit;
552 if (rmesa->radeon.radeonScreen->drmSupportsCubeMapsR200) {
553 ALLOC_STATE( cube[0], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-0", 0 );
554 ALLOC_STATE( cube[1], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-1", 1 );
555 ALLOC_STATE( cube[2], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-2", 2 );
556 ALLOC_STATE( cube[3], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-3", 3 );
557 ALLOC_STATE( cube[4], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-4", 4 );
558 ALLOC_STATE( cube[5], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-5", 5 );
559 for (i = 0; i < 5; i++)
560 rmesa->hw.cube[i].emit = cube_emit;
561 }
562 else {
563 ALLOC_STATE( cube[0], never, CUBE_STATE_SIZE, "CUBE/tex-0", 0 );
564 ALLOC_STATE( cube[1], never, CUBE_STATE_SIZE, "CUBE/tex-1", 1 );
565 ALLOC_STATE( cube[2], never, CUBE_STATE_SIZE, "CUBE/tex-2", 2 );
566 ALLOC_STATE( cube[3], never, CUBE_STATE_SIZE, "CUBE/tex-3", 3 );
567 ALLOC_STATE( cube[4], never, CUBE_STATE_SIZE, "CUBE/tex-4", 4 );
568 ALLOC_STATE( cube[5], never, CUBE_STATE_SIZE, "CUBE/tex-5", 5 );
569 }
570
571 if (rmesa->radeon.radeonScreen->drmSupportsVertexProgram) {
572 ALLOC_STATE( pvs, tcl_vp, PVS_STATE_SIZE, "PVS/pvscntl", 0 );
573 ALLOC_STATE( vpi[0], tcl_vp, VPI_STATE_SIZE, "VP/vertexprog-0", 0 );
574 ALLOC_STATE( vpi[1], tcl_vp_size, VPI_STATE_SIZE, "VP/vertexprog-1", 1 );
575 ALLOC_STATE( vpp[0], tcl_vp, VPP_STATE_SIZE, "VPP/vertexparam-0", 0 );
576 ALLOC_STATE( vpp[1], tcl_vpp_size, VPP_STATE_SIZE, "VPP/vertexparam-1", 1 );
577 }
578 else {
579 ALLOC_STATE( pvs, never, PVS_STATE_SIZE, "PVS/pvscntl", 0 );
580 ALLOC_STATE( vpi[0], never, VPI_STATE_SIZE, "VP/vertexprog-0", 0 );
581 ALLOC_STATE( vpi[1], never, VPI_STATE_SIZE, "VP/vertexprog-1", 1 );
582 ALLOC_STATE( vpp[0], never, VPP_STATE_SIZE, "VPP/vertexparam-0", 0 );
583 ALLOC_STATE( vpp[1], never, VPP_STATE_SIZE, "VPP/vertexparam-1", 1 );
584 }
585 /* FIXME: this atom has two commands, we need only one (ucp_vert_blend) for vp */
586 ALLOC_STATE( tcl, tcl_or_vp, TCL_STATE_SIZE, "TCL/tcl", 0 );
587 ALLOC_STATE( msl, tcl, MSL_STATE_SIZE, "MSL/matrix-select", 0 );
588 ALLOC_STATE( tcg, tcl, TCG_STATE_SIZE, "TCG/texcoordgen", 0 );
589 ALLOC_STATE( mtl[0], tcl_lighting, MTL_STATE_SIZE, "MTL0/material0", 0 );
590 ALLOC_STATE( mtl[1], tcl_lighting, MTL_STATE_SIZE, "MTL1/material1", 1 );
591 ALLOC_STATE( grd, tcl_or_vp, GRD_STATE_SIZE, "GRD/guard-band", 0 );
592 ALLOC_STATE( fog, tcl_fog, FOG_STATE_SIZE, "FOG/fog", 0 );
593 ALLOC_STATE( glt, tcl_lighting, GLT_STATE_SIZE, "GLT/light-global", 0 );
594 ALLOC_STATE( eye, tcl_lighting, EYE_STATE_SIZE, "EYE/eye-vector", 0 );
595 ALLOC_STATE( mat[R200_MTX_MV], tcl, MAT_STATE_SIZE, "MAT/modelview", 0 );
596 ALLOC_STATE( mat[R200_MTX_IMV], tcl, MAT_STATE_SIZE, "MAT/it-modelview", 0 );
597 ALLOC_STATE( mat[R200_MTX_MVP], tcl, MAT_STATE_SIZE, "MAT/modelproject", 0 );
598 ALLOC_STATE( mat[R200_MTX_TEX0], tcl_tex, MAT_STATE_SIZE, "MAT/texmat0", 0 );
599 ALLOC_STATE( mat[R200_MTX_TEX1], tcl_tex, MAT_STATE_SIZE, "MAT/texmat1", 1 );
600 ALLOC_STATE( mat[R200_MTX_TEX2], tcl_tex, MAT_STATE_SIZE, "MAT/texmat2", 2 );
601 ALLOC_STATE( mat[R200_MTX_TEX3], tcl_tex, MAT_STATE_SIZE, "MAT/texmat3", 3 );
602 ALLOC_STATE( mat[R200_MTX_TEX4], tcl_tex, MAT_STATE_SIZE, "MAT/texmat4", 4 );
603 ALLOC_STATE( mat[R200_MTX_TEX5], tcl_tex, MAT_STATE_SIZE, "MAT/texmat5", 5 );
604 ALLOC_STATE( ucp[0], tcl_ucp, UCP_STATE_SIZE, "UCP/userclip-0", 0 );
605 ALLOC_STATE( ucp[1], tcl_ucp, UCP_STATE_SIZE, "UCP/userclip-1", 1 );
606 ALLOC_STATE( ucp[2], tcl_ucp, UCP_STATE_SIZE, "UCP/userclip-2", 2 );
607 ALLOC_STATE( ucp[3], tcl_ucp, UCP_STATE_SIZE, "UCP/userclip-3", 3 );
608 ALLOC_STATE( ucp[4], tcl_ucp, UCP_STATE_SIZE, "UCP/userclip-4", 4 );
609 ALLOC_STATE( ucp[5], tcl_ucp, UCP_STATE_SIZE, "UCP/userclip-5", 5 );
610 ALLOC_STATE( lit[0], tcl_light, LIT_STATE_SIZE, "LIT/light-0", 0 );
611 ALLOC_STATE( lit[1], tcl_light, LIT_STATE_SIZE, "LIT/light-1", 1 );
612 ALLOC_STATE( lit[2], tcl_light, LIT_STATE_SIZE, "LIT/light-2", 2 );
613 ALLOC_STATE( lit[3], tcl_light, LIT_STATE_SIZE, "LIT/light-3", 3 );
614 ALLOC_STATE( lit[4], tcl_light, LIT_STATE_SIZE, "LIT/light-4", 4 );
615 ALLOC_STATE( lit[5], tcl_light, LIT_STATE_SIZE, "LIT/light-5", 5 );
616 ALLOC_STATE( lit[6], tcl_light, LIT_STATE_SIZE, "LIT/light-6", 6 );
617 ALLOC_STATE( lit[7], tcl_light, LIT_STATE_SIZE, "LIT/light-7", 7 );
618 ALLOC_STATE( pix[0], pix_zero, PIX_STATE_SIZE, "PIX/pixstage-0", 0 );
619 ALLOC_STATE( pix[1], texenv, PIX_STATE_SIZE, "PIX/pixstage-1", 1 );
620 ALLOC_STATE( pix[2], texenv, PIX_STATE_SIZE, "PIX/pixstage-2", 2 );
621 ALLOC_STATE( pix[3], texenv, PIX_STATE_SIZE, "PIX/pixstage-3", 3 );
622 ALLOC_STATE( pix[4], texenv, PIX_STATE_SIZE, "PIX/pixstage-4", 4 );
623 ALLOC_STATE( pix[5], texenv, PIX_STATE_SIZE, "PIX/pixstage-5", 5 );
624 if (rmesa->radeon.radeonScreen->drmSupportsTriPerf) {
625 ALLOC_STATE( prf, always, PRF_STATE_SIZE, "PRF/performance-tri", 0 );
626 }
627 else {
628 ALLOC_STATE( prf, never, PRF_STATE_SIZE, "PRF/performance-tri", 0 );
629 }
630 if (rmesa->radeon.radeonScreen->drmSupportsPointSprites) {
631 ALLOC_STATE( spr, always, SPR_STATE_SIZE, "SPR/pointsprite", 0 );
632 ALLOC_STATE( ptp, tcl, PTP_STATE_SIZE, "PTP/pointparams", 0 );
633 }
634 else {
635 ALLOC_STATE (spr, never, SPR_STATE_SIZE, "SPR/pointsprite", 0 );
636 ALLOC_STATE (ptp, never, PTP_STATE_SIZE, "PTP/pointparams", 0 );
637 }
638
639 r200SetUpAtomList( rmesa );
640
641 /* Fill in the packet headers:
642 */
643 rmesa->hw.ctx.cmd[CTX_CMD_0] = cmdpkt(RADEON_EMIT_PP_MISC);
644 rmesa->hw.ctx.cmd[CTX_CMD_1] = cmdpkt(RADEON_EMIT_PP_CNTL);
645 rmesa->hw.ctx.cmd[CTX_CMD_2] = cmdpkt(RADEON_EMIT_RB3D_COLORPITCH);
646 if (rmesa->radeon.radeonScreen->drmSupportsBlendColor)
647 rmesa->hw.ctx.cmd[CTX_CMD_3] = cmdpkt(R200_EMIT_RB3D_BLENDCOLOR);
648 rmesa->hw.lin.cmd[LIN_CMD_0] = cmdpkt(RADEON_EMIT_RE_LINE_PATTERN);
649 rmesa->hw.lin.cmd[LIN_CMD_1] = cmdpkt(RADEON_EMIT_SE_LINE_WIDTH);
650 rmesa->hw.msk.cmd[MSK_CMD_0] = cmdpkt(RADEON_EMIT_RB3D_STENCILREFMASK);
651 rmesa->hw.vpt.cmd[VPT_CMD_0] = cmdpkt(RADEON_EMIT_SE_VPORT_XSCALE);
652 rmesa->hw.set.cmd[SET_CMD_0] = cmdpkt(RADEON_EMIT_SE_CNTL);
653 rmesa->hw.msc.cmd[MSC_CMD_0] = cmdpkt(RADEON_EMIT_RE_MISC);
654 rmesa->hw.cst.cmd[CST_CMD_0] = cmdpkt(R200_EMIT_PP_CNTL_X);
655 rmesa->hw.cst.cmd[CST_CMD_1] = cmdpkt(R200_EMIT_RB3D_DEPTHXY_OFFSET);
656 rmesa->hw.cst.cmd[CST_CMD_2] = cmdpkt(R200_EMIT_RE_AUX_SCISSOR_CNTL);
657 rmesa->hw.cst.cmd[CST_CMD_3] = cmdpkt(R200_EMIT_RE_SCISSOR_TL_0);
658 rmesa->hw.cst.cmd[CST_CMD_4] = cmdpkt(R200_EMIT_SE_VAP_CNTL_STATUS);
659 rmesa->hw.cst.cmd[CST_CMD_5] = cmdpkt(R200_EMIT_RE_POINTSIZE);
660 rmesa->hw.cst.cmd[CST_CMD_6] = cmdpkt(R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0);
661 rmesa->hw.tam.cmd[TAM_CMD_0] = cmdpkt(R200_EMIT_PP_TAM_DEBUG3);
662 rmesa->hw.tf.cmd[TF_CMD_0] = cmdpkt(R200_EMIT_TFACTOR_0);
663 if (rmesa->radeon.radeonScreen->drmSupportsFragShader) {
664 rmesa->hw.atf.cmd[ATF_CMD_0] = cmdpkt(R200_EMIT_ATF_TFACTOR);
665 rmesa->hw.tex[0].cmd[TEX_CMD_0] = cmdpkt(R200_EMIT_PP_TXCTLALL_0);
666 rmesa->hw.tex[0].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(R200_EMIT_PP_TXOFFSET_0);
667 rmesa->hw.tex[1].cmd[TEX_CMD_0] = cmdpkt(R200_EMIT_PP_TXCTLALL_1);
668 rmesa->hw.tex[1].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(R200_EMIT_PP_TXOFFSET_1);
669 rmesa->hw.tex[2].cmd[TEX_CMD_0] = cmdpkt(R200_EMIT_PP_TXCTLALL_2);
670 rmesa->hw.tex[2].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(R200_EMIT_PP_TXOFFSET_2);
671 rmesa->hw.tex[3].cmd[TEX_CMD_0] = cmdpkt(R200_EMIT_PP_TXCTLALL_3);
672 rmesa->hw.tex[3].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(R200_EMIT_PP_TXOFFSET_3);
673 rmesa->hw.tex[4].cmd[TEX_CMD_0] = cmdpkt(R200_EMIT_PP_TXCTLALL_4);
674 rmesa->hw.tex[4].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(R200_EMIT_PP_TXOFFSET_4);
675 rmesa->hw.tex[5].cmd[TEX_CMD_0] = cmdpkt(R200_EMIT_PP_TXCTLALL_5);
676 rmesa->hw.tex[5].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(R200_EMIT_PP_TXOFFSET_5);
677 } else {
678 rmesa->hw.tex[0].cmd[TEX_CMD_0] = cmdpkt(R200_EMIT_PP_TXFILTER_0);
679 rmesa->hw.tex[0].cmd[TEX_CMD_1_OLDDRM] = cmdpkt(R200_EMIT_PP_TXOFFSET_0);
680 rmesa->hw.tex[1].cmd[TEX_CMD_0] = cmdpkt(R200_EMIT_PP_TXFILTER_1);
681 rmesa->hw.tex[1].cmd[TEX_CMD_1_OLDDRM] = cmdpkt(R200_EMIT_PP_TXOFFSET_1);
682 rmesa->hw.tex[2].cmd[TEX_CMD_0] = cmdpkt(R200_EMIT_PP_TXFILTER_2);
683 rmesa->hw.tex[2].cmd[TEX_CMD_1_OLDDRM] = cmdpkt(R200_EMIT_PP_TXOFFSET_2);
684 rmesa->hw.tex[3].cmd[TEX_CMD_0] = cmdpkt(R200_EMIT_PP_TXFILTER_3);
685 rmesa->hw.tex[3].cmd[TEX_CMD_1_OLDDRM] = cmdpkt(R200_EMIT_PP_TXOFFSET_3);
686 rmesa->hw.tex[4].cmd[TEX_CMD_0] = cmdpkt(R200_EMIT_PP_TXFILTER_4);
687 rmesa->hw.tex[4].cmd[TEX_CMD_1_OLDDRM] = cmdpkt(R200_EMIT_PP_TXOFFSET_4);
688 rmesa->hw.tex[5].cmd[TEX_CMD_0] = cmdpkt(R200_EMIT_PP_TXFILTER_5);
689 rmesa->hw.tex[5].cmd[TEX_CMD_1_OLDDRM] = cmdpkt(R200_EMIT_PP_TXOFFSET_5);
690 }
691 rmesa->hw.afs[0].cmd[AFS_CMD_0] = cmdpkt(R200_EMIT_PP_AFS_0);
692 rmesa->hw.afs[1].cmd[AFS_CMD_0] = cmdpkt(R200_EMIT_PP_AFS_1);
693 rmesa->hw.pvs.cmd[PVS_CMD_0] = cmdpkt(R200_EMIT_VAP_PVS_CNTL);
694 rmesa->hw.cube[0].cmd[CUBE_CMD_0] = cmdpkt(R200_EMIT_PP_CUBIC_FACES_0);
695 rmesa->hw.cube[0].cmd[CUBE_CMD_1] = cmdpkt(R200_EMIT_PP_CUBIC_OFFSETS_0);
696 rmesa->hw.cube[1].cmd[CUBE_CMD_0] = cmdpkt(R200_EMIT_PP_CUBIC_FACES_1);
697 rmesa->hw.cube[1].cmd[CUBE_CMD_1] = cmdpkt(R200_EMIT_PP_CUBIC_OFFSETS_1);
698 rmesa->hw.cube[2].cmd[CUBE_CMD_0] = cmdpkt(R200_EMIT_PP_CUBIC_FACES_2);
699 rmesa->hw.cube[2].cmd[CUBE_CMD_1] = cmdpkt(R200_EMIT_PP_CUBIC_OFFSETS_2);
700 rmesa->hw.cube[3].cmd[CUBE_CMD_0] = cmdpkt(R200_EMIT_PP_CUBIC_FACES_3);
701 rmesa->hw.cube[3].cmd[CUBE_CMD_1] = cmdpkt(R200_EMIT_PP_CUBIC_OFFSETS_3);
702 rmesa->hw.cube[4].cmd[CUBE_CMD_0] = cmdpkt(R200_EMIT_PP_CUBIC_FACES_4);
703 rmesa->hw.cube[4].cmd[CUBE_CMD_1] = cmdpkt(R200_EMIT_PP_CUBIC_OFFSETS_4);
704 rmesa->hw.cube[5].cmd[CUBE_CMD_0] = cmdpkt(R200_EMIT_PP_CUBIC_FACES_5);
705 rmesa->hw.cube[5].cmd[CUBE_CMD_1] = cmdpkt(R200_EMIT_PP_CUBIC_OFFSETS_5);
706 rmesa->hw.pix[0].cmd[PIX_CMD_0] = cmdpkt(R200_EMIT_PP_TXCBLEND_0);
707 rmesa->hw.pix[1].cmd[PIX_CMD_0] = cmdpkt(R200_EMIT_PP_TXCBLEND_1);
708 rmesa->hw.pix[2].cmd[PIX_CMD_0] = cmdpkt(R200_EMIT_PP_TXCBLEND_2);
709 rmesa->hw.pix[3].cmd[PIX_CMD_0] = cmdpkt(R200_EMIT_PP_TXCBLEND_3);
710 rmesa->hw.pix[4].cmd[PIX_CMD_0] = cmdpkt(R200_EMIT_PP_TXCBLEND_4);
711 rmesa->hw.pix[5].cmd[PIX_CMD_0] = cmdpkt(R200_EMIT_PP_TXCBLEND_5);
712 rmesa->hw.zbs.cmd[ZBS_CMD_0] = cmdpkt(RADEON_EMIT_SE_ZBIAS_FACTOR);
713 rmesa->hw.tcl.cmd[TCL_CMD_0] = cmdpkt(R200_EMIT_TCL_LIGHT_MODEL_CTL_0);
714 rmesa->hw.tcl.cmd[TCL_CMD_1] = cmdpkt(R200_EMIT_TCL_UCP_VERT_BLEND_CTL);
715 rmesa->hw.tcg.cmd[TCG_CMD_0] = cmdpkt(R200_EMIT_TEX_PROC_CTL_2);
716 rmesa->hw.msl.cmd[MSL_CMD_0] = cmdpkt(R200_EMIT_MATRIX_SELECT_0);
717 rmesa->hw.vap.cmd[VAP_CMD_0] = cmdpkt(R200_EMIT_VAP_CTL);
718 rmesa->hw.vtx.cmd[VTX_CMD_0] = cmdpkt(R200_EMIT_VTX_FMT_0);
719 rmesa->hw.vtx.cmd[VTX_CMD_1] = cmdpkt(R200_EMIT_OUTPUT_VTX_COMP_SEL);
720 rmesa->hw.vtx.cmd[VTX_CMD_2] = cmdpkt(R200_EMIT_SE_VTX_STATE_CNTL);
721 rmesa->hw.vte.cmd[VTE_CMD_0] = cmdpkt(R200_EMIT_VTE_CNTL);
722 rmesa->hw.prf.cmd[PRF_CMD_0] = cmdpkt(R200_EMIT_PP_TRI_PERF_CNTL);
723 rmesa->hw.spr.cmd[SPR_CMD_0] = cmdpkt(R200_EMIT_TCL_POINT_SPRITE_CNTL);
724 rmesa->hw.mtl[0].cmd[MTL_CMD_0] =
725 cmdvec( R200_VS_MAT_0_EMISS, 1, 16 );
726 rmesa->hw.mtl[0].cmd[MTL_CMD_1] =
727 cmdscl2( R200_SS_MAT_0_SHININESS, 1, 1 );
728 rmesa->hw.mtl[1].cmd[MTL_CMD_0] =
729 cmdvec( R200_VS_MAT_1_EMISS, 1, 16 );
730 rmesa->hw.mtl[1].cmd[MTL_CMD_1] =
731 cmdscl2( R200_SS_MAT_1_SHININESS, 1, 1 );
732
733 rmesa->hw.vpi[0].cmd[VPI_CMD_0] =
734 cmdveclinear( R200_PVS_PROG0, 64 );
735 rmesa->hw.vpi[1].cmd[VPI_CMD_0] =
736 cmdveclinear( R200_PVS_PROG1, 64 );
737 rmesa->hw.vpp[0].cmd[VPP_CMD_0] =
738 cmdveclinear( R200_PVS_PARAM0, 96 );
739 rmesa->hw.vpp[1].cmd[VPP_CMD_0] =
740 cmdveclinear( R200_PVS_PARAM1, 96 );
741
742 rmesa->hw.grd.cmd[GRD_CMD_0] =
743 cmdscl( R200_SS_VERT_GUARD_CLIP_ADJ_ADDR, 1, 4 );
744 rmesa->hw.fog.cmd[FOG_CMD_0] =
745 cmdvec( R200_VS_FOG_PARAM_ADDR, 1, 4 );
746 rmesa->hw.glt.cmd[GLT_CMD_0] =
747 cmdvec( R200_VS_GLOBAL_AMBIENT_ADDR, 1, 4 );
748 rmesa->hw.eye.cmd[EYE_CMD_0] =
749 cmdvec( R200_VS_EYE_VECTOR_ADDR, 1, 4 );
750
751 rmesa->hw.mat[R200_MTX_MV].cmd[MAT_CMD_0] =
752 cmdvec( R200_VS_MATRIX_0_MV, 1, 16);
753 rmesa->hw.mat[R200_MTX_IMV].cmd[MAT_CMD_0] =
754 cmdvec( R200_VS_MATRIX_1_INV_MV, 1, 16);
755 rmesa->hw.mat[R200_MTX_MVP].cmd[MAT_CMD_0] =
756 cmdvec( R200_VS_MATRIX_2_MVP, 1, 16);
757 rmesa->hw.mat[R200_MTX_TEX0].cmd[MAT_CMD_0] =
758 cmdvec( R200_VS_MATRIX_3_TEX0, 1, 16);
759 rmesa->hw.mat[R200_MTX_TEX1].cmd[MAT_CMD_0] =
760 cmdvec( R200_VS_MATRIX_4_TEX1, 1, 16);
761 rmesa->hw.mat[R200_MTX_TEX2].cmd[MAT_CMD_0] =
762 cmdvec( R200_VS_MATRIX_5_TEX2, 1, 16);
763 rmesa->hw.mat[R200_MTX_TEX3].cmd[MAT_CMD_0] =
764 cmdvec( R200_VS_MATRIX_6_TEX3, 1, 16);
765 rmesa->hw.mat[R200_MTX_TEX4].cmd[MAT_CMD_0] =
766 cmdvec( R200_VS_MATRIX_7_TEX4, 1, 16);
767 rmesa->hw.mat[R200_MTX_TEX5].cmd[MAT_CMD_0] =
768 cmdvec( R200_VS_MATRIX_8_TEX5, 1, 16);
769
770 for (i = 0 ; i < 8; i++) {
771 rmesa->hw.lit[i].cmd[LIT_CMD_0] =
772 cmdvec( R200_VS_LIGHT_AMBIENT_ADDR + i, 8, 24 );
773 rmesa->hw.lit[i].cmd[LIT_CMD_1] =
774 cmdscl( R200_SS_LIGHT_DCD_ADDR + i, 8, 7 );
775 }
776
777 for (i = 0 ; i < 6; i++) {
778 rmesa->hw.ucp[i].cmd[UCP_CMD_0] =
779 cmdvec( R200_VS_UCP_ADDR + i, 1, 4 );
780 }
781
782 rmesa->hw.ptp.cmd[PTP_CMD_0] =
783 cmdvec( R200_VS_PNT_SPRITE_VPORT_SCALE, 1, 4 );
784 rmesa->hw.ptp.cmd[PTP_CMD_1] =
785 cmdvec( R200_VS_PNT_SPRITE_ATT_CONST, 1, 12 );
786
787 /* Initial Harware state:
788 */
789 rmesa->hw.ctx.cmd[CTX_PP_MISC] = (R200_ALPHA_TEST_PASS
790 /* | R200_RIGHT_HAND_CUBE_OGL*/);
791
792 rmesa->hw.ctx.cmd[CTX_PP_FOG_COLOR] = (R200_FOG_VERTEX |
793 R200_FOG_USE_SPEC_ALPHA);
794
795 rmesa->hw.ctx.cmd[CTX_RE_SOLID_COLOR] = 0x00000000;
796
797 rmesa->hw.ctx.cmd[CTX_RB3D_BLENDCNTL] = (R200_COMB_FCN_ADD_CLAMP |
798 (R200_BLEND_GL_ONE << R200_SRC_BLEND_SHIFT) |
799 (R200_BLEND_GL_ZERO << R200_DST_BLEND_SHIFT));
800
801 if (rmesa->radeon.radeonScreen->drmSupportsBlendColor) {
802 rmesa->hw.ctx.cmd[CTX_RB3D_BLENDCOLOR] = 0x00000000;
803 rmesa->hw.ctx.cmd[CTX_RB3D_ABLENDCNTL] = (R200_COMB_FCN_ADD_CLAMP |
804 (R200_BLEND_GL_ONE << R200_SRC_BLEND_SHIFT) |
805 (R200_BLEND_GL_ZERO << R200_DST_BLEND_SHIFT));
806 rmesa->hw.ctx.cmd[CTX_RB3D_CBLENDCNTL] = (R200_COMB_FCN_ADD_CLAMP |
807 (R200_BLEND_GL_ONE << R200_SRC_BLEND_SHIFT) |
808 (R200_BLEND_GL_ZERO << R200_DST_BLEND_SHIFT));
809 }
810
811 rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHOFFSET] =
812 rmesa->radeon.radeonScreen->depthOffset + rmesa->radeon.radeonScreen->fbLocation;
813
814 rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHPITCH] =
815 ((rmesa->radeon.radeonScreen->depthPitch &
816 R200_DEPTHPITCH_MASK) |
817 R200_DEPTH_ENDIAN_NO_SWAP);
818
819 if (rmesa->using_hyperz)
820 rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHPITCH] |= R200_DEPTH_HYPERZ;
821
822 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] = (depth_fmt |
823 R200_Z_TEST_LESS |
824 R200_STENCIL_TEST_ALWAYS |
825 R200_STENCIL_FAIL_KEEP |
826 R200_STENCIL_ZPASS_KEEP |
827 R200_STENCIL_ZFAIL_KEEP |
828 R200_Z_WRITE_ENABLE);
829
830 if (rmesa->using_hyperz) {
831 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= R200_Z_COMPRESSION_ENABLE |
832 R200_Z_DECOMPRESSION_ENABLE;
833 /* if (rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_R200)
834 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_HIERARCHY_ENABLE;*/
835 }
836
837 rmesa->hw.ctx.cmd[CTX_PP_CNTL] = (R200_ANTI_ALIAS_NONE
838 | R200_TEX_BLEND_0_ENABLE);
839
840 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] = color_fmt;
841 switch ( driQueryOptioni( &rmesa->radeon.optionCache, "dither_mode" ) ) {
842 case DRI_CONF_DITHER_XERRORDIFFRESET:
843 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= R200_DITHER_INIT;
844 break;
845 case DRI_CONF_DITHER_ORDERED:
846 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= R200_SCALE_DITHER_ENABLE;
847 break;
848 }
849 if ( driQueryOptioni( &rmesa->radeon.optionCache, "round_mode" ) ==
850 DRI_CONF_ROUND_ROUND )
851 rmesa->radeon.state.color.roundEnable = R200_ROUND_ENABLE;
852 else
853 rmesa->radeon.state.color.roundEnable = 0;
854 if ( driQueryOptioni (&rmesa->radeon.optionCache, "color_reduction" ) ==
855 DRI_CONF_COLOR_REDUCTION_DITHER )
856 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= R200_DITHER_ENABLE;
857 else
858 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= rmesa->radeon.state.color.roundEnable;
859
860 #if 000
861 rmesa->hw.ctx.cmd[CTX_RB3D_COLOROFFSET] = ((rmesa->radeon.state.color.drawOffset +
862 rmesa->radeon.radeonScreen->fbLocation)
863 & R200_COLOROFFSET_MASK);
864
865 rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] = ((rmesa->radeon.state.color.drawPitch &
866 R200_COLORPITCH_MASK) |
867 R200_COLOR_ENDIAN_NO_SWAP);
868 #else
869 rmesa->hw.ctx.cmd[CTX_RB3D_COLOROFFSET] = ((drawOffset +
870 rmesa->radeon.radeonScreen->fbLocation)
871 & R200_COLOROFFSET_MASK);
872
873 rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] = ((drawPitch &
874 R200_COLORPITCH_MASK) |
875 R200_COLOR_ENDIAN_NO_SWAP);
876 #endif
877 /* (fixed size) sarea is initialized to zero afaics so can omit version check. Phew! */
878 if (rmesa->radeon.sarea->tiling_enabled) {
879 rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] |= R200_COLOR_TILE_ENABLE;
880 }
881
882 rmesa->hw.prf.cmd[PRF_PP_TRI_PERF] = R200_TRI_CUTOFF_MASK - R200_TRI_CUTOFF_MASK *
883 driQueryOptionf (&rmesa->radeon.optionCache,"texture_blend_quality");
884 rmesa->hw.prf.cmd[PRF_PP_PERF_CNTL] = 0;
885
886 rmesa->hw.set.cmd[SET_SE_CNTL] = (R200_FFACE_CULL_CCW |
887 R200_BFACE_SOLID |
888 R200_FFACE_SOLID |
889 R200_FLAT_SHADE_VTX_LAST |
890 R200_DIFFUSE_SHADE_GOURAUD |
891 R200_ALPHA_SHADE_GOURAUD |
892 R200_SPECULAR_SHADE_GOURAUD |
893 R200_FOG_SHADE_GOURAUD |
894 R200_DISC_FOG_SHADE_GOURAUD |
895 R200_VTX_PIX_CENTER_OGL |
896 R200_ROUND_MODE_TRUNC |
897 R200_ROUND_PREC_8TH_PIX);
898
899 rmesa->hw.set.cmd[SET_RE_CNTL] = (R200_PERSPECTIVE_ENABLE |
900 R200_SCISSOR_ENABLE);
901
902 rmesa->hw.lin.cmd[LIN_RE_LINE_PATTERN] = ((1 << 16) | 0xffff);
903
904 rmesa->hw.lin.cmd[LIN_RE_LINE_STATE] =
905 ((0 << R200_LINE_CURRENT_PTR_SHIFT) |
906 (1 << R200_LINE_CURRENT_COUNT_SHIFT));
907
908 rmesa->hw.lin.cmd[LIN_SE_LINE_WIDTH] = (1 << 4);
909
910 rmesa->hw.msk.cmd[MSK_RB3D_STENCILREFMASK] =
911 ((0x00 << R200_STENCIL_REF_SHIFT) |
912 (0xff << R200_STENCIL_MASK_SHIFT) |
913 (0xff << R200_STENCIL_WRITEMASK_SHIFT));
914
915 rmesa->hw.msk.cmd[MSK_RB3D_ROPCNTL] = R200_ROP_COPY;
916 rmesa->hw.msk.cmd[MSK_RB3D_PLANEMASK] = 0xffffffff;
917
918 rmesa->hw.tam.cmd[TAM_DEBUG3] = 0;
919
920 rmesa->hw.msc.cmd[MSC_RE_MISC] =
921 ((0 << R200_STIPPLE_X_OFFSET_SHIFT) |
922 (0 << R200_STIPPLE_Y_OFFSET_SHIFT) |
923 R200_STIPPLE_BIG_BIT_ORDER);
924
925
926 rmesa->hw.cst.cmd[CST_PP_CNTL_X] = 0;
927 rmesa->hw.cst.cmd[CST_RB3D_DEPTHXY_OFFSET] = 0;
928 rmesa->hw.cst.cmd[CST_RE_AUX_SCISSOR_CNTL] = 0x0;
929 rmesa->hw.cst.cmd[CST_RE_SCISSOR_TL_0] = 0;
930 rmesa->hw.cst.cmd[CST_RE_SCISSOR_BR_0] = 0;
931 rmesa->hw.cst.cmd[CST_SE_VAP_CNTL_STATUS] =
932 #ifdef MESA_BIG_ENDIAN
933 R200_VC_32BIT_SWAP;
934 #else
935 R200_VC_NO_SWAP;
936 #endif
937
938 if (!(rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL)) {
939 /* Bypass TCL */
940 rmesa->hw.cst.cmd[CST_SE_VAP_CNTL_STATUS] |= (1<<8);
941 }
942
943 rmesa->hw.cst.cmd[CST_RE_POINTSIZE] =
944 (((GLuint)(ctx->Const.MaxPointSize * 16.0)) << R200_MAXPOINTSIZE_SHIFT) | 0x10;
945 rmesa->hw.cst.cmd[CST_SE_TCL_INPUT_VTX_0] =
946 (0x0 << R200_VERTEX_POSITION_ADDR__SHIFT);
947 rmesa->hw.cst.cmd[CST_SE_TCL_INPUT_VTX_1] =
948 (0x02 << R200_VTX_COLOR_0_ADDR__SHIFT) |
949 (0x03 << R200_VTX_COLOR_1_ADDR__SHIFT);
950 rmesa->hw.cst.cmd[CST_SE_TCL_INPUT_VTX_2] =
951 (0x06 << R200_VTX_TEX_0_ADDR__SHIFT) |
952 (0x07 << R200_VTX_TEX_1_ADDR__SHIFT) |
953 (0x08 << R200_VTX_TEX_2_ADDR__SHIFT) |
954 (0x09 << R200_VTX_TEX_3_ADDR__SHIFT);
955 rmesa->hw.cst.cmd[CST_SE_TCL_INPUT_VTX_3] =
956 (0x0A << R200_VTX_TEX_4_ADDR__SHIFT) |
957 (0x0B << R200_VTX_TEX_5_ADDR__SHIFT);
958
959
960 rmesa->hw.vpt.cmd[VPT_SE_VPORT_XSCALE] = 0x00000000;
961 rmesa->hw.vpt.cmd[VPT_SE_VPORT_XOFFSET] = 0x00000000;
962 rmesa->hw.vpt.cmd[VPT_SE_VPORT_YSCALE] = 0x00000000;
963 rmesa->hw.vpt.cmd[VPT_SE_VPORT_YOFFSET] = 0x00000000;
964 rmesa->hw.vpt.cmd[VPT_SE_VPORT_ZSCALE] = 0x00000000;
965 rmesa->hw.vpt.cmd[VPT_SE_VPORT_ZOFFSET] = 0x00000000;
966
967 for ( i = 0 ; i < ctx->Const.MaxTextureUnits ; i++ ) {
968 rmesa->hw.tex[i].cmd[TEX_PP_TXFILTER] = R200_BORDER_MODE_OGL;
969 rmesa->hw.tex[i].cmd[TEX_PP_TXFORMAT] =
970 ((i << R200_TXFORMAT_ST_ROUTE_SHIFT) | /* <-- note i */
971 (2 << R200_TXFORMAT_WIDTH_SHIFT) |
972 (2 << R200_TXFORMAT_HEIGHT_SHIFT));
973 rmesa->hw.tex[i].cmd[TEX_PP_BORDER_COLOR] = 0;
974 rmesa->hw.tex[i].cmd[TEX_PP_TXFORMAT_X] =
975 (/* R200_TEXCOORD_PROJ | */
976 0x100000); /* Small default bias */
977 if (rmesa->radeon.radeonScreen->drmSupportsFragShader) {
978 rmesa->hw.tex[i].cmd[TEX_PP_TXOFFSET_NEWDRM] =
979 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
980 rmesa->hw.tex[i].cmd[TEX_PP_CUBIC_FACES] = 0;
981 rmesa->hw.tex[i].cmd[TEX_PP_TXMULTI_CTL] = 0;
982 }
983 else {
984 rmesa->hw.tex[i].cmd[TEX_PP_TXOFFSET_OLDDRM] =
985 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
986 }
987
988 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_FACES] = 0;
989 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F1] =
990 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
991 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F2] =
992 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
993 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F3] =
994 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
995 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F4] =
996 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
997 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F5] =
998 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
999
1000 rmesa->hw.pix[i].cmd[PIX_PP_TXCBLEND] =
1001 (R200_TXC_ARG_A_ZERO |
1002 R200_TXC_ARG_B_ZERO |
1003 R200_TXC_ARG_C_DIFFUSE_COLOR |
1004 R200_TXC_OP_MADD);
1005
1006 rmesa->hw.pix[i].cmd[PIX_PP_TXCBLEND2] =
1007 ((i << R200_TXC_TFACTOR_SEL_SHIFT) |
1008 R200_TXC_SCALE_1X |
1009 R200_TXC_CLAMP_0_1 |
1010 R200_TXC_OUTPUT_REG_R0);
1011
1012 rmesa->hw.pix[i].cmd[PIX_PP_TXABLEND] =
1013 (R200_TXA_ARG_A_ZERO |
1014 R200_TXA_ARG_B_ZERO |
1015 R200_TXA_ARG_C_DIFFUSE_ALPHA |
1016 R200_TXA_OP_MADD);
1017
1018 rmesa->hw.pix[i].cmd[PIX_PP_TXABLEND2] =
1019 ((i << R200_TXA_TFACTOR_SEL_SHIFT) |
1020 R200_TXA_SCALE_1X |
1021 R200_TXA_CLAMP_0_1 |
1022 R200_TXA_OUTPUT_REG_R0);
1023 }
1024
1025 rmesa->hw.tf.cmd[TF_TFACTOR_0] = 0;
1026 rmesa->hw.tf.cmd[TF_TFACTOR_1] = 0;
1027 rmesa->hw.tf.cmd[TF_TFACTOR_2] = 0;
1028 rmesa->hw.tf.cmd[TF_TFACTOR_3] = 0;
1029 rmesa->hw.tf.cmd[TF_TFACTOR_4] = 0;
1030 rmesa->hw.tf.cmd[TF_TFACTOR_5] = 0;
1031
1032 rmesa->hw.vap.cmd[VAP_SE_VAP_CNTL] =
1033 (R200_VAP_TCL_ENABLE |
1034 (0x9 << R200_VAP_VF_MAX_VTX_NUM__SHIFT));
1035
1036 rmesa->hw.vte.cmd[VTE_SE_VTE_CNTL] =
1037 (R200_VPORT_X_SCALE_ENA |
1038 R200_VPORT_Y_SCALE_ENA |
1039 R200_VPORT_Z_SCALE_ENA |
1040 R200_VPORT_X_OFFSET_ENA |
1041 R200_VPORT_Y_OFFSET_ENA |
1042 R200_VPORT_Z_OFFSET_ENA |
1043 /* FIXME: Turn on for tex rect only */
1044 R200_VTX_ST_DENORMALIZED |
1045 R200_VTX_W0_FMT);
1046
1047
1048 rmesa->hw.vtx.cmd[VTX_VTXFMT_0] = 0;
1049 rmesa->hw.vtx.cmd[VTX_VTXFMT_1] = 0;
1050 rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_VTXFMT_0] =
1051 ((R200_VTX_Z0 | R200_VTX_W0 |
1052 (R200_VTX_FP_RGBA << R200_VTX_COLOR_0_SHIFT)));
1053 rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_VTXFMT_1] = 0;
1054 rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_COMPSEL] = (R200_OUTPUT_XYZW);
1055 rmesa->hw.vtx.cmd[VTX_STATE_CNTL] = R200_VSC_UPDATE_USER_COLOR_0_ENABLE;
1056
1057
1058 /* Matrix selection */
1059 rmesa->hw.msl.cmd[MSL_MATRIX_SELECT_0] =
1060 (R200_MTX_MV << R200_MODELVIEW_0_SHIFT);
1061
1062 rmesa->hw.msl.cmd[MSL_MATRIX_SELECT_1] =
1063 (R200_MTX_IMV << R200_IT_MODELVIEW_0_SHIFT);
1064
1065 rmesa->hw.msl.cmd[MSL_MATRIX_SELECT_2] =
1066 (R200_MTX_MVP << R200_MODELPROJECT_0_SHIFT);
1067
1068 rmesa->hw.msl.cmd[MSL_MATRIX_SELECT_3] =
1069 ((R200_MTX_TEX0 << R200_TEXMAT_0_SHIFT) |
1070 (R200_MTX_TEX1 << R200_TEXMAT_1_SHIFT) |
1071 (R200_MTX_TEX2 << R200_TEXMAT_2_SHIFT) |
1072 (R200_MTX_TEX3 << R200_TEXMAT_3_SHIFT));
1073
1074 rmesa->hw.msl.cmd[MSL_MATRIX_SELECT_4] =
1075 ((R200_MTX_TEX4 << R200_TEXMAT_4_SHIFT) |
1076 (R200_MTX_TEX5 << R200_TEXMAT_5_SHIFT));
1077
1078
1079 /* General TCL state */
1080 rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL_0] =
1081 (R200_SPECULAR_LIGHTS |
1082 R200_DIFFUSE_SPECULAR_COMBINE |
1083 R200_LOCAL_LIGHT_VEC_GL |
1084 R200_LM0_SOURCE_MATERIAL_0 << R200_FRONT_SHININESS_SOURCE_SHIFT |
1085 R200_LM0_SOURCE_MATERIAL_1 << R200_BACK_SHININESS_SOURCE_SHIFT);
1086
1087 rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL_1] =
1088 ((R200_LM1_SOURCE_MATERIAL_0 << R200_FRONT_EMISSIVE_SOURCE_SHIFT) |
1089 (R200_LM1_SOURCE_MATERIAL_0 << R200_FRONT_AMBIENT_SOURCE_SHIFT) |
1090 (R200_LM1_SOURCE_MATERIAL_0 << R200_FRONT_DIFFUSE_SOURCE_SHIFT) |
1091 (R200_LM1_SOURCE_MATERIAL_0 << R200_FRONT_SPECULAR_SOURCE_SHIFT) |
1092 (R200_LM1_SOURCE_MATERIAL_1 << R200_BACK_EMISSIVE_SOURCE_SHIFT) |
1093 (R200_LM1_SOURCE_MATERIAL_1 << R200_BACK_AMBIENT_SOURCE_SHIFT) |
1094 (R200_LM1_SOURCE_MATERIAL_1 << R200_BACK_DIFFUSE_SOURCE_SHIFT) |
1095 (R200_LM1_SOURCE_MATERIAL_1 << R200_BACK_SPECULAR_SOURCE_SHIFT));
1096
1097 rmesa->hw.tcl.cmd[TCL_PER_LIGHT_CTL_0] = 0; /* filled in via callbacks */
1098 rmesa->hw.tcl.cmd[TCL_PER_LIGHT_CTL_1] = 0;
1099 rmesa->hw.tcl.cmd[TCL_PER_LIGHT_CTL_2] = 0;
1100 rmesa->hw.tcl.cmd[TCL_PER_LIGHT_CTL_3] = 0;
1101
1102 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] =
1103 (R200_UCP_IN_CLIP_SPACE |
1104 R200_CULL_FRONT_IS_CCW);
1105
1106 /* Texgen/Texmat state */
1107 rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_2] = 0x00ffffff;
1108 rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_3] =
1109 ((0 << R200_TEXGEN_0_INPUT_TEX_SHIFT) |
1110 (1 << R200_TEXGEN_1_INPUT_TEX_SHIFT) |
1111 (2 << R200_TEXGEN_2_INPUT_TEX_SHIFT) |
1112 (3 << R200_TEXGEN_3_INPUT_TEX_SHIFT) |
1113 (4 << R200_TEXGEN_4_INPUT_TEX_SHIFT) |
1114 (5 << R200_TEXGEN_5_INPUT_TEX_SHIFT));
1115 rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_0] = 0;
1116 rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_1] =
1117 ((0 << R200_TEXGEN_0_INPUT_SHIFT) |
1118 (1 << R200_TEXGEN_1_INPUT_SHIFT) |
1119 (2 << R200_TEXGEN_2_INPUT_SHIFT) |
1120 (3 << R200_TEXGEN_3_INPUT_SHIFT) |
1121 (4 << R200_TEXGEN_4_INPUT_SHIFT) |
1122 (5 << R200_TEXGEN_5_INPUT_SHIFT));
1123 rmesa->hw.tcg.cmd[TCG_TEX_CYL_WRAP_CTL] = 0;
1124
1125
1126 for (i = 0 ; i < 8; i++) {
1127 struct gl_light *l = &ctx->Light.Light[i];
1128 GLenum p = GL_LIGHT0 + i;
1129 *(float *)&(rmesa->hw.lit[i].cmd[LIT_RANGE_CUTOFF]) = FLT_MAX;
1130
1131 ctx->Driver.Lightfv( ctx, p, GL_AMBIENT, l->Ambient );
1132 ctx->Driver.Lightfv( ctx, p, GL_DIFFUSE, l->Diffuse );
1133 ctx->Driver.Lightfv( ctx, p, GL_SPECULAR, l->Specular );
1134 ctx->Driver.Lightfv( ctx, p, GL_POSITION, NULL );
1135 ctx->Driver.Lightfv( ctx, p, GL_SPOT_DIRECTION, NULL );
1136 ctx->Driver.Lightfv( ctx, p, GL_SPOT_EXPONENT, &l->SpotExponent );
1137 ctx->Driver.Lightfv( ctx, p, GL_SPOT_CUTOFF, &l->SpotCutoff );
1138 ctx->Driver.Lightfv( ctx, p, GL_CONSTANT_ATTENUATION,
1139 &l->ConstantAttenuation );
1140 ctx->Driver.Lightfv( ctx, p, GL_LINEAR_ATTENUATION,
1141 &l->LinearAttenuation );
1142 ctx->Driver.Lightfv( ctx, p, GL_QUADRATIC_ATTENUATION,
1143 &l->QuadraticAttenuation );
1144 *(float *)&(rmesa->hw.lit[i].cmd[LIT_ATTEN_XXX]) = 0.0;
1145 }
1146
1147 ctx->Driver.LightModelfv( ctx, GL_LIGHT_MODEL_AMBIENT,
1148 ctx->Light.Model.Ambient );
1149
1150 TNL_CONTEXT(ctx)->Driver.NotifyMaterialChange( ctx );
1151
1152 for (i = 0 ; i < 6; i++) {
1153 ctx->Driver.ClipPlane( ctx, GL_CLIP_PLANE0 + i, NULL );
1154 }
1155
1156 ctx->Driver.Fogfv( ctx, GL_FOG_MODE, NULL );
1157 ctx->Driver.Fogfv( ctx, GL_FOG_DENSITY, &ctx->Fog.Density );
1158 ctx->Driver.Fogfv( ctx, GL_FOG_START, &ctx->Fog.Start );
1159 ctx->Driver.Fogfv( ctx, GL_FOG_END, &ctx->Fog.End );
1160 ctx->Driver.Fogfv( ctx, GL_FOG_COLOR, ctx->Fog.Color );
1161 ctx->Driver.Fogfv( ctx, GL_FOG_COORDINATE_SOURCE_EXT, NULL );
1162
1163 rmesa->hw.grd.cmd[GRD_VERT_GUARD_CLIP_ADJ] = IEEE_ONE;
1164 rmesa->hw.grd.cmd[GRD_VERT_GUARD_DISCARD_ADJ] = IEEE_ONE;
1165 rmesa->hw.grd.cmd[GRD_HORZ_GUARD_CLIP_ADJ] = IEEE_ONE;
1166 rmesa->hw.grd.cmd[GRD_HORZ_GUARD_DISCARD_ADJ] = IEEE_ONE;
1167
1168 rmesa->hw.eye.cmd[EYE_X] = 0;
1169 rmesa->hw.eye.cmd[EYE_Y] = 0;
1170 rmesa->hw.eye.cmd[EYE_Z] = IEEE_ONE;
1171 rmesa->hw.eye.cmd[EYE_RESCALE_FACTOR] = IEEE_ONE;
1172
1173 rmesa->hw.spr.cmd[SPR_POINT_SPRITE_CNTL] =
1174 R200_PS_SE_SEL_STATE | R200_PS_MULT_CONST;
1175
1176 /* ptp_eye is presumably used to calculate the attenuation wrt a different
1177 location? In any case, since point attenuation triggers _needeyecoords,
1178 it is constant. Probably ignored as long as R200_PS_USE_MODEL_EYE_VEC
1179 isn't set */
1180 rmesa->hw.ptp.cmd[PTP_EYE_X] = 0;
1181 rmesa->hw.ptp.cmd[PTP_EYE_Y] = 0;
1182 rmesa->hw.ptp.cmd[PTP_EYE_Z] = IEEE_ONE | 0x80000000; /* -1.0 */
1183 rmesa->hw.ptp.cmd[PTP_EYE_3] = 0;
1184 /* no idea what the ptp_vport_scale values are good for, except the
1185 PTSIZE one - hopefully doesn't matter */
1186 rmesa->hw.ptp.cmd[PTP_VPORT_SCALE_0] = IEEE_ONE;
1187 rmesa->hw.ptp.cmd[PTP_VPORT_SCALE_1] = IEEE_ONE;
1188 rmesa->hw.ptp.cmd[PTP_VPORT_SCALE_PTSIZE] = IEEE_ONE;
1189 rmesa->hw.ptp.cmd[PTP_VPORT_SCALE_3] = IEEE_ONE;
1190 rmesa->hw.ptp.cmd[PTP_ATT_CONST_QUAD] = 0;
1191 rmesa->hw.ptp.cmd[PTP_ATT_CONST_LIN] = 0;
1192 rmesa->hw.ptp.cmd[PTP_ATT_CONST_CON] = IEEE_ONE;
1193 rmesa->hw.ptp.cmd[PTP_ATT_CONST_3] = 0;
1194 rmesa->hw.ptp.cmd[PTP_CLAMP_MIN] = IEEE_ONE;
1195 rmesa->hw.ptp.cmd[PTP_CLAMP_MAX] = 0x44ffe000; /* 2047 */
1196 rmesa->hw.ptp.cmd[PTP_CLAMP_2] = 0;
1197 rmesa->hw.ptp.cmd[PTP_CLAMP_3] = 0;
1198
1199 r200LightingSpaceChange( ctx );
1200
1201 rmesa->hw.all_dirty = GL_TRUE;
1202
1203 rcommonInitCmdBuf(&rmesa->radeon, rmesa->hw.max_state_size);
1204 }