1 /* $XFree86: xc/lib/GL/mesa/src/drv/r200/r200_state_init.c,v 1.4 2003/02/22 06:21:11 dawes Exp $ */
3 Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
5 The Weather Channel (TM) funded Tungsten Graphics to develop the
6 initial release of the Radeon 8500 driver under the XFree86 license.
7 This notice must be preserved.
9 Permission is hereby granted, free of charge, to any person obtaining
10 a copy of this software and associated documentation files (the
11 "Software"), to deal in the Software without restriction, including
12 without limitation the rights to use, copy, modify, merge, publish,
13 distribute, sublicense, and/or sell copies of the Software, and to
14 permit persons to whom the Software is furnished to do so, subject to
15 the following conditions:
17 The above copyright notice and this permission notice (including the
18 next paragraph) shall be included in all copies or substantial
19 portions of the Software.
21 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
22 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
23 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
24 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
25 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
26 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
27 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
32 * Keith Whitwell <keith@tungstengraphics.com>
39 #include "api_arrayelt.h"
41 #include "swrast/swrast.h"
42 #include "array_cache/acache.h"
44 #include "tnl/t_pipeline.h"
45 #include "swrast_setup/swrast_setup.h"
47 #include "r200_context.h"
48 #include "r200_ioctl.h"
49 #include "r200_state.h"
52 #include "r200_swtcl.h"
53 #include "r200_vtxfmt.h"
57 /* =============================================================
58 * State initialization
61 void r200PrintDirty( r200ContextPtr rmesa
, const char *msg
)
63 struct r200_state_atom
*l
;
66 fprintf(stderr
, ": ");
68 foreach(l
, &(rmesa
->hw
.dirty
)) {
69 fprintf(stderr
, "%s, ", l
->name
);
72 fprintf(stderr
, "\n");
75 static int cmdpkt( int id
)
77 drm_radeon_cmd_header_t h
;
79 h
.packet
.cmd_type
= RADEON_CMD_PACKET
;
80 h
.packet
.packet_id
= id
;
84 static int cmdvec( int offset
, int stride
, int count
)
86 drm_radeon_cmd_header_t h
;
88 h
.vectors
.cmd_type
= RADEON_CMD_VECTORS
;
89 h
.vectors
.offset
= offset
;
90 h
.vectors
.stride
= stride
;
91 h
.vectors
.count
= count
;
95 static int cmdscl( int offset
, int stride
, int count
)
97 drm_radeon_cmd_header_t h
;
99 h
.scalars
.cmd_type
= RADEON_CMD_SCALARS
;
100 h
.scalars
.offset
= offset
;
101 h
.scalars
.stride
= stride
;
102 h
.scalars
.count
= count
;
106 static int cmdscl2( int offset
, int stride
, int count
)
108 drm_radeon_cmd_header_t h
;
110 h
.scalars
.cmd_type
= RADEON_CMD_SCALARS2
;
111 h
.scalars
.offset
= offset
- 0x100;
112 h
.scalars
.stride
= stride
;
113 h
.scalars
.count
= count
;
117 #define CHECK( NM, FLAG ) \
118 static GLboolean check_##NM( GLcontext *ctx, int idx ) \
124 #define TCL_CHECK( NM, FLAG ) \
125 static GLboolean check_##NM( GLcontext *ctx, int idx ) \
127 r200ContextPtr rmesa = R200_CONTEXT(ctx); \
129 return !rmesa->TclFallback && (FLAG); \
134 CHECK( always
, GL_TRUE
)
135 CHECK( never
, GL_FALSE
)
136 CHECK( tex_any
, ctx
->Texture
._EnabledUnits
)
137 CHECK( tex_pair
, (ctx
->Texture
.Unit
[idx
]._ReallyEnabled
| ctx
->Texture
.Unit
[idx
& ~1]._ReallyEnabled
))
138 CHECK( tex
, ctx
->Texture
.Unit
[idx
]._ReallyEnabled
)
139 CHECK( tex_cube
, ctx
->Texture
.Unit
[idx
]._ReallyEnabled
& TEXTURE_CUBE_BIT
)
140 CHECK( fog
, ctx
->Fog
.Enabled
)
141 TCL_CHECK( tcl
, GL_TRUE
)
142 TCL_CHECK( tcl_tex
, ctx
->Texture
.Unit
[idx
]._ReallyEnabled
)
143 TCL_CHECK( tcl_lighting
, ctx
->Light
.Enabled
)
144 TCL_CHECK( tcl_light
, ctx
->Light
.Enabled
&& ctx
->Light
.Light
[idx
].Enabled
)
145 TCL_CHECK( tcl_ucp
, (ctx
->Transform
.ClipPlanesEnabled
& (1 << idx
)) )
148 /* Initialize the context's hardware state.
150 void r200InitState( r200ContextPtr rmesa
)
152 GLcontext
*ctx
= rmesa
->glCtx
;
153 GLuint color_fmt
, depth_fmt
, i
;
155 switch ( rmesa
->r200Screen
->cpp
) {
157 color_fmt
= R200_COLOR_FORMAT_RGB565
;
160 color_fmt
= R200_COLOR_FORMAT_ARGB8888
;
163 fprintf( stderr
, "Error: Unsupported pixel depth... exiting\n" );
167 rmesa
->state
.color
.clear
= 0x00000000;
169 switch ( ctx
->Visual
.depthBits
) {
171 rmesa
->state
.depth
.scale
= 1.0 / (GLfloat
)0xffff;
172 depth_fmt
= R200_DEPTH_FORMAT_16BIT_INT_Z
;
173 rmesa
->state
.stencil
.clear
= 0x00000000;
176 rmesa
->state
.depth
.scale
= 1.0 / (GLfloat
)0xffffff;
177 depth_fmt
= R200_DEPTH_FORMAT_24BIT_INT_Z
;
178 rmesa
->state
.stencil
.clear
= 0xff000000;
181 fprintf( stderr
, "Error: Unsupported depth %d... exiting\n",
182 ctx
->Visual
.depthBits
);
186 /* Only have hw stencil when depth buffer is 24 bits deep */
187 rmesa
->state
.stencil
.hwBuffer
= ( ctx
->Visual
.stencilBits
> 0 &&
188 ctx
->Visual
.depthBits
== 24 );
192 if ( ctx
->Visual
.doubleBufferMode
&& rmesa
->sarea
->pfCurrentPage
== 0 ) {
193 rmesa
->state
.color
.drawOffset
= rmesa
->r200Screen
->backOffset
;
194 rmesa
->state
.color
.drawPitch
= rmesa
->r200Screen
->backPitch
;
196 rmesa
->state
.color
.drawOffset
= rmesa
->r200Screen
->frontOffset
;
197 rmesa
->state
.color
.drawPitch
= rmesa
->r200Screen
->frontPitch
;
200 rmesa
->state
.pixel
.readOffset
= rmesa
->state
.color
.drawOffset
;
201 rmesa
->state
.pixel
.readPitch
= rmesa
->state
.color
.drawPitch
;
205 make_empty_list(&(rmesa
->hw
.dirty
)); rmesa
->hw
.dirty
.name
= "DIRTY";
206 make_empty_list(&(rmesa
->hw
.clean
)); rmesa
->hw
.clean
.name
= "CLEAN";
208 rmesa
->hw
.max_state_size
= 0;
210 #define ALLOC_STATE( ATOM, CHK, SZ, NM, IDX ) \
212 rmesa->hw.ATOM.cmd_size = SZ; \
213 rmesa->hw.ATOM.cmd = (int *)CALLOC(SZ * sizeof(int)); \
214 rmesa->hw.ATOM.lastcmd = (int *)CALLOC(SZ * sizeof(int)); \
215 rmesa->hw.ATOM.name = NM; \
216 rmesa->hw.ATOM.idx = IDX; \
217 rmesa->hw.ATOM.check = check_##CHK; \
218 insert_at_head(&(rmesa->hw.dirty), &(rmesa->hw.ATOM)); \
219 rmesa->hw.max_state_size += SZ * sizeof(int); \
223 /* Allocate state buffers:
225 if (rmesa
->r200Screen
->drmSupportsBlendColor
)
226 ALLOC_STATE( ctx
, always
, CTX_STATE_SIZE_NEWDRM
, "CTX/context", 0 );
228 ALLOC_STATE( ctx
, always
, CTX_STATE_SIZE_OLDDRM
, "CTX/context", 0 );
229 ALLOC_STATE( set
, always
, SET_STATE_SIZE
, "SET/setup", 0 );
230 ALLOC_STATE( lin
, always
, LIN_STATE_SIZE
, "LIN/line", 0 );
231 ALLOC_STATE( msk
, always
, MSK_STATE_SIZE
, "MSK/mask", 0 );
232 ALLOC_STATE( vpt
, always
, VPT_STATE_SIZE
, "VPT/viewport", 0 );
233 ALLOC_STATE( vtx
, always
, VTX_STATE_SIZE
, "VTX/vertex", 0 );
234 ALLOC_STATE( vap
, always
, VAP_STATE_SIZE
, "VAP/vap", 0 );
235 ALLOC_STATE( vte
, always
, VTE_STATE_SIZE
, "VTE/vte", 0 );
236 ALLOC_STATE( msc
, always
, MSC_STATE_SIZE
, "MSC/misc", 0 );
237 ALLOC_STATE( cst
, always
, CST_STATE_SIZE
, "CST/constant", 0 );
238 ALLOC_STATE( zbs
, always
, ZBS_STATE_SIZE
, "ZBS/zbias", 0 );
239 ALLOC_STATE( tf
, tex_any
, TF_STATE_SIZE
, "TF/tfactor", 0 );
240 if (rmesa
->r200Screen
->chipset
& R200_CHIPSET_REAL_R200
) {
241 /* make sure texture units 0/1 are emitted pair-wise for r200 t0 hang workaround */
242 ALLOC_STATE( tex
[0], tex_pair
, TEX_STATE_SIZE
, "TEX/tex-0", 0 );
243 ALLOC_STATE( tex
[1], tex_pair
, TEX_STATE_SIZE
, "TEX/tex-1", 1 );
244 ALLOC_STATE( tam
, tex_any
, TAM_STATE_SIZE
, "TAM/tam", 0 );
247 ALLOC_STATE( tex
[0], tex
, TEX_STATE_SIZE
, "TEX/tex-0", 0 );
248 ALLOC_STATE( tex
[1], tex
, TEX_STATE_SIZE
, "TEX/tex-1", 1 );
249 ALLOC_STATE( tam
, never
, TAM_STATE_SIZE
, "TAM/tam", 0 );
251 ALLOC_STATE( tex
[2], tex
, TEX_STATE_SIZE
, "TEX/tex-2", 2 );
252 ALLOC_STATE( tex
[3], tex
, TEX_STATE_SIZE
, "TEX/tex-3", 3 );
253 ALLOC_STATE( tex
[4], tex
, TEX_STATE_SIZE
, "TEX/tex-4", 4 );
254 ALLOC_STATE( tex
[5], tex
, TEX_STATE_SIZE
, "TEX/tex-5", 5 );
255 if (rmesa
->r200Screen
->drmSupportsCubeMaps
) {
256 ALLOC_STATE( cube
[0], tex_cube
, CUBE_STATE_SIZE
, "CUBE/tex-0", 0 );
257 ALLOC_STATE( cube
[1], tex_cube
, CUBE_STATE_SIZE
, "CUBE/tex-1", 1 );
258 ALLOC_STATE( cube
[2], tex_cube
, CUBE_STATE_SIZE
, "CUBE/tex-2", 2 );
259 ALLOC_STATE( cube
[3], tex_cube
, CUBE_STATE_SIZE
, "CUBE/tex-3", 3 );
260 ALLOC_STATE( cube
[4], tex_cube
, CUBE_STATE_SIZE
, "CUBE/tex-4", 4 );
261 ALLOC_STATE( cube
[5], tex_cube
, CUBE_STATE_SIZE
, "CUBE/tex-5", 5 );
264 ALLOC_STATE( cube
[0], never
, CUBE_STATE_SIZE
, "CUBE/tex-0", 0 );
265 ALLOC_STATE( cube
[1], never
, CUBE_STATE_SIZE
, "CUBE/tex-1", 1 );
266 ALLOC_STATE( cube
[2], never
, CUBE_STATE_SIZE
, "CUBE/tex-2", 2 );
267 ALLOC_STATE( cube
[3], never
, CUBE_STATE_SIZE
, "CUBE/tex-3", 3 );
268 ALLOC_STATE( cube
[4], never
, CUBE_STATE_SIZE
, "CUBE/tex-4", 4 );
269 ALLOC_STATE( cube
[5], never
, CUBE_STATE_SIZE
, "CUBE/tex-5", 5 );
272 ALLOC_STATE( tcl
, tcl
, TCL_STATE_SIZE
, "TCL/tcl", 0 );
273 ALLOC_STATE( msl
, tcl
, MSL_STATE_SIZE
, "MSL/matrix-select", 0 );
274 ALLOC_STATE( tcg
, tcl
, TCG_STATE_SIZE
, "TCG/texcoordgen", 0 );
275 ALLOC_STATE( mtl
[0], tcl_lighting
, MTL_STATE_SIZE
, "MTL0/material0", 0 );
276 ALLOC_STATE( mtl
[1], tcl_lighting
, MTL_STATE_SIZE
, "MTL1/material1", 1 );
277 ALLOC_STATE( grd
, tcl
, GRD_STATE_SIZE
, "GRD/guard-band", 0 );
278 ALLOC_STATE( fog
, fog
, FOG_STATE_SIZE
, "FOG/fog", 0 );
279 ALLOC_STATE( glt
, tcl_lighting
, GLT_STATE_SIZE
, "GLT/light-global", 0 );
280 ALLOC_STATE( eye
, tcl_lighting
, EYE_STATE_SIZE
, "EYE/eye-vector", 0 );
281 ALLOC_STATE( mat
[R200_MTX_MV
], tcl
, MAT_STATE_SIZE
, "MAT/modelview", 0 );
282 ALLOC_STATE( mat
[R200_MTX_IMV
], tcl
, MAT_STATE_SIZE
, "MAT/it-modelview", 0 );
283 ALLOC_STATE( mat
[R200_MTX_MVP
], tcl
, MAT_STATE_SIZE
, "MAT/modelproject", 0 );
284 ALLOC_STATE( mat
[R200_MTX_TEX0
], tcl_tex
, MAT_STATE_SIZE
, "MAT/texmat0", 0 );
285 ALLOC_STATE( mat
[R200_MTX_TEX1
], tcl_tex
, MAT_STATE_SIZE
, "MAT/texmat1", 1 );
286 ALLOC_STATE( mat
[R200_MTX_TEX2
], tcl_tex
, MAT_STATE_SIZE
, "MAT/texmat2", 2 );
287 ALLOC_STATE( mat
[R200_MTX_TEX3
], tcl_tex
, MAT_STATE_SIZE
, "MAT/texmat3", 3 );
288 ALLOC_STATE( mat
[R200_MTX_TEX4
], tcl_tex
, MAT_STATE_SIZE
, "MAT/texmat4", 4 );
289 ALLOC_STATE( mat
[R200_MTX_TEX5
], tcl_tex
, MAT_STATE_SIZE
, "MAT/texmat5", 5 );
290 ALLOC_STATE( ucp
[0], tcl_ucp
, UCP_STATE_SIZE
, "UCP/userclip-0", 0 );
291 ALLOC_STATE( ucp
[1], tcl_ucp
, UCP_STATE_SIZE
, "UCP/userclip-1", 1 );
292 ALLOC_STATE( ucp
[2], tcl_ucp
, UCP_STATE_SIZE
, "UCP/userclip-2", 2 );
293 ALLOC_STATE( ucp
[3], tcl_ucp
, UCP_STATE_SIZE
, "UCP/userclip-3", 3 );
294 ALLOC_STATE( ucp
[4], tcl_ucp
, UCP_STATE_SIZE
, "UCP/userclip-4", 4 );
295 ALLOC_STATE( ucp
[5], tcl_ucp
, UCP_STATE_SIZE
, "UCP/userclip-5", 5 );
296 ALLOC_STATE( lit
[0], tcl_light
, LIT_STATE_SIZE
, "LIT/light-0", 0 );
297 ALLOC_STATE( lit
[1], tcl_light
, LIT_STATE_SIZE
, "LIT/light-1", 1 );
298 ALLOC_STATE( lit
[2], tcl_light
, LIT_STATE_SIZE
, "LIT/light-2", 2 );
299 ALLOC_STATE( lit
[3], tcl_light
, LIT_STATE_SIZE
, "LIT/light-3", 3 );
300 ALLOC_STATE( lit
[4], tcl_light
, LIT_STATE_SIZE
, "LIT/light-4", 4 );
301 ALLOC_STATE( lit
[5], tcl_light
, LIT_STATE_SIZE
, "LIT/light-5", 5 );
302 ALLOC_STATE( lit
[6], tcl_light
, LIT_STATE_SIZE
, "LIT/light-6", 6 );
303 ALLOC_STATE( lit
[7], tcl_light
, LIT_STATE_SIZE
, "LIT/light-7", 7 );
304 ALLOC_STATE( pix
[0], always
, PIX_STATE_SIZE
, "PIX/pixstage-0", 0 );
305 ALLOC_STATE( pix
[1], tex
, PIX_STATE_SIZE
, "PIX/pixstage-1", 1 );
306 ALLOC_STATE( pix
[2], tex
, PIX_STATE_SIZE
, "PIX/pixstage-2", 2 );
307 ALLOC_STATE( pix
[3], tex
, PIX_STATE_SIZE
, "PIX/pixstage-3", 3 );
308 ALLOC_STATE( pix
[4], tex
, PIX_STATE_SIZE
, "PIX/pixstage-4", 4 );
309 ALLOC_STATE( pix
[5], tex
, PIX_STATE_SIZE
, "PIX/pixstage-5", 5 );
312 /* Fill in the packet headers:
314 rmesa
->hw
.ctx
.cmd
[CTX_CMD_0
] = cmdpkt(RADEON_EMIT_PP_MISC
);
315 rmesa
->hw
.ctx
.cmd
[CTX_CMD_1
] = cmdpkt(RADEON_EMIT_PP_CNTL
);
316 rmesa
->hw
.ctx
.cmd
[CTX_CMD_2
] = cmdpkt(RADEON_EMIT_RB3D_COLORPITCH
);
317 if (rmesa
->r200Screen
->drmSupportsBlendColor
)
318 rmesa
->hw
.ctx
.cmd
[CTX_CMD_3
] = cmdpkt(R200_EMIT_RB3D_BLENDCOLOR
);
319 rmesa
->hw
.lin
.cmd
[LIN_CMD_0
] = cmdpkt(RADEON_EMIT_RE_LINE_PATTERN
);
320 rmesa
->hw
.lin
.cmd
[LIN_CMD_1
] = cmdpkt(RADEON_EMIT_SE_LINE_WIDTH
);
321 rmesa
->hw
.msk
.cmd
[MSK_CMD_0
] = cmdpkt(RADEON_EMIT_RB3D_STENCILREFMASK
);
322 rmesa
->hw
.vpt
.cmd
[VPT_CMD_0
] = cmdpkt(RADEON_EMIT_SE_VPORT_XSCALE
);
323 rmesa
->hw
.set
.cmd
[SET_CMD_0
] = cmdpkt(RADEON_EMIT_SE_CNTL
);
324 rmesa
->hw
.msc
.cmd
[MSC_CMD_0
] = cmdpkt(RADEON_EMIT_RE_MISC
);
325 rmesa
->hw
.cst
.cmd
[CST_CMD_0
] = cmdpkt(R200_EMIT_PP_CNTL_X
);
326 rmesa
->hw
.cst
.cmd
[CST_CMD_1
] = cmdpkt(R200_EMIT_RB3D_DEPTHXY_OFFSET
);
327 rmesa
->hw
.cst
.cmd
[CST_CMD_2
] = cmdpkt(R200_EMIT_RE_AUX_SCISSOR_CNTL
);
328 rmesa
->hw
.cst
.cmd
[CST_CMD_3
] = cmdpkt(R200_EMIT_RE_SCISSOR_TL_0
);
329 rmesa
->hw
.cst
.cmd
[CST_CMD_4
] = cmdpkt(R200_EMIT_SE_VAP_CNTL_STATUS
);
330 rmesa
->hw
.cst
.cmd
[CST_CMD_5
] = cmdpkt(R200_EMIT_RE_POINTSIZE
);
331 rmesa
->hw
.cst
.cmd
[CST_CMD_6
] = cmdpkt(R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0
);
332 rmesa
->hw
.tam
.cmd
[TAM_CMD_0
] = cmdpkt(R200_EMIT_PP_TAM_DEBUG3
);
333 rmesa
->hw
.tf
.cmd
[TF_CMD_0
] = cmdpkt(R200_EMIT_TFACTOR_0
);
334 rmesa
->hw
.tex
[0].cmd
[TEX_CMD_0
] = cmdpkt(R200_EMIT_PP_TXFILTER_0
);
335 rmesa
->hw
.tex
[0].cmd
[TEX_CMD_1
] = cmdpkt(R200_EMIT_PP_TXOFFSET_0
);
336 rmesa
->hw
.tex
[1].cmd
[TEX_CMD_0
] = cmdpkt(R200_EMIT_PP_TXFILTER_1
);
337 rmesa
->hw
.tex
[1].cmd
[TEX_CMD_1
] = cmdpkt(R200_EMIT_PP_TXOFFSET_1
);
338 rmesa
->hw
.tex
[2].cmd
[TEX_CMD_0
] = cmdpkt(R200_EMIT_PP_TXFILTER_2
);
339 rmesa
->hw
.tex
[2].cmd
[TEX_CMD_1
] = cmdpkt(R200_EMIT_PP_TXOFFSET_2
);
340 rmesa
->hw
.tex
[3].cmd
[TEX_CMD_0
] = cmdpkt(R200_EMIT_PP_TXFILTER_3
);
341 rmesa
->hw
.tex
[3].cmd
[TEX_CMD_1
] = cmdpkt(R200_EMIT_PP_TXOFFSET_3
);
342 rmesa
->hw
.tex
[4].cmd
[TEX_CMD_0
] = cmdpkt(R200_EMIT_PP_TXFILTER_4
);
343 rmesa
->hw
.tex
[4].cmd
[TEX_CMD_1
] = cmdpkt(R200_EMIT_PP_TXOFFSET_4
);
344 rmesa
->hw
.tex
[5].cmd
[TEX_CMD_0
] = cmdpkt(R200_EMIT_PP_TXFILTER_5
);
345 rmesa
->hw
.tex
[5].cmd
[TEX_CMD_1
] = cmdpkt(R200_EMIT_PP_TXOFFSET_5
);
346 rmesa
->hw
.cube
[0].cmd
[CUBE_CMD_0
] = cmdpkt(R200_EMIT_PP_CUBIC_FACES_0
);
347 rmesa
->hw
.cube
[0].cmd
[CUBE_CMD_1
] = cmdpkt(R200_EMIT_PP_CUBIC_OFFSETS_0
);
348 rmesa
->hw
.cube
[1].cmd
[CUBE_CMD_0
] = cmdpkt(R200_EMIT_PP_CUBIC_FACES_1
);
349 rmesa
->hw
.cube
[1].cmd
[CUBE_CMD_1
] = cmdpkt(R200_EMIT_PP_CUBIC_OFFSETS_1
);
350 rmesa
->hw
.cube
[2].cmd
[CUBE_CMD_0
] = cmdpkt(R200_EMIT_PP_CUBIC_FACES_2
);
351 rmesa
->hw
.cube
[2].cmd
[CUBE_CMD_1
] = cmdpkt(R200_EMIT_PP_CUBIC_OFFSETS_2
);
352 rmesa
->hw
.cube
[3].cmd
[CUBE_CMD_0
] = cmdpkt(R200_EMIT_PP_CUBIC_FACES_3
);
353 rmesa
->hw
.cube
[3].cmd
[CUBE_CMD_1
] = cmdpkt(R200_EMIT_PP_CUBIC_OFFSETS_3
);
354 rmesa
->hw
.cube
[4].cmd
[CUBE_CMD_0
] = cmdpkt(R200_EMIT_PP_CUBIC_FACES_4
);
355 rmesa
->hw
.cube
[4].cmd
[CUBE_CMD_1
] = cmdpkt(R200_EMIT_PP_CUBIC_OFFSETS_4
);
356 rmesa
->hw
.cube
[5].cmd
[CUBE_CMD_0
] = cmdpkt(R200_EMIT_PP_CUBIC_FACES_5
);
357 rmesa
->hw
.cube
[5].cmd
[CUBE_CMD_1
] = cmdpkt(R200_EMIT_PP_CUBIC_OFFSETS_5
);
358 rmesa
->hw
.pix
[0].cmd
[PIX_CMD_0
] = cmdpkt(R200_EMIT_PP_TXCBLEND_0
);
359 rmesa
->hw
.pix
[1].cmd
[PIX_CMD_0
] = cmdpkt(R200_EMIT_PP_TXCBLEND_1
);
360 rmesa
->hw
.pix
[2].cmd
[PIX_CMD_0
] = cmdpkt(R200_EMIT_PP_TXCBLEND_2
);
361 rmesa
->hw
.pix
[3].cmd
[PIX_CMD_0
] = cmdpkt(R200_EMIT_PP_TXCBLEND_3
);
362 rmesa
->hw
.pix
[4].cmd
[PIX_CMD_0
] = cmdpkt(R200_EMIT_PP_TXCBLEND_4
);
363 rmesa
->hw
.pix
[5].cmd
[PIX_CMD_0
] = cmdpkt(R200_EMIT_PP_TXCBLEND_5
);
364 rmesa
->hw
.zbs
.cmd
[ZBS_CMD_0
] = cmdpkt(RADEON_EMIT_SE_ZBIAS_FACTOR
);
365 rmesa
->hw
.tcl
.cmd
[TCL_CMD_0
] = cmdpkt(R200_EMIT_TCL_LIGHT_MODEL_CTL_0
);
366 rmesa
->hw
.tcl
.cmd
[TCL_CMD_1
] = cmdpkt(R200_EMIT_TCL_UCP_VERT_BLEND_CTL
);
367 rmesa
->hw
.tcg
.cmd
[TCG_CMD_0
] = cmdpkt(R200_EMIT_TEX_PROC_CTL_2
);
368 rmesa
->hw
.msl
.cmd
[MSL_CMD_0
] = cmdpkt(R200_EMIT_MATRIX_SELECT_0
);
369 rmesa
->hw
.vap
.cmd
[VAP_CMD_0
] = cmdpkt(R200_EMIT_VAP_CTL
);
370 rmesa
->hw
.vtx
.cmd
[VTX_CMD_0
] = cmdpkt(R200_EMIT_VTX_FMT_0
);
371 rmesa
->hw
.vtx
.cmd
[VTX_CMD_1
] = cmdpkt(R200_EMIT_OUTPUT_VTX_COMP_SEL
);
372 rmesa
->hw
.vtx
.cmd
[VTX_CMD_2
] = cmdpkt(R200_EMIT_SE_VTX_STATE_CNTL
);
373 rmesa
->hw
.vte
.cmd
[VTE_CMD_0
] = cmdpkt(R200_EMIT_VTE_CNTL
);
374 rmesa
->hw
.mtl
[0].cmd
[MTL_CMD_0
] =
375 cmdvec( R200_VS_MAT_0_EMISS
, 1, 16 );
376 rmesa
->hw
.mtl
[0].cmd
[MTL_CMD_1
] =
377 cmdscl2( R200_SS_MAT_0_SHININESS
, 1, 1 );
378 rmesa
->hw
.mtl
[1].cmd
[MTL_CMD_0
] =
379 cmdvec( R200_VS_MAT_1_EMISS
, 1, 16 );
380 rmesa
->hw
.mtl
[1].cmd
[MTL_CMD_1
] =
381 cmdscl2( R200_SS_MAT_1_SHININESS
, 1, 1 );
383 rmesa
->hw
.grd
.cmd
[GRD_CMD_0
] =
384 cmdscl( R200_SS_VERT_GUARD_CLIP_ADJ_ADDR
, 1, 4 );
385 rmesa
->hw
.fog
.cmd
[FOG_CMD_0
] =
386 cmdvec( R200_VS_FOG_PARAM_ADDR
, 1, 4 );
387 rmesa
->hw
.glt
.cmd
[GLT_CMD_0
] =
388 cmdvec( R200_VS_GLOBAL_AMBIENT_ADDR
, 1, 4 );
389 rmesa
->hw
.eye
.cmd
[EYE_CMD_0
] =
390 cmdvec( R200_VS_EYE_VECTOR_ADDR
, 1, 4 );
392 rmesa
->hw
.mat
[R200_MTX_MV
].cmd
[MAT_CMD_0
] =
393 cmdvec( R200_VS_MATRIX_0_MV
, 1, 16);
394 rmesa
->hw
.mat
[R200_MTX_IMV
].cmd
[MAT_CMD_0
] =
395 cmdvec( R200_VS_MATRIX_1_INV_MV
, 1, 16);
396 rmesa
->hw
.mat
[R200_MTX_MVP
].cmd
[MAT_CMD_0
] =
397 cmdvec( R200_VS_MATRIX_2_MVP
, 1, 16);
398 rmesa
->hw
.mat
[R200_MTX_TEX0
].cmd
[MAT_CMD_0
] =
399 cmdvec( R200_VS_MATRIX_3_TEX0
, 1, 16);
400 rmesa
->hw
.mat
[R200_MTX_TEX1
].cmd
[MAT_CMD_0
] =
401 cmdvec( R200_VS_MATRIX_4_TEX1
, 1, 16);
402 rmesa
->hw
.mat
[R200_MTX_TEX2
].cmd
[MAT_CMD_0
] =
403 cmdvec( R200_VS_MATRIX_5_TEX2
, 1, 16);
404 rmesa
->hw
.mat
[R200_MTX_TEX3
].cmd
[MAT_CMD_0
] =
405 cmdvec( R200_VS_MATRIX_6_TEX3
, 1, 16);
406 rmesa
->hw
.mat
[R200_MTX_TEX4
].cmd
[MAT_CMD_0
] =
407 cmdvec( R200_VS_MATRIX_7_TEX4
, 1, 16);
408 rmesa
->hw
.mat
[R200_MTX_TEX5
].cmd
[MAT_CMD_0
] =
409 cmdvec( R200_VS_MATRIX_8_TEX5
, 1, 16);
411 for (i
= 0 ; i
< 8; i
++) {
412 rmesa
->hw
.lit
[i
].cmd
[LIT_CMD_0
] =
413 cmdvec( R200_VS_LIGHT_AMBIENT_ADDR
+ i
, 8, 24 );
414 rmesa
->hw
.lit
[i
].cmd
[LIT_CMD_1
] =
415 cmdscl( R200_SS_LIGHT_DCD_ADDR
+ i
, 8, 7 );
418 for (i
= 0 ; i
< 6; i
++) {
419 rmesa
->hw
.ucp
[i
].cmd
[UCP_CMD_0
] =
420 cmdvec( R200_VS_UCP_ADDR
+ i
, 1, 4 );
423 /* Initial Harware state:
425 rmesa
->hw
.ctx
.cmd
[CTX_PP_MISC
] = (R200_ALPHA_TEST_PASS
426 /* | R200_RIGHT_HAND_CUBE_OGL*/);
428 rmesa
->hw
.ctx
.cmd
[CTX_PP_FOG_COLOR
] = (R200_FOG_VERTEX
|
429 R200_FOG_USE_SPEC_ALPHA
);
431 rmesa
->hw
.ctx
.cmd
[CTX_RE_SOLID_COLOR
] = 0x00000000;
433 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_BLENDCNTL
] = (R200_COMB_FCN_ADD_CLAMP
|
434 (R200_BLEND_GL_ONE
<< R200_SRC_BLEND_SHIFT
) |
435 (R200_BLEND_GL_ZERO
<< R200_DST_BLEND_SHIFT
));
437 if (rmesa
->r200Screen
->drmSupportsBlendColor
) {
438 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_BLENDCOLOR
] = 0x00000000;
439 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ABLENDCNTL
] = (R200_COMB_FCN_ADD_CLAMP
|
440 (R200_BLEND_GL_ONE
<< R200_SRC_BLEND_SHIFT
) |
441 (R200_BLEND_GL_ZERO
<< R200_DST_BLEND_SHIFT
));
442 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_CBLENDCNTL
] = (R200_COMB_FCN_ADD_CLAMP
|
443 (R200_BLEND_GL_ONE
<< R200_SRC_BLEND_SHIFT
) |
444 (R200_BLEND_GL_ZERO
<< R200_DST_BLEND_SHIFT
));
447 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_DEPTHOFFSET
] =
448 rmesa
->r200Screen
->depthOffset
+ rmesa
->r200Screen
->fbLocation
;
450 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_DEPTHPITCH
] =
451 ((rmesa
->r200Screen
->depthPitch
&
452 R200_DEPTHPITCH_MASK
) |
453 R200_DEPTH_ENDIAN_NO_SWAP
);
455 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] = (depth_fmt
|
457 R200_STENCIL_TEST_ALWAYS
|
458 R200_STENCIL_FAIL_KEEP
|
459 R200_STENCIL_ZPASS_KEEP
|
460 R200_STENCIL_ZFAIL_KEEP
|
461 R200_Z_WRITE_ENABLE
);
463 rmesa
->hw
.ctx
.cmd
[CTX_PP_CNTL
] = (R200_ANTI_ALIAS_NONE
464 | R200_TEX_BLEND_0_ENABLE
);
466 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_CNTL
] = color_fmt
;
467 switch ( driQueryOptioni( &rmesa
->optionCache
, "dither_mode" ) ) {
468 case DRI_CONF_DITHER_XERRORDIFFRESET
:
469 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_CNTL
] |= R200_DITHER_INIT
;
471 case DRI_CONF_DITHER_ORDERED
:
472 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_CNTL
] |= R200_SCALE_DITHER_ENABLE
;
475 if ( driQueryOptioni( &rmesa
->optionCache
, "round_mode" ) ==
476 DRI_CONF_ROUND_ROUND
)
477 rmesa
->state
.color
.roundEnable
= R200_ROUND_ENABLE
;
479 rmesa
->state
.color
.roundEnable
= 0;
480 if ( driQueryOptioni (&rmesa
->optionCache
, "color_reduction" ) ==
481 DRI_CONF_COLOR_REDUCTION_DITHER
)
482 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_CNTL
] |= R200_DITHER_ENABLE
;
484 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_CNTL
] |= rmesa
->state
.color
.roundEnable
;
486 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_COLOROFFSET
] = ((rmesa
->state
.color
.drawOffset
+
487 rmesa
->r200Screen
->fbLocation
)
488 & R200_COLOROFFSET_MASK
);
490 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_COLORPITCH
] = ((rmesa
->state
.color
.drawPitch
&
491 R200_COLORPITCH_MASK
) |
492 R200_COLOR_ENDIAN_NO_SWAP
);
494 rmesa
->hw
.set
.cmd
[SET_SE_CNTL
] = (R200_FFACE_CULL_CCW
|
497 R200_FLAT_SHADE_VTX_LAST
|
498 R200_DIFFUSE_SHADE_GOURAUD
|
499 R200_ALPHA_SHADE_GOURAUD
|
500 R200_SPECULAR_SHADE_GOURAUD
|
501 R200_FOG_SHADE_GOURAUD
|
502 R200_VTX_PIX_CENTER_OGL
|
503 R200_ROUND_MODE_TRUNC
|
504 R200_ROUND_PREC_8TH_PIX
);
506 rmesa
->hw
.set
.cmd
[SET_RE_CNTL
] = (R200_PERSPECTIVE_ENABLE
|
507 R200_SCISSOR_ENABLE
);
509 rmesa
->hw
.lin
.cmd
[LIN_RE_LINE_PATTERN
] = ((1 << 16) | 0xffff);
511 rmesa
->hw
.lin
.cmd
[LIN_RE_LINE_STATE
] =
512 ((0 << R200_LINE_CURRENT_PTR_SHIFT
) |
513 (1 << R200_LINE_CURRENT_COUNT_SHIFT
));
515 rmesa
->hw
.lin
.cmd
[LIN_SE_LINE_WIDTH
] = (1 << 4);
517 rmesa
->hw
.msk
.cmd
[MSK_RB3D_STENCILREFMASK
] =
518 ((0x00 << R200_STENCIL_REF_SHIFT
) |
519 (0xff << R200_STENCIL_MASK_SHIFT
) |
520 (0xff << R200_STENCIL_WRITEMASK_SHIFT
));
522 rmesa
->hw
.msk
.cmd
[MSK_RB3D_ROPCNTL
] = R200_ROP_COPY
;
523 rmesa
->hw
.msk
.cmd
[MSK_RB3D_PLANEMASK
] = 0xffffffff;
525 rmesa
->hw
.tam
.cmd
[TAM_DEBUG3
] = 0;
527 rmesa
->hw
.msc
.cmd
[MSC_RE_MISC
] =
528 ((0 << R200_STIPPLE_X_OFFSET_SHIFT
) |
529 (0 << R200_STIPPLE_Y_OFFSET_SHIFT
) |
530 R200_STIPPLE_BIG_BIT_ORDER
);
533 rmesa
->hw
.cst
.cmd
[CST_PP_CNTL_X
] = 0;
534 rmesa
->hw
.cst
.cmd
[CST_RB3D_DEPTHXY_OFFSET
] = 0;
535 rmesa
->hw
.cst
.cmd
[CST_RE_AUX_SCISSOR_CNTL
] = 0x0;
536 rmesa
->hw
.cst
.cmd
[CST_RE_SCISSOR_TL_0
] = 0;
537 rmesa
->hw
.cst
.cmd
[CST_RE_SCISSOR_BR_0
] = 0;
538 rmesa
->hw
.cst
.cmd
[CST_SE_VAP_CNTL_STATUS
] =
539 #ifdef MESA_BIG_ENDIAN
545 if (!(rmesa
->r200Screen
->chipset
& R200_CHIPSET_TCL
)) {
547 rmesa
->hw
.cst
.cmd
[CST_SE_VAP_CNTL_STATUS
] |= (1<<8);
550 rmesa
->hw
.cst
.cmd
[CST_RE_POINTSIZE
] = 0x100010;
551 rmesa
->hw
.cst
.cmd
[CST_SE_TCL_INPUT_VTX_0
] =
552 (0x0 << R200_VERTEX_POSITION_ADDR__SHIFT
);
553 rmesa
->hw
.cst
.cmd
[CST_SE_TCL_INPUT_VTX_1
] =
554 (0x02 << R200_VTX_COLOR_0_ADDR__SHIFT
) |
555 (0x03 << R200_VTX_COLOR_1_ADDR__SHIFT
);
556 rmesa
->hw
.cst
.cmd
[CST_SE_TCL_INPUT_VTX_2
] =
557 (0x06 << R200_VTX_TEX_0_ADDR__SHIFT
) |
558 (0x07 << R200_VTX_TEX_1_ADDR__SHIFT
) |
559 (0x08 << R200_VTX_TEX_2_ADDR__SHIFT
) |
560 (0x09 << R200_VTX_TEX_3_ADDR__SHIFT
);
561 rmesa
->hw
.cst
.cmd
[CST_SE_TCL_INPUT_VTX_3
] =
562 (0x0A << R200_VTX_TEX_4_ADDR__SHIFT
) |
563 (0x0B << R200_VTX_TEX_5_ADDR__SHIFT
);
566 rmesa
->hw
.vpt
.cmd
[VPT_SE_VPORT_XSCALE
] = 0x00000000;
567 rmesa
->hw
.vpt
.cmd
[VPT_SE_VPORT_XOFFSET
] = 0x00000000;
568 rmesa
->hw
.vpt
.cmd
[VPT_SE_VPORT_YSCALE
] = 0x00000000;
569 rmesa
->hw
.vpt
.cmd
[VPT_SE_VPORT_YOFFSET
] = 0x00000000;
570 rmesa
->hw
.vpt
.cmd
[VPT_SE_VPORT_ZSCALE
] = 0x00000000;
571 rmesa
->hw
.vpt
.cmd
[VPT_SE_VPORT_ZOFFSET
] = 0x00000000;
573 for ( i
= 0 ; i
< ctx
->Const
.MaxTextureUnits
; i
++ ) {
574 rmesa
->hw
.tex
[i
].cmd
[TEX_PP_TXFILTER
] = R200_BORDER_MODE_OGL
;
575 rmesa
->hw
.tex
[i
].cmd
[TEX_PP_TXFORMAT
] =
576 ((i
<< R200_TXFORMAT_ST_ROUTE_SHIFT
) | /* <-- note i */
577 (2 << R200_TXFORMAT_WIDTH_SHIFT
) |
578 (2 << R200_TXFORMAT_HEIGHT_SHIFT
));
579 rmesa
->hw
.tex
[i
].cmd
[TEX_PP_TXOFFSET
] =
580 rmesa
->r200Screen
->texOffset
[RADEON_LOCAL_TEX_HEAP
];
581 rmesa
->hw
.tex
[i
].cmd
[TEX_PP_BORDER_COLOR
] = 0;
582 rmesa
->hw
.tex
[i
].cmd
[TEX_PP_TXFORMAT_X
] =
583 (/* R200_TEXCOORD_PROJ | */
584 0x100000); /* Small default bias */
586 rmesa
->hw
.cube
[i
].cmd
[CUBE_PP_CUBIC_FACES
] = 0;
587 rmesa
->hw
.cube
[i
].cmd
[CUBE_PP_CUBIC_OFFSET_F1
] =
588 rmesa
->r200Screen
->texOffset
[RADEON_LOCAL_TEX_HEAP
];
589 rmesa
->hw
.cube
[i
].cmd
[CUBE_PP_CUBIC_OFFSET_F2
] =
590 rmesa
->r200Screen
->texOffset
[RADEON_LOCAL_TEX_HEAP
];
591 rmesa
->hw
.cube
[i
].cmd
[CUBE_PP_CUBIC_OFFSET_F3
] =
592 rmesa
->r200Screen
->texOffset
[RADEON_LOCAL_TEX_HEAP
];
593 rmesa
->hw
.cube
[i
].cmd
[CUBE_PP_CUBIC_OFFSET_F4
] =
594 rmesa
->r200Screen
->texOffset
[RADEON_LOCAL_TEX_HEAP
];
595 rmesa
->hw
.cube
[i
].cmd
[CUBE_PP_CUBIC_OFFSET_F5
] =
596 rmesa
->r200Screen
->texOffset
[RADEON_LOCAL_TEX_HEAP
];
598 rmesa
->hw
.pix
[i
].cmd
[PIX_PP_TXCBLEND
] =
599 (R200_TXC_ARG_A_ZERO
|
600 R200_TXC_ARG_B_ZERO
|
601 R200_TXC_ARG_C_DIFFUSE_COLOR
|
604 rmesa
->hw
.pix
[i
].cmd
[PIX_PP_TXCBLEND2
] =
605 ((i
<< R200_TXC_TFACTOR_SEL_SHIFT
) |
608 R200_TXC_OUTPUT_REG_R0
);
610 rmesa
->hw
.pix
[i
].cmd
[PIX_PP_TXABLEND
] =
611 (R200_TXA_ARG_A_ZERO
|
612 R200_TXA_ARG_B_ZERO
|
613 R200_TXA_ARG_C_DIFFUSE_ALPHA
|
616 rmesa
->hw
.pix
[i
].cmd
[PIX_PP_TXABLEND2
] =
617 ((i
<< R200_TXA_TFACTOR_SEL_SHIFT
) |
620 R200_TXA_OUTPUT_REG_R0
);
623 rmesa
->hw
.tf
.cmd
[TF_TFACTOR_0
] = 0;
624 rmesa
->hw
.tf
.cmd
[TF_TFACTOR_1
] = 0;
625 rmesa
->hw
.tf
.cmd
[TF_TFACTOR_2
] = 0;
626 rmesa
->hw
.tf
.cmd
[TF_TFACTOR_3
] = 0;
627 rmesa
->hw
.tf
.cmd
[TF_TFACTOR_4
] = 0;
628 rmesa
->hw
.tf
.cmd
[TF_TFACTOR_5
] = 0;
630 rmesa
->hw
.vap
.cmd
[VAP_SE_VAP_CNTL
] =
631 (R200_VAP_TCL_ENABLE
|
632 (0x9 << R200_VAP_VF_MAX_VTX_NUM__SHIFT
));
634 rmesa
->hw
.vte
.cmd
[VTE_SE_VTE_CNTL
] =
635 (R200_VPORT_X_SCALE_ENA
|
636 R200_VPORT_Y_SCALE_ENA
|
637 R200_VPORT_Z_SCALE_ENA
|
638 R200_VPORT_X_OFFSET_ENA
|
639 R200_VPORT_Y_OFFSET_ENA
|
640 R200_VPORT_Z_OFFSET_ENA
|
641 /* FIXME: Turn on for tex rect only */
642 R200_VTX_ST_DENORMALIZED
|
646 rmesa
->hw
.vtx
.cmd
[VTX_VTXFMT_0
] = 0;
647 rmesa
->hw
.vtx
.cmd
[VTX_VTXFMT_1
] = 0;
648 rmesa
->hw
.vtx
.cmd
[VTX_TCL_OUTPUT_VTXFMT_0
] =
649 ((R200_VTX_Z0
| R200_VTX_W0
|
650 (R200_VTX_FP_RGBA
<< R200_VTX_COLOR_0_SHIFT
)));
651 rmesa
->hw
.vtx
.cmd
[VTX_TCL_OUTPUT_VTXFMT_1
] = 0;
652 rmesa
->hw
.vtx
.cmd
[VTX_TCL_OUTPUT_COMPSEL
] = (R200_OUTPUT_XYZW
);
653 rmesa
->hw
.vtx
.cmd
[VTX_STATE_CNTL
] = R200_VSC_UPDATE_USER_COLOR_0_ENABLE
;
656 /* Matrix selection */
657 rmesa
->hw
.msl
.cmd
[MSL_MATRIX_SELECT_0
] =
658 (R200_MTX_MV
<< R200_MODELVIEW_0_SHIFT
);
660 rmesa
->hw
.msl
.cmd
[MSL_MATRIX_SELECT_1
] =
661 (R200_MTX_IMV
<< R200_IT_MODELVIEW_0_SHIFT
);
663 rmesa
->hw
.msl
.cmd
[MSL_MATRIX_SELECT_2
] =
664 (R200_MTX_MVP
<< R200_MODELPROJECT_0_SHIFT
);
666 rmesa
->hw
.msl
.cmd
[MSL_MATRIX_SELECT_3
] =
667 ((R200_MTX_TEX0
<< R200_TEXMAT_0_SHIFT
) |
668 (R200_MTX_TEX1
<< R200_TEXMAT_1_SHIFT
) |
669 (R200_MTX_TEX2
<< R200_TEXMAT_2_SHIFT
) |
670 (R200_MTX_TEX3
<< R200_TEXMAT_3_SHIFT
));
672 rmesa
->hw
.msl
.cmd
[MSL_MATRIX_SELECT_4
] =
673 ((R200_MTX_TEX4
<< R200_TEXMAT_4_SHIFT
) |
674 (R200_MTX_TEX5
<< R200_TEXMAT_5_SHIFT
));
677 /* General TCL state */
678 rmesa
->hw
.tcl
.cmd
[TCL_LIGHT_MODEL_CTL_0
] =
679 (R200_SPECULAR_LIGHTS
|
680 R200_DIFFUSE_SPECULAR_COMBINE
|
681 R200_LOCAL_LIGHT_VEC_GL
|
682 R200_LM0_SOURCE_MATERIAL_0
<< R200_FRONT_SHININESS_SOURCE_SHIFT
|
683 R200_LM0_SOURCE_MATERIAL_1
<< R200_BACK_SHININESS_SOURCE_SHIFT
);
685 rmesa
->hw
.tcl
.cmd
[TCL_LIGHT_MODEL_CTL_1
] =
686 ((R200_LM1_SOURCE_MATERIAL_0
<< R200_FRONT_EMISSIVE_SOURCE_SHIFT
) |
687 (R200_LM1_SOURCE_MATERIAL_0
<< R200_FRONT_AMBIENT_SOURCE_SHIFT
) |
688 (R200_LM1_SOURCE_MATERIAL_0
<< R200_FRONT_DIFFUSE_SOURCE_SHIFT
) |
689 (R200_LM1_SOURCE_MATERIAL_0
<< R200_FRONT_SPECULAR_SOURCE_SHIFT
) |
690 (R200_LM1_SOURCE_MATERIAL_1
<< R200_BACK_EMISSIVE_SOURCE_SHIFT
) |
691 (R200_LM1_SOURCE_MATERIAL_1
<< R200_BACK_AMBIENT_SOURCE_SHIFT
) |
692 (R200_LM1_SOURCE_MATERIAL_1
<< R200_BACK_DIFFUSE_SOURCE_SHIFT
) |
693 (R200_LM1_SOURCE_MATERIAL_1
<< R200_BACK_SPECULAR_SOURCE_SHIFT
));
695 rmesa
->hw
.tcl
.cmd
[TCL_PER_LIGHT_CTL_0
] = 0; /* filled in via callbacks */
696 rmesa
->hw
.tcl
.cmd
[TCL_PER_LIGHT_CTL_1
] = 0;
697 rmesa
->hw
.tcl
.cmd
[TCL_PER_LIGHT_CTL_2
] = 0;
698 rmesa
->hw
.tcl
.cmd
[TCL_PER_LIGHT_CTL_3
] = 0;
700 rmesa
->hw
.tcl
.cmd
[TCL_UCP_VERT_BLEND_CTL
] =
701 (R200_UCP_IN_CLIP_SPACE
|
702 R200_CULL_FRONT_IS_CCW
);
704 /* Texgen/Texmat state */
705 rmesa
->hw
.tcg
.cmd
[TCG_TEX_PROC_CTL_2
] = 0x0; /* masks??? */
706 rmesa
->hw
.tcg
.cmd
[TCG_TEX_PROC_CTL_3
] =
707 ((0 << R200_TEXGEN_0_INPUT_TEX_SHIFT
) |
708 (1 << R200_TEXGEN_1_INPUT_TEX_SHIFT
) |
709 (2 << R200_TEXGEN_2_INPUT_TEX_SHIFT
) |
710 (3 << R200_TEXGEN_3_INPUT_TEX_SHIFT
) |
711 (4 << R200_TEXGEN_4_INPUT_TEX_SHIFT
) |
712 (5 << R200_TEXGEN_5_INPUT_TEX_SHIFT
));
713 rmesa
->hw
.tcg
.cmd
[TCG_TEX_PROC_CTL_0
] = 0;
714 rmesa
->hw
.tcg
.cmd
[TCG_TEX_PROC_CTL_1
] =
715 ((0 << R200_TEXGEN_0_INPUT_SHIFT
) |
716 (1 << R200_TEXGEN_1_INPUT_SHIFT
) |
717 (2 << R200_TEXGEN_2_INPUT_SHIFT
) |
718 (3 << R200_TEXGEN_3_INPUT_SHIFT
) |
719 (4 << R200_TEXGEN_4_INPUT_SHIFT
) |
720 (5 << R200_TEXGEN_5_INPUT_SHIFT
));
721 rmesa
->hw
.tcg
.cmd
[TCG_TEX_CYL_WRAP_CTL
] = 0;
723 rmesa
->TexGenInputs
= rmesa
->hw
.tcg
.cmd
[TCG_TEX_PROC_CTL_1
];
726 for (i
= 0 ; i
< 8; i
++) {
727 struct gl_light
*l
= &ctx
->Light
.Light
[i
];
728 GLenum p
= GL_LIGHT0
+ i
;
729 *(float *)&(rmesa
->hw
.lit
[i
].cmd
[LIT_RANGE_CUTOFF
]) = FLT_MAX
;
731 ctx
->Driver
.Lightfv( ctx
, p
, GL_AMBIENT
, l
->Ambient
);
732 ctx
->Driver
.Lightfv( ctx
, p
, GL_DIFFUSE
, l
->Diffuse
);
733 ctx
->Driver
.Lightfv( ctx
, p
, GL_SPECULAR
, l
->Specular
);
734 ctx
->Driver
.Lightfv( ctx
, p
, GL_POSITION
, 0 );
735 ctx
->Driver
.Lightfv( ctx
, p
, GL_SPOT_DIRECTION
, 0 );
736 ctx
->Driver
.Lightfv( ctx
, p
, GL_SPOT_EXPONENT
, &l
->SpotExponent
);
737 ctx
->Driver
.Lightfv( ctx
, p
, GL_SPOT_CUTOFF
, &l
->SpotCutoff
);
738 ctx
->Driver
.Lightfv( ctx
, p
, GL_CONSTANT_ATTENUATION
,
739 &l
->ConstantAttenuation
);
740 ctx
->Driver
.Lightfv( ctx
, p
, GL_LINEAR_ATTENUATION
,
741 &l
->LinearAttenuation
);
742 ctx
->Driver
.Lightfv( ctx
, p
, GL_QUADRATIC_ATTENUATION
,
743 &l
->QuadraticAttenuation
);
744 *(float *)&(rmesa
->hw
.lit
[i
].cmd
[LIT_ATTEN_XXX
]) = 0.0;
747 ctx
->Driver
.LightModelfv( ctx
, GL_LIGHT_MODEL_AMBIENT
,
748 ctx
->Light
.Model
.Ambient
);
750 TNL_CONTEXT(ctx
)->Driver
.NotifyMaterialChange( ctx
);
752 for (i
= 0 ; i
< 6; i
++) {
753 ctx
->Driver
.ClipPlane( ctx
, GL_CLIP_PLANE0
+ i
, NULL
);
756 ctx
->Driver
.Fogfv( ctx
, GL_FOG_MODE
, 0 );
757 ctx
->Driver
.Fogfv( ctx
, GL_FOG_DENSITY
, &ctx
->Fog
.Density
);
758 ctx
->Driver
.Fogfv( ctx
, GL_FOG_START
, &ctx
->Fog
.Start
);
759 ctx
->Driver
.Fogfv( ctx
, GL_FOG_END
, &ctx
->Fog
.End
);
760 ctx
->Driver
.Fogfv( ctx
, GL_FOG_COLOR
, ctx
->Fog
.Color
);
761 ctx
->Driver
.Fogfv( ctx
, GL_FOG_COORDINATE_SOURCE_EXT
, 0 );
763 rmesa
->hw
.grd
.cmd
[GRD_VERT_GUARD_CLIP_ADJ
] = IEEE_ONE
;
764 rmesa
->hw
.grd
.cmd
[GRD_VERT_GUARD_DISCARD_ADJ
] = IEEE_ONE
;
765 rmesa
->hw
.grd
.cmd
[GRD_HORZ_GUARD_CLIP_ADJ
] = IEEE_ONE
;
766 rmesa
->hw
.grd
.cmd
[GRD_HORZ_GUARD_DISCARD_ADJ
] = IEEE_ONE
;
768 rmesa
->hw
.eye
.cmd
[EYE_X
] = 0;
769 rmesa
->hw
.eye
.cmd
[EYE_Y
] = 0;
770 rmesa
->hw
.eye
.cmd
[EYE_Z
] = IEEE_ONE
;
771 rmesa
->hw
.eye
.cmd
[EYE_RESCALE_FACTOR
] = IEEE_ONE
;
773 r200LightingSpaceChange( ctx
);
775 rmesa
->lost_context
= 1;