2 Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
4 The Weather Channel (TM) funded Tungsten Graphics to develop the
5 initial release of the Radeon 8500 driver under the XFree86 license.
6 This notice must be preserved.
8 Permission is hereby granted, free of charge, to any person obtaining
9 a copy of this software and associated documentation files (the
10 "Software"), to deal in the Software without restriction, including
11 without limitation the rights to use, copy, modify, merge, publish,
12 distribute, sublicense, and/or sell copies of the Software, and to
13 permit persons to whom the Software is furnished to do so, subject to
14 the following conditions:
16 The above copyright notice and this permission notice (including the
17 next paragraph) shall be included in all copies or substantial
18 portions of the Software.
20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
31 * Keith Whitwell <keith@tungstengraphics.com>
34 #include "main/glheader.h"
35 #include "main/imports.h"
36 #include "main/enums.h"
37 #include "main/colormac.h"
38 #include "main/api_arrayelt.h"
40 #include "swrast/swrast.h"
43 #include "tnl/t_pipeline.h"
44 #include "swrast_setup/swrast_setup.h"
46 #include "r200_context.h"
47 #include "r200_ioctl.h"
48 #include "r200_state.h"
51 #include "r200_swtcl.h"
55 /* =============================================================
56 * State initialization
59 void r200PrintDirty( r200ContextPtr rmesa
, const char *msg
)
61 struct r200_state_atom
*l
;
64 fprintf(stderr
, ": ");
66 foreach(l
, &rmesa
->hw
.atomlist
) {
67 if (l
->dirty
|| rmesa
->hw
.all_dirty
)
68 fprintf(stderr
, "%s, ", l
->name
);
71 fprintf(stderr
, "\n");
74 static int cmdpkt( int id
)
76 drm_radeon_cmd_header_t h
;
78 h
.packet
.cmd_type
= RADEON_CMD_PACKET
;
79 h
.packet
.packet_id
= id
;
83 static int cmdvec( int offset
, int stride
, int count
)
85 drm_radeon_cmd_header_t h
;
87 h
.vectors
.cmd_type
= RADEON_CMD_VECTORS
;
88 h
.vectors
.offset
= offset
;
89 h
.vectors
.stride
= stride
;
90 h
.vectors
.count
= count
;
94 /* warning: the count here is divided by 4 compared to other cmds
95 (so it doesn't exceed the char size)! */
96 static int cmdveclinear( int offset
, int count
)
98 drm_radeon_cmd_header_t h
;
100 h
.veclinear
.cmd_type
= RADEON_CMD_VECLINEAR
;
101 h
.veclinear
.addr_lo
= offset
& 0xff;
102 h
.veclinear
.addr_hi
= (offset
& 0xff00) >> 8;
103 h
.veclinear
.count
= count
;
107 static int cmdscl( int offset
, int stride
, int count
)
109 drm_radeon_cmd_header_t h
;
111 h
.scalars
.cmd_type
= RADEON_CMD_SCALARS
;
112 h
.scalars
.offset
= offset
;
113 h
.scalars
.stride
= stride
;
114 h
.scalars
.count
= count
;
118 static int cmdscl2( int offset
, int stride
, int count
)
120 drm_radeon_cmd_header_t h
;
122 h
.scalars
.cmd_type
= RADEON_CMD_SCALARS2
;
123 h
.scalars
.offset
= offset
- 0x100;
124 h
.scalars
.stride
= stride
;
125 h
.scalars
.count
= count
;
129 #define CHECK( NM, FLAG ) \
130 static GLboolean check_##NM( GLcontext *ctx, int idx ) \
132 r200ContextPtr rmesa = R200_CONTEXT(ctx); \
138 #define TCL_CHECK( NM, FLAG ) \
139 static GLboolean check_##NM( GLcontext *ctx, int idx ) \
141 r200ContextPtr rmesa = R200_CONTEXT(ctx); \
143 return !rmesa->TclFallback && !ctx->VertexProgram._Enabled && (FLAG); \
146 #define TCL_OR_VP_CHECK( NM, FLAG ) \
147 static GLboolean check_##NM( GLcontext *ctx, int idx ) \
149 r200ContextPtr rmesa = R200_CONTEXT(ctx); \
151 return !rmesa->TclFallback && (FLAG); \
154 #define VP_CHECK( NM, FLAG ) \
155 static GLboolean check_##NM( GLcontext *ctx, int idx ) \
157 r200ContextPtr rmesa = R200_CONTEXT(ctx); \
159 return !rmesa->TclFallback && ctx->VertexProgram._Enabled && (FLAG); \
163 CHECK( always
, GL_TRUE
)
164 CHECK( never
, GL_FALSE
)
165 CHECK( tex_any
, ctx
->Texture
._EnabledUnits
)
166 CHECK( tf
, (ctx
->Texture
._EnabledUnits
&& !ctx
->ATIFragmentShader
._Enabled
) );
167 CHECK( tex_pair
, (rmesa
->state
.texture
.unit
[idx
].unitneeded
| rmesa
->state
.texture
.unit
[idx
& ~1].unitneeded
) )
168 CHECK( tex
, rmesa
->state
.texture
.unit
[idx
].unitneeded
)
169 CHECK( pix_zero
, !ctx
->ATIFragmentShader
._Enabled
)
170 CHECK( texenv
, (rmesa
->state
.envneeded
& (1 << idx
) && !ctx
->ATIFragmentShader
._Enabled
) )
171 CHECK( afs_pass1
, (ctx
->ATIFragmentShader
._Enabled
&& (ctx
->ATIFragmentShader
.Current
->NumPasses
> 1)) )
172 CHECK( afs
, ctx
->ATIFragmentShader
._Enabled
)
173 CHECK( tex_cube
, rmesa
->state
.texture
.unit
[idx
].unitneeded
& TEXTURE_CUBE_BIT
)
174 TCL_CHECK( tcl_fog
, ctx
->Fog
.Enabled
)
175 TCL_CHECK( tcl
, GL_TRUE
)
176 TCL_CHECK( tcl_tex
, rmesa
->state
.texture
.unit
[idx
].unitneeded
)
177 TCL_CHECK( tcl_lighting
, ctx
->Light
.Enabled
)
178 TCL_CHECK( tcl_light
, ctx
->Light
.Enabled
&& ctx
->Light
.Light
[idx
].Enabled
)
179 TCL_OR_VP_CHECK( tcl_ucp
, (ctx
->Transform
.ClipPlanesEnabled
& (1 << idx
)) )
180 TCL_OR_VP_CHECK( tcl_or_vp
, GL_TRUE
)
181 VP_CHECK( tcl_vp
, GL_TRUE
)
182 VP_CHECK( tcl_vp_size
, ctx
->VertexProgram
.Current
->Base
.NumNativeInstructions
> 64 )
183 VP_CHECK( tcl_vpp_size
, ctx
->VertexProgram
.Current
->Base
.NumNativeParameters
> 96 )
186 /* Initialize the context's hardware state.
188 void r200InitState( r200ContextPtr rmesa
)
190 GLcontext
*ctx
= rmesa
->glCtx
;
191 GLuint color_fmt
, depth_fmt
, i
;
192 GLint drawPitch
, drawOffset
;
194 switch ( rmesa
->r200Screen
->cpp
) {
196 color_fmt
= R200_COLOR_FORMAT_RGB565
;
199 color_fmt
= R200_COLOR_FORMAT_ARGB8888
;
202 fprintf( stderr
, "Error: Unsupported pixel depth... exiting\n" );
206 rmesa
->state
.color
.clear
= 0x00000000;
208 switch ( ctx
->Visual
.depthBits
) {
210 rmesa
->state
.depth
.clear
= 0x0000ffff;
211 rmesa
->state
.depth
.scale
= 1.0 / (GLfloat
)0xffff;
212 depth_fmt
= R200_DEPTH_FORMAT_16BIT_INT_Z
;
213 rmesa
->state
.stencil
.clear
= 0x00000000;
216 rmesa
->state
.depth
.clear
= 0x00ffffff;
217 rmesa
->state
.depth
.scale
= 1.0 / (GLfloat
)0xffffff;
218 depth_fmt
= R200_DEPTH_FORMAT_24BIT_INT_Z
;
219 rmesa
->state
.stencil
.clear
= 0xffff0000;
222 fprintf( stderr
, "Error: Unsupported depth %d... exiting\n",
223 ctx
->Visual
.depthBits
);
227 /* Only have hw stencil when depth buffer is 24 bits deep */
228 rmesa
->state
.stencil
.hwBuffer
= ( ctx
->Visual
.stencilBits
> 0 &&
229 ctx
->Visual
.depthBits
== 24 );
233 if ( ctx
->Visual
.doubleBufferMode
&& rmesa
->sarea
->pfCurrentPage
== 0 ) {
234 drawOffset
= rmesa
->r200Screen
->backOffset
;
235 drawPitch
= rmesa
->r200Screen
->backPitch
;
237 drawOffset
= rmesa
->r200Screen
->frontOffset
;
238 drawPitch
= rmesa
->r200Screen
->frontPitch
;
241 if ( ctx
->Visual
.doubleBufferMode
&& rmesa
->sarea
->pfCurrentPage
== 0 ) {
242 rmesa
->state
.color
.drawOffset
= rmesa
->r200Screen
->backOffset
;
243 rmesa
->state
.color
.drawPitch
= rmesa
->r200Screen
->backPitch
;
245 rmesa
->state
.color
.drawOffset
= rmesa
->r200Screen
->frontOffset
;
246 rmesa
->state
.color
.drawPitch
= rmesa
->r200Screen
->frontPitch
;
249 rmesa
->state
.pixel
.readOffset
= rmesa
->state
.color
.drawOffset
;
250 rmesa
->state
.pixel
.readPitch
= rmesa
->state
.color
.drawPitch
;
253 rmesa
->hw
.max_state_size
= 0;
255 #define ALLOC_STATE( ATOM, CHK, SZ, NM, IDX ) \
257 rmesa->hw.ATOM.cmd_size = SZ; \
258 rmesa->hw.ATOM.cmd = (int *)CALLOC(SZ * sizeof(int)); \
259 rmesa->hw.ATOM.lastcmd = (int *)CALLOC(SZ * sizeof(int)); \
260 rmesa->hw.ATOM.name = NM; \
261 rmesa->hw.ATOM.idx = IDX; \
262 rmesa->hw.ATOM.check = check_##CHK; \
263 rmesa->hw.ATOM.dirty = GL_FALSE; \
264 rmesa->hw.max_state_size += SZ * sizeof(int); \
268 /* Allocate state buffers:
270 if (rmesa
->r200Screen
->drmSupportsBlendColor
)
271 ALLOC_STATE( ctx
, always
, CTX_STATE_SIZE_NEWDRM
, "CTX/context", 0 );
273 ALLOC_STATE( ctx
, always
, CTX_STATE_SIZE_OLDDRM
, "CTX/context", 0 );
274 ALLOC_STATE( set
, always
, SET_STATE_SIZE
, "SET/setup", 0 );
275 ALLOC_STATE( lin
, always
, LIN_STATE_SIZE
, "LIN/line", 0 );
276 ALLOC_STATE( msk
, always
, MSK_STATE_SIZE
, "MSK/mask", 0 );
277 ALLOC_STATE( vpt
, always
, VPT_STATE_SIZE
, "VPT/viewport", 0 );
278 ALLOC_STATE( vtx
, always
, VTX_STATE_SIZE
, "VTX/vertex", 0 );
279 ALLOC_STATE( vap
, always
, VAP_STATE_SIZE
, "VAP/vap", 0 );
280 ALLOC_STATE( vte
, always
, VTE_STATE_SIZE
, "VTE/vte", 0 );
281 ALLOC_STATE( msc
, always
, MSC_STATE_SIZE
, "MSC/misc", 0 );
282 ALLOC_STATE( cst
, always
, CST_STATE_SIZE
, "CST/constant", 0 );
283 ALLOC_STATE( zbs
, always
, ZBS_STATE_SIZE
, "ZBS/zbias", 0 );
284 ALLOC_STATE( tf
, tf
, TF_STATE_SIZE
, "TF/tfactor", 0 );
285 if (rmesa
->r200Screen
->drmSupportsFragShader
) {
286 if (rmesa
->r200Screen
->chip_family
== CHIP_FAMILY_R200
) {
287 /* make sure texture units 0/1 are emitted pair-wise for r200 t0 hang workaround */
288 ALLOC_STATE( tex
[0], tex_pair
, TEX_STATE_SIZE_NEWDRM
, "TEX/tex-0", 0 );
289 ALLOC_STATE( tex
[1], tex_pair
, TEX_STATE_SIZE_NEWDRM
, "TEX/tex-1", 1 );
290 ALLOC_STATE( tam
, tex_any
, TAM_STATE_SIZE
, "TAM/tam", 0 );
293 ALLOC_STATE( tex
[0], tex
, TEX_STATE_SIZE_NEWDRM
, "TEX/tex-0", 0 );
294 ALLOC_STATE( tex
[1], tex
, TEX_STATE_SIZE_NEWDRM
, "TEX/tex-1", 1 );
295 ALLOC_STATE( tam
, never
, TAM_STATE_SIZE
, "TAM/tam", 0 );
297 ALLOC_STATE( tex
[2], tex
, TEX_STATE_SIZE_NEWDRM
, "TEX/tex-2", 2 );
298 ALLOC_STATE( tex
[3], tex
, TEX_STATE_SIZE_NEWDRM
, "TEX/tex-3", 3 );
299 ALLOC_STATE( tex
[4], tex
, TEX_STATE_SIZE_NEWDRM
, "TEX/tex-4", 4 );
300 ALLOC_STATE( tex
[5], tex
, TEX_STATE_SIZE_NEWDRM
, "TEX/tex-5", 5 );
301 ALLOC_STATE( atf
, afs
, ATF_STATE_SIZE
, "ATF/tfactor", 0 );
302 ALLOC_STATE( afs
[0], afs_pass1
, AFS_STATE_SIZE
, "AFS/afsinst-0", 0 );
303 ALLOC_STATE( afs
[1], afs
, AFS_STATE_SIZE
, "AFS/afsinst-1", 1 );
306 if (rmesa
->r200Screen
->chip_family
== CHIP_FAMILY_R200
) {
307 ALLOC_STATE( tex
[0], tex_pair
, TEX_STATE_SIZE_OLDDRM
, "TEX/tex-0", 0 );
308 ALLOC_STATE( tex
[1], tex_pair
, TEX_STATE_SIZE_OLDDRM
, "TEX/tex-1", 1 );
309 ALLOC_STATE( tam
, tex_any
, TAM_STATE_SIZE
, "TAM/tam", 0 );
312 ALLOC_STATE( tex
[0], tex
, TEX_STATE_SIZE_OLDDRM
, "TEX/tex-0", 0 );
313 ALLOC_STATE( tex
[1], tex
, TEX_STATE_SIZE_OLDDRM
, "TEX/tex-1", 1 );
314 ALLOC_STATE( tam
, never
, TAM_STATE_SIZE
, "TAM/tam", 0 );
316 ALLOC_STATE( tex
[2], tex
, TEX_STATE_SIZE_OLDDRM
, "TEX/tex-2", 2 );
317 ALLOC_STATE( tex
[3], tex
, TEX_STATE_SIZE_OLDDRM
, "TEX/tex-3", 3 );
318 ALLOC_STATE( tex
[4], tex
, TEX_STATE_SIZE_OLDDRM
, "TEX/tex-4", 4 );
319 ALLOC_STATE( tex
[5], tex
, TEX_STATE_SIZE_OLDDRM
, "TEX/tex-5", 5 );
320 ALLOC_STATE( atf
, never
, ATF_STATE_SIZE
, "TF/tfactor", 0 );
321 ALLOC_STATE( afs
[0], never
, AFS_STATE_SIZE
, "AFS/afsinst-0", 0 );
322 ALLOC_STATE( afs
[1], never
, AFS_STATE_SIZE
, "AFS/afsinst-1", 1 );
324 if (rmesa
->r200Screen
->drmSupportsCubeMapsR200
) {
325 ALLOC_STATE( cube
[0], tex_cube
, CUBE_STATE_SIZE
, "CUBE/tex-0", 0 );
326 ALLOC_STATE( cube
[1], tex_cube
, CUBE_STATE_SIZE
, "CUBE/tex-1", 1 );
327 ALLOC_STATE( cube
[2], tex_cube
, CUBE_STATE_SIZE
, "CUBE/tex-2", 2 );
328 ALLOC_STATE( cube
[3], tex_cube
, CUBE_STATE_SIZE
, "CUBE/tex-3", 3 );
329 ALLOC_STATE( cube
[4], tex_cube
, CUBE_STATE_SIZE
, "CUBE/tex-4", 4 );
330 ALLOC_STATE( cube
[5], tex_cube
, CUBE_STATE_SIZE
, "CUBE/tex-5", 5 );
333 ALLOC_STATE( cube
[0], never
, CUBE_STATE_SIZE
, "CUBE/tex-0", 0 );
334 ALLOC_STATE( cube
[1], never
, CUBE_STATE_SIZE
, "CUBE/tex-1", 1 );
335 ALLOC_STATE( cube
[2], never
, CUBE_STATE_SIZE
, "CUBE/tex-2", 2 );
336 ALLOC_STATE( cube
[3], never
, CUBE_STATE_SIZE
, "CUBE/tex-3", 3 );
337 ALLOC_STATE( cube
[4], never
, CUBE_STATE_SIZE
, "CUBE/tex-4", 4 );
338 ALLOC_STATE( cube
[5], never
, CUBE_STATE_SIZE
, "CUBE/tex-5", 5 );
340 if (rmesa
->r200Screen
->drmSupportsVertexProgram
) {
341 ALLOC_STATE( pvs
, tcl_vp
, PVS_STATE_SIZE
, "PVS/pvscntl", 0 );
342 ALLOC_STATE( vpi
[0], tcl_vp
, VPI_STATE_SIZE
, "VP/vertexprog-0", 0 );
343 ALLOC_STATE( vpi
[1], tcl_vp_size
, VPI_STATE_SIZE
, "VP/vertexprog-1", 1 );
344 ALLOC_STATE( vpp
[0], tcl_vp
, VPP_STATE_SIZE
, "VPP/vertexparam-0", 0 );
345 ALLOC_STATE( vpp
[1], tcl_vpp_size
, VPP_STATE_SIZE
, "VPP/vertexparam-1", 1 );
348 ALLOC_STATE( pvs
, never
, PVS_STATE_SIZE
, "PVS/pvscntl", 0 );
349 ALLOC_STATE( vpi
[0], never
, VPI_STATE_SIZE
, "VP/vertexprog-0", 0 );
350 ALLOC_STATE( vpi
[1], never
, VPI_STATE_SIZE
, "VP/vertexprog-1", 1 );
351 ALLOC_STATE( vpp
[0], never
, VPP_STATE_SIZE
, "VPP/vertexparam-0", 0 );
352 ALLOC_STATE( vpp
[1], never
, VPP_STATE_SIZE
, "VPP/vertexparam-1", 1 );
354 /* FIXME: this atom has two commands, we need only one (ucp_vert_blend) for vp */
355 ALLOC_STATE( tcl
, tcl_or_vp
, TCL_STATE_SIZE
, "TCL/tcl", 0 );
356 ALLOC_STATE( msl
, tcl
, MSL_STATE_SIZE
, "MSL/matrix-select", 0 );
357 ALLOC_STATE( tcg
, tcl
, TCG_STATE_SIZE
, "TCG/texcoordgen", 0 );
358 ALLOC_STATE( mtl
[0], tcl_lighting
, MTL_STATE_SIZE
, "MTL0/material0", 0 );
359 ALLOC_STATE( mtl
[1], tcl_lighting
, MTL_STATE_SIZE
, "MTL1/material1", 1 );
360 ALLOC_STATE( grd
, tcl_or_vp
, GRD_STATE_SIZE
, "GRD/guard-band", 0 );
361 ALLOC_STATE( fog
, tcl_fog
, FOG_STATE_SIZE
, "FOG/fog", 0 );
362 ALLOC_STATE( glt
, tcl_lighting
, GLT_STATE_SIZE
, "GLT/light-global", 0 );
363 ALLOC_STATE( eye
, tcl_lighting
, EYE_STATE_SIZE
, "EYE/eye-vector", 0 );
364 ALLOC_STATE( mat
[R200_MTX_MV
], tcl
, MAT_STATE_SIZE
, "MAT/modelview", 0 );
365 ALLOC_STATE( mat
[R200_MTX_IMV
], tcl
, MAT_STATE_SIZE
, "MAT/it-modelview", 0 );
366 ALLOC_STATE( mat
[R200_MTX_MVP
], tcl
, MAT_STATE_SIZE
, "MAT/modelproject", 0 );
367 ALLOC_STATE( mat
[R200_MTX_TEX0
], tcl_tex
, MAT_STATE_SIZE
, "MAT/texmat0", 0 );
368 ALLOC_STATE( mat
[R200_MTX_TEX1
], tcl_tex
, MAT_STATE_SIZE
, "MAT/texmat1", 1 );
369 ALLOC_STATE( mat
[R200_MTX_TEX2
], tcl_tex
, MAT_STATE_SIZE
, "MAT/texmat2", 2 );
370 ALLOC_STATE( mat
[R200_MTX_TEX3
], tcl_tex
, MAT_STATE_SIZE
, "MAT/texmat3", 3 );
371 ALLOC_STATE( mat
[R200_MTX_TEX4
], tcl_tex
, MAT_STATE_SIZE
, "MAT/texmat4", 4 );
372 ALLOC_STATE( mat
[R200_MTX_TEX5
], tcl_tex
, MAT_STATE_SIZE
, "MAT/texmat5", 5 );
373 ALLOC_STATE( ucp
[0], tcl_ucp
, UCP_STATE_SIZE
, "UCP/userclip-0", 0 );
374 ALLOC_STATE( ucp
[1], tcl_ucp
, UCP_STATE_SIZE
, "UCP/userclip-1", 1 );
375 ALLOC_STATE( ucp
[2], tcl_ucp
, UCP_STATE_SIZE
, "UCP/userclip-2", 2 );
376 ALLOC_STATE( ucp
[3], tcl_ucp
, UCP_STATE_SIZE
, "UCP/userclip-3", 3 );
377 ALLOC_STATE( ucp
[4], tcl_ucp
, UCP_STATE_SIZE
, "UCP/userclip-4", 4 );
378 ALLOC_STATE( ucp
[5], tcl_ucp
, UCP_STATE_SIZE
, "UCP/userclip-5", 5 );
379 ALLOC_STATE( lit
[0], tcl_light
, LIT_STATE_SIZE
, "LIT/light-0", 0 );
380 ALLOC_STATE( lit
[1], tcl_light
, LIT_STATE_SIZE
, "LIT/light-1", 1 );
381 ALLOC_STATE( lit
[2], tcl_light
, LIT_STATE_SIZE
, "LIT/light-2", 2 );
382 ALLOC_STATE( lit
[3], tcl_light
, LIT_STATE_SIZE
, "LIT/light-3", 3 );
383 ALLOC_STATE( lit
[4], tcl_light
, LIT_STATE_SIZE
, "LIT/light-4", 4 );
384 ALLOC_STATE( lit
[5], tcl_light
, LIT_STATE_SIZE
, "LIT/light-5", 5 );
385 ALLOC_STATE( lit
[6], tcl_light
, LIT_STATE_SIZE
, "LIT/light-6", 6 );
386 ALLOC_STATE( lit
[7], tcl_light
, LIT_STATE_SIZE
, "LIT/light-7", 7 );
387 ALLOC_STATE( pix
[0], pix_zero
, PIX_STATE_SIZE
, "PIX/pixstage-0", 0 );
388 ALLOC_STATE( pix
[1], texenv
, PIX_STATE_SIZE
, "PIX/pixstage-1", 1 );
389 ALLOC_STATE( pix
[2], texenv
, PIX_STATE_SIZE
, "PIX/pixstage-2", 2 );
390 ALLOC_STATE( pix
[3], texenv
, PIX_STATE_SIZE
, "PIX/pixstage-3", 3 );
391 ALLOC_STATE( pix
[4], texenv
, PIX_STATE_SIZE
, "PIX/pixstage-4", 4 );
392 ALLOC_STATE( pix
[5], texenv
, PIX_STATE_SIZE
, "PIX/pixstage-5", 5 );
393 if (rmesa
->r200Screen
->drmSupportsTriPerf
) {
394 ALLOC_STATE( prf
, always
, PRF_STATE_SIZE
, "PRF/performance-tri", 0 );
397 ALLOC_STATE( prf
, never
, PRF_STATE_SIZE
, "PRF/performance-tri", 0 );
399 if (rmesa
->r200Screen
->drmSupportsPointSprites
) {
400 ALLOC_STATE( spr
, always
, SPR_STATE_SIZE
, "SPR/pointsprite", 0 );
401 ALLOC_STATE( ptp
, tcl
, PTP_STATE_SIZE
, "PTP/pointparams", 0 );
404 ALLOC_STATE (spr
, never
, SPR_STATE_SIZE
, "SPR/pointsprite", 0 );
405 ALLOC_STATE (ptp
, never
, PTP_STATE_SIZE
, "PTP/pointparams", 0 );
408 r200SetUpAtomList( rmesa
);
410 /* Fill in the packet headers:
412 rmesa
->hw
.ctx
.cmd
[CTX_CMD_0
] = cmdpkt(RADEON_EMIT_PP_MISC
);
413 rmesa
->hw
.ctx
.cmd
[CTX_CMD_1
] = cmdpkt(RADEON_EMIT_PP_CNTL
);
414 rmesa
->hw
.ctx
.cmd
[CTX_CMD_2
] = cmdpkt(RADEON_EMIT_RB3D_COLORPITCH
);
415 if (rmesa
->r200Screen
->drmSupportsBlendColor
)
416 rmesa
->hw
.ctx
.cmd
[CTX_CMD_3
] = cmdpkt(R200_EMIT_RB3D_BLENDCOLOR
);
417 rmesa
->hw
.lin
.cmd
[LIN_CMD_0
] = cmdpkt(RADEON_EMIT_RE_LINE_PATTERN
);
418 rmesa
->hw
.lin
.cmd
[LIN_CMD_1
] = cmdpkt(RADEON_EMIT_SE_LINE_WIDTH
);
419 rmesa
->hw
.msk
.cmd
[MSK_CMD_0
] = cmdpkt(RADEON_EMIT_RB3D_STENCILREFMASK
);
420 rmesa
->hw
.vpt
.cmd
[VPT_CMD_0
] = cmdpkt(RADEON_EMIT_SE_VPORT_XSCALE
);
421 rmesa
->hw
.set
.cmd
[SET_CMD_0
] = cmdpkt(RADEON_EMIT_SE_CNTL
);
422 rmesa
->hw
.msc
.cmd
[MSC_CMD_0
] = cmdpkt(RADEON_EMIT_RE_MISC
);
423 rmesa
->hw
.cst
.cmd
[CST_CMD_0
] = cmdpkt(R200_EMIT_PP_CNTL_X
);
424 rmesa
->hw
.cst
.cmd
[CST_CMD_1
] = cmdpkt(R200_EMIT_RB3D_DEPTHXY_OFFSET
);
425 rmesa
->hw
.cst
.cmd
[CST_CMD_2
] = cmdpkt(R200_EMIT_RE_AUX_SCISSOR_CNTL
);
426 rmesa
->hw
.cst
.cmd
[CST_CMD_3
] = cmdpkt(R200_EMIT_RE_SCISSOR_TL_0
);
427 rmesa
->hw
.cst
.cmd
[CST_CMD_4
] = cmdpkt(R200_EMIT_SE_VAP_CNTL_STATUS
);
428 rmesa
->hw
.cst
.cmd
[CST_CMD_5
] = cmdpkt(R200_EMIT_RE_POINTSIZE
);
429 rmesa
->hw
.cst
.cmd
[CST_CMD_6
] = cmdpkt(R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0
);
430 rmesa
->hw
.tam
.cmd
[TAM_CMD_0
] = cmdpkt(R200_EMIT_PP_TAM_DEBUG3
);
431 rmesa
->hw
.tf
.cmd
[TF_CMD_0
] = cmdpkt(R200_EMIT_TFACTOR_0
);
432 if (rmesa
->r200Screen
->drmSupportsFragShader
) {
433 rmesa
->hw
.atf
.cmd
[ATF_CMD_0
] = cmdpkt(R200_EMIT_ATF_TFACTOR
);
434 rmesa
->hw
.tex
[0].cmd
[TEX_CMD_0
] = cmdpkt(R200_EMIT_PP_TXCTLALL_0
);
435 rmesa
->hw
.tex
[0].cmd
[TEX_CMD_1_NEWDRM
] = cmdpkt(R200_EMIT_PP_TXOFFSET_0
);
436 rmesa
->hw
.tex
[1].cmd
[TEX_CMD_0
] = cmdpkt(R200_EMIT_PP_TXCTLALL_1
);
437 rmesa
->hw
.tex
[1].cmd
[TEX_CMD_1_NEWDRM
] = cmdpkt(R200_EMIT_PP_TXOFFSET_1
);
438 rmesa
->hw
.tex
[2].cmd
[TEX_CMD_0
] = cmdpkt(R200_EMIT_PP_TXCTLALL_2
);
439 rmesa
->hw
.tex
[2].cmd
[TEX_CMD_1_NEWDRM
] = cmdpkt(R200_EMIT_PP_TXOFFSET_2
);
440 rmesa
->hw
.tex
[3].cmd
[TEX_CMD_0
] = cmdpkt(R200_EMIT_PP_TXCTLALL_3
);
441 rmesa
->hw
.tex
[3].cmd
[TEX_CMD_1_NEWDRM
] = cmdpkt(R200_EMIT_PP_TXOFFSET_3
);
442 rmesa
->hw
.tex
[4].cmd
[TEX_CMD_0
] = cmdpkt(R200_EMIT_PP_TXCTLALL_4
);
443 rmesa
->hw
.tex
[4].cmd
[TEX_CMD_1_NEWDRM
] = cmdpkt(R200_EMIT_PP_TXOFFSET_4
);
444 rmesa
->hw
.tex
[5].cmd
[TEX_CMD_0
] = cmdpkt(R200_EMIT_PP_TXCTLALL_5
);
445 rmesa
->hw
.tex
[5].cmd
[TEX_CMD_1_NEWDRM
] = cmdpkt(R200_EMIT_PP_TXOFFSET_5
);
447 rmesa
->hw
.tex
[0].cmd
[TEX_CMD_0
] = cmdpkt(R200_EMIT_PP_TXFILTER_0
);
448 rmesa
->hw
.tex
[0].cmd
[TEX_CMD_1_OLDDRM
] = cmdpkt(R200_EMIT_PP_TXOFFSET_0
);
449 rmesa
->hw
.tex
[1].cmd
[TEX_CMD_0
] = cmdpkt(R200_EMIT_PP_TXFILTER_1
);
450 rmesa
->hw
.tex
[1].cmd
[TEX_CMD_1_OLDDRM
] = cmdpkt(R200_EMIT_PP_TXOFFSET_1
);
451 rmesa
->hw
.tex
[2].cmd
[TEX_CMD_0
] = cmdpkt(R200_EMIT_PP_TXFILTER_2
);
452 rmesa
->hw
.tex
[2].cmd
[TEX_CMD_1_OLDDRM
] = cmdpkt(R200_EMIT_PP_TXOFFSET_2
);
453 rmesa
->hw
.tex
[3].cmd
[TEX_CMD_0
] = cmdpkt(R200_EMIT_PP_TXFILTER_3
);
454 rmesa
->hw
.tex
[3].cmd
[TEX_CMD_1_OLDDRM
] = cmdpkt(R200_EMIT_PP_TXOFFSET_3
);
455 rmesa
->hw
.tex
[4].cmd
[TEX_CMD_0
] = cmdpkt(R200_EMIT_PP_TXFILTER_4
);
456 rmesa
->hw
.tex
[4].cmd
[TEX_CMD_1_OLDDRM
] = cmdpkt(R200_EMIT_PP_TXOFFSET_4
);
457 rmesa
->hw
.tex
[5].cmd
[TEX_CMD_0
] = cmdpkt(R200_EMIT_PP_TXFILTER_5
);
458 rmesa
->hw
.tex
[5].cmd
[TEX_CMD_1_OLDDRM
] = cmdpkt(R200_EMIT_PP_TXOFFSET_5
);
460 rmesa
->hw
.afs
[0].cmd
[AFS_CMD_0
] = cmdpkt(R200_EMIT_PP_AFS_0
);
461 rmesa
->hw
.afs
[1].cmd
[AFS_CMD_0
] = cmdpkt(R200_EMIT_PP_AFS_1
);
462 rmesa
->hw
.pvs
.cmd
[PVS_CMD_0
] = cmdpkt(R200_EMIT_VAP_PVS_CNTL
);
463 rmesa
->hw
.cube
[0].cmd
[CUBE_CMD_0
] = cmdpkt(R200_EMIT_PP_CUBIC_FACES_0
);
464 rmesa
->hw
.cube
[0].cmd
[CUBE_CMD_1
] = cmdpkt(R200_EMIT_PP_CUBIC_OFFSETS_0
);
465 rmesa
->hw
.cube
[1].cmd
[CUBE_CMD_0
] = cmdpkt(R200_EMIT_PP_CUBIC_FACES_1
);
466 rmesa
->hw
.cube
[1].cmd
[CUBE_CMD_1
] = cmdpkt(R200_EMIT_PP_CUBIC_OFFSETS_1
);
467 rmesa
->hw
.cube
[2].cmd
[CUBE_CMD_0
] = cmdpkt(R200_EMIT_PP_CUBIC_FACES_2
);
468 rmesa
->hw
.cube
[2].cmd
[CUBE_CMD_1
] = cmdpkt(R200_EMIT_PP_CUBIC_OFFSETS_2
);
469 rmesa
->hw
.cube
[3].cmd
[CUBE_CMD_0
] = cmdpkt(R200_EMIT_PP_CUBIC_FACES_3
);
470 rmesa
->hw
.cube
[3].cmd
[CUBE_CMD_1
] = cmdpkt(R200_EMIT_PP_CUBIC_OFFSETS_3
);
471 rmesa
->hw
.cube
[4].cmd
[CUBE_CMD_0
] = cmdpkt(R200_EMIT_PP_CUBIC_FACES_4
);
472 rmesa
->hw
.cube
[4].cmd
[CUBE_CMD_1
] = cmdpkt(R200_EMIT_PP_CUBIC_OFFSETS_4
);
473 rmesa
->hw
.cube
[5].cmd
[CUBE_CMD_0
] = cmdpkt(R200_EMIT_PP_CUBIC_FACES_5
);
474 rmesa
->hw
.cube
[5].cmd
[CUBE_CMD_1
] = cmdpkt(R200_EMIT_PP_CUBIC_OFFSETS_5
);
475 rmesa
->hw
.pix
[0].cmd
[PIX_CMD_0
] = cmdpkt(R200_EMIT_PP_TXCBLEND_0
);
476 rmesa
->hw
.pix
[1].cmd
[PIX_CMD_0
] = cmdpkt(R200_EMIT_PP_TXCBLEND_1
);
477 rmesa
->hw
.pix
[2].cmd
[PIX_CMD_0
] = cmdpkt(R200_EMIT_PP_TXCBLEND_2
);
478 rmesa
->hw
.pix
[3].cmd
[PIX_CMD_0
] = cmdpkt(R200_EMIT_PP_TXCBLEND_3
);
479 rmesa
->hw
.pix
[4].cmd
[PIX_CMD_0
] = cmdpkt(R200_EMIT_PP_TXCBLEND_4
);
480 rmesa
->hw
.pix
[5].cmd
[PIX_CMD_0
] = cmdpkt(R200_EMIT_PP_TXCBLEND_5
);
481 rmesa
->hw
.zbs
.cmd
[ZBS_CMD_0
] = cmdpkt(RADEON_EMIT_SE_ZBIAS_FACTOR
);
482 rmesa
->hw
.tcl
.cmd
[TCL_CMD_0
] = cmdpkt(R200_EMIT_TCL_LIGHT_MODEL_CTL_0
);
483 rmesa
->hw
.tcl
.cmd
[TCL_CMD_1
] = cmdpkt(R200_EMIT_TCL_UCP_VERT_BLEND_CTL
);
484 rmesa
->hw
.tcg
.cmd
[TCG_CMD_0
] = cmdpkt(R200_EMIT_TEX_PROC_CTL_2
);
485 rmesa
->hw
.msl
.cmd
[MSL_CMD_0
] = cmdpkt(R200_EMIT_MATRIX_SELECT_0
);
486 rmesa
->hw
.vap
.cmd
[VAP_CMD_0
] = cmdpkt(R200_EMIT_VAP_CTL
);
487 rmesa
->hw
.vtx
.cmd
[VTX_CMD_0
] = cmdpkt(R200_EMIT_VTX_FMT_0
);
488 rmesa
->hw
.vtx
.cmd
[VTX_CMD_1
] = cmdpkt(R200_EMIT_OUTPUT_VTX_COMP_SEL
);
489 rmesa
->hw
.vtx
.cmd
[VTX_CMD_2
] = cmdpkt(R200_EMIT_SE_VTX_STATE_CNTL
);
490 rmesa
->hw
.vte
.cmd
[VTE_CMD_0
] = cmdpkt(R200_EMIT_VTE_CNTL
);
491 rmesa
->hw
.prf
.cmd
[PRF_CMD_0
] = cmdpkt(R200_EMIT_PP_TRI_PERF_CNTL
);
492 rmesa
->hw
.spr
.cmd
[SPR_CMD_0
] = cmdpkt(R200_EMIT_TCL_POINT_SPRITE_CNTL
);
493 rmesa
->hw
.mtl
[0].cmd
[MTL_CMD_0
] =
494 cmdvec( R200_VS_MAT_0_EMISS
, 1, 16 );
495 rmesa
->hw
.mtl
[0].cmd
[MTL_CMD_1
] =
496 cmdscl2( R200_SS_MAT_0_SHININESS
, 1, 1 );
497 rmesa
->hw
.mtl
[1].cmd
[MTL_CMD_0
] =
498 cmdvec( R200_VS_MAT_1_EMISS
, 1, 16 );
499 rmesa
->hw
.mtl
[1].cmd
[MTL_CMD_1
] =
500 cmdscl2( R200_SS_MAT_1_SHININESS
, 1, 1 );
502 rmesa
->hw
.vpi
[0].cmd
[VPI_CMD_0
] =
503 cmdveclinear( R200_PVS_PROG0
, 64 );
504 rmesa
->hw
.vpi
[1].cmd
[VPI_CMD_0
] =
505 cmdveclinear( R200_PVS_PROG1
, 64 );
506 rmesa
->hw
.vpp
[0].cmd
[VPP_CMD_0
] =
507 cmdveclinear( R200_PVS_PARAM0
, 96 );
508 rmesa
->hw
.vpp
[1].cmd
[VPP_CMD_0
] =
509 cmdveclinear( R200_PVS_PARAM1
, 96 );
511 rmesa
->hw
.grd
.cmd
[GRD_CMD_0
] =
512 cmdscl( R200_SS_VERT_GUARD_CLIP_ADJ_ADDR
, 1, 4 );
513 rmesa
->hw
.fog
.cmd
[FOG_CMD_0
] =
514 cmdvec( R200_VS_FOG_PARAM_ADDR
, 1, 4 );
515 rmesa
->hw
.glt
.cmd
[GLT_CMD_0
] =
516 cmdvec( R200_VS_GLOBAL_AMBIENT_ADDR
, 1, 4 );
517 rmesa
->hw
.eye
.cmd
[EYE_CMD_0
] =
518 cmdvec( R200_VS_EYE_VECTOR_ADDR
, 1, 4 );
520 rmesa
->hw
.mat
[R200_MTX_MV
].cmd
[MAT_CMD_0
] =
521 cmdvec( R200_VS_MATRIX_0_MV
, 1, 16);
522 rmesa
->hw
.mat
[R200_MTX_IMV
].cmd
[MAT_CMD_0
] =
523 cmdvec( R200_VS_MATRIX_1_INV_MV
, 1, 16);
524 rmesa
->hw
.mat
[R200_MTX_MVP
].cmd
[MAT_CMD_0
] =
525 cmdvec( R200_VS_MATRIX_2_MVP
, 1, 16);
526 rmesa
->hw
.mat
[R200_MTX_TEX0
].cmd
[MAT_CMD_0
] =
527 cmdvec( R200_VS_MATRIX_3_TEX0
, 1, 16);
528 rmesa
->hw
.mat
[R200_MTX_TEX1
].cmd
[MAT_CMD_0
] =
529 cmdvec( R200_VS_MATRIX_4_TEX1
, 1, 16);
530 rmesa
->hw
.mat
[R200_MTX_TEX2
].cmd
[MAT_CMD_0
] =
531 cmdvec( R200_VS_MATRIX_5_TEX2
, 1, 16);
532 rmesa
->hw
.mat
[R200_MTX_TEX3
].cmd
[MAT_CMD_0
] =
533 cmdvec( R200_VS_MATRIX_6_TEX3
, 1, 16);
534 rmesa
->hw
.mat
[R200_MTX_TEX4
].cmd
[MAT_CMD_0
] =
535 cmdvec( R200_VS_MATRIX_7_TEX4
, 1, 16);
536 rmesa
->hw
.mat
[R200_MTX_TEX5
].cmd
[MAT_CMD_0
] =
537 cmdvec( R200_VS_MATRIX_8_TEX5
, 1, 16);
539 for (i
= 0 ; i
< 8; i
++) {
540 rmesa
->hw
.lit
[i
].cmd
[LIT_CMD_0
] =
541 cmdvec( R200_VS_LIGHT_AMBIENT_ADDR
+ i
, 8, 24 );
542 rmesa
->hw
.lit
[i
].cmd
[LIT_CMD_1
] =
543 cmdscl( R200_SS_LIGHT_DCD_ADDR
+ i
, 8, 7 );
546 for (i
= 0 ; i
< 6; i
++) {
547 rmesa
->hw
.ucp
[i
].cmd
[UCP_CMD_0
] =
548 cmdvec( R200_VS_UCP_ADDR
+ i
, 1, 4 );
551 rmesa
->hw
.ptp
.cmd
[PTP_CMD_0
] =
552 cmdvec( R200_VS_PNT_SPRITE_VPORT_SCALE
, 1, 4 );
553 rmesa
->hw
.ptp
.cmd
[PTP_CMD_1
] =
554 cmdvec( R200_VS_PNT_SPRITE_ATT_CONST
, 1, 12 );
556 /* Initial Harware state:
558 rmesa
->hw
.ctx
.cmd
[CTX_PP_MISC
] = (R200_ALPHA_TEST_PASS
559 /* | R200_RIGHT_HAND_CUBE_OGL*/);
561 rmesa
->hw
.ctx
.cmd
[CTX_PP_FOG_COLOR
] = (R200_FOG_VERTEX
|
562 R200_FOG_USE_SPEC_ALPHA
);
564 rmesa
->hw
.ctx
.cmd
[CTX_RE_SOLID_COLOR
] = 0x00000000;
566 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_BLENDCNTL
] = (R200_COMB_FCN_ADD_CLAMP
|
567 (R200_BLEND_GL_ONE
<< R200_SRC_BLEND_SHIFT
) |
568 (R200_BLEND_GL_ZERO
<< R200_DST_BLEND_SHIFT
));
570 if (rmesa
->r200Screen
->drmSupportsBlendColor
) {
571 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_BLENDCOLOR
] = 0x00000000;
572 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ABLENDCNTL
] = (R200_COMB_FCN_ADD_CLAMP
|
573 (R200_BLEND_GL_ONE
<< R200_SRC_BLEND_SHIFT
) |
574 (R200_BLEND_GL_ZERO
<< R200_DST_BLEND_SHIFT
));
575 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_CBLENDCNTL
] = (R200_COMB_FCN_ADD_CLAMP
|
576 (R200_BLEND_GL_ONE
<< R200_SRC_BLEND_SHIFT
) |
577 (R200_BLEND_GL_ZERO
<< R200_DST_BLEND_SHIFT
));
580 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_DEPTHOFFSET
] =
581 rmesa
->r200Screen
->depthOffset
+ rmesa
->r200Screen
->fbLocation
;
583 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_DEPTHPITCH
] =
584 ((rmesa
->r200Screen
->depthPitch
&
585 R200_DEPTHPITCH_MASK
) |
586 R200_DEPTH_ENDIAN_NO_SWAP
);
588 if (rmesa
->using_hyperz
)
589 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_DEPTHPITCH
] |= R200_DEPTH_HYPERZ
;
591 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] = (depth_fmt
|
593 R200_STENCIL_TEST_ALWAYS
|
594 R200_STENCIL_FAIL_KEEP
|
595 R200_STENCIL_ZPASS_KEEP
|
596 R200_STENCIL_ZFAIL_KEEP
|
597 R200_Z_WRITE_ENABLE
);
599 if (rmesa
->using_hyperz
) {
600 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= R200_Z_COMPRESSION_ENABLE
|
601 R200_Z_DECOMPRESSION_ENABLE
;
602 /* if (rmesa->r200Screen->chip_family == CHIP_FAMILY_R200)
603 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_HIERARCHY_ENABLE;*/
606 rmesa
->hw
.ctx
.cmd
[CTX_PP_CNTL
] = (R200_ANTI_ALIAS_NONE
607 | R200_TEX_BLEND_0_ENABLE
);
609 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_CNTL
] = color_fmt
;
610 switch ( driQueryOptioni( &rmesa
->optionCache
, "dither_mode" ) ) {
611 case DRI_CONF_DITHER_XERRORDIFFRESET
:
612 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_CNTL
] |= R200_DITHER_INIT
;
614 case DRI_CONF_DITHER_ORDERED
:
615 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_CNTL
] |= R200_SCALE_DITHER_ENABLE
;
618 if ( driQueryOptioni( &rmesa
->optionCache
, "round_mode" ) ==
619 DRI_CONF_ROUND_ROUND
)
620 rmesa
->state
.color
.roundEnable
= R200_ROUND_ENABLE
;
622 rmesa
->state
.color
.roundEnable
= 0;
623 if ( driQueryOptioni (&rmesa
->optionCache
, "color_reduction" ) ==
624 DRI_CONF_COLOR_REDUCTION_DITHER
)
625 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_CNTL
] |= R200_DITHER_ENABLE
;
627 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_CNTL
] |= rmesa
->state
.color
.roundEnable
;
630 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_COLOROFFSET
] = ((rmesa
->state
.color
.drawOffset
+
631 rmesa
->r200Screen
->fbLocation
)
632 & R200_COLOROFFSET_MASK
);
634 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_COLORPITCH
] = ((rmesa
->state
.color
.drawPitch
&
635 R200_COLORPITCH_MASK
) |
636 R200_COLOR_ENDIAN_NO_SWAP
);
638 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_COLOROFFSET
] = ((drawOffset
+
639 rmesa
->r200Screen
->fbLocation
)
640 & R200_COLOROFFSET_MASK
);
642 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_COLORPITCH
] = ((drawPitch
&
643 R200_COLORPITCH_MASK
) |
644 R200_COLOR_ENDIAN_NO_SWAP
);
646 /* (fixed size) sarea is initialized to zero afaics so can omit version check. Phew! */
647 if (rmesa
->sarea
->tiling_enabled
) {
648 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_COLORPITCH
] |= R200_COLOR_TILE_ENABLE
;
651 rmesa
->hw
.prf
.cmd
[PRF_PP_TRI_PERF
] = R200_TRI_CUTOFF_MASK
- R200_TRI_CUTOFF_MASK
*
652 driQueryOptionf (&rmesa
->optionCache
,"texture_blend_quality");
653 rmesa
->hw
.prf
.cmd
[PRF_PP_PERF_CNTL
] = 0;
655 rmesa
->hw
.set
.cmd
[SET_SE_CNTL
] = (R200_FFACE_CULL_CCW
|
658 R200_FLAT_SHADE_VTX_LAST
|
659 R200_DIFFUSE_SHADE_GOURAUD
|
660 R200_ALPHA_SHADE_GOURAUD
|
661 R200_SPECULAR_SHADE_GOURAUD
|
662 R200_FOG_SHADE_GOURAUD
|
663 R200_DISC_FOG_SHADE_GOURAUD
|
664 R200_VTX_PIX_CENTER_OGL
|
665 R200_ROUND_MODE_TRUNC
|
666 R200_ROUND_PREC_8TH_PIX
);
668 rmesa
->hw
.set
.cmd
[SET_RE_CNTL
] = (R200_PERSPECTIVE_ENABLE
|
669 R200_SCISSOR_ENABLE
);
671 rmesa
->hw
.lin
.cmd
[LIN_RE_LINE_PATTERN
] = ((1 << 16) | 0xffff);
673 rmesa
->hw
.lin
.cmd
[LIN_RE_LINE_STATE
] =
674 ((0 << R200_LINE_CURRENT_PTR_SHIFT
) |
675 (1 << R200_LINE_CURRENT_COUNT_SHIFT
));
677 rmesa
->hw
.lin
.cmd
[LIN_SE_LINE_WIDTH
] = (1 << 4);
679 rmesa
->hw
.msk
.cmd
[MSK_RB3D_STENCILREFMASK
] =
680 ((0x00 << R200_STENCIL_REF_SHIFT
) |
681 (0xff << R200_STENCIL_MASK_SHIFT
) |
682 (0xff << R200_STENCIL_WRITEMASK_SHIFT
));
684 rmesa
->hw
.msk
.cmd
[MSK_RB3D_ROPCNTL
] = R200_ROP_COPY
;
685 rmesa
->hw
.msk
.cmd
[MSK_RB3D_PLANEMASK
] = 0xffffffff;
687 rmesa
->hw
.tam
.cmd
[TAM_DEBUG3
] = 0;
689 rmesa
->hw
.msc
.cmd
[MSC_RE_MISC
] =
690 ((0 << R200_STIPPLE_X_OFFSET_SHIFT
) |
691 (0 << R200_STIPPLE_Y_OFFSET_SHIFT
) |
692 R200_STIPPLE_BIG_BIT_ORDER
);
695 rmesa
->hw
.cst
.cmd
[CST_PP_CNTL_X
] = 0;
696 rmesa
->hw
.cst
.cmd
[CST_RB3D_DEPTHXY_OFFSET
] = 0;
697 rmesa
->hw
.cst
.cmd
[CST_RE_AUX_SCISSOR_CNTL
] = 0x0;
698 rmesa
->hw
.cst
.cmd
[CST_RE_SCISSOR_TL_0
] = 0;
699 rmesa
->hw
.cst
.cmd
[CST_RE_SCISSOR_BR_0
] = 0;
700 rmesa
->hw
.cst
.cmd
[CST_SE_VAP_CNTL_STATUS
] =
701 #ifdef MESA_BIG_ENDIAN
707 if (!(rmesa
->r200Screen
->chip_flags
& RADEON_CHIPSET_TCL
)) {
709 rmesa
->hw
.cst
.cmd
[CST_SE_VAP_CNTL_STATUS
] |= (1<<8);
712 rmesa
->hw
.cst
.cmd
[CST_RE_POINTSIZE
] =
713 (((GLuint
)(ctx
->Const
.MaxPointSize
* 16.0)) << R200_MAXPOINTSIZE_SHIFT
) | 0x10;
714 rmesa
->hw
.cst
.cmd
[CST_SE_TCL_INPUT_VTX_0
] =
715 (0x0 << R200_VERTEX_POSITION_ADDR__SHIFT
);
716 rmesa
->hw
.cst
.cmd
[CST_SE_TCL_INPUT_VTX_1
] =
717 (0x02 << R200_VTX_COLOR_0_ADDR__SHIFT
) |
718 (0x03 << R200_VTX_COLOR_1_ADDR__SHIFT
);
719 rmesa
->hw
.cst
.cmd
[CST_SE_TCL_INPUT_VTX_2
] =
720 (0x06 << R200_VTX_TEX_0_ADDR__SHIFT
) |
721 (0x07 << R200_VTX_TEX_1_ADDR__SHIFT
) |
722 (0x08 << R200_VTX_TEX_2_ADDR__SHIFT
) |
723 (0x09 << R200_VTX_TEX_3_ADDR__SHIFT
);
724 rmesa
->hw
.cst
.cmd
[CST_SE_TCL_INPUT_VTX_3
] =
725 (0x0A << R200_VTX_TEX_4_ADDR__SHIFT
) |
726 (0x0B << R200_VTX_TEX_5_ADDR__SHIFT
);
729 rmesa
->hw
.vpt
.cmd
[VPT_SE_VPORT_XSCALE
] = 0x00000000;
730 rmesa
->hw
.vpt
.cmd
[VPT_SE_VPORT_XOFFSET
] = 0x00000000;
731 rmesa
->hw
.vpt
.cmd
[VPT_SE_VPORT_YSCALE
] = 0x00000000;
732 rmesa
->hw
.vpt
.cmd
[VPT_SE_VPORT_YOFFSET
] = 0x00000000;
733 rmesa
->hw
.vpt
.cmd
[VPT_SE_VPORT_ZSCALE
] = 0x00000000;
734 rmesa
->hw
.vpt
.cmd
[VPT_SE_VPORT_ZOFFSET
] = 0x00000000;
736 for ( i
= 0 ; i
< ctx
->Const
.MaxTextureUnits
; i
++ ) {
737 rmesa
->hw
.tex
[i
].cmd
[TEX_PP_TXFILTER
] = R200_BORDER_MODE_OGL
;
738 rmesa
->hw
.tex
[i
].cmd
[TEX_PP_TXFORMAT
] =
739 ((i
<< R200_TXFORMAT_ST_ROUTE_SHIFT
) | /* <-- note i */
740 (2 << R200_TXFORMAT_WIDTH_SHIFT
) |
741 (2 << R200_TXFORMAT_HEIGHT_SHIFT
));
742 rmesa
->hw
.tex
[i
].cmd
[TEX_PP_BORDER_COLOR
] = 0;
743 rmesa
->hw
.tex
[i
].cmd
[TEX_PP_TXFORMAT_X
] =
744 (/* R200_TEXCOORD_PROJ | */
745 0x100000); /* Small default bias */
746 if (rmesa
->r200Screen
->drmSupportsFragShader
) {
747 rmesa
->hw
.tex
[i
].cmd
[TEX_PP_TXOFFSET_NEWDRM
] =
748 rmesa
->r200Screen
->texOffset
[RADEON_LOCAL_TEX_HEAP
];
749 rmesa
->hw
.tex
[i
].cmd
[TEX_PP_CUBIC_FACES
] = 0;
750 rmesa
->hw
.tex
[i
].cmd
[TEX_PP_TXMULTI_CTL
] = 0;
753 rmesa
->hw
.tex
[i
].cmd
[TEX_PP_TXOFFSET_OLDDRM
] =
754 rmesa
->r200Screen
->texOffset
[RADEON_LOCAL_TEX_HEAP
];
757 rmesa
->hw
.cube
[i
].cmd
[CUBE_PP_CUBIC_FACES
] = 0;
758 rmesa
->hw
.cube
[i
].cmd
[CUBE_PP_CUBIC_OFFSET_F1
] =
759 rmesa
->r200Screen
->texOffset
[RADEON_LOCAL_TEX_HEAP
];
760 rmesa
->hw
.cube
[i
].cmd
[CUBE_PP_CUBIC_OFFSET_F2
] =
761 rmesa
->r200Screen
->texOffset
[RADEON_LOCAL_TEX_HEAP
];
762 rmesa
->hw
.cube
[i
].cmd
[CUBE_PP_CUBIC_OFFSET_F3
] =
763 rmesa
->r200Screen
->texOffset
[RADEON_LOCAL_TEX_HEAP
];
764 rmesa
->hw
.cube
[i
].cmd
[CUBE_PP_CUBIC_OFFSET_F4
] =
765 rmesa
->r200Screen
->texOffset
[RADEON_LOCAL_TEX_HEAP
];
766 rmesa
->hw
.cube
[i
].cmd
[CUBE_PP_CUBIC_OFFSET_F5
] =
767 rmesa
->r200Screen
->texOffset
[RADEON_LOCAL_TEX_HEAP
];
769 rmesa
->hw
.pix
[i
].cmd
[PIX_PP_TXCBLEND
] =
770 (R200_TXC_ARG_A_ZERO
|
771 R200_TXC_ARG_B_ZERO
|
772 R200_TXC_ARG_C_DIFFUSE_COLOR
|
775 rmesa
->hw
.pix
[i
].cmd
[PIX_PP_TXCBLEND2
] =
776 ((i
<< R200_TXC_TFACTOR_SEL_SHIFT
) |
779 R200_TXC_OUTPUT_REG_R0
);
781 rmesa
->hw
.pix
[i
].cmd
[PIX_PP_TXABLEND
] =
782 (R200_TXA_ARG_A_ZERO
|
783 R200_TXA_ARG_B_ZERO
|
784 R200_TXA_ARG_C_DIFFUSE_ALPHA
|
787 rmesa
->hw
.pix
[i
].cmd
[PIX_PP_TXABLEND2
] =
788 ((i
<< R200_TXA_TFACTOR_SEL_SHIFT
) |
791 R200_TXA_OUTPUT_REG_R0
);
794 rmesa
->hw
.tf
.cmd
[TF_TFACTOR_0
] = 0;
795 rmesa
->hw
.tf
.cmd
[TF_TFACTOR_1
] = 0;
796 rmesa
->hw
.tf
.cmd
[TF_TFACTOR_2
] = 0;
797 rmesa
->hw
.tf
.cmd
[TF_TFACTOR_3
] = 0;
798 rmesa
->hw
.tf
.cmd
[TF_TFACTOR_4
] = 0;
799 rmesa
->hw
.tf
.cmd
[TF_TFACTOR_5
] = 0;
801 rmesa
->hw
.vap
.cmd
[VAP_SE_VAP_CNTL
] =
802 (R200_VAP_TCL_ENABLE
|
803 (0x9 << R200_VAP_VF_MAX_VTX_NUM__SHIFT
));
805 rmesa
->hw
.vte
.cmd
[VTE_SE_VTE_CNTL
] =
806 (R200_VPORT_X_SCALE_ENA
|
807 R200_VPORT_Y_SCALE_ENA
|
808 R200_VPORT_Z_SCALE_ENA
|
809 R200_VPORT_X_OFFSET_ENA
|
810 R200_VPORT_Y_OFFSET_ENA
|
811 R200_VPORT_Z_OFFSET_ENA
|
812 /* FIXME: Turn on for tex rect only */
813 R200_VTX_ST_DENORMALIZED
|
817 rmesa
->hw
.vtx
.cmd
[VTX_VTXFMT_0
] = 0;
818 rmesa
->hw
.vtx
.cmd
[VTX_VTXFMT_1
] = 0;
819 rmesa
->hw
.vtx
.cmd
[VTX_TCL_OUTPUT_VTXFMT_0
] =
820 ((R200_VTX_Z0
| R200_VTX_W0
|
821 (R200_VTX_FP_RGBA
<< R200_VTX_COLOR_0_SHIFT
)));
822 rmesa
->hw
.vtx
.cmd
[VTX_TCL_OUTPUT_VTXFMT_1
] = 0;
823 rmesa
->hw
.vtx
.cmd
[VTX_TCL_OUTPUT_COMPSEL
] = (R200_OUTPUT_XYZW
);
824 rmesa
->hw
.vtx
.cmd
[VTX_STATE_CNTL
] = R200_VSC_UPDATE_USER_COLOR_0_ENABLE
;
827 /* Matrix selection */
828 rmesa
->hw
.msl
.cmd
[MSL_MATRIX_SELECT_0
] =
829 (R200_MTX_MV
<< R200_MODELVIEW_0_SHIFT
);
831 rmesa
->hw
.msl
.cmd
[MSL_MATRIX_SELECT_1
] =
832 (R200_MTX_IMV
<< R200_IT_MODELVIEW_0_SHIFT
);
834 rmesa
->hw
.msl
.cmd
[MSL_MATRIX_SELECT_2
] =
835 (R200_MTX_MVP
<< R200_MODELPROJECT_0_SHIFT
);
837 rmesa
->hw
.msl
.cmd
[MSL_MATRIX_SELECT_3
] =
838 ((R200_MTX_TEX0
<< R200_TEXMAT_0_SHIFT
) |
839 (R200_MTX_TEX1
<< R200_TEXMAT_1_SHIFT
) |
840 (R200_MTX_TEX2
<< R200_TEXMAT_2_SHIFT
) |
841 (R200_MTX_TEX3
<< R200_TEXMAT_3_SHIFT
));
843 rmesa
->hw
.msl
.cmd
[MSL_MATRIX_SELECT_4
] =
844 ((R200_MTX_TEX4
<< R200_TEXMAT_4_SHIFT
) |
845 (R200_MTX_TEX5
<< R200_TEXMAT_5_SHIFT
));
848 /* General TCL state */
849 rmesa
->hw
.tcl
.cmd
[TCL_LIGHT_MODEL_CTL_0
] =
850 (R200_SPECULAR_LIGHTS
|
851 R200_DIFFUSE_SPECULAR_COMBINE
|
852 R200_LOCAL_LIGHT_VEC_GL
|
853 R200_LM0_SOURCE_MATERIAL_0
<< R200_FRONT_SHININESS_SOURCE_SHIFT
|
854 R200_LM0_SOURCE_MATERIAL_1
<< R200_BACK_SHININESS_SOURCE_SHIFT
);
856 rmesa
->hw
.tcl
.cmd
[TCL_LIGHT_MODEL_CTL_1
] =
857 ((R200_LM1_SOURCE_MATERIAL_0
<< R200_FRONT_EMISSIVE_SOURCE_SHIFT
) |
858 (R200_LM1_SOURCE_MATERIAL_0
<< R200_FRONT_AMBIENT_SOURCE_SHIFT
) |
859 (R200_LM1_SOURCE_MATERIAL_0
<< R200_FRONT_DIFFUSE_SOURCE_SHIFT
) |
860 (R200_LM1_SOURCE_MATERIAL_0
<< R200_FRONT_SPECULAR_SOURCE_SHIFT
) |
861 (R200_LM1_SOURCE_MATERIAL_1
<< R200_BACK_EMISSIVE_SOURCE_SHIFT
) |
862 (R200_LM1_SOURCE_MATERIAL_1
<< R200_BACK_AMBIENT_SOURCE_SHIFT
) |
863 (R200_LM1_SOURCE_MATERIAL_1
<< R200_BACK_DIFFUSE_SOURCE_SHIFT
) |
864 (R200_LM1_SOURCE_MATERIAL_1
<< R200_BACK_SPECULAR_SOURCE_SHIFT
));
866 rmesa
->hw
.tcl
.cmd
[TCL_PER_LIGHT_CTL_0
] = 0; /* filled in via callbacks */
867 rmesa
->hw
.tcl
.cmd
[TCL_PER_LIGHT_CTL_1
] = 0;
868 rmesa
->hw
.tcl
.cmd
[TCL_PER_LIGHT_CTL_2
] = 0;
869 rmesa
->hw
.tcl
.cmd
[TCL_PER_LIGHT_CTL_3
] = 0;
871 rmesa
->hw
.tcl
.cmd
[TCL_UCP_VERT_BLEND_CTL
] =
872 (R200_UCP_IN_CLIP_SPACE
|
873 R200_CULL_FRONT_IS_CCW
);
875 /* Texgen/Texmat state */
876 rmesa
->hw
.tcg
.cmd
[TCG_TEX_PROC_CTL_2
] = 0x00ffffff;
877 rmesa
->hw
.tcg
.cmd
[TCG_TEX_PROC_CTL_3
] =
878 ((0 << R200_TEXGEN_0_INPUT_TEX_SHIFT
) |
879 (1 << R200_TEXGEN_1_INPUT_TEX_SHIFT
) |
880 (2 << R200_TEXGEN_2_INPUT_TEX_SHIFT
) |
881 (3 << R200_TEXGEN_3_INPUT_TEX_SHIFT
) |
882 (4 << R200_TEXGEN_4_INPUT_TEX_SHIFT
) |
883 (5 << R200_TEXGEN_5_INPUT_TEX_SHIFT
));
884 rmesa
->hw
.tcg
.cmd
[TCG_TEX_PROC_CTL_0
] = 0;
885 rmesa
->hw
.tcg
.cmd
[TCG_TEX_PROC_CTL_1
] =
886 ((0 << R200_TEXGEN_0_INPUT_SHIFT
) |
887 (1 << R200_TEXGEN_1_INPUT_SHIFT
) |
888 (2 << R200_TEXGEN_2_INPUT_SHIFT
) |
889 (3 << R200_TEXGEN_3_INPUT_SHIFT
) |
890 (4 << R200_TEXGEN_4_INPUT_SHIFT
) |
891 (5 << R200_TEXGEN_5_INPUT_SHIFT
));
892 rmesa
->hw
.tcg
.cmd
[TCG_TEX_CYL_WRAP_CTL
] = 0;
895 for (i
= 0 ; i
< 8; i
++) {
896 struct gl_light
*l
= &ctx
->Light
.Light
[i
];
897 GLenum p
= GL_LIGHT0
+ i
;
898 *(float *)&(rmesa
->hw
.lit
[i
].cmd
[LIT_RANGE_CUTOFF
]) = FLT_MAX
;
900 ctx
->Driver
.Lightfv( ctx
, p
, GL_AMBIENT
, l
->Ambient
);
901 ctx
->Driver
.Lightfv( ctx
, p
, GL_DIFFUSE
, l
->Diffuse
);
902 ctx
->Driver
.Lightfv( ctx
, p
, GL_SPECULAR
, l
->Specular
);
903 ctx
->Driver
.Lightfv( ctx
, p
, GL_POSITION
, NULL
);
904 ctx
->Driver
.Lightfv( ctx
, p
, GL_SPOT_DIRECTION
, NULL
);
905 ctx
->Driver
.Lightfv( ctx
, p
, GL_SPOT_EXPONENT
, &l
->SpotExponent
);
906 ctx
->Driver
.Lightfv( ctx
, p
, GL_SPOT_CUTOFF
, &l
->SpotCutoff
);
907 ctx
->Driver
.Lightfv( ctx
, p
, GL_CONSTANT_ATTENUATION
,
908 &l
->ConstantAttenuation
);
909 ctx
->Driver
.Lightfv( ctx
, p
, GL_LINEAR_ATTENUATION
,
910 &l
->LinearAttenuation
);
911 ctx
->Driver
.Lightfv( ctx
, p
, GL_QUADRATIC_ATTENUATION
,
912 &l
->QuadraticAttenuation
);
913 *(float *)&(rmesa
->hw
.lit
[i
].cmd
[LIT_ATTEN_XXX
]) = 0.0;
916 ctx
->Driver
.LightModelfv( ctx
, GL_LIGHT_MODEL_AMBIENT
,
917 ctx
->Light
.Model
.Ambient
);
919 TNL_CONTEXT(ctx
)->Driver
.NotifyMaterialChange( ctx
);
921 for (i
= 0 ; i
< 6; i
++) {
922 ctx
->Driver
.ClipPlane( ctx
, GL_CLIP_PLANE0
+ i
, NULL
);
925 ctx
->Driver
.Fogfv( ctx
, GL_FOG_MODE
, NULL
);
926 ctx
->Driver
.Fogfv( ctx
, GL_FOG_DENSITY
, &ctx
->Fog
.Density
);
927 ctx
->Driver
.Fogfv( ctx
, GL_FOG_START
, &ctx
->Fog
.Start
);
928 ctx
->Driver
.Fogfv( ctx
, GL_FOG_END
, &ctx
->Fog
.End
);
929 ctx
->Driver
.Fogfv( ctx
, GL_FOG_COLOR
, ctx
->Fog
.Color
);
930 ctx
->Driver
.Fogfv( ctx
, GL_FOG_COORDINATE_SOURCE_EXT
, NULL
);
932 rmesa
->hw
.grd
.cmd
[GRD_VERT_GUARD_CLIP_ADJ
] = IEEE_ONE
;
933 rmesa
->hw
.grd
.cmd
[GRD_VERT_GUARD_DISCARD_ADJ
] = IEEE_ONE
;
934 rmesa
->hw
.grd
.cmd
[GRD_HORZ_GUARD_CLIP_ADJ
] = IEEE_ONE
;
935 rmesa
->hw
.grd
.cmd
[GRD_HORZ_GUARD_DISCARD_ADJ
] = IEEE_ONE
;
937 rmesa
->hw
.eye
.cmd
[EYE_X
] = 0;
938 rmesa
->hw
.eye
.cmd
[EYE_Y
] = 0;
939 rmesa
->hw
.eye
.cmd
[EYE_Z
] = IEEE_ONE
;
940 rmesa
->hw
.eye
.cmd
[EYE_RESCALE_FACTOR
] = IEEE_ONE
;
942 rmesa
->hw
.spr
.cmd
[SPR_POINT_SPRITE_CNTL
] =
943 R200_PS_SE_SEL_STATE
| R200_PS_MULT_CONST
;
945 /* ptp_eye is presumably used to calculate the attenuation wrt a different
946 location? In any case, since point attenuation triggers _needeyecoords,
947 it is constant. Probably ignored as long as R200_PS_USE_MODEL_EYE_VEC
949 rmesa
->hw
.ptp
.cmd
[PTP_EYE_X
] = 0;
950 rmesa
->hw
.ptp
.cmd
[PTP_EYE_Y
] = 0;
951 rmesa
->hw
.ptp
.cmd
[PTP_EYE_Z
] = IEEE_ONE
| 0x80000000; /* -1.0 */
952 rmesa
->hw
.ptp
.cmd
[PTP_EYE_3
] = 0;
953 /* no idea what the ptp_vport_scale values are good for, except the
954 PTSIZE one - hopefully doesn't matter */
955 rmesa
->hw
.ptp
.cmd
[PTP_VPORT_SCALE_0
] = IEEE_ONE
;
956 rmesa
->hw
.ptp
.cmd
[PTP_VPORT_SCALE_1
] = IEEE_ONE
;
957 rmesa
->hw
.ptp
.cmd
[PTP_VPORT_SCALE_PTSIZE
] = IEEE_ONE
;
958 rmesa
->hw
.ptp
.cmd
[PTP_VPORT_SCALE_3
] = IEEE_ONE
;
959 rmesa
->hw
.ptp
.cmd
[PTP_ATT_CONST_QUAD
] = 0;
960 rmesa
->hw
.ptp
.cmd
[PTP_ATT_CONST_LIN
] = 0;
961 rmesa
->hw
.ptp
.cmd
[PTP_ATT_CONST_CON
] = IEEE_ONE
;
962 rmesa
->hw
.ptp
.cmd
[PTP_ATT_CONST_3
] = 0;
963 rmesa
->hw
.ptp
.cmd
[PTP_CLAMP_MIN
] = IEEE_ONE
;
964 rmesa
->hw
.ptp
.cmd
[PTP_CLAMP_MAX
] = 0x44ffe000; /* 2047 */
965 rmesa
->hw
.ptp
.cmd
[PTP_CLAMP_2
] = 0;
966 rmesa
->hw
.ptp
.cmd
[PTP_CLAMP_3
] = 0;
968 r200LightingSpaceChange( ctx
);
970 rmesa
->hw
.all_dirty
= GL_TRUE
;