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[mesa.git] / src / mesa / drivers / dri / r200 / r200_state_init.c
1 /*
2 Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
3
4 The Weather Channel (TM) funded Tungsten Graphics to develop the
5 initial release of the Radeon 8500 driver under the XFree86 license.
6 This notice must be preserved.
7
8 Permission is hereby granted, free of charge, to any person obtaining
9 a copy of this software and associated documentation files (the
10 "Software"), to deal in the Software without restriction, including
11 without limitation the rights to use, copy, modify, merge, publish,
12 distribute, sublicense, and/or sell copies of the Software, and to
13 permit persons to whom the Software is furnished to do so, subject to
14 the following conditions:
15
16 The above copyright notice and this permission notice (including the
17 next paragraph) shall be included in all copies or substantial
18 portions of the Software.
19
20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 */
28
29 /*
30 * Authors:
31 * Keith Whitwell <keith@tungstengraphics.com>
32 */
33
34 #include "main/glheader.h"
35 #include "main/imports.h"
36 #include "main/enums.h"
37 #include "main/colormac.h"
38 #include "main/api_arrayelt.h"
39
40 #include "swrast/swrast.h"
41 #include "vbo/vbo.h"
42 #include "tnl/tnl.h"
43 #include "tnl/t_pipeline.h"
44 #include "swrast_setup/swrast_setup.h"
45
46 #include "radeon_common.h"
47 #include "radeon_mipmap_tree.h"
48 #include "r200_context.h"
49 #include "r200_ioctl.h"
50 #include "r200_state.h"
51 #include "r200_tcl.h"
52 #include "r200_tex.h"
53 #include "r200_swtcl.h"
54
55 #include "xmlpool.h"
56
57 /* New (1.3) state mechanism. 3 commands (packet, scalar, vector) in
58 * 1.3 cmdbuffers allow all previous state to be updated as well as
59 * the tcl scalar and vector areas.
60 */
61 static struct {
62 int start;
63 int len;
64 const char *name;
65 } packet[RADEON_MAX_STATE_PACKETS] = {
66 {RADEON_PP_MISC, 7, "RADEON_PP_MISC"},
67 {RADEON_PP_CNTL, 3, "RADEON_PP_CNTL"},
68 {RADEON_RB3D_COLORPITCH, 1, "RADEON_RB3D_COLORPITCH"},
69 {RADEON_RE_LINE_PATTERN, 2, "RADEON_RE_LINE_PATTERN"},
70 {RADEON_SE_LINE_WIDTH, 1, "RADEON_SE_LINE_WIDTH"},
71 {RADEON_PP_LUM_MATRIX, 1, "RADEON_PP_LUM_MATRIX"},
72 {RADEON_PP_ROT_MATRIX_0, 2, "RADEON_PP_ROT_MATRIX_0"},
73 {RADEON_RB3D_STENCILREFMASK, 3, "RADEON_RB3D_STENCILREFMASK"},
74 {RADEON_SE_VPORT_XSCALE, 6, "RADEON_SE_VPORT_XSCALE"},
75 {RADEON_SE_CNTL, 2, "RADEON_SE_CNTL"},
76 {RADEON_SE_CNTL_STATUS, 1, "RADEON_SE_CNTL_STATUS"},
77 {RADEON_RE_MISC, 1, "RADEON_RE_MISC"},
78 {RADEON_PP_TXFILTER_0, 6, "RADEON_PP_TXFILTER_0"},
79 {RADEON_PP_BORDER_COLOR_0, 1, "RADEON_PP_BORDER_COLOR_0"},
80 {RADEON_PP_TXFILTER_1, 6, "RADEON_PP_TXFILTER_1"},
81 {RADEON_PP_BORDER_COLOR_1, 1, "RADEON_PP_BORDER_COLOR_1"},
82 {RADEON_PP_TXFILTER_2, 6, "RADEON_PP_TXFILTER_2"},
83 {RADEON_PP_BORDER_COLOR_2, 1, "RADEON_PP_BORDER_COLOR_2"},
84 {RADEON_SE_ZBIAS_FACTOR, 2, "RADEON_SE_ZBIAS_FACTOR"},
85 {RADEON_SE_TCL_OUTPUT_VTX_FMT, 11, "RADEON_SE_TCL_OUTPUT_VTX_FMT"},
86 {RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED, 17,
87 "RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED"},
88 {R200_PP_TXCBLEND_0, 4, "R200_PP_TXCBLEND_0"},
89 {R200_PP_TXCBLEND_1, 4, "R200_PP_TXCBLEND_1"},
90 {R200_PP_TXCBLEND_2, 4, "R200_PP_TXCBLEND_2"},
91 {R200_PP_TXCBLEND_3, 4, "R200_PP_TXCBLEND_3"},
92 {R200_PP_TXCBLEND_4, 4, "R200_PP_TXCBLEND_4"},
93 {R200_PP_TXCBLEND_5, 4, "R200_PP_TXCBLEND_5"},
94 {R200_PP_TXCBLEND_6, 4, "R200_PP_TXCBLEND_6"},
95 {R200_PP_TXCBLEND_7, 4, "R200_PP_TXCBLEND_7"},
96 {R200_SE_TCL_LIGHT_MODEL_CTL_0, 6, "R200_SE_TCL_LIGHT_MODEL_CTL_0"},
97 {R200_PP_TFACTOR_0, 6, "R200_PP_TFACTOR_0"},
98 {R200_SE_VTX_FMT_0, 4, "R200_SE_VTX_FMT_0"},
99 {R200_SE_VAP_CNTL, 1, "R200_SE_VAP_CNTL"},
100 {R200_SE_TCL_MATRIX_SEL_0, 5, "R200_SE_TCL_MATRIX_SEL_0"},
101 {R200_SE_TCL_TEX_PROC_CTL_2, 5, "R200_SE_TCL_TEX_PROC_CTL_2"},
102 {R200_SE_TCL_UCP_VERT_BLEND_CTL, 1, "R200_SE_TCL_UCP_VERT_BLEND_CTL"},
103 {R200_PP_TXFILTER_0, 6, "R200_PP_TXFILTER_0"},
104 {R200_PP_TXFILTER_1, 6, "R200_PP_TXFILTER_1"},
105 {R200_PP_TXFILTER_2, 6, "R200_PP_TXFILTER_2"},
106 {R200_PP_TXFILTER_3, 6, "R200_PP_TXFILTER_3"},
107 {R200_PP_TXFILTER_4, 6, "R200_PP_TXFILTER_4"},
108 {R200_PP_TXFILTER_5, 6, "R200_PP_TXFILTER_5"},
109 {R200_PP_TXOFFSET_0, 1, "R200_PP_TXOFFSET_0"},
110 {R200_PP_TXOFFSET_1, 1, "R200_PP_TXOFFSET_1"},
111 {R200_PP_TXOFFSET_2, 1, "R200_PP_TXOFFSET_2"},
112 {R200_PP_TXOFFSET_3, 1, "R200_PP_TXOFFSET_3"},
113 {R200_PP_TXOFFSET_4, 1, "R200_PP_TXOFFSET_4"},
114 {R200_PP_TXOFFSET_5, 1, "R200_PP_TXOFFSET_5"},
115 {R200_SE_VTE_CNTL, 1, "R200_SE_VTE_CNTL"},
116 {R200_SE_TCL_OUTPUT_VTX_COMP_SEL, 1,
117 "R200_SE_TCL_OUTPUT_VTX_COMP_SEL"},
118 {R200_PP_TAM_DEBUG3, 1, "R200_PP_TAM_DEBUG3"},
119 {R200_PP_CNTL_X, 1, "R200_PP_CNTL_X"},
120 {R200_RB3D_DEPTHXY_OFFSET, 1, "R200_RB3D_DEPTHXY_OFFSET"},
121 {R200_RE_AUX_SCISSOR_CNTL, 1, "R200_RE_AUX_SCISSOR_CNTL"},
122 {R200_RE_SCISSOR_TL_0, 2, "R200_RE_SCISSOR_TL_0"},
123 {R200_RE_SCISSOR_TL_1, 2, "R200_RE_SCISSOR_TL_1"},
124 {R200_RE_SCISSOR_TL_2, 2, "R200_RE_SCISSOR_TL_2"},
125 {R200_SE_VAP_CNTL_STATUS, 1, "R200_SE_VAP_CNTL_STATUS"},
126 {R200_SE_VTX_STATE_CNTL, 1, "R200_SE_VTX_STATE_CNTL"},
127 {R200_RE_POINTSIZE, 1, "R200_RE_POINTSIZE"},
128 {R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0, 4,
129 "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0"},
130 {R200_PP_CUBIC_FACES_0, 1, "R200_PP_CUBIC_FACES_0"}, /* 61 */
131 {R200_PP_CUBIC_OFFSET_F1_0, 5, "R200_PP_CUBIC_OFFSET_F1_0"}, /* 62 */
132 {R200_PP_CUBIC_FACES_1, 1, "R200_PP_CUBIC_FACES_1"},
133 {R200_PP_CUBIC_OFFSET_F1_1, 5, "R200_PP_CUBIC_OFFSET_F1_1"},
134 {R200_PP_CUBIC_FACES_2, 1, "R200_PP_CUBIC_FACES_2"},
135 {R200_PP_CUBIC_OFFSET_F1_2, 5, "R200_PP_CUBIC_OFFSET_F1_2"},
136 {R200_PP_CUBIC_FACES_3, 1, "R200_PP_CUBIC_FACES_3"},
137 {R200_PP_CUBIC_OFFSET_F1_3, 5, "R200_PP_CUBIC_OFFSET_F1_3"},
138 {R200_PP_CUBIC_FACES_4, 1, "R200_PP_CUBIC_FACES_4"},
139 {R200_PP_CUBIC_OFFSET_F1_4, 5, "R200_PP_CUBIC_OFFSET_F1_4"},
140 {R200_PP_CUBIC_FACES_5, 1, "R200_PP_CUBIC_FACES_5"},
141 {R200_PP_CUBIC_OFFSET_F1_5, 5, "R200_PP_CUBIC_OFFSET_F1_5"},
142 {RADEON_PP_TEX_SIZE_0, 2, "RADEON_PP_TEX_SIZE_0"},
143 {RADEON_PP_TEX_SIZE_1, 2, "RADEON_PP_TEX_SIZE_1"},
144 {RADEON_PP_TEX_SIZE_2, 2, "RADEON_PP_TEX_SIZE_2"},
145 {R200_RB3D_BLENDCOLOR, 3, "R200_RB3D_BLENDCOLOR"},
146 {R200_SE_TCL_POINT_SPRITE_CNTL, 1, "R200_SE_TCL_POINT_SPRITE_CNTL"},
147 {RADEON_PP_CUBIC_FACES_0, 1, "RADEON_PP_CUBIC_FACES_0"},
148 {RADEON_PP_CUBIC_OFFSET_T0_0, 5, "RADEON_PP_CUBIC_OFFSET_T0_0"},
149 {RADEON_PP_CUBIC_FACES_1, 1, "RADEON_PP_CUBIC_FACES_1"},
150 {RADEON_PP_CUBIC_OFFSET_T1_0, 5, "RADEON_PP_CUBIC_OFFSET_T1_0"},
151 {RADEON_PP_CUBIC_FACES_2, 1, "RADEON_PP_CUBIC_FACES_2"},
152 {RADEON_PP_CUBIC_OFFSET_T2_0, 5, "RADEON_PP_CUBIC_OFFSET_T2_0"},
153 {R200_PP_TRI_PERF, 2, "R200_PP_TRI_PERF"},
154 {R200_PP_TXCBLEND_8, 32, "R200_PP_AFS_0"}, /* 85 */
155 {R200_PP_TXCBLEND_0, 32, "R200_PP_AFS_1"},
156 {R200_PP_TFACTOR_0, 8, "R200_ATF_TFACTOR"},
157 {R200_PP_TXFILTER_0, 8, "R200_PP_TXCTLALL_0"},
158 {R200_PP_TXFILTER_1, 8, "R200_PP_TXCTLALL_1"},
159 {R200_PP_TXFILTER_2, 8, "R200_PP_TXCTLALL_2"},
160 {R200_PP_TXFILTER_3, 8, "R200_PP_TXCTLALL_3"},
161 {R200_PP_TXFILTER_4, 8, "R200_PP_TXCTLALL_4"},
162 {R200_PP_TXFILTER_5, 8, "R200_PP_TXCTLALL_5"},
163 {R200_VAP_PVS_CNTL_1, 2, "R200_VAP_PVS_CNTL"},
164 };
165
166 /* =============================================================
167 * State initialization
168 */
169
170 void r200PrintDirty( r200ContextPtr rmesa, const char *msg )
171 {
172 struct radeon_state_atom *l;
173
174 fprintf(stderr, msg);
175 fprintf(stderr, ": ");
176
177 foreach(l, &rmesa->radeon.hw.atomlist) {
178 if (l->dirty || rmesa->radeon.hw.all_dirty)
179 fprintf(stderr, "%s, ", l->name);
180 }
181
182 fprintf(stderr, "\n");
183 }
184
185 static int cmdpkt( r200ContextPtr rmesa, int id )
186 {
187 drm_radeon_cmd_header_t h;
188
189 if (rmesa->radeon.radeonScreen->kernel_mm) {
190 return CP_PACKET0(packet[id].start, packet[id].len - 1);
191 } else {
192 h.i = 0;
193 h.packet.cmd_type = RADEON_CMD_PACKET;
194 h.packet.packet_id = id;
195 }
196 return h.i;
197 }
198
199 static int cmdvec( int offset, int stride, int count )
200 {
201 drm_radeon_cmd_header_t h;
202 h.i = 0;
203 h.vectors.cmd_type = RADEON_CMD_VECTORS;
204 h.vectors.offset = offset;
205 h.vectors.stride = stride;
206 h.vectors.count = count;
207 return h.i;
208 }
209
210 /* warning: the count here is divided by 4 compared to other cmds
211 (so it doesn't exceed the char size)! */
212 static int cmdveclinear( int offset, int count )
213 {
214 drm_radeon_cmd_header_t h;
215 h.i = 0;
216 h.veclinear.cmd_type = RADEON_CMD_VECLINEAR;
217 h.veclinear.addr_lo = offset & 0xff;
218 h.veclinear.addr_hi = (offset & 0xff00) >> 8;
219 h.veclinear.count = count;
220 return h.i;
221 }
222
223 static int cmdscl( int offset, int stride, int count )
224 {
225 drm_radeon_cmd_header_t h;
226 h.i = 0;
227 h.scalars.cmd_type = RADEON_CMD_SCALARS;
228 h.scalars.offset = offset;
229 h.scalars.stride = stride;
230 h.scalars.count = count;
231 return h.i;
232 }
233
234 static int cmdscl2( int offset, int stride, int count )
235 {
236 drm_radeon_cmd_header_t h;
237 h.i = 0;
238 h.scalars.cmd_type = RADEON_CMD_SCALARS2;
239 h.scalars.offset = offset - 0x100;
240 h.scalars.stride = stride;
241 h.scalars.count = count;
242 return h.i;
243 }
244
245 #define CHECK( NM, FLAG ) \
246 static int check_##NM( GLcontext *ctx, struct radeon_state_atom *atom) \
247 { \
248 r200ContextPtr rmesa = R200_CONTEXT(ctx); \
249 (void) rmesa; \
250 return (FLAG) ? atom->cmd_size : 0; \
251 }
252
253 #define TCL_CHECK( NM, FLAG ) \
254 static int check_##NM( GLcontext *ctx, struct radeon_state_atom *atom) \
255 { \
256 r200ContextPtr rmesa = R200_CONTEXT(ctx); \
257 return (!rmesa->radeon.TclFallback && !ctx->VertexProgram._Enabled && (FLAG)) ? atom->cmd_size : 0; \
258 }
259
260 #define TCL_OR_VP_CHECK( NM, FLAG ) \
261 static int check_##NM( GLcontext *ctx, struct radeon_state_atom *atom ) \
262 { \
263 r200ContextPtr rmesa = R200_CONTEXT(ctx); \
264 return (!rmesa->radeon.TclFallback && (FLAG)) ? atom->cmd_size : 0; \
265 }
266
267 #define VP_CHECK( NM, FLAG ) \
268 static int check_##NM( GLcontext *ctx, struct radeon_state_atom *atom ) \
269 { \
270 r200ContextPtr rmesa = R200_CONTEXT(ctx); \
271 (void) atom; \
272 return (!rmesa->radeon.TclFallback && ctx->VertexProgram._Enabled && (FLAG)) ? atom->cmd_size : 0; \
273 }
274
275 CHECK( always, GL_TRUE )
276 CHECK( never, GL_FALSE )
277 CHECK( tex_any, ctx->Texture._EnabledUnits )
278 CHECK( tf, (ctx->Texture._EnabledUnits && !ctx->ATIFragmentShader._Enabled) );
279 CHECK( tex_pair, (rmesa->state.texture.unit[atom->idx].unitneeded | rmesa->state.texture.unit[atom->idx & ~1].unitneeded) )
280 CHECK( tex, rmesa->state.texture.unit[atom->idx].unitneeded )
281 CHECK( pix_zero, !ctx->ATIFragmentShader._Enabled )
282 CHECK( texenv, (rmesa->state.envneeded & (1 << (atom->idx)) && !ctx->ATIFragmentShader._Enabled) )
283 CHECK( afs_pass1, (ctx->ATIFragmentShader._Enabled && (ctx->ATIFragmentShader.Current->NumPasses > 1)) )
284 CHECK( afs, ctx->ATIFragmentShader._Enabled )
285 CHECK( tex_cube, rmesa->state.texture.unit[atom->idx].unitneeded & TEXTURE_CUBE_BIT )
286 TCL_CHECK( tcl_fog, ctx->Fog.Enabled )
287 TCL_CHECK( tcl, GL_TRUE )
288 TCL_CHECK( tcl_tex, rmesa->state.texture.unit[atom->idx].unitneeded )
289 TCL_CHECK( tcl_lighting, ctx->Light.Enabled )
290 TCL_CHECK( tcl_light, ctx->Light.Enabled && ctx->Light.Light[atom->idx].Enabled )
291 TCL_OR_VP_CHECK( tcl_ucp, (ctx->Transform.ClipPlanesEnabled & (1 << (atom->idx))) )
292 TCL_OR_VP_CHECK( tcl_or_vp, GL_TRUE )
293 VP_CHECK( tcl_vp, GL_TRUE )
294 VP_CHECK( tcl_vp_size, ctx->VertexProgram.Current->Base.NumNativeInstructions > 64 )
295 VP_CHECK( tcl_vpp_size, ctx->VertexProgram.Current->Base.NumNativeParameters > 96 )
296
297 #define OUT_VEC(hdr, data) do { \
298 drm_radeon_cmd_header_t h; \
299 h.i = hdr; \
300 OUT_BATCH(CP_PACKET0(RADEON_SE_TCL_STATE_FLUSH, 0)); \
301 OUT_BATCH(0); \
302 OUT_BATCH(CP_PACKET0(R200_SE_TCL_VECTOR_INDX_REG, 0)); \
303 OUT_BATCH(h.vectors.offset | (h.vectors.stride << RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT)); \
304 OUT_BATCH(CP_PACKET0_ONE(R200_SE_TCL_VECTOR_DATA_REG, h.vectors.count - 1)); \
305 OUT_BATCH_TABLE((data), h.vectors.count); \
306 } while(0)
307
308 #define OUT_VECLINEAR(hdr, data) do { \
309 drm_radeon_cmd_header_t h; \
310 uint32_t _start = h.veclinear.addr_lo | (h.veclinear.addr_hi << 8); \
311 uint32_t _sz = h.veclinear.count * 4; \
312 h.i = hdr; \
313 OUT_BATCH(CP_PACKET0(RADEON_SE_TCL_STATE_FLUSH, 0)); \
314 OUT_BATCH(0); \
315 OUT_BATCH(CP_PACKET0(R200_SE_TCL_VECTOR_INDX_REG, 0)); \
316 OUT_BATCH(_start | (1 << RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT)); \
317 OUT_BATCH(CP_PACKET0_ONE(R200_SE_TCL_VECTOR_DATA_REG, _sz - 1)); \
318 OUT_BATCH_TABLE((data), _sz); \
319 } while(0)
320
321 #define OUT_SCL(hdr, data) do { \
322 drm_radeon_cmd_header_t h; \
323 h.i = hdr; \
324 OUT_BATCH(CP_PACKET0(R200_SE_TCL_SCALAR_INDX_REG, 0)); \
325 OUT_BATCH((h.scalars.offset) | (h.scalars.stride << RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT)); \
326 OUT_BATCH(CP_PACKET0_ONE(R200_SE_TCL_SCALAR_DATA_REG, h.scalars.count - 1)); \
327 OUT_BATCH_TABLE((data), h.scalars.count); \
328 } while(0)
329
330 #define OUT_SCL2(hdr, data) do { \
331 drm_radeon_cmd_header_t h; \
332 h.i = hdr; \
333 OUT_BATCH(CP_PACKET0(R200_SE_TCL_SCALAR_INDX_REG, 0)); \
334 OUT_BATCH((h.scalars.offset + 0x100) | (h.scalars.stride << RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT)); \
335 OUT_BATCH(CP_PACKET0_ONE(R200_SE_TCL_SCALAR_DATA_REG, h.scalars.count - 1)); \
336 OUT_BATCH_TABLE((data), h.scalars.count); \
337 } while(0)
338
339 static void mtl_emit(GLcontext *ctx, struct radeon_state_atom *atom)
340 {
341 r200ContextPtr r200 = R200_CONTEXT(ctx);
342 BATCH_LOCALS(&r200->radeon);
343 uint32_t dwords = atom->cmd_size;
344
345 dwords += 6;
346 BEGIN_BATCH_NO_AUTOSTATE(dwords);
347 OUT_VEC(atom->cmd[MTL_CMD_0], (atom->cmd+1));
348 OUT_SCL2(atom->cmd[MTL_CMD_1], (atom->cmd + 18));
349 END_BATCH();
350 }
351
352 static void lit_emit(GLcontext *ctx, struct radeon_state_atom *atom)
353 {
354 r200ContextPtr r200 = R200_CONTEXT(ctx);
355 BATCH_LOCALS(&r200->radeon);
356 uint32_t dwords = atom->cmd_size;
357
358 dwords += 8;
359 BEGIN_BATCH_NO_AUTOSTATE(dwords);
360 OUT_VEC(atom->cmd[LIT_CMD_0], atom->cmd+1);
361 OUT_VEC(atom->cmd[LIT_CMD_1], atom->cmd+LIT_CMD_1+1);
362 END_BATCH();
363 }
364
365 static void ptp_emit(GLcontext *ctx, struct radeon_state_atom *atom)
366 {
367 r200ContextPtr r200 = R200_CONTEXT(ctx);
368 BATCH_LOCALS(&r200->radeon);
369 uint32_t dwords = atom->cmd_size;
370
371 dwords += 8;
372 BEGIN_BATCH_NO_AUTOSTATE(dwords);
373 OUT_VEC(atom->cmd[PTP_CMD_0], atom->cmd+1);
374 OUT_VEC(atom->cmd[PTP_CMD_1], atom->cmd+PTP_CMD_1+1);
375 END_BATCH();
376 }
377
378 static void veclinear_emit(GLcontext *ctx, struct radeon_state_atom *atom)
379 {
380 r200ContextPtr r200 = R200_CONTEXT(ctx);
381 BATCH_LOCALS(&r200->radeon);
382 uint32_t dwords = atom->cmd_size;
383
384 dwords += 4;
385 BEGIN_BATCH_NO_AUTOSTATE(dwords);
386 OUT_VECLINEAR(atom->cmd[0], atom->cmd+1);
387 END_BATCH();
388 }
389
390 static void scl_emit(GLcontext *ctx, struct radeon_state_atom *atom)
391 {
392 r200ContextPtr r200 = R200_CONTEXT(ctx);
393 BATCH_LOCALS(&r200->radeon);
394 uint32_t dwords = atom->cmd_size;
395
396 dwords += 2;
397 BEGIN_BATCH_NO_AUTOSTATE(dwords);
398 OUT_SCL(atom->cmd[0], atom->cmd+1);
399 END_BATCH();
400 }
401
402
403 static void vec_emit(GLcontext *ctx, struct radeon_state_atom *atom)
404 {
405 r200ContextPtr r200 = R200_CONTEXT(ctx);
406 BATCH_LOCALS(&r200->radeon);
407 uint32_t dwords = atom->cmd_size;
408
409 dwords += 4;
410 BEGIN_BATCH_NO_AUTOSTATE(dwords);
411 OUT_VEC(atom->cmd[0], atom->cmd+1);
412 END_BATCH();
413 }
414
415 static void ctx_emit(GLcontext *ctx, struct radeon_state_atom *atom)
416 {
417 r200ContextPtr r200 = R200_CONTEXT(ctx);
418 BATCH_LOCALS(&r200->radeon);
419 struct radeon_renderbuffer *rrb;
420 uint32_t cbpitch;
421 uint32_t zbpitch, depth_fmt;
422 uint32_t dwords = atom->cmd_size;
423
424 /* output the first 7 bytes of context */
425 BEGIN_BATCH_NO_AUTOSTATE(dwords+2+2);
426 OUT_BATCH_TABLE(atom->cmd, 5);
427
428 rrb = radeon_get_depthbuffer(&r200->radeon);
429 if (!rrb) {
430 OUT_BATCH(0);
431 OUT_BATCH(0);
432 } else {
433 zbpitch = (rrb->pitch / rrb->cpp);
434 if (r200->using_hyperz)
435 zbpitch |= RADEON_DEPTH_HYPERZ;
436 OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
437 OUT_BATCH(zbpitch);
438 if (rrb->cpp == 4)
439 depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
440 else
441 depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
442 atom->cmd[CTX_RB3D_ZSTENCILCNTL] &= ~RADEON_DEPTH_FORMAT_MASK;
443 atom->cmd[CTX_RB3D_ZSTENCILCNTL] |= depth_fmt;
444 }
445
446 OUT_BATCH(atom->cmd[CTX_RB3D_ZSTENCILCNTL]);
447 OUT_BATCH(atom->cmd[CTX_CMD_1]);
448 OUT_BATCH(atom->cmd[CTX_PP_CNTL]);
449
450 rrb = radeon_get_colorbuffer(&r200->radeon);
451 if (!rrb || !rrb->bo) {
452 OUT_BATCH(atom->cmd[CTX_RB3D_CNTL]);
453 OUT_BATCH(atom->cmd[CTX_RB3D_COLOROFFSET]);
454 } else {
455 atom->cmd[CTX_RB3D_CNTL] &= ~(0xf << 10);
456 if (rrb->cpp == 4)
457 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB8888;
458 else
459 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_RGB565;
460
461 OUT_BATCH(atom->cmd[CTX_RB3D_CNTL]);
462 OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
463 }
464
465 OUT_BATCH(atom->cmd[CTX_CMD_2]);
466
467 if (!rrb || !rrb->bo) {
468 OUT_BATCH(atom->cmd[CTX_RB3D_COLORPITCH]);
469 } else {
470 cbpitch = (rrb->pitch / rrb->cpp);
471 if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE)
472 cbpitch |= R200_COLOR_TILE_ENABLE;
473 OUT_BATCH(cbpitch);
474 }
475
476 if (atom->cmd_size == CTX_STATE_SIZE_NEWDRM)
477 OUT_BATCH_TABLE((atom->cmd + 14), 4);
478
479 END_BATCH();
480 }
481
482 static void ctx_emit_cs(GLcontext *ctx, struct radeon_state_atom *atom)
483 {
484 r200ContextPtr r200 = R200_CONTEXT(ctx);
485 BATCH_LOCALS(&r200->radeon);
486 struct radeon_renderbuffer *rrb, *drb;
487 uint32_t cbpitch = 0;
488 uint32_t zbpitch = 0;
489 uint32_t dwords = atom->cmd_size;
490 uint32_t depth_fmt;
491
492 rrb = radeon_get_colorbuffer(&r200->radeon);
493 if (!rrb || !rrb->bo) {
494 return;
495 }
496
497 atom->cmd[CTX_RB3D_CNTL] &= ~(0xf << 10);
498 if (rrb->cpp == 4)
499 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB8888;
500 else
501 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_RGB565;
502
503 cbpitch = (rrb->pitch / rrb->cpp);
504 if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE)
505 cbpitch |= R200_COLOR_TILE_ENABLE;
506
507 drb = radeon_get_depthbuffer(&r200->radeon);
508 if (drb) {
509 zbpitch = (drb->pitch / drb->cpp);
510 if (drb->cpp == 4)
511 depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
512 else
513 depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
514 atom->cmd[CTX_RB3D_ZSTENCILCNTL] &= ~RADEON_DEPTH_FORMAT_MASK;
515 atom->cmd[CTX_RB3D_ZSTENCILCNTL] |= depth_fmt;
516 }
517
518 if (drb)
519 dwords += 4;
520 if (rrb)
521 dwords += 4;
522
523 /* output the first 7 bytes of context */
524 BEGIN_BATCH_NO_AUTOSTATE(dwords);
525
526 /* In the CS case we need to split this up */
527 OUT_BATCH(CP_PACKET0(packet[0].start, 3));
528 OUT_BATCH_TABLE((atom->cmd + 1), 4);
529
530 if (drb) {
531 OUT_BATCH(CP_PACKET0(RADEON_RB3D_DEPTHOFFSET, 0));
532 OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
533
534 OUT_BATCH(CP_PACKET0(RADEON_RB3D_DEPTHPITCH, 0));
535 OUT_BATCH(zbpitch);
536 }
537
538 OUT_BATCH(CP_PACKET0(RADEON_RB3D_ZSTENCILCNTL, 0));
539 OUT_BATCH(atom->cmd[CTX_RB3D_ZSTENCILCNTL]);
540 OUT_BATCH(CP_PACKET0(RADEON_PP_CNTL, 1));
541 OUT_BATCH(atom->cmd[CTX_PP_CNTL]);
542 OUT_BATCH(atom->cmd[CTX_RB3D_CNTL]);
543
544
545 if (rrb) {
546 OUT_BATCH(CP_PACKET0(RADEON_RB3D_COLOROFFSET, 0));
547 OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
548 }
549
550 if (rrb) {
551 OUT_BATCH(CP_PACKET0(RADEON_RB3D_COLORPITCH, 0));
552 OUT_BATCH(cbpitch);
553 }
554
555 if (atom->cmd_size == CTX_STATE_SIZE_NEWDRM) {
556 OUT_BATCH_TABLE((atom->cmd + 14), 4);
557 }
558
559 END_BATCH();
560 }
561
562 static void tex_emit(GLcontext *ctx, struct radeon_state_atom *atom)
563 {
564 r200ContextPtr r200 = R200_CONTEXT(ctx);
565 BATCH_LOCALS(&r200->radeon);
566 uint32_t dwords = atom->cmd_size;
567 int i = atom->idx;
568 radeonTexObj *t = r200->state.texture.unit[i].texobj;
569
570 if (t && t->mt && !t->image_override)
571 dwords += 2;
572 BEGIN_BATCH_NO_AUTOSTATE(dwords);
573 OUT_BATCH_TABLE(atom->cmd, 10);
574 if (t && !t->image_override) {
575 OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, 0,
576 RADEON_GEM_DOMAIN_VRAM, 0, 0);
577 } else if (!t) {
578 /* workaround for old CS mechanism */
579 OUT_BATCH(r200->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP]);
580 } else if (t->image_override)
581 OUT_BATCH(t->override_offset);
582
583 END_BATCH();
584 }
585
586 static void cube_emit(GLcontext *ctx, struct radeon_state_atom *atom)
587 {
588 r200ContextPtr r200 = R200_CONTEXT(ctx);
589 BATCH_LOCALS(&r200->radeon);
590 uint32_t dwords = atom->cmd_size;
591 int i = atom->idx;
592 radeonTexObj *t = r200->state.texture.unit[i].texobj;
593 GLuint size;
594
595 BEGIN_BATCH_NO_AUTOSTATE(dwords + (2 * 5));
596 OUT_BATCH_TABLE(atom->cmd, 3);
597
598 if (t && !t->image_override) {
599 size = t->mt->totalsize / 6;
600 OUT_BATCH_RELOC(0, t->mt->bo, size, RADEON_GEM_DOMAIN_VRAM, 0, 0);
601 OUT_BATCH_RELOC(0, t->mt->bo, size * 2, RADEON_GEM_DOMAIN_VRAM, 0, 0);
602 OUT_BATCH_RELOC(0, t->mt->bo, size * 3, RADEON_GEM_DOMAIN_VRAM, 0, 0);
603 OUT_BATCH_RELOC(0, t->mt->bo, size * 4, RADEON_GEM_DOMAIN_VRAM, 0, 0);
604 OUT_BATCH_RELOC(0, t->mt->bo, size * 5, RADEON_GEM_DOMAIN_VRAM, 0, 0);
605 }
606 END_BATCH();
607 }
608
609 /* Initialize the context's hardware state.
610 */
611 void r200InitState( r200ContextPtr rmesa )
612 {
613 GLcontext *ctx = rmesa->radeon.glCtx;
614 GLuint i;
615
616 rmesa->radeon.state.color.clear = 0x00000000;
617
618 switch ( ctx->Visual.depthBits ) {
619 case 16:
620 rmesa->radeon.state.depth.clear = 0x0000ffff;
621 rmesa->radeon.state.depth.scale = 1.0 / (GLfloat)0xffff;
622 rmesa->radeon.state.stencil.clear = 0x00000000;
623 break;
624 case 24:
625 rmesa->radeon.state.depth.clear = 0x00ffffff;
626 rmesa->radeon.state.depth.scale = 1.0 / (GLfloat)0xffffff;
627 rmesa->radeon.state.stencil.clear = 0xffff0000;
628 break;
629 default:
630 fprintf( stderr, "Error: Unsupported depth %d... exiting\n",
631 ctx->Visual.depthBits );
632 exit( -1 );
633 }
634
635 /* Only have hw stencil when depth buffer is 24 bits deep */
636 rmesa->radeon.state.stencil.hwBuffer = ( ctx->Visual.stencilBits > 0 &&
637 ctx->Visual.depthBits == 24 );
638
639 rmesa->radeon.Fallback = 0;
640
641 rmesa->radeon.hw.max_state_size = 0;
642
643 #define ALLOC_STATE( ATOM, CHK, SZ, NM, IDX ) \
644 do { \
645 rmesa->hw.ATOM.cmd_size = SZ; \
646 rmesa->hw.ATOM.cmd = (GLuint *)CALLOC(SZ * sizeof(int)); \
647 rmesa->hw.ATOM.lastcmd = (GLuint *)CALLOC(SZ * sizeof(int)); \
648 rmesa->hw.ATOM.name = NM; \
649 rmesa->hw.ATOM.idx = IDX; \
650 rmesa->hw.ATOM.check = check_##CHK; \
651 rmesa->hw.ATOM.dirty = GL_FALSE; \
652 rmesa->radeon.hw.max_state_size += SZ * sizeof(int); \
653 } while (0)
654
655
656 /* Allocate state buffers:
657 */
658 if (rmesa->radeon.radeonScreen->drmSupportsBlendColor)
659 ALLOC_STATE( ctx, always, CTX_STATE_SIZE_NEWDRM, "CTX/context", 0 );
660 else
661 ALLOC_STATE( ctx, always, CTX_STATE_SIZE_OLDDRM, "CTX/context", 0 );
662
663 if (rmesa->radeon.radeonScreen->kernel_mm)
664 rmesa->hw.ctx.emit = ctx_emit_cs;
665 else
666 rmesa->hw.ctx.emit = ctx_emit;
667 ALLOC_STATE( set, always, SET_STATE_SIZE, "SET/setup", 0 );
668 ALLOC_STATE( lin, always, LIN_STATE_SIZE, "LIN/line", 0 );
669 ALLOC_STATE( msk, always, MSK_STATE_SIZE, "MSK/mask", 0 );
670 ALLOC_STATE( vpt, always, VPT_STATE_SIZE, "VPT/viewport", 0 );
671 ALLOC_STATE( vtx, always, VTX_STATE_SIZE, "VTX/vertex", 0 );
672 ALLOC_STATE( vap, always, VAP_STATE_SIZE, "VAP/vap", 0 );
673 ALLOC_STATE( vte, always, VTE_STATE_SIZE, "VTE/vte", 0 );
674 ALLOC_STATE( msc, always, MSC_STATE_SIZE, "MSC/misc", 0 );
675 ALLOC_STATE( cst, always, CST_STATE_SIZE, "CST/constant", 0 );
676 ALLOC_STATE( zbs, always, ZBS_STATE_SIZE, "ZBS/zbias", 0 );
677 ALLOC_STATE( tf, tf, TF_STATE_SIZE, "TF/tfactor", 0 );
678 if (rmesa->radeon.radeonScreen->drmSupportsFragShader) {
679 if (rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_R200) {
680 /* make sure texture units 0/1 are emitted pair-wise for r200 t0 hang workaround */
681 ALLOC_STATE( tex[0], tex_pair, TEX_STATE_SIZE_NEWDRM, "TEX/tex-0", 0 );
682 ALLOC_STATE( tex[1], tex_pair, TEX_STATE_SIZE_NEWDRM, "TEX/tex-1", 1 );
683 ALLOC_STATE( tam, tex_any, TAM_STATE_SIZE, "TAM/tam", 0 );
684 }
685 else {
686 ALLOC_STATE( tex[0], tex, TEX_STATE_SIZE_NEWDRM, "TEX/tex-0", 0 );
687 ALLOC_STATE( tex[1], tex, TEX_STATE_SIZE_NEWDRM, "TEX/tex-1", 1 );
688 ALLOC_STATE( tam, never, TAM_STATE_SIZE, "TAM/tam", 0 );
689 }
690 ALLOC_STATE( tex[2], tex, TEX_STATE_SIZE_NEWDRM, "TEX/tex-2", 2 );
691 ALLOC_STATE( tex[3], tex, TEX_STATE_SIZE_NEWDRM, "TEX/tex-3", 3 );
692 ALLOC_STATE( tex[4], tex, TEX_STATE_SIZE_NEWDRM, "TEX/tex-4", 4 );
693 ALLOC_STATE( tex[5], tex, TEX_STATE_SIZE_NEWDRM, "TEX/tex-5", 5 );
694 ALLOC_STATE( atf, afs, ATF_STATE_SIZE, "ATF/tfactor", 0 );
695 ALLOC_STATE( afs[0], afs_pass1, AFS_STATE_SIZE, "AFS/afsinst-0", 0 );
696 ALLOC_STATE( afs[1], afs, AFS_STATE_SIZE, "AFS/afsinst-1", 1 );
697 }
698 else {
699 if (rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_R200) {
700 ALLOC_STATE( tex[0], tex_pair, TEX_STATE_SIZE_OLDDRM, "TEX/tex-0", 0 );
701 ALLOC_STATE( tex[1], tex_pair, TEX_STATE_SIZE_OLDDRM, "TEX/tex-1", 1 );
702 ALLOC_STATE( tam, tex_any, TAM_STATE_SIZE, "TAM/tam", 0 );
703 }
704 else {
705 ALLOC_STATE( tex[0], tex, TEX_STATE_SIZE_OLDDRM, "TEX/tex-0", 0 );
706 ALLOC_STATE( tex[1], tex, TEX_STATE_SIZE_OLDDRM, "TEX/tex-1", 1 );
707 ALLOC_STATE( tam, never, TAM_STATE_SIZE, "TAM/tam", 0 );
708 }
709 ALLOC_STATE( tex[2], tex, TEX_STATE_SIZE_OLDDRM, "TEX/tex-2", 2 );
710 ALLOC_STATE( tex[3], tex, TEX_STATE_SIZE_OLDDRM, "TEX/tex-3", 3 );
711 ALLOC_STATE( tex[4], tex, TEX_STATE_SIZE_OLDDRM, "TEX/tex-4", 4 );
712 ALLOC_STATE( tex[5], tex, TEX_STATE_SIZE_OLDDRM, "TEX/tex-5", 5 );
713 ALLOC_STATE( atf, never, ATF_STATE_SIZE, "TF/tfactor", 0 );
714 ALLOC_STATE( afs[0], never, AFS_STATE_SIZE, "AFS/afsinst-0", 0 );
715 ALLOC_STATE( afs[1], never, AFS_STATE_SIZE, "AFS/afsinst-1", 1 );
716 }
717
718 for (i = 0; i < 5; i++)
719 rmesa->hw.tex[i].emit = tex_emit;
720 if (rmesa->radeon.radeonScreen->drmSupportsCubeMapsR200) {
721 ALLOC_STATE( cube[0], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-0", 0 );
722 ALLOC_STATE( cube[1], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-1", 1 );
723 ALLOC_STATE( cube[2], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-2", 2 );
724 ALLOC_STATE( cube[3], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-3", 3 );
725 ALLOC_STATE( cube[4], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-4", 4 );
726 ALLOC_STATE( cube[5], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-5", 5 );
727 for (i = 0; i < 5; i++)
728 rmesa->hw.cube[i].emit = cube_emit;
729 }
730 else {
731 ALLOC_STATE( cube[0], never, CUBE_STATE_SIZE, "CUBE/tex-0", 0 );
732 ALLOC_STATE( cube[1], never, CUBE_STATE_SIZE, "CUBE/tex-1", 1 );
733 ALLOC_STATE( cube[2], never, CUBE_STATE_SIZE, "CUBE/tex-2", 2 );
734 ALLOC_STATE( cube[3], never, CUBE_STATE_SIZE, "CUBE/tex-3", 3 );
735 ALLOC_STATE( cube[4], never, CUBE_STATE_SIZE, "CUBE/tex-4", 4 );
736 ALLOC_STATE( cube[5], never, CUBE_STATE_SIZE, "CUBE/tex-5", 5 );
737 }
738
739 if (rmesa->radeon.radeonScreen->drmSupportsVertexProgram) {
740 ALLOC_STATE( pvs, tcl_vp, PVS_STATE_SIZE, "PVS/pvscntl", 0 );
741 ALLOC_STATE( vpi[0], tcl_vp, VPI_STATE_SIZE, "VP/vertexprog-0", 0 );
742 ALLOC_STATE( vpi[1], tcl_vp_size, VPI_STATE_SIZE, "VP/vertexprog-1", 1 );
743 ALLOC_STATE( vpp[0], tcl_vp, VPP_STATE_SIZE, "VPP/vertexparam-0", 0 );
744 ALLOC_STATE( vpp[1], tcl_vpp_size, VPP_STATE_SIZE, "VPP/vertexparam-1", 1 );
745 }
746 else {
747 ALLOC_STATE( pvs, never, PVS_STATE_SIZE, "PVS/pvscntl", 0 );
748 ALLOC_STATE( vpi[0], never, VPI_STATE_SIZE, "VP/vertexprog-0", 0 );
749 ALLOC_STATE( vpi[1], never, VPI_STATE_SIZE, "VP/vertexprog-1", 1 );
750 ALLOC_STATE( vpp[0], never, VPP_STATE_SIZE, "VPP/vertexparam-0", 0 );
751 ALLOC_STATE( vpp[1], never, VPP_STATE_SIZE, "VPP/vertexparam-1", 1 );
752 }
753 /* FIXME: this atom has two commands, we need only one (ucp_vert_blend) for vp */
754 ALLOC_STATE( tcl, tcl_or_vp, TCL_STATE_SIZE, "TCL/tcl", 0 );
755 ALLOC_STATE( msl, tcl, MSL_STATE_SIZE, "MSL/matrix-select", 0 );
756 ALLOC_STATE( tcg, tcl, TCG_STATE_SIZE, "TCG/texcoordgen", 0 );
757 ALLOC_STATE( mtl[0], tcl_lighting, MTL_STATE_SIZE, "MTL0/material0", 0 );
758 ALLOC_STATE( mtl[1], tcl_lighting, MTL_STATE_SIZE, "MTL1/material1", 1 );
759 ALLOC_STATE( grd, tcl_or_vp, GRD_STATE_SIZE, "GRD/guard-band", 0 );
760 ALLOC_STATE( fog, tcl_fog, FOG_STATE_SIZE, "FOG/fog", 0 );
761 ALLOC_STATE( glt, tcl_lighting, GLT_STATE_SIZE, "GLT/light-global", 0 );
762 ALLOC_STATE( eye, tcl_lighting, EYE_STATE_SIZE, "EYE/eye-vector", 0 );
763 ALLOC_STATE( mat[R200_MTX_MV], tcl, MAT_STATE_SIZE, "MAT/modelview", 0 );
764 ALLOC_STATE( mat[R200_MTX_IMV], tcl, MAT_STATE_SIZE, "MAT/it-modelview", 0 );
765 ALLOC_STATE( mat[R200_MTX_MVP], tcl, MAT_STATE_SIZE, "MAT/modelproject", 0 );
766 ALLOC_STATE( mat[R200_MTX_TEX0], tcl_tex, MAT_STATE_SIZE, "MAT/texmat0", 0 );
767 ALLOC_STATE( mat[R200_MTX_TEX1], tcl_tex, MAT_STATE_SIZE, "MAT/texmat1", 1 );
768 ALLOC_STATE( mat[R200_MTX_TEX2], tcl_tex, MAT_STATE_SIZE, "MAT/texmat2", 2 );
769 ALLOC_STATE( mat[R200_MTX_TEX3], tcl_tex, MAT_STATE_SIZE, "MAT/texmat3", 3 );
770 ALLOC_STATE( mat[R200_MTX_TEX4], tcl_tex, MAT_STATE_SIZE, "MAT/texmat4", 4 );
771 ALLOC_STATE( mat[R200_MTX_TEX5], tcl_tex, MAT_STATE_SIZE, "MAT/texmat5", 5 );
772 ALLOC_STATE( ucp[0], tcl_ucp, UCP_STATE_SIZE, "UCP/userclip-0", 0 );
773 ALLOC_STATE( ucp[1], tcl_ucp, UCP_STATE_SIZE, "UCP/userclip-1", 1 );
774 ALLOC_STATE( ucp[2], tcl_ucp, UCP_STATE_SIZE, "UCP/userclip-2", 2 );
775 ALLOC_STATE( ucp[3], tcl_ucp, UCP_STATE_SIZE, "UCP/userclip-3", 3 );
776 ALLOC_STATE( ucp[4], tcl_ucp, UCP_STATE_SIZE, "UCP/userclip-4", 4 );
777 ALLOC_STATE( ucp[5], tcl_ucp, UCP_STATE_SIZE, "UCP/userclip-5", 5 );
778 ALLOC_STATE( lit[0], tcl_light, LIT_STATE_SIZE, "LIT/light-0", 0 );
779 ALLOC_STATE( lit[1], tcl_light, LIT_STATE_SIZE, "LIT/light-1", 1 );
780 ALLOC_STATE( lit[2], tcl_light, LIT_STATE_SIZE, "LIT/light-2", 2 );
781 ALLOC_STATE( lit[3], tcl_light, LIT_STATE_SIZE, "LIT/light-3", 3 );
782 ALLOC_STATE( lit[4], tcl_light, LIT_STATE_SIZE, "LIT/light-4", 4 );
783 ALLOC_STATE( lit[5], tcl_light, LIT_STATE_SIZE, "LIT/light-5", 5 );
784 ALLOC_STATE( lit[6], tcl_light, LIT_STATE_SIZE, "LIT/light-6", 6 );
785 ALLOC_STATE( lit[7], tcl_light, LIT_STATE_SIZE, "LIT/light-7", 7 );
786 ALLOC_STATE( pix[0], pix_zero, PIX_STATE_SIZE, "PIX/pixstage-0", 0 );
787 ALLOC_STATE( pix[1], texenv, PIX_STATE_SIZE, "PIX/pixstage-1", 1 );
788 ALLOC_STATE( pix[2], texenv, PIX_STATE_SIZE, "PIX/pixstage-2", 2 );
789 ALLOC_STATE( pix[3], texenv, PIX_STATE_SIZE, "PIX/pixstage-3", 3 );
790 ALLOC_STATE( pix[4], texenv, PIX_STATE_SIZE, "PIX/pixstage-4", 4 );
791 ALLOC_STATE( pix[5], texenv, PIX_STATE_SIZE, "PIX/pixstage-5", 5 );
792 if (rmesa->radeon.radeonScreen->drmSupportsTriPerf) {
793 ALLOC_STATE( prf, always, PRF_STATE_SIZE, "PRF/performance-tri", 0 );
794 }
795 else {
796 ALLOC_STATE( prf, never, PRF_STATE_SIZE, "PRF/performance-tri", 0 );
797 }
798 if (rmesa->radeon.radeonScreen->drmSupportsPointSprites) {
799 ALLOC_STATE( spr, always, SPR_STATE_SIZE, "SPR/pointsprite", 0 );
800 ALLOC_STATE( ptp, tcl, PTP_STATE_SIZE, "PTP/pointparams", 0 );
801 }
802 else {
803 ALLOC_STATE (spr, never, SPR_STATE_SIZE, "SPR/pointsprite", 0 );
804 ALLOC_STATE (ptp, never, PTP_STATE_SIZE, "PTP/pointparams", 0 );
805 }
806
807 r200SetUpAtomList( rmesa );
808
809 /* Fill in the packet headers:
810 */
811 rmesa->hw.ctx.cmd[CTX_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_MISC);
812 rmesa->hw.ctx.cmd[CTX_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_PP_CNTL);
813 rmesa->hw.ctx.cmd[CTX_CMD_2] = cmdpkt(rmesa, RADEON_EMIT_RB3D_COLORPITCH);
814 if (rmesa->radeon.radeonScreen->drmSupportsBlendColor)
815 rmesa->hw.ctx.cmd[CTX_CMD_3] = cmdpkt(rmesa, R200_EMIT_RB3D_BLENDCOLOR);
816 rmesa->hw.lin.cmd[LIN_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_RE_LINE_PATTERN);
817 rmesa->hw.lin.cmd[LIN_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_SE_LINE_WIDTH);
818 rmesa->hw.msk.cmd[MSK_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_RB3D_STENCILREFMASK);
819 rmesa->hw.vpt.cmd[VPT_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_SE_VPORT_XSCALE);
820 rmesa->hw.set.cmd[SET_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_SE_CNTL);
821 rmesa->hw.msc.cmd[MSC_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_RE_MISC);
822 rmesa->hw.cst.cmd[CST_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_CNTL_X);
823 rmesa->hw.cst.cmd[CST_CMD_1] = cmdpkt(rmesa, R200_EMIT_RB3D_DEPTHXY_OFFSET);
824 rmesa->hw.cst.cmd[CST_CMD_2] = cmdpkt(rmesa, R200_EMIT_RE_AUX_SCISSOR_CNTL);
825 rmesa->hw.cst.cmd[CST_CMD_3] = cmdpkt(rmesa, R200_EMIT_RE_SCISSOR_TL_0);
826 rmesa->hw.cst.cmd[CST_CMD_4] = cmdpkt(rmesa, R200_EMIT_SE_VAP_CNTL_STATUS);
827 rmesa->hw.cst.cmd[CST_CMD_5] = cmdpkt(rmesa, R200_EMIT_RE_POINTSIZE);
828 rmesa->hw.cst.cmd[CST_CMD_6] = cmdpkt(rmesa, R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0);
829 rmesa->hw.tam.cmd[TAM_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TAM_DEBUG3);
830 rmesa->hw.tf.cmd[TF_CMD_0] = cmdpkt(rmesa, R200_EMIT_TFACTOR_0);
831 if (rmesa->radeon.radeonScreen->drmSupportsFragShader) {
832 rmesa->hw.atf.cmd[ATF_CMD_0] = cmdpkt(rmesa, R200_EMIT_ATF_TFACTOR);
833 rmesa->hw.tex[0].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCTLALL_0);
834 rmesa->hw.tex[0].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_0);
835 rmesa->hw.tex[1].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCTLALL_1);
836 rmesa->hw.tex[1].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_1);
837 rmesa->hw.tex[2].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCTLALL_2);
838 rmesa->hw.tex[2].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_2);
839 rmesa->hw.tex[3].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCTLALL_3);
840 rmesa->hw.tex[3].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_3);
841 rmesa->hw.tex[4].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCTLALL_4);
842 rmesa->hw.tex[4].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_4);
843 rmesa->hw.tex[5].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCTLALL_5);
844 rmesa->hw.tex[5].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_5);
845 } else {
846 rmesa->hw.tex[0].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXFILTER_0);
847 rmesa->hw.tex[0].cmd[TEX_CMD_1_OLDDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_0);
848 rmesa->hw.tex[1].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXFILTER_1);
849 rmesa->hw.tex[1].cmd[TEX_CMD_1_OLDDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_1);
850 rmesa->hw.tex[2].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXFILTER_2);
851 rmesa->hw.tex[2].cmd[TEX_CMD_1_OLDDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_2);
852 rmesa->hw.tex[3].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXFILTER_3);
853 rmesa->hw.tex[3].cmd[TEX_CMD_1_OLDDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_3);
854 rmesa->hw.tex[4].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXFILTER_4);
855 rmesa->hw.tex[4].cmd[TEX_CMD_1_OLDDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_4);
856 rmesa->hw.tex[5].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXFILTER_5);
857 rmesa->hw.tex[5].cmd[TEX_CMD_1_OLDDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_5);
858 }
859 rmesa->hw.afs[0].cmd[AFS_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_AFS_0);
860 rmesa->hw.afs[1].cmd[AFS_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_AFS_1);
861 rmesa->hw.pvs.cmd[PVS_CMD_0] = cmdpkt(rmesa, R200_EMIT_VAP_PVS_CNTL);
862 rmesa->hw.cube[0].cmd[CUBE_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_FACES_0);
863 rmesa->hw.cube[0].cmd[CUBE_CMD_1] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_OFFSETS_0);
864 rmesa->hw.cube[1].cmd[CUBE_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_FACES_1);
865 rmesa->hw.cube[1].cmd[CUBE_CMD_1] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_OFFSETS_1);
866 rmesa->hw.cube[2].cmd[CUBE_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_FACES_2);
867 rmesa->hw.cube[2].cmd[CUBE_CMD_1] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_OFFSETS_2);
868 rmesa->hw.cube[3].cmd[CUBE_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_FACES_3);
869 rmesa->hw.cube[3].cmd[CUBE_CMD_1] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_OFFSETS_3);
870 rmesa->hw.cube[4].cmd[CUBE_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_FACES_4);
871 rmesa->hw.cube[4].cmd[CUBE_CMD_1] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_OFFSETS_4);
872 rmesa->hw.cube[5].cmd[CUBE_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_FACES_5);
873 rmesa->hw.cube[5].cmd[CUBE_CMD_1] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_OFFSETS_5);
874 rmesa->hw.pix[0].cmd[PIX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCBLEND_0);
875 rmesa->hw.pix[1].cmd[PIX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCBLEND_1);
876 rmesa->hw.pix[2].cmd[PIX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCBLEND_2);
877 rmesa->hw.pix[3].cmd[PIX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCBLEND_3);
878 rmesa->hw.pix[4].cmd[PIX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCBLEND_4);
879 rmesa->hw.pix[5].cmd[PIX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCBLEND_5);
880 rmesa->hw.zbs.cmd[ZBS_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_SE_ZBIAS_FACTOR);
881 rmesa->hw.tcl.cmd[TCL_CMD_0] = cmdpkt(rmesa, R200_EMIT_TCL_LIGHT_MODEL_CTL_0);
882 rmesa->hw.tcl.cmd[TCL_CMD_1] = cmdpkt(rmesa, R200_EMIT_TCL_UCP_VERT_BLEND_CTL);
883 rmesa->hw.tcg.cmd[TCG_CMD_0] = cmdpkt(rmesa, R200_EMIT_TEX_PROC_CTL_2);
884 rmesa->hw.msl.cmd[MSL_CMD_0] = cmdpkt(rmesa, R200_EMIT_MATRIX_SELECT_0);
885 rmesa->hw.vap.cmd[VAP_CMD_0] = cmdpkt(rmesa, R200_EMIT_VAP_CTL);
886 rmesa->hw.vtx.cmd[VTX_CMD_0] = cmdpkt(rmesa, R200_EMIT_VTX_FMT_0);
887 rmesa->hw.vtx.cmd[VTX_CMD_1] = cmdpkt(rmesa, R200_EMIT_OUTPUT_VTX_COMP_SEL);
888 rmesa->hw.vtx.cmd[VTX_CMD_2] = cmdpkt(rmesa, R200_EMIT_SE_VTX_STATE_CNTL);
889 rmesa->hw.vte.cmd[VTE_CMD_0] = cmdpkt(rmesa, R200_EMIT_VTE_CNTL);
890 rmesa->hw.prf.cmd[PRF_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TRI_PERF_CNTL);
891 rmesa->hw.spr.cmd[SPR_CMD_0] = cmdpkt(rmesa, R200_EMIT_TCL_POINT_SPRITE_CNTL);
892 if (rmesa->radeon.radeonScreen->kernel_mm) {
893 rmesa->hw.mtl[0].emit = mtl_emit;
894 rmesa->hw.mtl[1].emit = mtl_emit;
895
896 rmesa->hw.vpi[0].emit = veclinear_emit;
897 rmesa->hw.vpi[1].emit = veclinear_emit;
898 rmesa->hw.vpp[0].emit = veclinear_emit;
899 rmesa->hw.vpp[1].emit = veclinear_emit;
900
901 rmesa->hw.grd.emit = scl_emit;
902 rmesa->hw.fog.emit = vec_emit;
903 rmesa->hw.glt.emit = vec_emit;
904 rmesa->hw.eye.emit = vec_emit;
905
906 for (i = R200_MTX_MV; i <= R200_MTX_TEX5; i++)
907 rmesa->hw.mat[i].emit = vec_emit;
908
909 for (i = 0; i < 8; i++)
910 rmesa->hw.lit[i].emit = lit_emit;
911
912 for (i = 0; i < 6; i++)
913 rmesa->hw.ucp[i].emit = vec_emit;
914
915 rmesa->hw.ptp.emit = ptp_emit;
916 }
917
918
919
920 rmesa->hw.mtl[0].cmd[MTL_CMD_0] =
921 cmdvec( R200_VS_MAT_0_EMISS, 1, 16 );
922 rmesa->hw.mtl[0].cmd[MTL_CMD_1] =
923 cmdscl2( R200_SS_MAT_0_SHININESS, 1, 1 );
924 rmesa->hw.mtl[1].cmd[MTL_CMD_0] =
925 cmdvec( R200_VS_MAT_1_EMISS, 1, 16 );
926 rmesa->hw.mtl[1].cmd[MTL_CMD_1] =
927 cmdscl2( R200_SS_MAT_1_SHININESS, 1, 1 );
928
929 rmesa->hw.vpi[0].cmd[VPI_CMD_0] =
930 cmdveclinear( R200_PVS_PROG0, 64 );
931 rmesa->hw.vpi[1].cmd[VPI_CMD_0] =
932 cmdveclinear( R200_PVS_PROG1, 64 );
933 rmesa->hw.vpp[0].cmd[VPP_CMD_0] =
934 cmdveclinear( R200_PVS_PARAM0, 96 );
935 rmesa->hw.vpp[1].cmd[VPP_CMD_0] =
936 cmdveclinear( R200_PVS_PARAM1, 96 );
937
938 rmesa->hw.grd.cmd[GRD_CMD_0] =
939 cmdscl( R200_SS_VERT_GUARD_CLIP_ADJ_ADDR, 1, 4 );
940 rmesa->hw.fog.cmd[FOG_CMD_0] =
941 cmdvec( R200_VS_FOG_PARAM_ADDR, 1, 4 );
942 rmesa->hw.glt.cmd[GLT_CMD_0] =
943 cmdvec( R200_VS_GLOBAL_AMBIENT_ADDR, 1, 4 );
944 rmesa->hw.eye.cmd[EYE_CMD_0] =
945 cmdvec( R200_VS_EYE_VECTOR_ADDR, 1, 4 );
946
947 rmesa->hw.mat[R200_MTX_MV].cmd[MAT_CMD_0] =
948 cmdvec( R200_VS_MATRIX_0_MV, 1, 16);
949 rmesa->hw.mat[R200_MTX_IMV].cmd[MAT_CMD_0] =
950 cmdvec( R200_VS_MATRIX_1_INV_MV, 1, 16);
951 rmesa->hw.mat[R200_MTX_MVP].cmd[MAT_CMD_0] =
952 cmdvec( R200_VS_MATRIX_2_MVP, 1, 16);
953 rmesa->hw.mat[R200_MTX_TEX0].cmd[MAT_CMD_0] =
954 cmdvec( R200_VS_MATRIX_3_TEX0, 1, 16);
955 rmesa->hw.mat[R200_MTX_TEX1].cmd[MAT_CMD_0] =
956 cmdvec( R200_VS_MATRIX_4_TEX1, 1, 16);
957 rmesa->hw.mat[R200_MTX_TEX2].cmd[MAT_CMD_0] =
958 cmdvec( R200_VS_MATRIX_5_TEX2, 1, 16);
959 rmesa->hw.mat[R200_MTX_TEX3].cmd[MAT_CMD_0] =
960 cmdvec( R200_VS_MATRIX_6_TEX3, 1, 16);
961 rmesa->hw.mat[R200_MTX_TEX4].cmd[MAT_CMD_0] =
962 cmdvec( R200_VS_MATRIX_7_TEX4, 1, 16);
963 rmesa->hw.mat[R200_MTX_TEX5].cmd[MAT_CMD_0] =
964 cmdvec( R200_VS_MATRIX_8_TEX5, 1, 16);
965
966 for (i = 0 ; i < 8; i++) {
967 rmesa->hw.lit[i].cmd[LIT_CMD_0] =
968 cmdvec( R200_VS_LIGHT_AMBIENT_ADDR + i, 8, 24 );
969 rmesa->hw.lit[i].cmd[LIT_CMD_1] =
970 cmdscl( R200_SS_LIGHT_DCD_ADDR + i, 8, 7 );
971 }
972
973 for (i = 0 ; i < 6; i++) {
974 rmesa->hw.ucp[i].cmd[UCP_CMD_0] =
975 cmdvec( R200_VS_UCP_ADDR + i, 1, 4 );
976 }
977
978 rmesa->hw.ptp.cmd[PTP_CMD_0] =
979 cmdvec( R200_VS_PNT_SPRITE_VPORT_SCALE, 1, 4 );
980 rmesa->hw.ptp.cmd[PTP_CMD_1] =
981 cmdvec( R200_VS_PNT_SPRITE_ATT_CONST, 1, 12 );
982
983 /* Initial Harware state:
984 */
985 rmesa->hw.ctx.cmd[CTX_PP_MISC] = (R200_ALPHA_TEST_PASS
986 /* | R200_RIGHT_HAND_CUBE_OGL*/);
987
988 rmesa->hw.ctx.cmd[CTX_PP_FOG_COLOR] = (R200_FOG_VERTEX |
989 R200_FOG_USE_SPEC_ALPHA);
990
991 rmesa->hw.ctx.cmd[CTX_RE_SOLID_COLOR] = 0x00000000;
992
993 rmesa->hw.ctx.cmd[CTX_RB3D_BLENDCNTL] = (R200_COMB_FCN_ADD_CLAMP |
994 (R200_BLEND_GL_ONE << R200_SRC_BLEND_SHIFT) |
995 (R200_BLEND_GL_ZERO << R200_DST_BLEND_SHIFT));
996
997 if (rmesa->radeon.radeonScreen->drmSupportsBlendColor) {
998 rmesa->hw.ctx.cmd[CTX_RB3D_BLENDCOLOR] = 0x00000000;
999 rmesa->hw.ctx.cmd[CTX_RB3D_ABLENDCNTL] = (R200_COMB_FCN_ADD_CLAMP |
1000 (R200_BLEND_GL_ONE << R200_SRC_BLEND_SHIFT) |
1001 (R200_BLEND_GL_ZERO << R200_DST_BLEND_SHIFT));
1002 rmesa->hw.ctx.cmd[CTX_RB3D_CBLENDCNTL] = (R200_COMB_FCN_ADD_CLAMP |
1003 (R200_BLEND_GL_ONE << R200_SRC_BLEND_SHIFT) |
1004 (R200_BLEND_GL_ZERO << R200_DST_BLEND_SHIFT));
1005 }
1006
1007 rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHOFFSET] =
1008 rmesa->radeon.radeonScreen->depthOffset + rmesa->radeon.radeonScreen->fbLocation;
1009
1010 rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHPITCH] =
1011 ((rmesa->radeon.radeonScreen->depthPitch &
1012 R200_DEPTHPITCH_MASK) |
1013 R200_DEPTH_ENDIAN_NO_SWAP);
1014
1015 if (rmesa->using_hyperz)
1016 rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHPITCH] |= R200_DEPTH_HYPERZ;
1017
1018 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] = (R200_Z_TEST_LESS |
1019 R200_STENCIL_TEST_ALWAYS |
1020 R200_STENCIL_FAIL_KEEP |
1021 R200_STENCIL_ZPASS_KEEP |
1022 R200_STENCIL_ZFAIL_KEEP |
1023 R200_Z_WRITE_ENABLE);
1024
1025 if (rmesa->using_hyperz) {
1026 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= R200_Z_COMPRESSION_ENABLE |
1027 R200_Z_DECOMPRESSION_ENABLE;
1028 /* if (rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_R200)
1029 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_HIERARCHY_ENABLE;*/
1030 }
1031
1032 rmesa->hw.ctx.cmd[CTX_PP_CNTL] = (R200_ANTI_ALIAS_NONE
1033 | R200_TEX_BLEND_0_ENABLE);
1034
1035 switch ( driQueryOptioni( &rmesa->radeon.optionCache, "dither_mode" ) ) {
1036 case DRI_CONF_DITHER_XERRORDIFFRESET:
1037 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= R200_DITHER_INIT;
1038 break;
1039 case DRI_CONF_DITHER_ORDERED:
1040 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= R200_SCALE_DITHER_ENABLE;
1041 break;
1042 }
1043 if ( driQueryOptioni( &rmesa->radeon.optionCache, "round_mode" ) ==
1044 DRI_CONF_ROUND_ROUND )
1045 rmesa->radeon.state.color.roundEnable = R200_ROUND_ENABLE;
1046 else
1047 rmesa->radeon.state.color.roundEnable = 0;
1048 if ( driQueryOptioni (&rmesa->radeon.optionCache, "color_reduction" ) ==
1049 DRI_CONF_COLOR_REDUCTION_DITHER )
1050 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= R200_DITHER_ENABLE;
1051 else
1052 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= rmesa->radeon.state.color.roundEnable;
1053
1054 rmesa->hw.prf.cmd[PRF_PP_TRI_PERF] = R200_TRI_CUTOFF_MASK - R200_TRI_CUTOFF_MASK *
1055 driQueryOptionf (&rmesa->radeon.optionCache,"texture_blend_quality");
1056 rmesa->hw.prf.cmd[PRF_PP_PERF_CNTL] = 0;
1057
1058 rmesa->hw.set.cmd[SET_SE_CNTL] = (R200_FFACE_CULL_CCW |
1059 R200_BFACE_SOLID |
1060 R200_FFACE_SOLID |
1061 R200_FLAT_SHADE_VTX_LAST |
1062 R200_DIFFUSE_SHADE_GOURAUD |
1063 R200_ALPHA_SHADE_GOURAUD |
1064 R200_SPECULAR_SHADE_GOURAUD |
1065 R200_FOG_SHADE_GOURAUD |
1066 R200_DISC_FOG_SHADE_GOURAUD |
1067 R200_VTX_PIX_CENTER_OGL |
1068 R200_ROUND_MODE_TRUNC |
1069 R200_ROUND_PREC_8TH_PIX);
1070
1071 rmesa->hw.set.cmd[SET_RE_CNTL] = (R200_PERSPECTIVE_ENABLE |
1072 R200_SCISSOR_ENABLE);
1073
1074 rmesa->hw.lin.cmd[LIN_RE_LINE_PATTERN] = ((1 << 16) | 0xffff);
1075
1076 rmesa->hw.lin.cmd[LIN_RE_LINE_STATE] =
1077 ((0 << R200_LINE_CURRENT_PTR_SHIFT) |
1078 (1 << R200_LINE_CURRENT_COUNT_SHIFT));
1079
1080 rmesa->hw.lin.cmd[LIN_SE_LINE_WIDTH] = (1 << 4);
1081
1082 rmesa->hw.msk.cmd[MSK_RB3D_STENCILREFMASK] =
1083 ((0x00 << R200_STENCIL_REF_SHIFT) |
1084 (0xff << R200_STENCIL_MASK_SHIFT) |
1085 (0xff << R200_STENCIL_WRITEMASK_SHIFT));
1086
1087 rmesa->hw.msk.cmd[MSK_RB3D_ROPCNTL] = R200_ROP_COPY;
1088 rmesa->hw.msk.cmd[MSK_RB3D_PLANEMASK] = 0xffffffff;
1089
1090 rmesa->hw.tam.cmd[TAM_DEBUG3] = 0;
1091
1092 rmesa->hw.msc.cmd[MSC_RE_MISC] =
1093 ((0 << R200_STIPPLE_X_OFFSET_SHIFT) |
1094 (0 << R200_STIPPLE_Y_OFFSET_SHIFT) |
1095 R200_STIPPLE_BIG_BIT_ORDER);
1096
1097
1098 rmesa->hw.cst.cmd[CST_PP_CNTL_X] = 0;
1099 rmesa->hw.cst.cmd[CST_RB3D_DEPTHXY_OFFSET] = 0;
1100 rmesa->hw.cst.cmd[CST_RE_AUX_SCISSOR_CNTL] = 0x0;
1101 rmesa->hw.cst.cmd[CST_RE_SCISSOR_TL_0] = 0;
1102 rmesa->hw.cst.cmd[CST_RE_SCISSOR_BR_0] = 0;
1103 rmesa->hw.cst.cmd[CST_SE_VAP_CNTL_STATUS] =
1104 #ifdef MESA_BIG_ENDIAN
1105 R200_VC_32BIT_SWAP;
1106 #else
1107 R200_VC_NO_SWAP;
1108 #endif
1109
1110 if (!(rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL)) {
1111 /* Bypass TCL */
1112 rmesa->hw.cst.cmd[CST_SE_VAP_CNTL_STATUS] |= (1<<8);
1113 }
1114
1115 rmesa->hw.cst.cmd[CST_RE_POINTSIZE] =
1116 (((GLuint)(ctx->Const.MaxPointSize * 16.0)) << R200_MAXPOINTSIZE_SHIFT) | 0x10;
1117 rmesa->hw.cst.cmd[CST_SE_TCL_INPUT_VTX_0] =
1118 (0x0 << R200_VERTEX_POSITION_ADDR__SHIFT);
1119 rmesa->hw.cst.cmd[CST_SE_TCL_INPUT_VTX_1] =
1120 (0x02 << R200_VTX_COLOR_0_ADDR__SHIFT) |
1121 (0x03 << R200_VTX_COLOR_1_ADDR__SHIFT);
1122 rmesa->hw.cst.cmd[CST_SE_TCL_INPUT_VTX_2] =
1123 (0x06 << R200_VTX_TEX_0_ADDR__SHIFT) |
1124 (0x07 << R200_VTX_TEX_1_ADDR__SHIFT) |
1125 (0x08 << R200_VTX_TEX_2_ADDR__SHIFT) |
1126 (0x09 << R200_VTX_TEX_3_ADDR__SHIFT);
1127 rmesa->hw.cst.cmd[CST_SE_TCL_INPUT_VTX_3] =
1128 (0x0A << R200_VTX_TEX_4_ADDR__SHIFT) |
1129 (0x0B << R200_VTX_TEX_5_ADDR__SHIFT);
1130
1131
1132 rmesa->hw.vpt.cmd[VPT_SE_VPORT_XSCALE] = 0x00000000;
1133 rmesa->hw.vpt.cmd[VPT_SE_VPORT_XOFFSET] = 0x00000000;
1134 rmesa->hw.vpt.cmd[VPT_SE_VPORT_YSCALE] = 0x00000000;
1135 rmesa->hw.vpt.cmd[VPT_SE_VPORT_YOFFSET] = 0x00000000;
1136 rmesa->hw.vpt.cmd[VPT_SE_VPORT_ZSCALE] = 0x00000000;
1137 rmesa->hw.vpt.cmd[VPT_SE_VPORT_ZOFFSET] = 0x00000000;
1138
1139 for ( i = 0 ; i < ctx->Const.MaxTextureUnits ; i++ ) {
1140 rmesa->hw.tex[i].cmd[TEX_PP_TXFILTER] = R200_BORDER_MODE_OGL;
1141 rmesa->hw.tex[i].cmd[TEX_PP_TXFORMAT] =
1142 ((i << R200_TXFORMAT_ST_ROUTE_SHIFT) | /* <-- note i */
1143 (2 << R200_TXFORMAT_WIDTH_SHIFT) |
1144 (2 << R200_TXFORMAT_HEIGHT_SHIFT));
1145 rmesa->hw.tex[i].cmd[TEX_PP_BORDER_COLOR] = 0;
1146 rmesa->hw.tex[i].cmd[TEX_PP_TXFORMAT_X] =
1147 (/* R200_TEXCOORD_PROJ | */
1148 0x100000); /* Small default bias */
1149 if (rmesa->radeon.radeonScreen->drmSupportsFragShader) {
1150 rmesa->hw.tex[i].cmd[TEX_PP_TXOFFSET_NEWDRM] =
1151 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
1152 rmesa->hw.tex[i].cmd[TEX_PP_CUBIC_FACES] = 0;
1153 rmesa->hw.tex[i].cmd[TEX_PP_TXMULTI_CTL] = 0;
1154 }
1155 else {
1156 rmesa->hw.tex[i].cmd[TEX_PP_TXOFFSET_OLDDRM] =
1157 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
1158 }
1159
1160 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_FACES] = 0;
1161 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F1] =
1162 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
1163 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F2] =
1164 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
1165 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F3] =
1166 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
1167 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F4] =
1168 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
1169 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F5] =
1170 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
1171
1172 rmesa->hw.pix[i].cmd[PIX_PP_TXCBLEND] =
1173 (R200_TXC_ARG_A_ZERO |
1174 R200_TXC_ARG_B_ZERO |
1175 R200_TXC_ARG_C_DIFFUSE_COLOR |
1176 R200_TXC_OP_MADD);
1177
1178 rmesa->hw.pix[i].cmd[PIX_PP_TXCBLEND2] =
1179 ((i << R200_TXC_TFACTOR_SEL_SHIFT) |
1180 R200_TXC_SCALE_1X |
1181 R200_TXC_CLAMP_0_1 |
1182 R200_TXC_OUTPUT_REG_R0);
1183
1184 rmesa->hw.pix[i].cmd[PIX_PP_TXABLEND] =
1185 (R200_TXA_ARG_A_ZERO |
1186 R200_TXA_ARG_B_ZERO |
1187 R200_TXA_ARG_C_DIFFUSE_ALPHA |
1188 R200_TXA_OP_MADD);
1189
1190 rmesa->hw.pix[i].cmd[PIX_PP_TXABLEND2] =
1191 ((i << R200_TXA_TFACTOR_SEL_SHIFT) |
1192 R200_TXA_SCALE_1X |
1193 R200_TXA_CLAMP_0_1 |
1194 R200_TXA_OUTPUT_REG_R0);
1195 }
1196
1197 rmesa->hw.tf.cmd[TF_TFACTOR_0] = 0;
1198 rmesa->hw.tf.cmd[TF_TFACTOR_1] = 0;
1199 rmesa->hw.tf.cmd[TF_TFACTOR_2] = 0;
1200 rmesa->hw.tf.cmd[TF_TFACTOR_3] = 0;
1201 rmesa->hw.tf.cmd[TF_TFACTOR_4] = 0;
1202 rmesa->hw.tf.cmd[TF_TFACTOR_5] = 0;
1203
1204 rmesa->hw.vap.cmd[VAP_SE_VAP_CNTL] =
1205 (R200_VAP_TCL_ENABLE |
1206 (0x9 << R200_VAP_VF_MAX_VTX_NUM__SHIFT));
1207
1208 rmesa->hw.vte.cmd[VTE_SE_VTE_CNTL] =
1209 (R200_VPORT_X_SCALE_ENA |
1210 R200_VPORT_Y_SCALE_ENA |
1211 R200_VPORT_Z_SCALE_ENA |
1212 R200_VPORT_X_OFFSET_ENA |
1213 R200_VPORT_Y_OFFSET_ENA |
1214 R200_VPORT_Z_OFFSET_ENA |
1215 /* FIXME: Turn on for tex rect only */
1216 R200_VTX_ST_DENORMALIZED |
1217 R200_VTX_W0_FMT);
1218
1219
1220 rmesa->hw.vtx.cmd[VTX_VTXFMT_0] = 0;
1221 rmesa->hw.vtx.cmd[VTX_VTXFMT_1] = 0;
1222 rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_VTXFMT_0] =
1223 ((R200_VTX_Z0 | R200_VTX_W0 |
1224 (R200_VTX_FP_RGBA << R200_VTX_COLOR_0_SHIFT)));
1225 rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_VTXFMT_1] = 0;
1226 rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_COMPSEL] = (R200_OUTPUT_XYZW);
1227 rmesa->hw.vtx.cmd[VTX_STATE_CNTL] = R200_VSC_UPDATE_USER_COLOR_0_ENABLE;
1228
1229
1230 /* Matrix selection */
1231 rmesa->hw.msl.cmd[MSL_MATRIX_SELECT_0] =
1232 (R200_MTX_MV << R200_MODELVIEW_0_SHIFT);
1233
1234 rmesa->hw.msl.cmd[MSL_MATRIX_SELECT_1] =
1235 (R200_MTX_IMV << R200_IT_MODELVIEW_0_SHIFT);
1236
1237 rmesa->hw.msl.cmd[MSL_MATRIX_SELECT_2] =
1238 (R200_MTX_MVP << R200_MODELPROJECT_0_SHIFT);
1239
1240 rmesa->hw.msl.cmd[MSL_MATRIX_SELECT_3] =
1241 ((R200_MTX_TEX0 << R200_TEXMAT_0_SHIFT) |
1242 (R200_MTX_TEX1 << R200_TEXMAT_1_SHIFT) |
1243 (R200_MTX_TEX2 << R200_TEXMAT_2_SHIFT) |
1244 (R200_MTX_TEX3 << R200_TEXMAT_3_SHIFT));
1245
1246 rmesa->hw.msl.cmd[MSL_MATRIX_SELECT_4] =
1247 ((R200_MTX_TEX4 << R200_TEXMAT_4_SHIFT) |
1248 (R200_MTX_TEX5 << R200_TEXMAT_5_SHIFT));
1249
1250
1251 /* General TCL state */
1252 rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL_0] =
1253 (R200_SPECULAR_LIGHTS |
1254 R200_DIFFUSE_SPECULAR_COMBINE |
1255 R200_LOCAL_LIGHT_VEC_GL |
1256 R200_LM0_SOURCE_MATERIAL_0 << R200_FRONT_SHININESS_SOURCE_SHIFT |
1257 R200_LM0_SOURCE_MATERIAL_1 << R200_BACK_SHININESS_SOURCE_SHIFT);
1258
1259 rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL_1] =
1260 ((R200_LM1_SOURCE_MATERIAL_0 << R200_FRONT_EMISSIVE_SOURCE_SHIFT) |
1261 (R200_LM1_SOURCE_MATERIAL_0 << R200_FRONT_AMBIENT_SOURCE_SHIFT) |
1262 (R200_LM1_SOURCE_MATERIAL_0 << R200_FRONT_DIFFUSE_SOURCE_SHIFT) |
1263 (R200_LM1_SOURCE_MATERIAL_0 << R200_FRONT_SPECULAR_SOURCE_SHIFT) |
1264 (R200_LM1_SOURCE_MATERIAL_1 << R200_BACK_EMISSIVE_SOURCE_SHIFT) |
1265 (R200_LM1_SOURCE_MATERIAL_1 << R200_BACK_AMBIENT_SOURCE_SHIFT) |
1266 (R200_LM1_SOURCE_MATERIAL_1 << R200_BACK_DIFFUSE_SOURCE_SHIFT) |
1267 (R200_LM1_SOURCE_MATERIAL_1 << R200_BACK_SPECULAR_SOURCE_SHIFT));
1268
1269 rmesa->hw.tcl.cmd[TCL_PER_LIGHT_CTL_0] = 0; /* filled in via callbacks */
1270 rmesa->hw.tcl.cmd[TCL_PER_LIGHT_CTL_1] = 0;
1271 rmesa->hw.tcl.cmd[TCL_PER_LIGHT_CTL_2] = 0;
1272 rmesa->hw.tcl.cmd[TCL_PER_LIGHT_CTL_3] = 0;
1273
1274 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] =
1275 (R200_UCP_IN_CLIP_SPACE |
1276 R200_CULL_FRONT_IS_CCW);
1277
1278 /* Texgen/Texmat state */
1279 rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_2] = 0x00ffffff;
1280 rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_3] =
1281 ((0 << R200_TEXGEN_0_INPUT_TEX_SHIFT) |
1282 (1 << R200_TEXGEN_1_INPUT_TEX_SHIFT) |
1283 (2 << R200_TEXGEN_2_INPUT_TEX_SHIFT) |
1284 (3 << R200_TEXGEN_3_INPUT_TEX_SHIFT) |
1285 (4 << R200_TEXGEN_4_INPUT_TEX_SHIFT) |
1286 (5 << R200_TEXGEN_5_INPUT_TEX_SHIFT));
1287 rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_0] = 0;
1288 rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_1] =
1289 ((0 << R200_TEXGEN_0_INPUT_SHIFT) |
1290 (1 << R200_TEXGEN_1_INPUT_SHIFT) |
1291 (2 << R200_TEXGEN_2_INPUT_SHIFT) |
1292 (3 << R200_TEXGEN_3_INPUT_SHIFT) |
1293 (4 << R200_TEXGEN_4_INPUT_SHIFT) |
1294 (5 << R200_TEXGEN_5_INPUT_SHIFT));
1295 rmesa->hw.tcg.cmd[TCG_TEX_CYL_WRAP_CTL] = 0;
1296
1297
1298 for (i = 0 ; i < 8; i++) {
1299 struct gl_light *l = &ctx->Light.Light[i];
1300 GLenum p = GL_LIGHT0 + i;
1301 *(float *)&(rmesa->hw.lit[i].cmd[LIT_RANGE_CUTOFF]) = FLT_MAX;
1302
1303 ctx->Driver.Lightfv( ctx, p, GL_AMBIENT, l->Ambient );
1304 ctx->Driver.Lightfv( ctx, p, GL_DIFFUSE, l->Diffuse );
1305 ctx->Driver.Lightfv( ctx, p, GL_SPECULAR, l->Specular );
1306 ctx->Driver.Lightfv( ctx, p, GL_POSITION, NULL );
1307 ctx->Driver.Lightfv( ctx, p, GL_SPOT_DIRECTION, NULL );
1308 ctx->Driver.Lightfv( ctx, p, GL_SPOT_EXPONENT, &l->SpotExponent );
1309 ctx->Driver.Lightfv( ctx, p, GL_SPOT_CUTOFF, &l->SpotCutoff );
1310 ctx->Driver.Lightfv( ctx, p, GL_CONSTANT_ATTENUATION,
1311 &l->ConstantAttenuation );
1312 ctx->Driver.Lightfv( ctx, p, GL_LINEAR_ATTENUATION,
1313 &l->LinearAttenuation );
1314 ctx->Driver.Lightfv( ctx, p, GL_QUADRATIC_ATTENUATION,
1315 &l->QuadraticAttenuation );
1316 *(float *)&(rmesa->hw.lit[i].cmd[LIT_ATTEN_XXX]) = 0.0;
1317 }
1318
1319 ctx->Driver.LightModelfv( ctx, GL_LIGHT_MODEL_AMBIENT,
1320 ctx->Light.Model.Ambient );
1321
1322 TNL_CONTEXT(ctx)->Driver.NotifyMaterialChange( ctx );
1323
1324 for (i = 0 ; i < 6; i++) {
1325 ctx->Driver.ClipPlane( ctx, GL_CLIP_PLANE0 + i, NULL );
1326 }
1327
1328 ctx->Driver.Fogfv( ctx, GL_FOG_MODE, NULL );
1329 ctx->Driver.Fogfv( ctx, GL_FOG_DENSITY, &ctx->Fog.Density );
1330 ctx->Driver.Fogfv( ctx, GL_FOG_START, &ctx->Fog.Start );
1331 ctx->Driver.Fogfv( ctx, GL_FOG_END, &ctx->Fog.End );
1332 ctx->Driver.Fogfv( ctx, GL_FOG_COLOR, ctx->Fog.Color );
1333 ctx->Driver.Fogfv( ctx, GL_FOG_COORDINATE_SOURCE_EXT, NULL );
1334
1335 rmesa->hw.grd.cmd[GRD_VERT_GUARD_CLIP_ADJ] = IEEE_ONE;
1336 rmesa->hw.grd.cmd[GRD_VERT_GUARD_DISCARD_ADJ] = IEEE_ONE;
1337 rmesa->hw.grd.cmd[GRD_HORZ_GUARD_CLIP_ADJ] = IEEE_ONE;
1338 rmesa->hw.grd.cmd[GRD_HORZ_GUARD_DISCARD_ADJ] = IEEE_ONE;
1339
1340 rmesa->hw.eye.cmd[EYE_X] = 0;
1341 rmesa->hw.eye.cmd[EYE_Y] = 0;
1342 rmesa->hw.eye.cmd[EYE_Z] = IEEE_ONE;
1343 rmesa->hw.eye.cmd[EYE_RESCALE_FACTOR] = IEEE_ONE;
1344
1345 rmesa->hw.spr.cmd[SPR_POINT_SPRITE_CNTL] =
1346 R200_PS_SE_SEL_STATE | R200_PS_MULT_CONST;
1347
1348 /* ptp_eye is presumably used to calculate the attenuation wrt a different
1349 location? In any case, since point attenuation triggers _needeyecoords,
1350 it is constant. Probably ignored as long as R200_PS_USE_MODEL_EYE_VEC
1351 isn't set */
1352 rmesa->hw.ptp.cmd[PTP_EYE_X] = 0;
1353 rmesa->hw.ptp.cmd[PTP_EYE_Y] = 0;
1354 rmesa->hw.ptp.cmd[PTP_EYE_Z] = IEEE_ONE | 0x80000000; /* -1.0 */
1355 rmesa->hw.ptp.cmd[PTP_EYE_3] = 0;
1356 /* no idea what the ptp_vport_scale values are good for, except the
1357 PTSIZE one - hopefully doesn't matter */
1358 rmesa->hw.ptp.cmd[PTP_VPORT_SCALE_0] = IEEE_ONE;
1359 rmesa->hw.ptp.cmd[PTP_VPORT_SCALE_1] = IEEE_ONE;
1360 rmesa->hw.ptp.cmd[PTP_VPORT_SCALE_PTSIZE] = IEEE_ONE;
1361 rmesa->hw.ptp.cmd[PTP_VPORT_SCALE_3] = IEEE_ONE;
1362 rmesa->hw.ptp.cmd[PTP_ATT_CONST_QUAD] = 0;
1363 rmesa->hw.ptp.cmd[PTP_ATT_CONST_LIN] = 0;
1364 rmesa->hw.ptp.cmd[PTP_ATT_CONST_CON] = IEEE_ONE;
1365 rmesa->hw.ptp.cmd[PTP_ATT_CONST_3] = 0;
1366 rmesa->hw.ptp.cmd[PTP_CLAMP_MIN] = IEEE_ONE;
1367 rmesa->hw.ptp.cmd[PTP_CLAMP_MAX] = 0x44ffe000; /* 2047 */
1368 rmesa->hw.ptp.cmd[PTP_CLAMP_2] = 0;
1369 rmesa->hw.ptp.cmd[PTP_CLAMP_3] = 0;
1370
1371 r200LightingSpaceChange( ctx );
1372
1373 rmesa->radeon.hw.all_dirty = GL_TRUE;
1374
1375 rcommonInitCmdBuf(&rmesa->radeon);
1376 }