1 /* $XFree86: xc/lib/GL/mesa/src/drv/r200/r200_state_init.c,v 1.4 2003/02/22 06:21:11 dawes Exp $ */
3 Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
5 The Weather Channel (TM) funded Tungsten Graphics to develop the
6 initial release of the Radeon 8500 driver under the XFree86 license.
7 This notice must be preserved.
9 Permission is hereby granted, free of charge, to any person obtaining
10 a copy of this software and associated documentation files (the
11 "Software"), to deal in the Software without restriction, including
12 without limitation the rights to use, copy, modify, merge, publish,
13 distribute, sublicense, and/or sell copies of the Software, and to
14 permit persons to whom the Software is furnished to do so, subject to
15 the following conditions:
17 The above copyright notice and this permission notice (including the
18 next paragraph) shall be included in all copies or substantial
19 portions of the Software.
21 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
22 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
23 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
24 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
25 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
26 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
27 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
32 * Keith Whitwell <keith@tungstengraphics.com>
39 #include "api_arrayelt.h"
41 #include "swrast/swrast.h"
42 #include "array_cache/acache.h"
44 #include "tnl/t_pipeline.h"
45 #include "swrast_setup/swrast_setup.h"
47 #include "r200_context.h"
48 #include "r200_ioctl.h"
49 #include "r200_state.h"
52 #include "r200_swtcl.h"
53 #include "r200_vtxfmt.h"
57 /* =============================================================
58 * State initialization
61 void r200PrintDirty( r200ContextPtr rmesa
, const char *msg
)
63 struct r200_state_atom
*l
;
66 fprintf(stderr
, ": ");
68 foreach(l
, &rmesa
->hw
.atomlist
) {
69 if (l
->dirty
|| rmesa
->hw
.all_dirty
)
70 fprintf(stderr
, "%s, ", l
->name
);
73 fprintf(stderr
, "\n");
76 static int cmdpkt( int id
)
78 drm_radeon_cmd_header_t h
;
80 h
.packet
.cmd_type
= RADEON_CMD_PACKET
;
81 h
.packet
.packet_id
= id
;
85 static int cmdvec( int offset
, int stride
, int count
)
87 drm_radeon_cmd_header_t h
;
89 h
.vectors
.cmd_type
= RADEON_CMD_VECTORS
;
90 h
.vectors
.offset
= offset
;
91 h
.vectors
.stride
= stride
;
92 h
.vectors
.count
= count
;
96 static int cmdscl( int offset
, int stride
, int count
)
98 drm_radeon_cmd_header_t h
;
100 h
.scalars
.cmd_type
= RADEON_CMD_SCALARS
;
101 h
.scalars
.offset
= offset
;
102 h
.scalars
.stride
= stride
;
103 h
.scalars
.count
= count
;
107 static int cmdscl2( int offset
, int stride
, int count
)
109 drm_radeon_cmd_header_t h
;
111 h
.scalars
.cmd_type
= RADEON_CMD_SCALARS2
;
112 h
.scalars
.offset
= offset
- 0x100;
113 h
.scalars
.stride
= stride
;
114 h
.scalars
.count
= count
;
118 #define CHECK( NM, FLAG ) \
119 static GLboolean check_##NM( GLcontext *ctx, int idx ) \
121 r200ContextPtr rmesa = R200_CONTEXT(ctx); \
127 #define TCL_CHECK( NM, FLAG ) \
128 static GLboolean check_##NM( GLcontext *ctx, int idx ) \
130 r200ContextPtr rmesa = R200_CONTEXT(ctx); \
132 return !rmesa->TclFallback && (FLAG); \
137 CHECK( always
, GL_TRUE
)
138 CHECK( never
, GL_FALSE
)
139 CHECK( tex_any
, ctx
->Texture
._EnabledUnits
)
140 CHECK( tf
, (ctx
->Texture
._EnabledUnits
&& !ctx
->ATIFragmentShader
._Enabled
) );
141 CHECK( tex_pair
, (rmesa
->state
.texture
.unit
[idx
].unitneeded
| rmesa
->state
.texture
.unit
[idx
& ~1].unitneeded
) )
142 CHECK( tex
, rmesa
->state
.texture
.unit
[idx
].unitneeded
)
143 CHECK( pix_zero
, !ctx
->ATIFragmentShader
._Enabled
)
144 CHECK( texenv
, (rmesa
->state
.envneeded
& (1 << idx
) && !ctx
->ATIFragmentShader
._Enabled
) )
145 CHECK( afs_pass1
, (ctx
->ATIFragmentShader
._Enabled
&& (ctx
->ATIFragmentShader
.Current
->NumPasses
> 1)) )
146 CHECK( afs
, ctx
->ATIFragmentShader
._Enabled
)
147 CHECK( tex_cube
, rmesa
->state
.texture
.unit
[idx
].unitneeded
& TEXTURE_CUBE_BIT
)
148 CHECK( fog
, ctx
->Fog
.Enabled
)
149 TCL_CHECK( tcl
, GL_TRUE
)
150 TCL_CHECK( tcl_tex
, rmesa
->state
.texture
.unit
[idx
].unitneeded
)
151 TCL_CHECK( tcl_lighting
, ctx
->Light
.Enabled
)
152 TCL_CHECK( tcl_light
, ctx
->Light
.Enabled
&& ctx
->Light
.Light
[idx
].Enabled
)
153 TCL_CHECK( tcl_ucp
, (ctx
->Transform
.ClipPlanesEnabled
& (1 << idx
)) )
156 /* Initialize the context's hardware state.
158 void r200InitState( r200ContextPtr rmesa
)
160 GLcontext
*ctx
= rmesa
->glCtx
;
161 GLuint color_fmt
, depth_fmt
, i
;
162 GLint drawPitch
, drawOffset
;
164 switch ( rmesa
->r200Screen
->cpp
) {
166 color_fmt
= R200_COLOR_FORMAT_RGB565
;
169 color_fmt
= R200_COLOR_FORMAT_ARGB8888
;
172 fprintf( stderr
, "Error: Unsupported pixel depth... exiting\n" );
176 rmesa
->state
.color
.clear
= 0x00000000;
178 switch ( ctx
->Visual
.depthBits
) {
180 rmesa
->state
.depth
.clear
= 0x0000ffff;
181 rmesa
->state
.depth
.scale
= 1.0 / (GLfloat
)0xffff;
182 depth_fmt
= R200_DEPTH_FORMAT_16BIT_INT_Z
;
183 rmesa
->state
.stencil
.clear
= 0x00000000;
186 rmesa
->state
.depth
.clear
= 0x00ffffff;
187 rmesa
->state
.depth
.scale
= 1.0 / (GLfloat
)0xffffff;
188 depth_fmt
= R200_DEPTH_FORMAT_24BIT_INT_Z
;
189 rmesa
->state
.stencil
.clear
= 0xffff0000;
192 fprintf( stderr
, "Error: Unsupported depth %d... exiting\n",
193 ctx
->Visual
.depthBits
);
197 /* Only have hw stencil when depth buffer is 24 bits deep */
198 rmesa
->state
.stencil
.hwBuffer
= ( ctx
->Visual
.stencilBits
> 0 &&
199 ctx
->Visual
.depthBits
== 24 );
203 if ( ctx
->Visual
.doubleBufferMode
&& rmesa
->sarea
->pfCurrentPage
== 0 ) {
204 drawOffset
= rmesa
->r200Screen
->backOffset
;
205 drawPitch
= rmesa
->r200Screen
->backPitch
;
207 drawOffset
= rmesa
->r200Screen
->frontOffset
;
208 drawPitch
= rmesa
->r200Screen
->frontPitch
;
211 if ( ctx
->Visual
.doubleBufferMode
&& rmesa
->sarea
->pfCurrentPage
== 0 ) {
212 rmesa
->state
.color
.drawOffset
= rmesa
->r200Screen
->backOffset
;
213 rmesa
->state
.color
.drawPitch
= rmesa
->r200Screen
->backPitch
;
215 rmesa
->state
.color
.drawOffset
= rmesa
->r200Screen
->frontOffset
;
216 rmesa
->state
.color
.drawPitch
= rmesa
->r200Screen
->frontPitch
;
219 rmesa
->state
.pixel
.readOffset
= rmesa
->state
.color
.drawOffset
;
220 rmesa
->state
.pixel
.readPitch
= rmesa
->state
.color
.drawPitch
;
223 rmesa
->hw
.max_state_size
= 0;
225 #define ALLOC_STATE( ATOM, CHK, SZ, NM, IDX ) \
227 rmesa->hw.ATOM.cmd_size = SZ; \
228 rmesa->hw.ATOM.cmd = (int *)CALLOC(SZ * sizeof(int)); \
229 rmesa->hw.ATOM.lastcmd = (int *)CALLOC(SZ * sizeof(int)); \
230 rmesa->hw.ATOM.name = NM; \
231 rmesa->hw.ATOM.idx = IDX; \
232 rmesa->hw.ATOM.check = check_##CHK; \
233 rmesa->hw.ATOM.dirty = GL_FALSE; \
234 rmesa->hw.max_state_size += SZ * sizeof(int); \
238 /* Allocate state buffers:
240 if (rmesa
->r200Screen
->drmSupportsBlendColor
)
241 ALLOC_STATE( ctx
, always
, CTX_STATE_SIZE_NEWDRM
, "CTX/context", 0 );
243 ALLOC_STATE( ctx
, always
, CTX_STATE_SIZE_OLDDRM
, "CTX/context", 0 );
244 ALLOC_STATE( set
, always
, SET_STATE_SIZE
, "SET/setup", 0 );
245 ALLOC_STATE( lin
, always
, LIN_STATE_SIZE
, "LIN/line", 0 );
246 ALLOC_STATE( msk
, always
, MSK_STATE_SIZE
, "MSK/mask", 0 );
247 ALLOC_STATE( vpt
, always
, VPT_STATE_SIZE
, "VPT/viewport", 0 );
248 ALLOC_STATE( vtx
, always
, VTX_STATE_SIZE
, "VTX/vertex", 0 );
249 ALLOC_STATE( vap
, always
, VAP_STATE_SIZE
, "VAP/vap", 0 );
250 ALLOC_STATE( vte
, always
, VTE_STATE_SIZE
, "VTE/vte", 0 );
251 ALLOC_STATE( msc
, always
, MSC_STATE_SIZE
, "MSC/misc", 0 );
252 ALLOC_STATE( cst
, always
, CST_STATE_SIZE
, "CST/constant", 0 );
253 ALLOC_STATE( zbs
, always
, ZBS_STATE_SIZE
, "ZBS/zbias", 0 );
254 ALLOC_STATE( tf
, tf
, TF_STATE_SIZE
, "TF/tfactor", 0 );
255 if (rmesa
->r200Screen
->drmSupportsFragShader
) {
256 if (rmesa
->r200Screen
->chipset
& R200_CHIPSET_REAL_R200
) {
257 /* make sure texture units 0/1 are emitted pair-wise for r200 t0 hang workaround */
258 ALLOC_STATE( tex
[0], tex_pair
, TEX_STATE_SIZE_NEWDRM
, "TEX/tex-0", 0 );
259 ALLOC_STATE( tex
[1], tex_pair
, TEX_STATE_SIZE_NEWDRM
, "TEX/tex-1", 1 );
260 ALLOC_STATE( tam
, tex_any
, TAM_STATE_SIZE
, "TAM/tam", 0 );
263 ALLOC_STATE( tex
[0], tex
, TEX_STATE_SIZE_NEWDRM
, "TEX/tex-0", 0 );
264 ALLOC_STATE( tex
[1], tex
, TEX_STATE_SIZE_NEWDRM
, "TEX/tex-1", 1 );
265 ALLOC_STATE( tam
, never
, TAM_STATE_SIZE
, "TAM/tam", 0 );
267 ALLOC_STATE( tex
[2], tex
, TEX_STATE_SIZE_NEWDRM
, "TEX/tex-2", 2 );
268 ALLOC_STATE( tex
[3], tex
, TEX_STATE_SIZE_NEWDRM
, "TEX/tex-3", 3 );
269 ALLOC_STATE( tex
[4], tex
, TEX_STATE_SIZE_NEWDRM
, "TEX/tex-4", 4 );
270 ALLOC_STATE( tex
[5], tex
, TEX_STATE_SIZE_NEWDRM
, "TEX/tex-5", 5 );
271 ALLOC_STATE( atf
, afs
, ATF_STATE_SIZE
, "ATF/tfactor", 0 );
272 ALLOC_STATE( afs
[0], afs_pass1
, AFS_STATE_SIZE
, "AFS/afsinst-0", 0 );
273 ALLOC_STATE( afs
[1], afs
, AFS_STATE_SIZE
, "AFS/afsinst-1", 1 );
276 if (rmesa
->r200Screen
->chipset
& R200_CHIPSET_REAL_R200
) {
277 ALLOC_STATE( tex
[0], tex_pair
, TEX_STATE_SIZE_OLDDRM
, "TEX/tex-0", 0 );
278 ALLOC_STATE( tex
[1], tex_pair
, TEX_STATE_SIZE_OLDDRM
, "TEX/tex-1", 1 );
279 ALLOC_STATE( tam
, tex_any
, TAM_STATE_SIZE
, "TAM/tam", 0 );
282 ALLOC_STATE( tex
[0], tex
, TEX_STATE_SIZE_OLDDRM
, "TEX/tex-0", 0 );
283 ALLOC_STATE( tex
[1], tex
, TEX_STATE_SIZE_OLDDRM
, "TEX/tex-1", 1 );
284 ALLOC_STATE( tam
, never
, TAM_STATE_SIZE
, "TAM/tam", 0 );
286 ALLOC_STATE( tex
[2], tex
, TEX_STATE_SIZE_OLDDRM
, "TEX/tex-2", 2 );
287 ALLOC_STATE( tex
[3], tex
, TEX_STATE_SIZE_OLDDRM
, "TEX/tex-3", 3 );
288 ALLOC_STATE( tex
[4], tex
, TEX_STATE_SIZE_OLDDRM
, "TEX/tex-4", 4 );
289 ALLOC_STATE( tex
[5], tex
, TEX_STATE_SIZE_OLDDRM
, "TEX/tex-5", 5 );
290 ALLOC_STATE( atf
, never
, ATF_STATE_SIZE
, "TF/tfactor", 0 );
291 ALLOC_STATE( afs
[0], never
, AFS_STATE_SIZE
, "AFS/afsinst-0", 0 );
292 ALLOC_STATE( afs
[1], never
, AFS_STATE_SIZE
, "AFS/afsinst-1", 1 );
294 if (rmesa
->r200Screen
->drmSupportsCubeMaps
) {
295 ALLOC_STATE( cube
[0], tex_cube
, CUBE_STATE_SIZE
, "CUBE/tex-0", 0 );
296 ALLOC_STATE( cube
[1], tex_cube
, CUBE_STATE_SIZE
, "CUBE/tex-1", 1 );
297 ALLOC_STATE( cube
[2], tex_cube
, CUBE_STATE_SIZE
, "CUBE/tex-2", 2 );
298 ALLOC_STATE( cube
[3], tex_cube
, CUBE_STATE_SIZE
, "CUBE/tex-3", 3 );
299 ALLOC_STATE( cube
[4], tex_cube
, CUBE_STATE_SIZE
, "CUBE/tex-4", 4 );
300 ALLOC_STATE( cube
[5], tex_cube
, CUBE_STATE_SIZE
, "CUBE/tex-5", 5 );
303 ALLOC_STATE( cube
[0], never
, CUBE_STATE_SIZE
, "CUBE/tex-0", 0 );
304 ALLOC_STATE( cube
[1], never
, CUBE_STATE_SIZE
, "CUBE/tex-1", 1 );
305 ALLOC_STATE( cube
[2], never
, CUBE_STATE_SIZE
, "CUBE/tex-2", 2 );
306 ALLOC_STATE( cube
[3], never
, CUBE_STATE_SIZE
, "CUBE/tex-3", 3 );
307 ALLOC_STATE( cube
[4], never
, CUBE_STATE_SIZE
, "CUBE/tex-4", 4 );
308 ALLOC_STATE( cube
[5], never
, CUBE_STATE_SIZE
, "CUBE/tex-5", 5 );
311 ALLOC_STATE( tcl
, tcl
, TCL_STATE_SIZE
, "TCL/tcl", 0 );
312 ALLOC_STATE( msl
, tcl
, MSL_STATE_SIZE
, "MSL/matrix-select", 0 );
313 ALLOC_STATE( tcg
, tcl
, TCG_STATE_SIZE
, "TCG/texcoordgen", 0 );
314 ALLOC_STATE( mtl
[0], tcl_lighting
, MTL_STATE_SIZE
, "MTL0/material0", 0 );
315 ALLOC_STATE( mtl
[1], tcl_lighting
, MTL_STATE_SIZE
, "MTL1/material1", 1 );
316 ALLOC_STATE( grd
, tcl
, GRD_STATE_SIZE
, "GRD/guard-band", 0 );
317 ALLOC_STATE( fog
, fog
, FOG_STATE_SIZE
, "FOG/fog", 0 );
318 ALLOC_STATE( glt
, tcl_lighting
, GLT_STATE_SIZE
, "GLT/light-global", 0 );
319 ALLOC_STATE( eye
, tcl_lighting
, EYE_STATE_SIZE
, "EYE/eye-vector", 0 );
320 ALLOC_STATE( mat
[R200_MTX_MV
], tcl
, MAT_STATE_SIZE
, "MAT/modelview", 0 );
321 ALLOC_STATE( mat
[R200_MTX_IMV
], tcl
, MAT_STATE_SIZE
, "MAT/it-modelview", 0 );
322 ALLOC_STATE( mat
[R200_MTX_MVP
], tcl
, MAT_STATE_SIZE
, "MAT/modelproject", 0 );
323 ALLOC_STATE( mat
[R200_MTX_TEX0
], tcl_tex
, MAT_STATE_SIZE
, "MAT/texmat0", 0 );
324 ALLOC_STATE( mat
[R200_MTX_TEX1
], tcl_tex
, MAT_STATE_SIZE
, "MAT/texmat1", 1 );
325 ALLOC_STATE( mat
[R200_MTX_TEX2
], tcl_tex
, MAT_STATE_SIZE
, "MAT/texmat2", 2 );
326 ALLOC_STATE( mat
[R200_MTX_TEX3
], tcl_tex
, MAT_STATE_SIZE
, "MAT/texmat3", 3 );
327 ALLOC_STATE( mat
[R200_MTX_TEX4
], tcl_tex
, MAT_STATE_SIZE
, "MAT/texmat4", 4 );
328 ALLOC_STATE( mat
[R200_MTX_TEX5
], tcl_tex
, MAT_STATE_SIZE
, "MAT/texmat5", 5 );
329 ALLOC_STATE( ucp
[0], tcl_ucp
, UCP_STATE_SIZE
, "UCP/userclip-0", 0 );
330 ALLOC_STATE( ucp
[1], tcl_ucp
, UCP_STATE_SIZE
, "UCP/userclip-1", 1 );
331 ALLOC_STATE( ucp
[2], tcl_ucp
, UCP_STATE_SIZE
, "UCP/userclip-2", 2 );
332 ALLOC_STATE( ucp
[3], tcl_ucp
, UCP_STATE_SIZE
, "UCP/userclip-3", 3 );
333 ALLOC_STATE( ucp
[4], tcl_ucp
, UCP_STATE_SIZE
, "UCP/userclip-4", 4 );
334 ALLOC_STATE( ucp
[5], tcl_ucp
, UCP_STATE_SIZE
, "UCP/userclip-5", 5 );
335 ALLOC_STATE( lit
[0], tcl_light
, LIT_STATE_SIZE
, "LIT/light-0", 0 );
336 ALLOC_STATE( lit
[1], tcl_light
, LIT_STATE_SIZE
, "LIT/light-1", 1 );
337 ALLOC_STATE( lit
[2], tcl_light
, LIT_STATE_SIZE
, "LIT/light-2", 2 );
338 ALLOC_STATE( lit
[3], tcl_light
, LIT_STATE_SIZE
, "LIT/light-3", 3 );
339 ALLOC_STATE( lit
[4], tcl_light
, LIT_STATE_SIZE
, "LIT/light-4", 4 );
340 ALLOC_STATE( lit
[5], tcl_light
, LIT_STATE_SIZE
, "LIT/light-5", 5 );
341 ALLOC_STATE( lit
[6], tcl_light
, LIT_STATE_SIZE
, "LIT/light-6", 6 );
342 ALLOC_STATE( lit
[7], tcl_light
, LIT_STATE_SIZE
, "LIT/light-7", 7 );
343 ALLOC_STATE( pix
[0], pix_zero
, PIX_STATE_SIZE
, "PIX/pixstage-0", 0 );
344 ALLOC_STATE( pix
[1], texenv
, PIX_STATE_SIZE
, "PIX/pixstage-1", 1 );
345 ALLOC_STATE( pix
[2], texenv
, PIX_STATE_SIZE
, "PIX/pixstage-2", 2 );
346 ALLOC_STATE( pix
[3], texenv
, PIX_STATE_SIZE
, "PIX/pixstage-3", 3 );
347 ALLOC_STATE( pix
[4], texenv
, PIX_STATE_SIZE
, "PIX/pixstage-4", 4 );
348 ALLOC_STATE( pix
[5], texenv
, PIX_STATE_SIZE
, "PIX/pixstage-5", 5 );
349 if (rmesa
->r200Screen
->drmSupportsTriPerf
) {
350 ALLOC_STATE( prf
, always
, PRF_STATE_SIZE
, "PRF/performance-tri", 0 );
353 ALLOC_STATE( prf
, never
, PRF_STATE_SIZE
, "PRF/performance-tri", 0 );
355 if (rmesa
->r200Screen
->drmSupportsPointSprites
)
356 ALLOC_STATE( spr
, always
, SPR_STATE_SIZE
, "SPR/pointsprite", 0 );
358 ALLOC_STATE (spr
, never
, SPR_STATE_SIZE
, "SPR/pointsprite", 0 );
360 r200SetUpAtomList( rmesa
);
362 /* Fill in the packet headers:
364 rmesa
->hw
.ctx
.cmd
[CTX_CMD_0
] = cmdpkt(RADEON_EMIT_PP_MISC
);
365 rmesa
->hw
.ctx
.cmd
[CTX_CMD_1
] = cmdpkt(RADEON_EMIT_PP_CNTL
);
366 rmesa
->hw
.ctx
.cmd
[CTX_CMD_2
] = cmdpkt(RADEON_EMIT_RB3D_COLORPITCH
);
367 if (rmesa
->r200Screen
->drmSupportsBlendColor
)
368 rmesa
->hw
.ctx
.cmd
[CTX_CMD_3
] = cmdpkt(R200_EMIT_RB3D_BLENDCOLOR
);
369 rmesa
->hw
.lin
.cmd
[LIN_CMD_0
] = cmdpkt(RADEON_EMIT_RE_LINE_PATTERN
);
370 rmesa
->hw
.lin
.cmd
[LIN_CMD_1
] = cmdpkt(RADEON_EMIT_SE_LINE_WIDTH
);
371 rmesa
->hw
.msk
.cmd
[MSK_CMD_0
] = cmdpkt(RADEON_EMIT_RB3D_STENCILREFMASK
);
372 rmesa
->hw
.vpt
.cmd
[VPT_CMD_0
] = cmdpkt(RADEON_EMIT_SE_VPORT_XSCALE
);
373 rmesa
->hw
.set
.cmd
[SET_CMD_0
] = cmdpkt(RADEON_EMIT_SE_CNTL
);
374 rmesa
->hw
.msc
.cmd
[MSC_CMD_0
] = cmdpkt(RADEON_EMIT_RE_MISC
);
375 rmesa
->hw
.cst
.cmd
[CST_CMD_0
] = cmdpkt(R200_EMIT_PP_CNTL_X
);
376 rmesa
->hw
.cst
.cmd
[CST_CMD_1
] = cmdpkt(R200_EMIT_RB3D_DEPTHXY_OFFSET
);
377 rmesa
->hw
.cst
.cmd
[CST_CMD_2
] = cmdpkt(R200_EMIT_RE_AUX_SCISSOR_CNTL
);
378 rmesa
->hw
.cst
.cmd
[CST_CMD_3
] = cmdpkt(R200_EMIT_RE_SCISSOR_TL_0
);
379 rmesa
->hw
.cst
.cmd
[CST_CMD_4
] = cmdpkt(R200_EMIT_SE_VAP_CNTL_STATUS
);
380 rmesa
->hw
.cst
.cmd
[CST_CMD_5
] = cmdpkt(R200_EMIT_RE_POINTSIZE
);
381 rmesa
->hw
.cst
.cmd
[CST_CMD_6
] = cmdpkt(R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0
);
382 rmesa
->hw
.tam
.cmd
[TAM_CMD_0
] = cmdpkt(R200_EMIT_PP_TAM_DEBUG3
);
383 rmesa
->hw
.tf
.cmd
[TF_CMD_0
] = cmdpkt(R200_EMIT_TFACTOR_0
);
384 if (rmesa
->r200Screen
->drmSupportsFragShader
) {
385 rmesa
->hw
.atf
.cmd
[ATF_CMD_0
] = cmdpkt(R200_EMIT_ATF_TFACTOR
);
386 rmesa
->hw
.tex
[0].cmd
[TEX_CMD_0
] = cmdpkt(R200_EMIT_PP_TXCTLALL_0
);
387 rmesa
->hw
.tex
[0].cmd
[TEX_CMD_1_NEWDRM
] = cmdpkt(R200_EMIT_PP_TXOFFSET_0
);
388 rmesa
->hw
.tex
[1].cmd
[TEX_CMD_0
] = cmdpkt(R200_EMIT_PP_TXCTLALL_1
);
389 rmesa
->hw
.tex
[1].cmd
[TEX_CMD_1_NEWDRM
] = cmdpkt(R200_EMIT_PP_TXOFFSET_1
);
390 rmesa
->hw
.tex
[2].cmd
[TEX_CMD_0
] = cmdpkt(R200_EMIT_PP_TXCTLALL_2
);
391 rmesa
->hw
.tex
[2].cmd
[TEX_CMD_1_NEWDRM
] = cmdpkt(R200_EMIT_PP_TXOFFSET_2
);
392 rmesa
->hw
.tex
[3].cmd
[TEX_CMD_0
] = cmdpkt(R200_EMIT_PP_TXCTLALL_3
);
393 rmesa
->hw
.tex
[3].cmd
[TEX_CMD_1_NEWDRM
] = cmdpkt(R200_EMIT_PP_TXOFFSET_3
);
394 rmesa
->hw
.tex
[4].cmd
[TEX_CMD_0
] = cmdpkt(R200_EMIT_PP_TXCTLALL_4
);
395 rmesa
->hw
.tex
[4].cmd
[TEX_CMD_1_NEWDRM
] = cmdpkt(R200_EMIT_PP_TXOFFSET_4
);
396 rmesa
->hw
.tex
[5].cmd
[TEX_CMD_0
] = cmdpkt(R200_EMIT_PP_TXCTLALL_5
);
397 rmesa
->hw
.tex
[5].cmd
[TEX_CMD_1_NEWDRM
] = cmdpkt(R200_EMIT_PP_TXOFFSET_5
);
399 rmesa
->hw
.tex
[0].cmd
[TEX_CMD_0
] = cmdpkt(R200_EMIT_PP_TXFILTER_0
);
400 rmesa
->hw
.tex
[0].cmd
[TEX_CMD_1_OLDDRM
] = cmdpkt(R200_EMIT_PP_TXOFFSET_0
);
401 rmesa
->hw
.tex
[1].cmd
[TEX_CMD_0
] = cmdpkt(R200_EMIT_PP_TXFILTER_1
);
402 rmesa
->hw
.tex
[1].cmd
[TEX_CMD_1_OLDDRM
] = cmdpkt(R200_EMIT_PP_TXOFFSET_1
);
403 rmesa
->hw
.tex
[2].cmd
[TEX_CMD_0
] = cmdpkt(R200_EMIT_PP_TXFILTER_2
);
404 rmesa
->hw
.tex
[2].cmd
[TEX_CMD_1_OLDDRM
] = cmdpkt(R200_EMIT_PP_TXOFFSET_2
);
405 rmesa
->hw
.tex
[3].cmd
[TEX_CMD_0
] = cmdpkt(R200_EMIT_PP_TXFILTER_3
);
406 rmesa
->hw
.tex
[3].cmd
[TEX_CMD_1_OLDDRM
] = cmdpkt(R200_EMIT_PP_TXOFFSET_3
);
407 rmesa
->hw
.tex
[4].cmd
[TEX_CMD_0
] = cmdpkt(R200_EMIT_PP_TXFILTER_4
);
408 rmesa
->hw
.tex
[4].cmd
[TEX_CMD_1_OLDDRM
] = cmdpkt(R200_EMIT_PP_TXOFFSET_4
);
409 rmesa
->hw
.tex
[5].cmd
[TEX_CMD_0
] = cmdpkt(R200_EMIT_PP_TXFILTER_5
);
410 rmesa
->hw
.tex
[5].cmd
[TEX_CMD_1_OLDDRM
] = cmdpkt(R200_EMIT_PP_TXOFFSET_5
);
412 rmesa
->hw
.afs
[0].cmd
[AFS_CMD_0
] = cmdpkt(R200_EMIT_PP_AFS_0
);
413 rmesa
->hw
.afs
[1].cmd
[AFS_CMD_0
] = cmdpkt(R200_EMIT_PP_AFS_1
);
414 rmesa
->hw
.cube
[0].cmd
[CUBE_CMD_0
] = cmdpkt(R200_EMIT_PP_CUBIC_FACES_0
);
415 rmesa
->hw
.cube
[0].cmd
[CUBE_CMD_1
] = cmdpkt(R200_EMIT_PP_CUBIC_OFFSETS_0
);
416 rmesa
->hw
.cube
[1].cmd
[CUBE_CMD_0
] = cmdpkt(R200_EMIT_PP_CUBIC_FACES_1
);
417 rmesa
->hw
.cube
[1].cmd
[CUBE_CMD_1
] = cmdpkt(R200_EMIT_PP_CUBIC_OFFSETS_1
);
418 rmesa
->hw
.cube
[2].cmd
[CUBE_CMD_0
] = cmdpkt(R200_EMIT_PP_CUBIC_FACES_2
);
419 rmesa
->hw
.cube
[2].cmd
[CUBE_CMD_1
] = cmdpkt(R200_EMIT_PP_CUBIC_OFFSETS_2
);
420 rmesa
->hw
.cube
[3].cmd
[CUBE_CMD_0
] = cmdpkt(R200_EMIT_PP_CUBIC_FACES_3
);
421 rmesa
->hw
.cube
[3].cmd
[CUBE_CMD_1
] = cmdpkt(R200_EMIT_PP_CUBIC_OFFSETS_3
);
422 rmesa
->hw
.cube
[4].cmd
[CUBE_CMD_0
] = cmdpkt(R200_EMIT_PP_CUBIC_FACES_4
);
423 rmesa
->hw
.cube
[4].cmd
[CUBE_CMD_1
] = cmdpkt(R200_EMIT_PP_CUBIC_OFFSETS_4
);
424 rmesa
->hw
.cube
[5].cmd
[CUBE_CMD_0
] = cmdpkt(R200_EMIT_PP_CUBIC_FACES_5
);
425 rmesa
->hw
.cube
[5].cmd
[CUBE_CMD_1
] = cmdpkt(R200_EMIT_PP_CUBIC_OFFSETS_5
);
426 rmesa
->hw
.pix
[0].cmd
[PIX_CMD_0
] = cmdpkt(R200_EMIT_PP_TXCBLEND_0
);
427 rmesa
->hw
.pix
[1].cmd
[PIX_CMD_0
] = cmdpkt(R200_EMIT_PP_TXCBLEND_1
);
428 rmesa
->hw
.pix
[2].cmd
[PIX_CMD_0
] = cmdpkt(R200_EMIT_PP_TXCBLEND_2
);
429 rmesa
->hw
.pix
[3].cmd
[PIX_CMD_0
] = cmdpkt(R200_EMIT_PP_TXCBLEND_3
);
430 rmesa
->hw
.pix
[4].cmd
[PIX_CMD_0
] = cmdpkt(R200_EMIT_PP_TXCBLEND_4
);
431 rmesa
->hw
.pix
[5].cmd
[PIX_CMD_0
] = cmdpkt(R200_EMIT_PP_TXCBLEND_5
);
432 rmesa
->hw
.zbs
.cmd
[ZBS_CMD_0
] = cmdpkt(RADEON_EMIT_SE_ZBIAS_FACTOR
);
433 rmesa
->hw
.tcl
.cmd
[TCL_CMD_0
] = cmdpkt(R200_EMIT_TCL_LIGHT_MODEL_CTL_0
);
434 rmesa
->hw
.tcl
.cmd
[TCL_CMD_1
] = cmdpkt(R200_EMIT_TCL_UCP_VERT_BLEND_CTL
);
435 rmesa
->hw
.tcg
.cmd
[TCG_CMD_0
] = cmdpkt(R200_EMIT_TEX_PROC_CTL_2
);
436 rmesa
->hw
.msl
.cmd
[MSL_CMD_0
] = cmdpkt(R200_EMIT_MATRIX_SELECT_0
);
437 rmesa
->hw
.vap
.cmd
[VAP_CMD_0
] = cmdpkt(R200_EMIT_VAP_CTL
);
438 rmesa
->hw
.vtx
.cmd
[VTX_CMD_0
] = cmdpkt(R200_EMIT_VTX_FMT_0
);
439 rmesa
->hw
.vtx
.cmd
[VTX_CMD_1
] = cmdpkt(R200_EMIT_OUTPUT_VTX_COMP_SEL
);
440 rmesa
->hw
.vtx
.cmd
[VTX_CMD_2
] = cmdpkt(R200_EMIT_SE_VTX_STATE_CNTL
);
441 rmesa
->hw
.vte
.cmd
[VTE_CMD_0
] = cmdpkt(R200_EMIT_VTE_CNTL
);
442 rmesa
->hw
.prf
.cmd
[PRF_CMD_0
] = cmdpkt(R200_EMIT_PP_TRI_PERF_CNTL
);
443 rmesa
->hw
.spr
.cmd
[SPR_CMD_0
] = cmdpkt(R200_EMIT_TCL_POINT_SPRITE_CNTL
);
444 rmesa
->hw
.mtl
[0].cmd
[MTL_CMD_0
] =
445 cmdvec( R200_VS_MAT_0_EMISS
, 1, 16 );
446 rmesa
->hw
.mtl
[0].cmd
[MTL_CMD_1
] =
447 cmdscl2( R200_SS_MAT_0_SHININESS
, 1, 1 );
448 rmesa
->hw
.mtl
[1].cmd
[MTL_CMD_0
] =
449 cmdvec( R200_VS_MAT_1_EMISS
, 1, 16 );
450 rmesa
->hw
.mtl
[1].cmd
[MTL_CMD_1
] =
451 cmdscl2( R200_SS_MAT_1_SHININESS
, 1, 1 );
453 rmesa
->hw
.grd
.cmd
[GRD_CMD_0
] =
454 cmdscl( R200_SS_VERT_GUARD_CLIP_ADJ_ADDR
, 1, 4 );
455 rmesa
->hw
.fog
.cmd
[FOG_CMD_0
] =
456 cmdvec( R200_VS_FOG_PARAM_ADDR
, 1, 4 );
457 rmesa
->hw
.glt
.cmd
[GLT_CMD_0
] =
458 cmdvec( R200_VS_GLOBAL_AMBIENT_ADDR
, 1, 4 );
459 rmesa
->hw
.eye
.cmd
[EYE_CMD_0
] =
460 cmdvec( R200_VS_EYE_VECTOR_ADDR
, 1, 4 );
462 rmesa
->hw
.mat
[R200_MTX_MV
].cmd
[MAT_CMD_0
] =
463 cmdvec( R200_VS_MATRIX_0_MV
, 1, 16);
464 rmesa
->hw
.mat
[R200_MTX_IMV
].cmd
[MAT_CMD_0
] =
465 cmdvec( R200_VS_MATRIX_1_INV_MV
, 1, 16);
466 rmesa
->hw
.mat
[R200_MTX_MVP
].cmd
[MAT_CMD_0
] =
467 cmdvec( R200_VS_MATRIX_2_MVP
, 1, 16);
468 rmesa
->hw
.mat
[R200_MTX_TEX0
].cmd
[MAT_CMD_0
] =
469 cmdvec( R200_VS_MATRIX_3_TEX0
, 1, 16);
470 rmesa
->hw
.mat
[R200_MTX_TEX1
].cmd
[MAT_CMD_0
] =
471 cmdvec( R200_VS_MATRIX_4_TEX1
, 1, 16);
472 rmesa
->hw
.mat
[R200_MTX_TEX2
].cmd
[MAT_CMD_0
] =
473 cmdvec( R200_VS_MATRIX_5_TEX2
, 1, 16);
474 rmesa
->hw
.mat
[R200_MTX_TEX3
].cmd
[MAT_CMD_0
] =
475 cmdvec( R200_VS_MATRIX_6_TEX3
, 1, 16);
476 rmesa
->hw
.mat
[R200_MTX_TEX4
].cmd
[MAT_CMD_0
] =
477 cmdvec( R200_VS_MATRIX_7_TEX4
, 1, 16);
478 rmesa
->hw
.mat
[R200_MTX_TEX5
].cmd
[MAT_CMD_0
] =
479 cmdvec( R200_VS_MATRIX_8_TEX5
, 1, 16);
481 for (i
= 0 ; i
< 8; i
++) {
482 rmesa
->hw
.lit
[i
].cmd
[LIT_CMD_0
] =
483 cmdvec( R200_VS_LIGHT_AMBIENT_ADDR
+ i
, 8, 24 );
484 rmesa
->hw
.lit
[i
].cmd
[LIT_CMD_1
] =
485 cmdscl( R200_SS_LIGHT_DCD_ADDR
+ i
, 8, 7 );
488 for (i
= 0 ; i
< 6; i
++) {
489 rmesa
->hw
.ucp
[i
].cmd
[UCP_CMD_0
] =
490 cmdvec( R200_VS_UCP_ADDR
+ i
, 1, 4 );
493 /* Initial Harware state:
495 rmesa
->hw
.ctx
.cmd
[CTX_PP_MISC
] = (R200_ALPHA_TEST_PASS
496 /* | R200_RIGHT_HAND_CUBE_OGL*/);
498 rmesa
->hw
.ctx
.cmd
[CTX_PP_FOG_COLOR
] = (R200_FOG_VERTEX
|
499 R200_FOG_USE_SPEC_ALPHA
);
501 rmesa
->hw
.ctx
.cmd
[CTX_RE_SOLID_COLOR
] = 0x00000000;
503 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_BLENDCNTL
] = (R200_COMB_FCN_ADD_CLAMP
|
504 (R200_BLEND_GL_ONE
<< R200_SRC_BLEND_SHIFT
) |
505 (R200_BLEND_GL_ZERO
<< R200_DST_BLEND_SHIFT
));
507 if (rmesa
->r200Screen
->drmSupportsBlendColor
) {
508 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_BLENDCOLOR
] = 0x00000000;
509 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ABLENDCNTL
] = (R200_COMB_FCN_ADD_CLAMP
|
510 (R200_BLEND_GL_ONE
<< R200_SRC_BLEND_SHIFT
) |
511 (R200_BLEND_GL_ZERO
<< R200_DST_BLEND_SHIFT
));
512 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_CBLENDCNTL
] = (R200_COMB_FCN_ADD_CLAMP
|
513 (R200_BLEND_GL_ONE
<< R200_SRC_BLEND_SHIFT
) |
514 (R200_BLEND_GL_ZERO
<< R200_DST_BLEND_SHIFT
));
517 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_DEPTHOFFSET
] =
518 rmesa
->r200Screen
->depthOffset
+ rmesa
->r200Screen
->fbLocation
;
520 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_DEPTHPITCH
] =
521 ((rmesa
->r200Screen
->depthPitch
&
522 R200_DEPTHPITCH_MASK
) |
523 R200_DEPTH_ENDIAN_NO_SWAP
);
525 if (rmesa
->using_hyperz
)
526 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_DEPTHPITCH
] |= R200_DEPTH_HYPERZ
;
528 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] = (depth_fmt
|
530 R200_STENCIL_TEST_ALWAYS
|
531 R200_STENCIL_FAIL_KEEP
|
532 R200_STENCIL_ZPASS_KEEP
|
533 R200_STENCIL_ZFAIL_KEEP
|
534 R200_Z_WRITE_ENABLE
);
536 if (rmesa
->using_hyperz
) {
537 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= R200_Z_COMPRESSION_ENABLE
|
538 R200_Z_DECOMPRESSION_ENABLE
;
539 /* if (rmesa->r200Screen->chipset & R200_CHIPSET_REAL_R200)
540 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_HIERARCHY_ENABLE;*/
543 rmesa
->hw
.ctx
.cmd
[CTX_PP_CNTL
] = (R200_ANTI_ALIAS_NONE
544 | R200_TEX_BLEND_0_ENABLE
);
546 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_CNTL
] = color_fmt
;
547 switch ( driQueryOptioni( &rmesa
->optionCache
, "dither_mode" ) ) {
548 case DRI_CONF_DITHER_XERRORDIFFRESET
:
549 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_CNTL
] |= R200_DITHER_INIT
;
551 case DRI_CONF_DITHER_ORDERED
:
552 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_CNTL
] |= R200_SCALE_DITHER_ENABLE
;
555 if ( driQueryOptioni( &rmesa
->optionCache
, "round_mode" ) ==
556 DRI_CONF_ROUND_ROUND
)
557 rmesa
->state
.color
.roundEnable
= R200_ROUND_ENABLE
;
559 rmesa
->state
.color
.roundEnable
= 0;
560 if ( driQueryOptioni (&rmesa
->optionCache
, "color_reduction" ) ==
561 DRI_CONF_COLOR_REDUCTION_DITHER
)
562 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_CNTL
] |= R200_DITHER_ENABLE
;
564 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_CNTL
] |= rmesa
->state
.color
.roundEnable
;
567 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_COLOROFFSET
] = ((rmesa
->state
.color
.drawOffset
+
568 rmesa
->r200Screen
->fbLocation
)
569 & R200_COLOROFFSET_MASK
);
571 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_COLORPITCH
] = ((rmesa
->state
.color
.drawPitch
&
572 R200_COLORPITCH_MASK
) |
573 R200_COLOR_ENDIAN_NO_SWAP
);
575 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_COLOROFFSET
] = ((drawOffset
+
576 rmesa
->r200Screen
->fbLocation
)
577 & R200_COLOROFFSET_MASK
);
579 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_COLORPITCH
] = ((drawPitch
&
580 R200_COLORPITCH_MASK
) |
581 R200_COLOR_ENDIAN_NO_SWAP
);
583 /* (fixed size) sarea is initialized to zero afaics so can omit version check. Phew! */
584 if (rmesa
->sarea
->tiling_enabled
) {
585 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_COLORPITCH
] |= R200_COLOR_TILE_ENABLE
;
588 rmesa
->hw
.prf
.cmd
[PRF_PP_TRI_PERF
] = R200_TRI_CUTOFF_MASK
- R200_TRI_CUTOFF_MASK
*
589 driQueryOptionf (&rmesa
->optionCache
,"texture_blend_quality");
590 rmesa
->hw
.prf
.cmd
[PRF_PP_PERF_CNTL
] = 0;
592 rmesa
->hw
.set
.cmd
[SET_SE_CNTL
] = (R200_FFACE_CULL_CCW
|
595 R200_FLAT_SHADE_VTX_LAST
|
596 R200_DIFFUSE_SHADE_GOURAUD
|
597 R200_ALPHA_SHADE_GOURAUD
|
598 R200_SPECULAR_SHADE_GOURAUD
|
599 R200_FOG_SHADE_GOURAUD
|
600 R200_VTX_PIX_CENTER_OGL
|
601 R200_ROUND_MODE_TRUNC
|
602 R200_ROUND_PREC_8TH_PIX
);
604 rmesa
->hw
.set
.cmd
[SET_RE_CNTL
] = (R200_PERSPECTIVE_ENABLE
|
605 R200_SCISSOR_ENABLE
);
607 rmesa
->hw
.lin
.cmd
[LIN_RE_LINE_PATTERN
] = ((1 << 16) | 0xffff);
609 rmesa
->hw
.lin
.cmd
[LIN_RE_LINE_STATE
] =
610 ((0 << R200_LINE_CURRENT_PTR_SHIFT
) |
611 (1 << R200_LINE_CURRENT_COUNT_SHIFT
));
613 rmesa
->hw
.lin
.cmd
[LIN_SE_LINE_WIDTH
] = (1 << 4);
615 rmesa
->hw
.msk
.cmd
[MSK_RB3D_STENCILREFMASK
] =
616 ((0x00 << R200_STENCIL_REF_SHIFT
) |
617 (0xff << R200_STENCIL_MASK_SHIFT
) |
618 (0xff << R200_STENCIL_WRITEMASK_SHIFT
));
620 rmesa
->hw
.msk
.cmd
[MSK_RB3D_ROPCNTL
] = R200_ROP_COPY
;
621 rmesa
->hw
.msk
.cmd
[MSK_RB3D_PLANEMASK
] = 0xffffffff;
623 rmesa
->hw
.tam
.cmd
[TAM_DEBUG3
] = 0;
625 rmesa
->hw
.msc
.cmd
[MSC_RE_MISC
] =
626 ((0 << R200_STIPPLE_X_OFFSET_SHIFT
) |
627 (0 << R200_STIPPLE_Y_OFFSET_SHIFT
) |
628 R200_STIPPLE_BIG_BIT_ORDER
);
631 rmesa
->hw
.cst
.cmd
[CST_PP_CNTL_X
] = 0;
632 rmesa
->hw
.cst
.cmd
[CST_RB3D_DEPTHXY_OFFSET
] = 0;
633 rmesa
->hw
.cst
.cmd
[CST_RE_AUX_SCISSOR_CNTL
] = 0x0;
634 rmesa
->hw
.cst
.cmd
[CST_RE_SCISSOR_TL_0
] = 0;
635 rmesa
->hw
.cst
.cmd
[CST_RE_SCISSOR_BR_0
] = 0;
636 rmesa
->hw
.cst
.cmd
[CST_SE_VAP_CNTL_STATUS
] =
637 #ifdef MESA_BIG_ENDIAN
643 if (!(rmesa
->r200Screen
->chipset
& R200_CHIPSET_TCL
)) {
645 rmesa
->hw
.cst
.cmd
[CST_SE_VAP_CNTL_STATUS
] |= (1<<8);
648 rmesa
->hw
.cst
.cmd
[CST_RE_POINTSIZE
] =
649 (((GLuint
)(ctx
->Const
.MaxPointSize
* 16.0)) << R200_MAXPOINTSIZE_SHIFT
) | 0x10;
650 rmesa
->hw
.cst
.cmd
[CST_SE_TCL_INPUT_VTX_0
] =
651 (0x0 << R200_VERTEX_POSITION_ADDR__SHIFT
);
652 rmesa
->hw
.cst
.cmd
[CST_SE_TCL_INPUT_VTX_1
] =
653 (0x02 << R200_VTX_COLOR_0_ADDR__SHIFT
) |
654 (0x03 << R200_VTX_COLOR_1_ADDR__SHIFT
);
655 rmesa
->hw
.cst
.cmd
[CST_SE_TCL_INPUT_VTX_2
] =
656 (0x06 << R200_VTX_TEX_0_ADDR__SHIFT
) |
657 (0x07 << R200_VTX_TEX_1_ADDR__SHIFT
) |
658 (0x08 << R200_VTX_TEX_2_ADDR__SHIFT
) |
659 (0x09 << R200_VTX_TEX_3_ADDR__SHIFT
);
660 rmesa
->hw
.cst
.cmd
[CST_SE_TCL_INPUT_VTX_3
] =
661 (0x0A << R200_VTX_TEX_4_ADDR__SHIFT
) |
662 (0x0B << R200_VTX_TEX_5_ADDR__SHIFT
);
665 rmesa
->hw
.vpt
.cmd
[VPT_SE_VPORT_XSCALE
] = 0x00000000;
666 rmesa
->hw
.vpt
.cmd
[VPT_SE_VPORT_XOFFSET
] = 0x00000000;
667 rmesa
->hw
.vpt
.cmd
[VPT_SE_VPORT_YSCALE
] = 0x00000000;
668 rmesa
->hw
.vpt
.cmd
[VPT_SE_VPORT_YOFFSET
] = 0x00000000;
669 rmesa
->hw
.vpt
.cmd
[VPT_SE_VPORT_ZSCALE
] = 0x00000000;
670 rmesa
->hw
.vpt
.cmd
[VPT_SE_VPORT_ZOFFSET
] = 0x00000000;
672 for ( i
= 0 ; i
< ctx
->Const
.MaxTextureUnits
; i
++ ) {
673 rmesa
->hw
.tex
[i
].cmd
[TEX_PP_TXFILTER
] = R200_BORDER_MODE_OGL
;
674 rmesa
->hw
.tex
[i
].cmd
[TEX_PP_TXFORMAT
] =
675 ((i
<< R200_TXFORMAT_ST_ROUTE_SHIFT
) | /* <-- note i */
676 (2 << R200_TXFORMAT_WIDTH_SHIFT
) |
677 (2 << R200_TXFORMAT_HEIGHT_SHIFT
));
678 rmesa
->hw
.tex
[i
].cmd
[TEX_PP_BORDER_COLOR
] = 0;
679 rmesa
->hw
.tex
[i
].cmd
[TEX_PP_TXFORMAT_X
] =
680 (/* R200_TEXCOORD_PROJ | */
681 0x100000); /* Small default bias */
682 if (rmesa
->r200Screen
->drmSupportsFragShader
) {
683 rmesa
->hw
.tex
[i
].cmd
[TEX_PP_TXOFFSET_NEWDRM
] =
684 rmesa
->r200Screen
->texOffset
[RADEON_LOCAL_TEX_HEAP
];
685 rmesa
->hw
.tex
[i
].cmd
[TEX_PP_CUBIC_FACES
] = 0;
686 rmesa
->hw
.tex
[i
].cmd
[TEX_PP_TXMULTI_CTL
] = 0;
689 rmesa
->hw
.tex
[i
].cmd
[TEX_PP_TXOFFSET_OLDDRM
] =
690 rmesa
->r200Screen
->texOffset
[RADEON_LOCAL_TEX_HEAP
];
693 rmesa
->hw
.cube
[i
].cmd
[CUBE_PP_CUBIC_FACES
] = 0;
694 rmesa
->hw
.cube
[i
].cmd
[CUBE_PP_CUBIC_OFFSET_F1
] =
695 rmesa
->r200Screen
->texOffset
[RADEON_LOCAL_TEX_HEAP
];
696 rmesa
->hw
.cube
[i
].cmd
[CUBE_PP_CUBIC_OFFSET_F2
] =
697 rmesa
->r200Screen
->texOffset
[RADEON_LOCAL_TEX_HEAP
];
698 rmesa
->hw
.cube
[i
].cmd
[CUBE_PP_CUBIC_OFFSET_F3
] =
699 rmesa
->r200Screen
->texOffset
[RADEON_LOCAL_TEX_HEAP
];
700 rmesa
->hw
.cube
[i
].cmd
[CUBE_PP_CUBIC_OFFSET_F4
] =
701 rmesa
->r200Screen
->texOffset
[RADEON_LOCAL_TEX_HEAP
];
702 rmesa
->hw
.cube
[i
].cmd
[CUBE_PP_CUBIC_OFFSET_F5
] =
703 rmesa
->r200Screen
->texOffset
[RADEON_LOCAL_TEX_HEAP
];
705 rmesa
->hw
.pix
[i
].cmd
[PIX_PP_TXCBLEND
] =
706 (R200_TXC_ARG_A_ZERO
|
707 R200_TXC_ARG_B_ZERO
|
708 R200_TXC_ARG_C_DIFFUSE_COLOR
|
711 rmesa
->hw
.pix
[i
].cmd
[PIX_PP_TXCBLEND2
] =
712 ((i
<< R200_TXC_TFACTOR_SEL_SHIFT
) |
715 R200_TXC_OUTPUT_REG_R0
);
717 rmesa
->hw
.pix
[i
].cmd
[PIX_PP_TXABLEND
] =
718 (R200_TXA_ARG_A_ZERO
|
719 R200_TXA_ARG_B_ZERO
|
720 R200_TXA_ARG_C_DIFFUSE_ALPHA
|
723 rmesa
->hw
.pix
[i
].cmd
[PIX_PP_TXABLEND2
] =
724 ((i
<< R200_TXA_TFACTOR_SEL_SHIFT
) |
727 R200_TXA_OUTPUT_REG_R0
);
730 rmesa
->hw
.tf
.cmd
[TF_TFACTOR_0
] = 0;
731 rmesa
->hw
.tf
.cmd
[TF_TFACTOR_1
] = 0;
732 rmesa
->hw
.tf
.cmd
[TF_TFACTOR_2
] = 0;
733 rmesa
->hw
.tf
.cmd
[TF_TFACTOR_3
] = 0;
734 rmesa
->hw
.tf
.cmd
[TF_TFACTOR_4
] = 0;
735 rmesa
->hw
.tf
.cmd
[TF_TFACTOR_5
] = 0;
737 rmesa
->hw
.vap
.cmd
[VAP_SE_VAP_CNTL
] =
738 (R200_VAP_TCL_ENABLE
|
739 (0x9 << R200_VAP_VF_MAX_VTX_NUM__SHIFT
));
741 rmesa
->hw
.vte
.cmd
[VTE_SE_VTE_CNTL
] =
742 (R200_VPORT_X_SCALE_ENA
|
743 R200_VPORT_Y_SCALE_ENA
|
744 R200_VPORT_Z_SCALE_ENA
|
745 R200_VPORT_X_OFFSET_ENA
|
746 R200_VPORT_Y_OFFSET_ENA
|
747 R200_VPORT_Z_OFFSET_ENA
|
748 /* FIXME: Turn on for tex rect only */
749 R200_VTX_ST_DENORMALIZED
|
753 rmesa
->hw
.vtx
.cmd
[VTX_VTXFMT_0
] = 0;
754 rmesa
->hw
.vtx
.cmd
[VTX_VTXFMT_1
] = 0;
755 rmesa
->hw
.vtx
.cmd
[VTX_TCL_OUTPUT_VTXFMT_0
] =
756 ((R200_VTX_Z0
| R200_VTX_W0
|
757 (R200_VTX_FP_RGBA
<< R200_VTX_COLOR_0_SHIFT
)));
758 rmesa
->hw
.vtx
.cmd
[VTX_TCL_OUTPUT_VTXFMT_1
] = 0;
759 rmesa
->hw
.vtx
.cmd
[VTX_TCL_OUTPUT_COMPSEL
] = (R200_OUTPUT_XYZW
);
760 rmesa
->hw
.vtx
.cmd
[VTX_STATE_CNTL
] = R200_VSC_UPDATE_USER_COLOR_0_ENABLE
;
763 /* Matrix selection */
764 rmesa
->hw
.msl
.cmd
[MSL_MATRIX_SELECT_0
] =
765 (R200_MTX_MV
<< R200_MODELVIEW_0_SHIFT
);
767 rmesa
->hw
.msl
.cmd
[MSL_MATRIX_SELECT_1
] =
768 (R200_MTX_IMV
<< R200_IT_MODELVIEW_0_SHIFT
);
770 rmesa
->hw
.msl
.cmd
[MSL_MATRIX_SELECT_2
] =
771 (R200_MTX_MVP
<< R200_MODELPROJECT_0_SHIFT
);
773 rmesa
->hw
.msl
.cmd
[MSL_MATRIX_SELECT_3
] =
774 ((R200_MTX_TEX0
<< R200_TEXMAT_0_SHIFT
) |
775 (R200_MTX_TEX1
<< R200_TEXMAT_1_SHIFT
) |
776 (R200_MTX_TEX2
<< R200_TEXMAT_2_SHIFT
) |
777 (R200_MTX_TEX3
<< R200_TEXMAT_3_SHIFT
));
779 rmesa
->hw
.msl
.cmd
[MSL_MATRIX_SELECT_4
] =
780 ((R200_MTX_TEX4
<< R200_TEXMAT_4_SHIFT
) |
781 (R200_MTX_TEX5
<< R200_TEXMAT_5_SHIFT
));
784 /* General TCL state */
785 rmesa
->hw
.tcl
.cmd
[TCL_LIGHT_MODEL_CTL_0
] =
786 (R200_SPECULAR_LIGHTS
|
787 R200_DIFFUSE_SPECULAR_COMBINE
|
788 R200_LOCAL_LIGHT_VEC_GL
|
789 R200_LM0_SOURCE_MATERIAL_0
<< R200_FRONT_SHININESS_SOURCE_SHIFT
|
790 R200_LM0_SOURCE_MATERIAL_1
<< R200_BACK_SHININESS_SOURCE_SHIFT
);
792 rmesa
->hw
.tcl
.cmd
[TCL_LIGHT_MODEL_CTL_1
] =
793 ((R200_LM1_SOURCE_MATERIAL_0
<< R200_FRONT_EMISSIVE_SOURCE_SHIFT
) |
794 (R200_LM1_SOURCE_MATERIAL_0
<< R200_FRONT_AMBIENT_SOURCE_SHIFT
) |
795 (R200_LM1_SOURCE_MATERIAL_0
<< R200_FRONT_DIFFUSE_SOURCE_SHIFT
) |
796 (R200_LM1_SOURCE_MATERIAL_0
<< R200_FRONT_SPECULAR_SOURCE_SHIFT
) |
797 (R200_LM1_SOURCE_MATERIAL_1
<< R200_BACK_EMISSIVE_SOURCE_SHIFT
) |
798 (R200_LM1_SOURCE_MATERIAL_1
<< R200_BACK_AMBIENT_SOURCE_SHIFT
) |
799 (R200_LM1_SOURCE_MATERIAL_1
<< R200_BACK_DIFFUSE_SOURCE_SHIFT
) |
800 (R200_LM1_SOURCE_MATERIAL_1
<< R200_BACK_SPECULAR_SOURCE_SHIFT
));
802 rmesa
->hw
.tcl
.cmd
[TCL_PER_LIGHT_CTL_0
] = 0; /* filled in via callbacks */
803 rmesa
->hw
.tcl
.cmd
[TCL_PER_LIGHT_CTL_1
] = 0;
804 rmesa
->hw
.tcl
.cmd
[TCL_PER_LIGHT_CTL_2
] = 0;
805 rmesa
->hw
.tcl
.cmd
[TCL_PER_LIGHT_CTL_3
] = 0;
807 rmesa
->hw
.tcl
.cmd
[TCL_UCP_VERT_BLEND_CTL
] =
808 (R200_UCP_IN_CLIP_SPACE
|
809 R200_CULL_FRONT_IS_CCW
);
811 /* Texgen/Texmat state */
812 rmesa
->hw
.tcg
.cmd
[TCG_TEX_PROC_CTL_2
] = 0x00ffffff;
813 rmesa
->hw
.tcg
.cmd
[TCG_TEX_PROC_CTL_3
] =
814 ((0 << R200_TEXGEN_0_INPUT_TEX_SHIFT
) |
815 (1 << R200_TEXGEN_1_INPUT_TEX_SHIFT
) |
816 (2 << R200_TEXGEN_2_INPUT_TEX_SHIFT
) |
817 (3 << R200_TEXGEN_3_INPUT_TEX_SHIFT
) |
818 (4 << R200_TEXGEN_4_INPUT_TEX_SHIFT
) |
819 (5 << R200_TEXGEN_5_INPUT_TEX_SHIFT
));
820 rmesa
->hw
.tcg
.cmd
[TCG_TEX_PROC_CTL_0
] = 0;
821 rmesa
->hw
.tcg
.cmd
[TCG_TEX_PROC_CTL_1
] =
822 ((0 << R200_TEXGEN_0_INPUT_SHIFT
) |
823 (1 << R200_TEXGEN_1_INPUT_SHIFT
) |
824 (2 << R200_TEXGEN_2_INPUT_SHIFT
) |
825 (3 << R200_TEXGEN_3_INPUT_SHIFT
) |
826 (4 << R200_TEXGEN_4_INPUT_SHIFT
) |
827 (5 << R200_TEXGEN_5_INPUT_SHIFT
));
828 rmesa
->hw
.tcg
.cmd
[TCG_TEX_CYL_WRAP_CTL
] = 0;
831 for (i
= 0 ; i
< 8; i
++) {
832 struct gl_light
*l
= &ctx
->Light
.Light
[i
];
833 GLenum p
= GL_LIGHT0
+ i
;
834 *(float *)&(rmesa
->hw
.lit
[i
].cmd
[LIT_RANGE_CUTOFF
]) = FLT_MAX
;
836 ctx
->Driver
.Lightfv( ctx
, p
, GL_AMBIENT
, l
->Ambient
);
837 ctx
->Driver
.Lightfv( ctx
, p
, GL_DIFFUSE
, l
->Diffuse
);
838 ctx
->Driver
.Lightfv( ctx
, p
, GL_SPECULAR
, l
->Specular
);
839 ctx
->Driver
.Lightfv( ctx
, p
, GL_POSITION
, NULL
);
840 ctx
->Driver
.Lightfv( ctx
, p
, GL_SPOT_DIRECTION
, NULL
);
841 ctx
->Driver
.Lightfv( ctx
, p
, GL_SPOT_EXPONENT
, &l
->SpotExponent
);
842 ctx
->Driver
.Lightfv( ctx
, p
, GL_SPOT_CUTOFF
, &l
->SpotCutoff
);
843 ctx
->Driver
.Lightfv( ctx
, p
, GL_CONSTANT_ATTENUATION
,
844 &l
->ConstantAttenuation
);
845 ctx
->Driver
.Lightfv( ctx
, p
, GL_LINEAR_ATTENUATION
,
846 &l
->LinearAttenuation
);
847 ctx
->Driver
.Lightfv( ctx
, p
, GL_QUADRATIC_ATTENUATION
,
848 &l
->QuadraticAttenuation
);
849 *(float *)&(rmesa
->hw
.lit
[i
].cmd
[LIT_ATTEN_XXX
]) = 0.0;
852 ctx
->Driver
.LightModelfv( ctx
, GL_LIGHT_MODEL_AMBIENT
,
853 ctx
->Light
.Model
.Ambient
);
855 TNL_CONTEXT(ctx
)->Driver
.NotifyMaterialChange( ctx
);
857 for (i
= 0 ; i
< 6; i
++) {
858 ctx
->Driver
.ClipPlane( ctx
, GL_CLIP_PLANE0
+ i
, NULL
);
861 ctx
->Driver
.Fogfv( ctx
, GL_FOG_MODE
, NULL
);
862 ctx
->Driver
.Fogfv( ctx
, GL_FOG_DENSITY
, &ctx
->Fog
.Density
);
863 ctx
->Driver
.Fogfv( ctx
, GL_FOG_START
, &ctx
->Fog
.Start
);
864 ctx
->Driver
.Fogfv( ctx
, GL_FOG_END
, &ctx
->Fog
.End
);
865 ctx
->Driver
.Fogfv( ctx
, GL_FOG_COLOR
, ctx
->Fog
.Color
);
866 ctx
->Driver
.Fogfv( ctx
, GL_FOG_COORDINATE_SOURCE_EXT
, NULL
);
868 rmesa
->hw
.grd
.cmd
[GRD_VERT_GUARD_CLIP_ADJ
] = IEEE_ONE
;
869 rmesa
->hw
.grd
.cmd
[GRD_VERT_GUARD_DISCARD_ADJ
] = IEEE_ONE
;
870 rmesa
->hw
.grd
.cmd
[GRD_HORZ_GUARD_CLIP_ADJ
] = IEEE_ONE
;
871 rmesa
->hw
.grd
.cmd
[GRD_HORZ_GUARD_DISCARD_ADJ
] = IEEE_ONE
;
873 rmesa
->hw
.eye
.cmd
[EYE_X
] = 0;
874 rmesa
->hw
.eye
.cmd
[EYE_Y
] = 0;
875 rmesa
->hw
.eye
.cmd
[EYE_Z
] = IEEE_ONE
;
876 rmesa
->hw
.eye
.cmd
[EYE_RESCALE_FACTOR
] = IEEE_ONE
;
878 rmesa
->hw
.spr
.cmd
[SPR_POINT_SPRITE_CNTL
] = R200_POINTSIZE_SEL_STATE
;
880 r200LightingSpaceChange( ctx
);
882 rmesa
->hw
.all_dirty
= GL_TRUE
;