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r200: fix veclinear emission
[mesa.git] / src / mesa / drivers / dri / r200 / r200_state_init.c
1 /*
2 Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
3
4 The Weather Channel (TM) funded Tungsten Graphics to develop the
5 initial release of the Radeon 8500 driver under the XFree86 license.
6 This notice must be preserved.
7
8 Permission is hereby granted, free of charge, to any person obtaining
9 a copy of this software and associated documentation files (the
10 "Software"), to deal in the Software without restriction, including
11 without limitation the rights to use, copy, modify, merge, publish,
12 distribute, sublicense, and/or sell copies of the Software, and to
13 permit persons to whom the Software is furnished to do so, subject to
14 the following conditions:
15
16 The above copyright notice and this permission notice (including the
17 next paragraph) shall be included in all copies or substantial
18 portions of the Software.
19
20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 */
28
29 /*
30 * Authors:
31 * Keith Whitwell <keith@tungstengraphics.com>
32 */
33
34 #include "main/glheader.h"
35 #include "main/imports.h"
36 #include "main/enums.h"
37 #include "main/colormac.h"
38 #include "main/api_arrayelt.h"
39
40 #include "swrast/swrast.h"
41 #include "vbo/vbo.h"
42 #include "tnl/tnl.h"
43 #include "tnl/t_pipeline.h"
44 #include "swrast_setup/swrast_setup.h"
45
46 #include "radeon_common.h"
47 #include "radeon_mipmap_tree.h"
48 #include "r200_context.h"
49 #include "r200_ioctl.h"
50 #include "r200_state.h"
51 #include "r200_tcl.h"
52 #include "r200_tex.h"
53 #include "r200_swtcl.h"
54
55 #include "xmlpool.h"
56
57 /* New (1.3) state mechanism. 3 commands (packet, scalar, vector) in
58 * 1.3 cmdbuffers allow all previous state to be updated as well as
59 * the tcl scalar and vector areas.
60 */
61 static struct {
62 int start;
63 int len;
64 const char *name;
65 } packet[RADEON_MAX_STATE_PACKETS] = {
66 {RADEON_PP_MISC, 7, "RADEON_PP_MISC"},
67 {RADEON_PP_CNTL, 3, "RADEON_PP_CNTL"},
68 {RADEON_RB3D_COLORPITCH, 1, "RADEON_RB3D_COLORPITCH"},
69 {RADEON_RE_LINE_PATTERN, 2, "RADEON_RE_LINE_PATTERN"},
70 {RADEON_SE_LINE_WIDTH, 1, "RADEON_SE_LINE_WIDTH"},
71 {RADEON_PP_LUM_MATRIX, 1, "RADEON_PP_LUM_MATRIX"},
72 {RADEON_PP_ROT_MATRIX_0, 2, "RADEON_PP_ROT_MATRIX_0"},
73 {RADEON_RB3D_STENCILREFMASK, 3, "RADEON_RB3D_STENCILREFMASK"},
74 {RADEON_SE_VPORT_XSCALE, 6, "RADEON_SE_VPORT_XSCALE"},
75 {RADEON_SE_CNTL, 2, "RADEON_SE_CNTL"},
76 {RADEON_SE_CNTL_STATUS, 1, "RADEON_SE_CNTL_STATUS"},
77 {RADEON_RE_MISC, 1, "RADEON_RE_MISC"},
78 {RADEON_PP_TXFILTER_0, 6, "RADEON_PP_TXFILTER_0"},
79 {RADEON_PP_BORDER_COLOR_0, 1, "RADEON_PP_BORDER_COLOR_0"},
80 {RADEON_PP_TXFILTER_1, 6, "RADEON_PP_TXFILTER_1"},
81 {RADEON_PP_BORDER_COLOR_1, 1, "RADEON_PP_BORDER_COLOR_1"},
82 {RADEON_PP_TXFILTER_2, 6, "RADEON_PP_TXFILTER_2"},
83 {RADEON_PP_BORDER_COLOR_2, 1, "RADEON_PP_BORDER_COLOR_2"},
84 {RADEON_SE_ZBIAS_FACTOR, 2, "RADEON_SE_ZBIAS_FACTOR"},
85 {RADEON_SE_TCL_OUTPUT_VTX_FMT, 11, "RADEON_SE_TCL_OUTPUT_VTX_FMT"},
86 {RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED, 17,
87 "RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED"},
88 {R200_PP_TXCBLEND_0, 4, "R200_PP_TXCBLEND_0"},
89 {R200_PP_TXCBLEND_1, 4, "R200_PP_TXCBLEND_1"},
90 {R200_PP_TXCBLEND_2, 4, "R200_PP_TXCBLEND_2"},
91 {R200_PP_TXCBLEND_3, 4, "R200_PP_TXCBLEND_3"},
92 {R200_PP_TXCBLEND_4, 4, "R200_PP_TXCBLEND_4"},
93 {R200_PP_TXCBLEND_5, 4, "R200_PP_TXCBLEND_5"},
94 {R200_PP_TXCBLEND_6, 4, "R200_PP_TXCBLEND_6"},
95 {R200_PP_TXCBLEND_7, 4, "R200_PP_TXCBLEND_7"},
96 {R200_SE_TCL_LIGHT_MODEL_CTL_0, 6, "R200_SE_TCL_LIGHT_MODEL_CTL_0"},
97 {R200_PP_TFACTOR_0, 6, "R200_PP_TFACTOR_0"},
98 {R200_SE_VTX_FMT_0, 4, "R200_SE_VTX_FMT_0"},
99 {R200_SE_VAP_CNTL, 1, "R200_SE_VAP_CNTL"},
100 {R200_SE_TCL_MATRIX_SEL_0, 5, "R200_SE_TCL_MATRIX_SEL_0"},
101 {R200_SE_TCL_TEX_PROC_CTL_2, 5, "R200_SE_TCL_TEX_PROC_CTL_2"},
102 {R200_SE_TCL_UCP_VERT_BLEND_CTL, 1, "R200_SE_TCL_UCP_VERT_BLEND_CTL"},
103 {R200_PP_TXFILTER_0, 6, "R200_PP_TXFILTER_0"},
104 {R200_PP_TXFILTER_1, 6, "R200_PP_TXFILTER_1"},
105 {R200_PP_TXFILTER_2, 6, "R200_PP_TXFILTER_2"},
106 {R200_PP_TXFILTER_3, 6, "R200_PP_TXFILTER_3"},
107 {R200_PP_TXFILTER_4, 6, "R200_PP_TXFILTER_4"},
108 {R200_PP_TXFILTER_5, 6, "R200_PP_TXFILTER_5"},
109 {R200_PP_TXOFFSET_0, 1, "R200_PP_TXOFFSET_0"},
110 {R200_PP_TXOFFSET_1, 1, "R200_PP_TXOFFSET_1"},
111 {R200_PP_TXOFFSET_2, 1, "R200_PP_TXOFFSET_2"},
112 {R200_PP_TXOFFSET_3, 1, "R200_PP_TXOFFSET_3"},
113 {R200_PP_TXOFFSET_4, 1, "R200_PP_TXOFFSET_4"},
114 {R200_PP_TXOFFSET_5, 1, "R200_PP_TXOFFSET_5"},
115 {R200_SE_VTE_CNTL, 1, "R200_SE_VTE_CNTL"},
116 {R200_SE_TCL_OUTPUT_VTX_COMP_SEL, 1,
117 "R200_SE_TCL_OUTPUT_VTX_COMP_SEL"},
118 {R200_PP_TAM_DEBUG3, 1, "R200_PP_TAM_DEBUG3"},
119 {R200_PP_CNTL_X, 1, "R200_PP_CNTL_X"},
120 {R200_RB3D_DEPTHXY_OFFSET, 1, "R200_RB3D_DEPTHXY_OFFSET"},
121 {R200_RE_AUX_SCISSOR_CNTL, 1, "R200_RE_AUX_SCISSOR_CNTL"},
122 {R200_RE_SCISSOR_TL_0, 2, "R200_RE_SCISSOR_TL_0"},
123 {R200_RE_SCISSOR_TL_1, 2, "R200_RE_SCISSOR_TL_1"},
124 {R200_RE_SCISSOR_TL_2, 2, "R200_RE_SCISSOR_TL_2"},
125 {R200_SE_VAP_CNTL_STATUS, 1, "R200_SE_VAP_CNTL_STATUS"},
126 {R200_SE_VTX_STATE_CNTL, 1, "R200_SE_VTX_STATE_CNTL"},
127 {R200_RE_POINTSIZE, 1, "R200_RE_POINTSIZE"},
128 {R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0, 4,
129 "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0"},
130 {R200_PP_CUBIC_FACES_0, 1, "R200_PP_CUBIC_FACES_0"}, /* 61 */
131 {R200_PP_CUBIC_OFFSET_F1_0, 5, "R200_PP_CUBIC_OFFSET_F1_0"}, /* 62 */
132 {R200_PP_CUBIC_FACES_1, 1, "R200_PP_CUBIC_FACES_1"},
133 {R200_PP_CUBIC_OFFSET_F1_1, 5, "R200_PP_CUBIC_OFFSET_F1_1"},
134 {R200_PP_CUBIC_FACES_2, 1, "R200_PP_CUBIC_FACES_2"},
135 {R200_PP_CUBIC_OFFSET_F1_2, 5, "R200_PP_CUBIC_OFFSET_F1_2"},
136 {R200_PP_CUBIC_FACES_3, 1, "R200_PP_CUBIC_FACES_3"},
137 {R200_PP_CUBIC_OFFSET_F1_3, 5, "R200_PP_CUBIC_OFFSET_F1_3"},
138 {R200_PP_CUBIC_FACES_4, 1, "R200_PP_CUBIC_FACES_4"},
139 {R200_PP_CUBIC_OFFSET_F1_4, 5, "R200_PP_CUBIC_OFFSET_F1_4"},
140 {R200_PP_CUBIC_FACES_5, 1, "R200_PP_CUBIC_FACES_5"},
141 {R200_PP_CUBIC_OFFSET_F1_5, 5, "R200_PP_CUBIC_OFFSET_F1_5"},
142 {RADEON_PP_TEX_SIZE_0, 2, "RADEON_PP_TEX_SIZE_0"},
143 {RADEON_PP_TEX_SIZE_1, 2, "RADEON_PP_TEX_SIZE_1"},
144 {RADEON_PP_TEX_SIZE_2, 2, "RADEON_PP_TEX_SIZE_2"},
145 {R200_RB3D_BLENDCOLOR, 3, "R200_RB3D_BLENDCOLOR"},
146 {R200_SE_TCL_POINT_SPRITE_CNTL, 1, "R200_SE_TCL_POINT_SPRITE_CNTL"},
147 {RADEON_PP_CUBIC_FACES_0, 1, "RADEON_PP_CUBIC_FACES_0"},
148 {RADEON_PP_CUBIC_OFFSET_T0_0, 5, "RADEON_PP_CUBIC_OFFSET_T0_0"},
149 {RADEON_PP_CUBIC_FACES_1, 1, "RADEON_PP_CUBIC_FACES_1"},
150 {RADEON_PP_CUBIC_OFFSET_T1_0, 5, "RADEON_PP_CUBIC_OFFSET_T1_0"},
151 {RADEON_PP_CUBIC_FACES_2, 1, "RADEON_PP_CUBIC_FACES_2"},
152 {RADEON_PP_CUBIC_OFFSET_T2_0, 5, "RADEON_PP_CUBIC_OFFSET_T2_0"},
153 {R200_PP_TRI_PERF, 2, "R200_PP_TRI_PERF"},
154 {R200_PP_TXCBLEND_8, 32, "R200_PP_AFS_0"}, /* 85 */
155 {R200_PP_TXCBLEND_0, 32, "R200_PP_AFS_1"},
156 {R200_PP_TFACTOR_0, 8, "R200_ATF_TFACTOR"},
157 {R200_PP_TXFILTER_0, 8, "R200_PP_TXCTLALL_0"},
158 {R200_PP_TXFILTER_1, 8, "R200_PP_TXCTLALL_1"},
159 {R200_PP_TXFILTER_2, 8, "R200_PP_TXCTLALL_2"},
160 {R200_PP_TXFILTER_3, 8, "R200_PP_TXCTLALL_3"},
161 {R200_PP_TXFILTER_4, 8, "R200_PP_TXCTLALL_4"},
162 {R200_PP_TXFILTER_5, 8, "R200_PP_TXCTLALL_5"},
163 {R200_VAP_PVS_CNTL_1, 2, "R200_VAP_PVS_CNTL"},
164 };
165
166 /* =============================================================
167 * State initialization
168 */
169
170 void r200PrintDirty( r200ContextPtr rmesa, const char *msg )
171 {
172 struct radeon_state_atom *l;
173
174 fprintf(stderr, msg);
175 fprintf(stderr, ": ");
176
177 foreach(l, &rmesa->radeon.hw.atomlist) {
178 if (l->dirty || rmesa->radeon.hw.all_dirty)
179 fprintf(stderr, "%s, ", l->name);
180 }
181
182 fprintf(stderr, "\n");
183 }
184
185 static int cmdpkt( r200ContextPtr rmesa, int id )
186 {
187 drm_radeon_cmd_header_t h;
188
189 if (rmesa->radeon.radeonScreen->kernel_mm) {
190 return CP_PACKET0(packet[id].start, packet[id].len - 1);
191 } else {
192 h.i = 0;
193 h.packet.cmd_type = RADEON_CMD_PACKET;
194 h.packet.packet_id = id;
195 }
196 return h.i;
197 }
198
199 static int cmdvec( int offset, int stride, int count )
200 {
201 drm_radeon_cmd_header_t h;
202 h.i = 0;
203 h.vectors.cmd_type = RADEON_CMD_VECTORS;
204 h.vectors.offset = offset;
205 h.vectors.stride = stride;
206 h.vectors.count = count;
207 return h.i;
208 }
209
210 /* warning: the count here is divided by 4 compared to other cmds
211 (so it doesn't exceed the char size)! */
212 static int cmdveclinear( int offset, int count )
213 {
214 drm_radeon_cmd_header_t h;
215 h.i = 0;
216 h.veclinear.cmd_type = RADEON_CMD_VECLINEAR;
217 h.veclinear.addr_lo = offset & 0xff;
218 h.veclinear.addr_hi = (offset & 0xff00) >> 8;
219 h.veclinear.count = count;
220 return h.i;
221 }
222
223 static int cmdscl( int offset, int stride, int count )
224 {
225 drm_radeon_cmd_header_t h;
226 h.i = 0;
227 h.scalars.cmd_type = RADEON_CMD_SCALARS;
228 h.scalars.offset = offset;
229 h.scalars.stride = stride;
230 h.scalars.count = count;
231 return h.i;
232 }
233
234 static int cmdscl2( int offset, int stride, int count )
235 {
236 drm_radeon_cmd_header_t h;
237 h.i = 0;
238 h.scalars.cmd_type = RADEON_CMD_SCALARS2;
239 h.scalars.offset = offset - 0x100;
240 h.scalars.stride = stride;
241 h.scalars.count = count;
242 return h.i;
243 }
244
245 #define CHECK( NM, FLAG ) \
246 static int check_##NM( GLcontext *ctx, struct radeon_state_atom *atom) \
247 { \
248 r200ContextPtr rmesa = R200_CONTEXT(ctx); \
249 (void) rmesa; \
250 return (FLAG) ? atom->cmd_size : 0; \
251 }
252
253 #define TCL_CHECK( NM, FLAG ) \
254 static int check_##NM( GLcontext *ctx, struct radeon_state_atom *atom) \
255 { \
256 r200ContextPtr rmesa = R200_CONTEXT(ctx); \
257 return (!rmesa->radeon.TclFallback && !ctx->VertexProgram._Enabled && (FLAG)) ? atom->cmd_size : 0; \
258 }
259
260 #define TCL_OR_VP_CHECK( NM, FLAG ) \
261 static int check_##NM( GLcontext *ctx, struct radeon_state_atom *atom ) \
262 { \
263 r200ContextPtr rmesa = R200_CONTEXT(ctx); \
264 return (!rmesa->radeon.TclFallback && (FLAG)) ? atom->cmd_size : 0; \
265 }
266
267 #define VP_CHECK( NM, FLAG ) \
268 static int check_##NM( GLcontext *ctx, struct radeon_state_atom *atom ) \
269 { \
270 r200ContextPtr rmesa = R200_CONTEXT(ctx); \
271 (void) atom; \
272 return (!rmesa->radeon.TclFallback && ctx->VertexProgram._Enabled && (FLAG)) ? atom->cmd_size : 0; \
273 }
274
275 CHECK( always, GL_TRUE )
276 CHECK( never, GL_FALSE )
277 CHECK( tex_any, ctx->Texture._EnabledUnits )
278 CHECK( tf, (ctx->Texture._EnabledUnits && !ctx->ATIFragmentShader._Enabled) );
279 CHECK( tex_pair, (rmesa->state.texture.unit[atom->idx].unitneeded | rmesa->state.texture.unit[atom->idx & ~1].unitneeded) )
280 CHECK( tex, rmesa->state.texture.unit[atom->idx].unitneeded )
281 CHECK( pix_zero, !ctx->ATIFragmentShader._Enabled )
282 CHECK( texenv, (rmesa->state.envneeded & (1 << (atom->idx)) && !ctx->ATIFragmentShader._Enabled) )
283 CHECK( afs_pass1, (ctx->ATIFragmentShader._Enabled && (ctx->ATIFragmentShader.Current->NumPasses > 1)) )
284 CHECK( afs, ctx->ATIFragmentShader._Enabled )
285 CHECK( tex_cube, rmesa->state.texture.unit[atom->idx].unitneeded & TEXTURE_CUBE_BIT )
286 TCL_CHECK( tcl_fog, ctx->Fog.Enabled )
287 TCL_CHECK( tcl, GL_TRUE )
288 TCL_CHECK( tcl_tex, rmesa->state.texture.unit[atom->idx].unitneeded )
289 TCL_CHECK( tcl_lighting, ctx->Light.Enabled )
290 TCL_CHECK( tcl_light, ctx->Light.Enabled && ctx->Light.Light[atom->idx].Enabled )
291 TCL_OR_VP_CHECK( tcl_ucp, (ctx->Transform.ClipPlanesEnabled & (1 << (atom->idx))) )
292 TCL_OR_VP_CHECK( tcl_or_vp, GL_TRUE )
293 VP_CHECK( tcl_vp, GL_TRUE )
294 VP_CHECK( tcl_vp_size, ctx->VertexProgram.Current->Base.NumNativeInstructions > 64 )
295 VP_CHECK( tcl_vpp_size, ctx->VertexProgram.Current->Base.NumNativeParameters > 96 )
296
297 #define OUT_VEC(hdr, data) do { \
298 drm_radeon_cmd_header_t h; \
299 h.i = hdr; \
300 OUT_BATCH(CP_PACKET0(RADEON_SE_TCL_STATE_FLUSH, 0)); \
301 OUT_BATCH(0); \
302 OUT_BATCH(CP_PACKET0(R200_SE_TCL_VECTOR_INDX_REG, 0)); \
303 OUT_BATCH(h.vectors.offset | (h.vectors.stride << RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT)); \
304 OUT_BATCH(CP_PACKET0_ONE(R200_SE_TCL_VECTOR_DATA_REG, h.vectors.count - 1)); \
305 OUT_BATCH_TABLE((data), h.vectors.count); \
306 } while(0)
307
308 #define OUT_VECLINEAR(hdr, data) do { \
309 drm_radeon_cmd_header_t h; \
310 uint32_t _start, _sz; \
311 h.i = hdr; \
312 _start = h.veclinear.addr_lo | (h.veclinear.addr_hi << 8); \
313 _sz = h.veclinear.count * 4; \
314 OUT_BATCH(CP_PACKET0(RADEON_SE_TCL_STATE_FLUSH, 0)); \
315 OUT_BATCH(0); \
316 OUT_BATCH(CP_PACKET0(R200_SE_TCL_VECTOR_INDX_REG, 0)); \
317 OUT_BATCH(_start | (1 << RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT)); \
318 OUT_BATCH(CP_PACKET0_ONE(R200_SE_TCL_VECTOR_DATA_REG, _sz - 1)); \
319 OUT_BATCH_TABLE((data), _sz); \
320 } while(0)
321
322 #define OUT_SCL(hdr, data) do { \
323 drm_radeon_cmd_header_t h; \
324 h.i = hdr; \
325 OUT_BATCH(CP_PACKET0(R200_SE_TCL_SCALAR_INDX_REG, 0)); \
326 OUT_BATCH((h.scalars.offset) | (h.scalars.stride << RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT)); \
327 OUT_BATCH(CP_PACKET0_ONE(R200_SE_TCL_SCALAR_DATA_REG, h.scalars.count - 1)); \
328 OUT_BATCH_TABLE((data), h.scalars.count); \
329 } while(0)
330
331 #define OUT_SCL2(hdr, data) do { \
332 drm_radeon_cmd_header_t h; \
333 h.i = hdr; \
334 OUT_BATCH(CP_PACKET0(R200_SE_TCL_SCALAR_INDX_REG, 0)); \
335 OUT_BATCH((h.scalars.offset + 0x100) | (h.scalars.stride << RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT)); \
336 OUT_BATCH(CP_PACKET0_ONE(R200_SE_TCL_SCALAR_DATA_REG, h.scalars.count - 1)); \
337 OUT_BATCH_TABLE((data), h.scalars.count); \
338 } while(0)
339
340 static void mtl_emit(GLcontext *ctx, struct radeon_state_atom *atom)
341 {
342 r200ContextPtr r200 = R200_CONTEXT(ctx);
343 BATCH_LOCALS(&r200->radeon);
344 uint32_t dwords = atom->cmd_size;
345
346 dwords += 6;
347 BEGIN_BATCH_NO_AUTOSTATE(dwords);
348 OUT_VEC(atom->cmd[MTL_CMD_0], (atom->cmd+1));
349 OUT_SCL2(atom->cmd[MTL_CMD_1], (atom->cmd + 18));
350 END_BATCH();
351 }
352
353 static void lit_emit(GLcontext *ctx, struct radeon_state_atom *atom)
354 {
355 r200ContextPtr r200 = R200_CONTEXT(ctx);
356 BATCH_LOCALS(&r200->radeon);
357 uint32_t dwords = atom->cmd_size;
358
359 dwords += 8;
360 BEGIN_BATCH_NO_AUTOSTATE(dwords);
361 OUT_VEC(atom->cmd[LIT_CMD_0], atom->cmd+1);
362 OUT_VEC(atom->cmd[LIT_CMD_1], atom->cmd+LIT_CMD_1+1);
363 END_BATCH();
364 }
365
366 static void ptp_emit(GLcontext *ctx, struct radeon_state_atom *atom)
367 {
368 r200ContextPtr r200 = R200_CONTEXT(ctx);
369 BATCH_LOCALS(&r200->radeon);
370 uint32_t dwords = atom->cmd_size;
371
372 dwords += 8;
373 BEGIN_BATCH_NO_AUTOSTATE(dwords);
374 OUT_VEC(atom->cmd[PTP_CMD_0], atom->cmd+1);
375 OUT_VEC(atom->cmd[PTP_CMD_1], atom->cmd+PTP_CMD_1+1);
376 END_BATCH();
377 }
378
379 static void veclinear_emit(GLcontext *ctx, struct radeon_state_atom *atom)
380 {
381 r200ContextPtr r200 = R200_CONTEXT(ctx);
382 BATCH_LOCALS(&r200->radeon);
383 uint32_t dwords = atom->cmd_size;
384
385 dwords += 4;
386 BEGIN_BATCH_NO_AUTOSTATE(dwords);
387 OUT_VECLINEAR(atom->cmd[0], atom->cmd+1);
388 END_BATCH();
389 }
390
391 static void scl_emit(GLcontext *ctx, struct radeon_state_atom *atom)
392 {
393 r200ContextPtr r200 = R200_CONTEXT(ctx);
394 BATCH_LOCALS(&r200->radeon);
395 uint32_t dwords = atom->cmd_size;
396
397 dwords += 2;
398 BEGIN_BATCH_NO_AUTOSTATE(dwords);
399 OUT_SCL(atom->cmd[0], atom->cmd+1);
400 END_BATCH();
401 }
402
403
404 static void vec_emit(GLcontext *ctx, struct radeon_state_atom *atom)
405 {
406 r200ContextPtr r200 = R200_CONTEXT(ctx);
407 BATCH_LOCALS(&r200->radeon);
408 uint32_t dwords = atom->cmd_size;
409
410 dwords += 4;
411 BEGIN_BATCH_NO_AUTOSTATE(dwords);
412 OUT_VEC(atom->cmd[0], atom->cmd+1);
413 END_BATCH();
414 }
415
416 static void ctx_emit(GLcontext *ctx, struct radeon_state_atom *atom)
417 {
418 r200ContextPtr r200 = R200_CONTEXT(ctx);
419 BATCH_LOCALS(&r200->radeon);
420 struct radeon_renderbuffer *rrb;
421 uint32_t cbpitch;
422 uint32_t zbpitch, depth_fmt;
423 uint32_t dwords = atom->cmd_size;
424
425 /* output the first 7 bytes of context */
426 BEGIN_BATCH_NO_AUTOSTATE(dwords+2+2);
427 OUT_BATCH_TABLE(atom->cmd, 5);
428
429 rrb = radeon_get_depthbuffer(&r200->radeon);
430 if (!rrb) {
431 OUT_BATCH(0);
432 OUT_BATCH(0);
433 } else {
434 zbpitch = (rrb->pitch / rrb->cpp);
435 if (r200->using_hyperz)
436 zbpitch |= RADEON_DEPTH_HYPERZ;
437 OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
438 OUT_BATCH(zbpitch);
439 if (rrb->cpp == 4)
440 depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
441 else
442 depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
443 atom->cmd[CTX_RB3D_ZSTENCILCNTL] &= ~RADEON_DEPTH_FORMAT_MASK;
444 atom->cmd[CTX_RB3D_ZSTENCILCNTL] |= depth_fmt;
445 }
446
447 OUT_BATCH(atom->cmd[CTX_RB3D_ZSTENCILCNTL]);
448 OUT_BATCH(atom->cmd[CTX_CMD_1]);
449 OUT_BATCH(atom->cmd[CTX_PP_CNTL]);
450
451 rrb = radeon_get_colorbuffer(&r200->radeon);
452 if (!rrb || !rrb->bo) {
453 OUT_BATCH(atom->cmd[CTX_RB3D_CNTL]);
454 OUT_BATCH(atom->cmd[CTX_RB3D_COLOROFFSET]);
455 } else {
456 atom->cmd[CTX_RB3D_CNTL] &= ~(0xf << 10);
457 if (rrb->cpp == 4)
458 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB8888;
459 else
460 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_RGB565;
461
462 OUT_BATCH(atom->cmd[CTX_RB3D_CNTL]);
463 OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
464 }
465
466 OUT_BATCH(atom->cmd[CTX_CMD_2]);
467
468 if (!rrb || !rrb->bo) {
469 OUT_BATCH(atom->cmd[CTX_RB3D_COLORPITCH]);
470 } else {
471 cbpitch = (rrb->pitch / rrb->cpp);
472 if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE)
473 cbpitch |= R200_COLOR_TILE_ENABLE;
474 OUT_BATCH(cbpitch);
475 }
476
477 if (atom->cmd_size == CTX_STATE_SIZE_NEWDRM)
478 OUT_BATCH_TABLE((atom->cmd + 14), 4);
479
480 END_BATCH();
481 }
482
483 static void ctx_emit_cs(GLcontext *ctx, struct radeon_state_atom *atom)
484 {
485 r200ContextPtr r200 = R200_CONTEXT(ctx);
486 BATCH_LOCALS(&r200->radeon);
487 struct radeon_renderbuffer *rrb, *drb;
488 uint32_t cbpitch = 0;
489 uint32_t zbpitch = 0;
490 uint32_t dwords = atom->cmd_size;
491 uint32_t depth_fmt;
492
493 rrb = radeon_get_colorbuffer(&r200->radeon);
494 if (!rrb || !rrb->bo) {
495 return;
496 }
497
498 atom->cmd[CTX_RB3D_CNTL] &= ~(0xf << 10);
499 if (rrb->cpp == 4)
500 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB8888;
501 else
502 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_RGB565;
503
504 cbpitch = (rrb->pitch / rrb->cpp);
505 if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE)
506 cbpitch |= R200_COLOR_TILE_ENABLE;
507
508 drb = radeon_get_depthbuffer(&r200->radeon);
509 if (drb) {
510 zbpitch = (drb->pitch / drb->cpp);
511 if (drb->cpp == 4)
512 depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
513 else
514 depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
515 atom->cmd[CTX_RB3D_ZSTENCILCNTL] &= ~RADEON_DEPTH_FORMAT_MASK;
516 atom->cmd[CTX_RB3D_ZSTENCILCNTL] |= depth_fmt;
517 }
518
519 dwords = 10;
520 if (drb)
521 dwords += 6;
522 if (rrb)
523 dwords += 6;
524
525 /* output the first 7 bytes of context */
526 BEGIN_BATCH_NO_AUTOSTATE(dwords);
527
528 /* In the CS case we need to split this up */
529 OUT_BATCH(CP_PACKET0(packet[0].start, 3));
530 OUT_BATCH_TABLE((atom->cmd + 1), 4);
531
532 if (drb) {
533 OUT_BATCH(CP_PACKET0(RADEON_RB3D_DEPTHOFFSET, 0));
534 OUT_BATCH_RELOC(0, drb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
535
536 OUT_BATCH(CP_PACKET0(RADEON_RB3D_DEPTHPITCH, 0));
537 OUT_BATCH(zbpitch);
538 }
539
540 OUT_BATCH(CP_PACKET0(RADEON_RB3D_ZSTENCILCNTL, 0));
541 OUT_BATCH(atom->cmd[CTX_RB3D_ZSTENCILCNTL]);
542 OUT_BATCH(CP_PACKET0(RADEON_PP_CNTL, 1));
543 OUT_BATCH(atom->cmd[CTX_PP_CNTL]);
544 OUT_BATCH(atom->cmd[CTX_RB3D_CNTL]);
545
546
547 if (rrb) {
548 OUT_BATCH(CP_PACKET0(RADEON_RB3D_COLOROFFSET, 0));
549 OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
550
551 OUT_BATCH(CP_PACKET0(RADEON_RB3D_COLORPITCH, 0));
552 OUT_BATCH(cbpitch);
553 }
554
555 if (atom->cmd_size == CTX_STATE_SIZE_NEWDRM) {
556 OUT_BATCH_TABLE((atom->cmd + 14), 4);
557 }
558
559 END_BATCH();
560 }
561
562 static void tex_emit(GLcontext *ctx, struct radeon_state_atom *atom)
563 {
564 r200ContextPtr r200 = R200_CONTEXT(ctx);
565 BATCH_LOCALS(&r200->radeon);
566 uint32_t dwords = atom->cmd_size;
567 int i = atom->idx;
568 radeonTexObj *t = r200->state.texture.unit[i].texobj;
569 radeon_mipmap_level *lvl;
570
571 if (t && t->mt && !t->image_override)
572 dwords += 2;
573 BEGIN_BATCH_NO_AUTOSTATE(dwords);
574 OUT_BATCH_TABLE(atom->cmd, 10);
575
576 if (t && t->mt && !t->image_override) {
577 if ((ctx->Texture.Unit[i]._ReallyEnabled & TEXTURE_CUBE_BIT)) {
578 lvl = &t->mt->levels[0];
579 OUT_BATCH_RELOC(lvl->faces[5].offset, t->mt->bo, lvl->faces[5].offset,
580 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
581 } else {
582 OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, 0,
583 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
584 }
585 } else if (!t) {
586 /* workaround for old CS mechanism */
587 OUT_BATCH(r200->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP]);
588 } else {
589 OUT_BATCH(t->override_offset);
590 }
591
592 END_BATCH();
593 }
594
595 static void tex_emit_cs(GLcontext *ctx, struct radeon_state_atom *atom)
596 {
597 r200ContextPtr r200 = R200_CONTEXT(ctx);
598 BATCH_LOCALS(&r200->radeon);
599 uint32_t dwords = atom->cmd_size;
600 int i = atom->idx;
601 radeonTexObj *t = r200->state.texture.unit[i].texobj;
602 radeon_mipmap_level *lvl;
603 int hastexture = 1;
604
605 if (!t)
606 hastexture = 0;
607 else {
608 if (!t->mt && !t->bo)
609 hastexture = 0;
610 }
611
612 dwords += 2;
613 if (hastexture)
614 dwords += 2;
615 else
616 dwords -= 2;
617 BEGIN_BATCH_NO_AUTOSTATE(dwords);
618
619 OUT_BATCH(CP_PACKET0(R200_PP_TXFILTER_0 + (24 * i), 7));
620 OUT_BATCH_TABLE((atom->cmd + 1), 8);
621
622 if (hastexture) {
623 OUT_BATCH(CP_PACKET0(R200_PP_TXOFFSET_0 + (24 * i), 0));
624 if (t->mt && !t->image_override) {
625 if ((ctx->Texture.Unit[i]._ReallyEnabled & TEXTURE_CUBE_BIT)) {
626 lvl = &t->mt->levels[0];
627 OUT_BATCH_RELOC(lvl->faces[5].offset, t->mt->bo, lvl->faces[5].offset,
628 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
629 } else {
630 OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, 0,
631 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
632 }
633 } else {
634 if (t->bo)
635 OUT_BATCH_RELOC(t->tile_bits, t->bo, 0,
636 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
637 }
638 }
639 END_BATCH();
640 }
641
642
643 static void cube_emit(GLcontext *ctx, struct radeon_state_atom *atom)
644 {
645 r200ContextPtr r200 = R200_CONTEXT(ctx);
646 BATCH_LOCALS(&r200->radeon);
647 uint32_t dwords = atom->cmd_size;
648 int i = atom->idx;
649 radeonTexObj *t = r200->state.texture.unit[i].texobj;
650 GLuint size;
651
652 BEGIN_BATCH_NO_AUTOSTATE(dwords + (2 * 5));
653 OUT_BATCH_TABLE(atom->cmd, 3);
654
655 if (t && !t->image_override) {
656 size = t->mt->totalsize / 6;
657 OUT_BATCH_RELOC(0, t->mt->bo, size, RADEON_GEM_DOMAIN_VRAM, 0, 0);
658 OUT_BATCH_RELOC(0, t->mt->bo, size * 2, RADEON_GEM_DOMAIN_VRAM, 0, 0);
659 OUT_BATCH_RELOC(0, t->mt->bo, size * 3, RADEON_GEM_DOMAIN_VRAM, 0, 0);
660 OUT_BATCH_RELOC(0, t->mt->bo, size * 4, RADEON_GEM_DOMAIN_VRAM, 0, 0);
661 OUT_BATCH_RELOC(0, t->mt->bo, size * 5, RADEON_GEM_DOMAIN_VRAM, 0, 0);
662 }
663 END_BATCH();
664 }
665
666 /* Initialize the context's hardware state.
667 */
668 void r200InitState( r200ContextPtr rmesa )
669 {
670 GLcontext *ctx = rmesa->radeon.glCtx;
671 GLuint i;
672
673 rmesa->radeon.state.color.clear = 0x00000000;
674
675 switch ( ctx->Visual.depthBits ) {
676 case 16:
677 rmesa->radeon.state.depth.clear = 0x0000ffff;
678 rmesa->radeon.state.stencil.clear = 0x00000000;
679 break;
680 case 24:
681 default:
682 rmesa->radeon.state.depth.clear = 0x00ffffff;
683 rmesa->radeon.state.stencil.clear = 0xffff0000;
684 break;
685 }
686
687 rmesa->radeon.Fallback = 0;
688
689 rmesa->radeon.hw.max_state_size = 0;
690
691 #define ALLOC_STATE( ATOM, CHK, SZ, NM, IDX ) \
692 do { \
693 rmesa->hw.ATOM.cmd_size = SZ; \
694 rmesa->hw.ATOM.cmd = (GLuint *)CALLOC(SZ * sizeof(int)); \
695 rmesa->hw.ATOM.lastcmd = (GLuint *)CALLOC(SZ * sizeof(int)); \
696 rmesa->hw.ATOM.name = NM; \
697 rmesa->hw.ATOM.idx = IDX; \
698 rmesa->hw.ATOM.check = check_##CHK; \
699 rmesa->hw.ATOM.dirty = GL_FALSE; \
700 rmesa->radeon.hw.max_state_size += SZ * sizeof(int); \
701 } while (0)
702
703
704 /* Allocate state buffers:
705 */
706 if (rmesa->radeon.radeonScreen->drmSupportsBlendColor)
707 ALLOC_STATE( ctx, always, CTX_STATE_SIZE_NEWDRM, "CTX/context", 0 );
708 else
709 ALLOC_STATE( ctx, always, CTX_STATE_SIZE_OLDDRM, "CTX/context", 0 );
710
711 if (rmesa->radeon.radeonScreen->kernel_mm)
712 rmesa->hw.ctx.emit = ctx_emit_cs;
713 else
714 rmesa->hw.ctx.emit = ctx_emit;
715 ALLOC_STATE( set, always, SET_STATE_SIZE, "SET/setup", 0 );
716 ALLOC_STATE( lin, always, LIN_STATE_SIZE, "LIN/line", 0 );
717 ALLOC_STATE( msk, always, MSK_STATE_SIZE, "MSK/mask", 0 );
718 ALLOC_STATE( vpt, always, VPT_STATE_SIZE, "VPT/viewport", 0 );
719 ALLOC_STATE( vtx, always, VTX_STATE_SIZE, "VTX/vertex", 0 );
720 ALLOC_STATE( vap, always, VAP_STATE_SIZE, "VAP/vap", 0 );
721 ALLOC_STATE( vte, always, VTE_STATE_SIZE, "VTE/vte", 0 );
722 ALLOC_STATE( msc, always, MSC_STATE_SIZE, "MSC/misc", 0 );
723 ALLOC_STATE( cst, always, CST_STATE_SIZE, "CST/constant", 0 );
724 ALLOC_STATE( zbs, always, ZBS_STATE_SIZE, "ZBS/zbias", 0 );
725 ALLOC_STATE( tf, tf, TF_STATE_SIZE, "TF/tfactor", 0 );
726 if (rmesa->radeon.radeonScreen->drmSupportsFragShader) {
727 if (rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_R200) {
728 /* make sure texture units 0/1 are emitted pair-wise for r200 t0 hang workaround */
729 ALLOC_STATE( tex[0], tex_pair, TEX_STATE_SIZE_NEWDRM, "TEX/tex-0", 0 );
730 ALLOC_STATE( tex[1], tex_pair, TEX_STATE_SIZE_NEWDRM, "TEX/tex-1", 1 );
731 ALLOC_STATE( tam, tex_any, TAM_STATE_SIZE, "TAM/tam", 0 );
732 }
733 else {
734 ALLOC_STATE( tex[0], tex, TEX_STATE_SIZE_NEWDRM, "TEX/tex-0", 0 );
735 ALLOC_STATE( tex[1], tex, TEX_STATE_SIZE_NEWDRM, "TEX/tex-1", 1 );
736 ALLOC_STATE( tam, never, TAM_STATE_SIZE, "TAM/tam", 0 );
737 }
738 ALLOC_STATE( tex[2], tex, TEX_STATE_SIZE_NEWDRM, "TEX/tex-2", 2 );
739 ALLOC_STATE( tex[3], tex, TEX_STATE_SIZE_NEWDRM, "TEX/tex-3", 3 );
740 ALLOC_STATE( tex[4], tex, TEX_STATE_SIZE_NEWDRM, "TEX/tex-4", 4 );
741 ALLOC_STATE( tex[5], tex, TEX_STATE_SIZE_NEWDRM, "TEX/tex-5", 5 );
742 ALLOC_STATE( atf, afs, ATF_STATE_SIZE, "ATF/tfactor", 0 );
743 ALLOC_STATE( afs[0], afs_pass1, AFS_STATE_SIZE, "AFS/afsinst-0", 0 );
744 ALLOC_STATE( afs[1], afs, AFS_STATE_SIZE, "AFS/afsinst-1", 1 );
745 }
746 else {
747 if (rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_R200) {
748 ALLOC_STATE( tex[0], tex_pair, TEX_STATE_SIZE_OLDDRM, "TEX/tex-0", 0 );
749 ALLOC_STATE( tex[1], tex_pair, TEX_STATE_SIZE_OLDDRM, "TEX/tex-1", 1 );
750 ALLOC_STATE( tam, tex_any, TAM_STATE_SIZE, "TAM/tam", 0 );
751 }
752 else {
753 ALLOC_STATE( tex[0], tex, TEX_STATE_SIZE_OLDDRM, "TEX/tex-0", 0 );
754 ALLOC_STATE( tex[1], tex, TEX_STATE_SIZE_OLDDRM, "TEX/tex-1", 1 );
755 ALLOC_STATE( tam, never, TAM_STATE_SIZE, "TAM/tam", 0 );
756 }
757 ALLOC_STATE( tex[2], tex, TEX_STATE_SIZE_OLDDRM, "TEX/tex-2", 2 );
758 ALLOC_STATE( tex[3], tex, TEX_STATE_SIZE_OLDDRM, "TEX/tex-3", 3 );
759 ALLOC_STATE( tex[4], tex, TEX_STATE_SIZE_OLDDRM, "TEX/tex-4", 4 );
760 ALLOC_STATE( tex[5], tex, TEX_STATE_SIZE_OLDDRM, "TEX/tex-5", 5 );
761 ALLOC_STATE( atf, never, ATF_STATE_SIZE, "TF/tfactor", 0 );
762 ALLOC_STATE( afs[0], never, AFS_STATE_SIZE, "AFS/afsinst-0", 0 );
763 ALLOC_STATE( afs[1], never, AFS_STATE_SIZE, "AFS/afsinst-1", 1 );
764 }
765
766 for (i = 0; i < 5; i++)
767 if (rmesa->radeon.radeonScreen->kernel_mm)
768 rmesa->hw.tex[i].emit = tex_emit_cs;
769 else
770 rmesa->hw.tex[i].emit = tex_emit;
771 if (rmesa->radeon.radeonScreen->drmSupportsCubeMapsR200) {
772 ALLOC_STATE( cube[0], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-0", 0 );
773 ALLOC_STATE( cube[1], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-1", 1 );
774 ALLOC_STATE( cube[2], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-2", 2 );
775 ALLOC_STATE( cube[3], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-3", 3 );
776 ALLOC_STATE( cube[4], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-4", 4 );
777 ALLOC_STATE( cube[5], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-5", 5 );
778 for (i = 0; i < 5; i++)
779 rmesa->hw.cube[i].emit = cube_emit;
780 }
781 else {
782 ALLOC_STATE( cube[0], never, CUBE_STATE_SIZE, "CUBE/tex-0", 0 );
783 ALLOC_STATE( cube[1], never, CUBE_STATE_SIZE, "CUBE/tex-1", 1 );
784 ALLOC_STATE( cube[2], never, CUBE_STATE_SIZE, "CUBE/tex-2", 2 );
785 ALLOC_STATE( cube[3], never, CUBE_STATE_SIZE, "CUBE/tex-3", 3 );
786 ALLOC_STATE( cube[4], never, CUBE_STATE_SIZE, "CUBE/tex-4", 4 );
787 ALLOC_STATE( cube[5], never, CUBE_STATE_SIZE, "CUBE/tex-5", 5 );
788 }
789
790 if (rmesa->radeon.radeonScreen->drmSupportsVertexProgram) {
791 ALLOC_STATE( pvs, tcl_vp, PVS_STATE_SIZE, "PVS/pvscntl", 0 );
792 ALLOC_STATE( vpi[0], tcl_vp, VPI_STATE_SIZE, "VP/vertexprog-0", 0 );
793 ALLOC_STATE( vpi[1], tcl_vp_size, VPI_STATE_SIZE, "VP/vertexprog-1", 1 );
794 ALLOC_STATE( vpp[0], tcl_vp, VPP_STATE_SIZE, "VPP/vertexparam-0", 0 );
795 ALLOC_STATE( vpp[1], tcl_vpp_size, VPP_STATE_SIZE, "VPP/vertexparam-1", 1 );
796 }
797 else {
798 ALLOC_STATE( pvs, never, PVS_STATE_SIZE, "PVS/pvscntl", 0 );
799 ALLOC_STATE( vpi[0], never, VPI_STATE_SIZE, "VP/vertexprog-0", 0 );
800 ALLOC_STATE( vpi[1], never, VPI_STATE_SIZE, "VP/vertexprog-1", 1 );
801 ALLOC_STATE( vpp[0], never, VPP_STATE_SIZE, "VPP/vertexparam-0", 0 );
802 ALLOC_STATE( vpp[1], never, VPP_STATE_SIZE, "VPP/vertexparam-1", 1 );
803 }
804 /* FIXME: this atom has two commands, we need only one (ucp_vert_blend) for vp */
805 ALLOC_STATE( tcl, tcl_or_vp, TCL_STATE_SIZE, "TCL/tcl", 0 );
806 ALLOC_STATE( msl, tcl, MSL_STATE_SIZE, "MSL/matrix-select", 0 );
807 ALLOC_STATE( tcg, tcl, TCG_STATE_SIZE, "TCG/texcoordgen", 0 );
808 ALLOC_STATE( mtl[0], tcl_lighting, MTL_STATE_SIZE, "MTL0/material0", 0 );
809 ALLOC_STATE( mtl[1], tcl_lighting, MTL_STATE_SIZE, "MTL1/material1", 1 );
810 ALLOC_STATE( grd, tcl_or_vp, GRD_STATE_SIZE, "GRD/guard-band", 0 );
811 ALLOC_STATE( fog, tcl_fog, FOG_STATE_SIZE, "FOG/fog", 0 );
812 ALLOC_STATE( glt, tcl_lighting, GLT_STATE_SIZE, "GLT/light-global", 0 );
813 ALLOC_STATE( eye, tcl_lighting, EYE_STATE_SIZE, "EYE/eye-vector", 0 );
814 ALLOC_STATE( mat[R200_MTX_MV], tcl, MAT_STATE_SIZE, "MAT/modelview", 0 );
815 ALLOC_STATE( mat[R200_MTX_IMV], tcl, MAT_STATE_SIZE, "MAT/it-modelview", 0 );
816 ALLOC_STATE( mat[R200_MTX_MVP], tcl, MAT_STATE_SIZE, "MAT/modelproject", 0 );
817 ALLOC_STATE( mat[R200_MTX_TEX0], tcl_tex, MAT_STATE_SIZE, "MAT/texmat0", 0 );
818 ALLOC_STATE( mat[R200_MTX_TEX1], tcl_tex, MAT_STATE_SIZE, "MAT/texmat1", 1 );
819 ALLOC_STATE( mat[R200_MTX_TEX2], tcl_tex, MAT_STATE_SIZE, "MAT/texmat2", 2 );
820 ALLOC_STATE( mat[R200_MTX_TEX3], tcl_tex, MAT_STATE_SIZE, "MAT/texmat3", 3 );
821 ALLOC_STATE( mat[R200_MTX_TEX4], tcl_tex, MAT_STATE_SIZE, "MAT/texmat4", 4 );
822 ALLOC_STATE( mat[R200_MTX_TEX5], tcl_tex, MAT_STATE_SIZE, "MAT/texmat5", 5 );
823 ALLOC_STATE( ucp[0], tcl_ucp, UCP_STATE_SIZE, "UCP/userclip-0", 0 );
824 ALLOC_STATE( ucp[1], tcl_ucp, UCP_STATE_SIZE, "UCP/userclip-1", 1 );
825 ALLOC_STATE( ucp[2], tcl_ucp, UCP_STATE_SIZE, "UCP/userclip-2", 2 );
826 ALLOC_STATE( ucp[3], tcl_ucp, UCP_STATE_SIZE, "UCP/userclip-3", 3 );
827 ALLOC_STATE( ucp[4], tcl_ucp, UCP_STATE_SIZE, "UCP/userclip-4", 4 );
828 ALLOC_STATE( ucp[5], tcl_ucp, UCP_STATE_SIZE, "UCP/userclip-5", 5 );
829 ALLOC_STATE( lit[0], tcl_light, LIT_STATE_SIZE, "LIT/light-0", 0 );
830 ALLOC_STATE( lit[1], tcl_light, LIT_STATE_SIZE, "LIT/light-1", 1 );
831 ALLOC_STATE( lit[2], tcl_light, LIT_STATE_SIZE, "LIT/light-2", 2 );
832 ALLOC_STATE( lit[3], tcl_light, LIT_STATE_SIZE, "LIT/light-3", 3 );
833 ALLOC_STATE( lit[4], tcl_light, LIT_STATE_SIZE, "LIT/light-4", 4 );
834 ALLOC_STATE( lit[5], tcl_light, LIT_STATE_SIZE, "LIT/light-5", 5 );
835 ALLOC_STATE( lit[6], tcl_light, LIT_STATE_SIZE, "LIT/light-6", 6 );
836 ALLOC_STATE( lit[7], tcl_light, LIT_STATE_SIZE, "LIT/light-7", 7 );
837 ALLOC_STATE( pix[0], pix_zero, PIX_STATE_SIZE, "PIX/pixstage-0", 0 );
838 ALLOC_STATE( pix[1], texenv, PIX_STATE_SIZE, "PIX/pixstage-1", 1 );
839 ALLOC_STATE( pix[2], texenv, PIX_STATE_SIZE, "PIX/pixstage-2", 2 );
840 ALLOC_STATE( pix[3], texenv, PIX_STATE_SIZE, "PIX/pixstage-3", 3 );
841 ALLOC_STATE( pix[4], texenv, PIX_STATE_SIZE, "PIX/pixstage-4", 4 );
842 ALLOC_STATE( pix[5], texenv, PIX_STATE_SIZE, "PIX/pixstage-5", 5 );
843 if (rmesa->radeon.radeonScreen->drmSupportsTriPerf) {
844 ALLOC_STATE( prf, always, PRF_STATE_SIZE, "PRF/performance-tri", 0 );
845 }
846 else {
847 ALLOC_STATE( prf, never, PRF_STATE_SIZE, "PRF/performance-tri", 0 );
848 }
849 if (rmesa->radeon.radeonScreen->drmSupportsPointSprites) {
850 ALLOC_STATE( spr, always, SPR_STATE_SIZE, "SPR/pointsprite", 0 );
851 ALLOC_STATE( ptp, tcl, PTP_STATE_SIZE, "PTP/pointparams", 0 );
852 }
853 else {
854 ALLOC_STATE (spr, never, SPR_STATE_SIZE, "SPR/pointsprite", 0 );
855 ALLOC_STATE (ptp, never, PTP_STATE_SIZE, "PTP/pointparams", 0 );
856 }
857
858 r200SetUpAtomList( rmesa );
859
860 /* Fill in the packet headers:
861 */
862 rmesa->hw.ctx.cmd[CTX_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_MISC);
863 rmesa->hw.ctx.cmd[CTX_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_PP_CNTL);
864 rmesa->hw.ctx.cmd[CTX_CMD_2] = cmdpkt(rmesa, RADEON_EMIT_RB3D_COLORPITCH);
865 if (rmesa->radeon.radeonScreen->drmSupportsBlendColor)
866 rmesa->hw.ctx.cmd[CTX_CMD_3] = cmdpkt(rmesa, R200_EMIT_RB3D_BLENDCOLOR);
867 rmesa->hw.lin.cmd[LIN_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_RE_LINE_PATTERN);
868 rmesa->hw.lin.cmd[LIN_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_SE_LINE_WIDTH);
869 rmesa->hw.msk.cmd[MSK_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_RB3D_STENCILREFMASK);
870 rmesa->hw.vpt.cmd[VPT_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_SE_VPORT_XSCALE);
871 rmesa->hw.set.cmd[SET_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_SE_CNTL);
872 rmesa->hw.msc.cmd[MSC_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_RE_MISC);
873 rmesa->hw.cst.cmd[CST_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_CNTL_X);
874 rmesa->hw.cst.cmd[CST_CMD_1] = cmdpkt(rmesa, R200_EMIT_RB3D_DEPTHXY_OFFSET);
875 rmesa->hw.cst.cmd[CST_CMD_2] = cmdpkt(rmesa, R200_EMIT_RE_AUX_SCISSOR_CNTL);
876 rmesa->hw.cst.cmd[CST_CMD_3] = cmdpkt(rmesa, R200_EMIT_RE_SCISSOR_TL_0);
877 rmesa->hw.cst.cmd[CST_CMD_4] = cmdpkt(rmesa, R200_EMIT_SE_VAP_CNTL_STATUS);
878 rmesa->hw.cst.cmd[CST_CMD_5] = cmdpkt(rmesa, R200_EMIT_RE_POINTSIZE);
879 rmesa->hw.cst.cmd[CST_CMD_6] = cmdpkt(rmesa, R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0);
880 rmesa->hw.tam.cmd[TAM_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TAM_DEBUG3);
881 rmesa->hw.tf.cmd[TF_CMD_0] = cmdpkt(rmesa, R200_EMIT_TFACTOR_0);
882 if (rmesa->radeon.radeonScreen->drmSupportsFragShader) {
883 rmesa->hw.atf.cmd[ATF_CMD_0] = cmdpkt(rmesa, R200_EMIT_ATF_TFACTOR);
884 rmesa->hw.tex[0].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCTLALL_0);
885 rmesa->hw.tex[0].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_0);
886 rmesa->hw.tex[1].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCTLALL_1);
887 rmesa->hw.tex[1].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_1);
888 rmesa->hw.tex[2].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCTLALL_2);
889 rmesa->hw.tex[2].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_2);
890 rmesa->hw.tex[3].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCTLALL_3);
891 rmesa->hw.tex[3].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_3);
892 rmesa->hw.tex[4].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCTLALL_4);
893 rmesa->hw.tex[4].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_4);
894 rmesa->hw.tex[5].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCTLALL_5);
895 rmesa->hw.tex[5].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_5);
896 } else {
897 rmesa->hw.tex[0].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXFILTER_0);
898 rmesa->hw.tex[0].cmd[TEX_CMD_1_OLDDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_0);
899 rmesa->hw.tex[1].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXFILTER_1);
900 rmesa->hw.tex[1].cmd[TEX_CMD_1_OLDDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_1);
901 rmesa->hw.tex[2].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXFILTER_2);
902 rmesa->hw.tex[2].cmd[TEX_CMD_1_OLDDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_2);
903 rmesa->hw.tex[3].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXFILTER_3);
904 rmesa->hw.tex[3].cmd[TEX_CMD_1_OLDDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_3);
905 rmesa->hw.tex[4].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXFILTER_4);
906 rmesa->hw.tex[4].cmd[TEX_CMD_1_OLDDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_4);
907 rmesa->hw.tex[5].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXFILTER_5);
908 rmesa->hw.tex[5].cmd[TEX_CMD_1_OLDDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_5);
909 }
910 rmesa->hw.afs[0].cmd[AFS_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_AFS_0);
911 rmesa->hw.afs[1].cmd[AFS_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_AFS_1);
912 rmesa->hw.pvs.cmd[PVS_CMD_0] = cmdpkt(rmesa, R200_EMIT_VAP_PVS_CNTL);
913 rmesa->hw.cube[0].cmd[CUBE_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_FACES_0);
914 rmesa->hw.cube[0].cmd[CUBE_CMD_1] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_OFFSETS_0);
915 rmesa->hw.cube[1].cmd[CUBE_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_FACES_1);
916 rmesa->hw.cube[1].cmd[CUBE_CMD_1] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_OFFSETS_1);
917 rmesa->hw.cube[2].cmd[CUBE_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_FACES_2);
918 rmesa->hw.cube[2].cmd[CUBE_CMD_1] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_OFFSETS_2);
919 rmesa->hw.cube[3].cmd[CUBE_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_FACES_3);
920 rmesa->hw.cube[3].cmd[CUBE_CMD_1] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_OFFSETS_3);
921 rmesa->hw.cube[4].cmd[CUBE_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_FACES_4);
922 rmesa->hw.cube[4].cmd[CUBE_CMD_1] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_OFFSETS_4);
923 rmesa->hw.cube[5].cmd[CUBE_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_FACES_5);
924 rmesa->hw.cube[5].cmd[CUBE_CMD_1] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_OFFSETS_5);
925 rmesa->hw.pix[0].cmd[PIX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCBLEND_0);
926 rmesa->hw.pix[1].cmd[PIX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCBLEND_1);
927 rmesa->hw.pix[2].cmd[PIX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCBLEND_2);
928 rmesa->hw.pix[3].cmd[PIX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCBLEND_3);
929 rmesa->hw.pix[4].cmd[PIX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCBLEND_4);
930 rmesa->hw.pix[5].cmd[PIX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCBLEND_5);
931 rmesa->hw.zbs.cmd[ZBS_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_SE_ZBIAS_FACTOR);
932 rmesa->hw.tcl.cmd[TCL_CMD_0] = cmdpkt(rmesa, R200_EMIT_TCL_LIGHT_MODEL_CTL_0);
933 rmesa->hw.tcl.cmd[TCL_CMD_1] = cmdpkt(rmesa, R200_EMIT_TCL_UCP_VERT_BLEND_CTL);
934 rmesa->hw.tcg.cmd[TCG_CMD_0] = cmdpkt(rmesa, R200_EMIT_TEX_PROC_CTL_2);
935 rmesa->hw.msl.cmd[MSL_CMD_0] = cmdpkt(rmesa, R200_EMIT_MATRIX_SELECT_0);
936 rmesa->hw.vap.cmd[VAP_CMD_0] = cmdpkt(rmesa, R200_EMIT_VAP_CTL);
937 rmesa->hw.vtx.cmd[VTX_CMD_0] = cmdpkt(rmesa, R200_EMIT_VTX_FMT_0);
938 rmesa->hw.vtx.cmd[VTX_CMD_1] = cmdpkt(rmesa, R200_EMIT_OUTPUT_VTX_COMP_SEL);
939 rmesa->hw.vtx.cmd[VTX_CMD_2] = cmdpkt(rmesa, R200_EMIT_SE_VTX_STATE_CNTL);
940 rmesa->hw.vte.cmd[VTE_CMD_0] = cmdpkt(rmesa, R200_EMIT_VTE_CNTL);
941 rmesa->hw.prf.cmd[PRF_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TRI_PERF_CNTL);
942 rmesa->hw.spr.cmd[SPR_CMD_0] = cmdpkt(rmesa, R200_EMIT_TCL_POINT_SPRITE_CNTL);
943 if (rmesa->radeon.radeonScreen->kernel_mm) {
944 rmesa->hw.mtl[0].emit = mtl_emit;
945 rmesa->hw.mtl[1].emit = mtl_emit;
946
947 rmesa->hw.vpi[0].emit = veclinear_emit;
948 rmesa->hw.vpi[1].emit = veclinear_emit;
949 rmesa->hw.vpp[0].emit = veclinear_emit;
950 rmesa->hw.vpp[1].emit = veclinear_emit;
951
952 rmesa->hw.grd.emit = scl_emit;
953 rmesa->hw.fog.emit = vec_emit;
954 rmesa->hw.glt.emit = vec_emit;
955 rmesa->hw.eye.emit = vec_emit;
956
957 for (i = R200_MTX_MV; i <= R200_MTX_TEX5; i++)
958 rmesa->hw.mat[i].emit = vec_emit;
959
960 for (i = 0; i < 8; i++)
961 rmesa->hw.lit[i].emit = lit_emit;
962
963 for (i = 0; i < 6; i++)
964 rmesa->hw.ucp[i].emit = vec_emit;
965
966 rmesa->hw.ptp.emit = ptp_emit;
967 }
968
969
970
971 rmesa->hw.mtl[0].cmd[MTL_CMD_0] =
972 cmdvec( R200_VS_MAT_0_EMISS, 1, 16 );
973 rmesa->hw.mtl[0].cmd[MTL_CMD_1] =
974 cmdscl2( R200_SS_MAT_0_SHININESS, 1, 1 );
975 rmesa->hw.mtl[1].cmd[MTL_CMD_0] =
976 cmdvec( R200_VS_MAT_1_EMISS, 1, 16 );
977 rmesa->hw.mtl[1].cmd[MTL_CMD_1] =
978 cmdscl2( R200_SS_MAT_1_SHININESS, 1, 1 );
979
980 rmesa->hw.vpi[0].cmd[VPI_CMD_0] =
981 cmdveclinear( R200_PVS_PROG0, 64 );
982 rmesa->hw.vpi[1].cmd[VPI_CMD_0] =
983 cmdveclinear( R200_PVS_PROG1, 64 );
984 rmesa->hw.vpp[0].cmd[VPP_CMD_0] =
985 cmdveclinear( R200_PVS_PARAM0, 96 );
986 rmesa->hw.vpp[1].cmd[VPP_CMD_0] =
987 cmdveclinear( R200_PVS_PARAM1, 96 );
988
989 rmesa->hw.grd.cmd[GRD_CMD_0] =
990 cmdscl( R200_SS_VERT_GUARD_CLIP_ADJ_ADDR, 1, 4 );
991 rmesa->hw.fog.cmd[FOG_CMD_0] =
992 cmdvec( R200_VS_FOG_PARAM_ADDR, 1, 4 );
993 rmesa->hw.glt.cmd[GLT_CMD_0] =
994 cmdvec( R200_VS_GLOBAL_AMBIENT_ADDR, 1, 4 );
995 rmesa->hw.eye.cmd[EYE_CMD_0] =
996 cmdvec( R200_VS_EYE_VECTOR_ADDR, 1, 4 );
997
998 rmesa->hw.mat[R200_MTX_MV].cmd[MAT_CMD_0] =
999 cmdvec( R200_VS_MATRIX_0_MV, 1, 16);
1000 rmesa->hw.mat[R200_MTX_IMV].cmd[MAT_CMD_0] =
1001 cmdvec( R200_VS_MATRIX_1_INV_MV, 1, 16);
1002 rmesa->hw.mat[R200_MTX_MVP].cmd[MAT_CMD_0] =
1003 cmdvec( R200_VS_MATRIX_2_MVP, 1, 16);
1004 rmesa->hw.mat[R200_MTX_TEX0].cmd[MAT_CMD_0] =
1005 cmdvec( R200_VS_MATRIX_3_TEX0, 1, 16);
1006 rmesa->hw.mat[R200_MTX_TEX1].cmd[MAT_CMD_0] =
1007 cmdvec( R200_VS_MATRIX_4_TEX1, 1, 16);
1008 rmesa->hw.mat[R200_MTX_TEX2].cmd[MAT_CMD_0] =
1009 cmdvec( R200_VS_MATRIX_5_TEX2, 1, 16);
1010 rmesa->hw.mat[R200_MTX_TEX3].cmd[MAT_CMD_0] =
1011 cmdvec( R200_VS_MATRIX_6_TEX3, 1, 16);
1012 rmesa->hw.mat[R200_MTX_TEX4].cmd[MAT_CMD_0] =
1013 cmdvec( R200_VS_MATRIX_7_TEX4, 1, 16);
1014 rmesa->hw.mat[R200_MTX_TEX5].cmd[MAT_CMD_0] =
1015 cmdvec( R200_VS_MATRIX_8_TEX5, 1, 16);
1016
1017 for (i = 0 ; i < 8; i++) {
1018 rmesa->hw.lit[i].cmd[LIT_CMD_0] =
1019 cmdvec( R200_VS_LIGHT_AMBIENT_ADDR + i, 8, 24 );
1020 rmesa->hw.lit[i].cmd[LIT_CMD_1] =
1021 cmdscl( R200_SS_LIGHT_DCD_ADDR + i, 8, 7 );
1022 }
1023
1024 for (i = 0 ; i < 6; i++) {
1025 rmesa->hw.ucp[i].cmd[UCP_CMD_0] =
1026 cmdvec( R200_VS_UCP_ADDR + i, 1, 4 );
1027 }
1028
1029 rmesa->hw.ptp.cmd[PTP_CMD_0] =
1030 cmdvec( R200_VS_PNT_SPRITE_VPORT_SCALE, 1, 4 );
1031 rmesa->hw.ptp.cmd[PTP_CMD_1] =
1032 cmdvec( R200_VS_PNT_SPRITE_ATT_CONST, 1, 12 );
1033
1034 /* Initial Harware state:
1035 */
1036 rmesa->hw.ctx.cmd[CTX_PP_MISC] = (R200_ALPHA_TEST_PASS
1037 /* | R200_RIGHT_HAND_CUBE_OGL*/);
1038
1039 rmesa->hw.ctx.cmd[CTX_PP_FOG_COLOR] = (R200_FOG_VERTEX |
1040 R200_FOG_USE_SPEC_ALPHA);
1041
1042 rmesa->hw.ctx.cmd[CTX_RE_SOLID_COLOR] = 0x00000000;
1043
1044 rmesa->hw.ctx.cmd[CTX_RB3D_BLENDCNTL] = (R200_COMB_FCN_ADD_CLAMP |
1045 (R200_BLEND_GL_ONE << R200_SRC_BLEND_SHIFT) |
1046 (R200_BLEND_GL_ZERO << R200_DST_BLEND_SHIFT));
1047
1048 if (rmesa->radeon.radeonScreen->drmSupportsBlendColor) {
1049 rmesa->hw.ctx.cmd[CTX_RB3D_BLENDCOLOR] = 0x00000000;
1050 rmesa->hw.ctx.cmd[CTX_RB3D_ABLENDCNTL] = (R200_COMB_FCN_ADD_CLAMP |
1051 (R200_BLEND_GL_ONE << R200_SRC_BLEND_SHIFT) |
1052 (R200_BLEND_GL_ZERO << R200_DST_BLEND_SHIFT));
1053 rmesa->hw.ctx.cmd[CTX_RB3D_CBLENDCNTL] = (R200_COMB_FCN_ADD_CLAMP |
1054 (R200_BLEND_GL_ONE << R200_SRC_BLEND_SHIFT) |
1055 (R200_BLEND_GL_ZERO << R200_DST_BLEND_SHIFT));
1056 }
1057
1058 rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHOFFSET] =
1059 rmesa->radeon.radeonScreen->depthOffset + rmesa->radeon.radeonScreen->fbLocation;
1060
1061 rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHPITCH] =
1062 ((rmesa->radeon.radeonScreen->depthPitch &
1063 R200_DEPTHPITCH_MASK) |
1064 R200_DEPTH_ENDIAN_NO_SWAP);
1065
1066 if (rmesa->using_hyperz)
1067 rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHPITCH] |= R200_DEPTH_HYPERZ;
1068
1069 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] = (R200_Z_TEST_LESS |
1070 R200_STENCIL_TEST_ALWAYS |
1071 R200_STENCIL_FAIL_KEEP |
1072 R200_STENCIL_ZPASS_KEEP |
1073 R200_STENCIL_ZFAIL_KEEP |
1074 R200_Z_WRITE_ENABLE);
1075
1076 if (rmesa->using_hyperz) {
1077 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= R200_Z_COMPRESSION_ENABLE |
1078 R200_Z_DECOMPRESSION_ENABLE;
1079 /* if (rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_R200)
1080 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_HIERARCHY_ENABLE;*/
1081 }
1082
1083 rmesa->hw.ctx.cmd[CTX_PP_CNTL] = (R200_ANTI_ALIAS_NONE
1084 | R200_TEX_BLEND_0_ENABLE);
1085
1086 switch ( driQueryOptioni( &rmesa->radeon.optionCache, "dither_mode" ) ) {
1087 case DRI_CONF_DITHER_XERRORDIFFRESET:
1088 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= R200_DITHER_INIT;
1089 break;
1090 case DRI_CONF_DITHER_ORDERED:
1091 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= R200_SCALE_DITHER_ENABLE;
1092 break;
1093 }
1094 if ( driQueryOptioni( &rmesa->radeon.optionCache, "round_mode" ) ==
1095 DRI_CONF_ROUND_ROUND )
1096 rmesa->radeon.state.color.roundEnable = R200_ROUND_ENABLE;
1097 else
1098 rmesa->radeon.state.color.roundEnable = 0;
1099 if ( driQueryOptioni (&rmesa->radeon.optionCache, "color_reduction" ) ==
1100 DRI_CONF_COLOR_REDUCTION_DITHER )
1101 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= R200_DITHER_ENABLE;
1102 else
1103 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= rmesa->radeon.state.color.roundEnable;
1104
1105 rmesa->hw.prf.cmd[PRF_PP_TRI_PERF] = R200_TRI_CUTOFF_MASK - R200_TRI_CUTOFF_MASK *
1106 driQueryOptionf (&rmesa->radeon.optionCache,"texture_blend_quality");
1107 rmesa->hw.prf.cmd[PRF_PP_PERF_CNTL] = 0;
1108
1109 rmesa->hw.set.cmd[SET_SE_CNTL] = (R200_FFACE_CULL_CCW |
1110 R200_BFACE_SOLID |
1111 R200_FFACE_SOLID |
1112 R200_FLAT_SHADE_VTX_LAST |
1113 R200_DIFFUSE_SHADE_GOURAUD |
1114 R200_ALPHA_SHADE_GOURAUD |
1115 R200_SPECULAR_SHADE_GOURAUD |
1116 R200_FOG_SHADE_GOURAUD |
1117 R200_DISC_FOG_SHADE_GOURAUD |
1118 R200_VTX_PIX_CENTER_OGL |
1119 R200_ROUND_MODE_TRUNC |
1120 R200_ROUND_PREC_8TH_PIX);
1121
1122 rmesa->hw.set.cmd[SET_RE_CNTL] = (R200_PERSPECTIVE_ENABLE |
1123 R200_SCISSOR_ENABLE);
1124
1125 rmesa->hw.lin.cmd[LIN_RE_LINE_PATTERN] = ((1 << 16) | 0xffff);
1126
1127 rmesa->hw.lin.cmd[LIN_RE_LINE_STATE] =
1128 ((0 << R200_LINE_CURRENT_PTR_SHIFT) |
1129 (1 << R200_LINE_CURRENT_COUNT_SHIFT));
1130
1131 rmesa->hw.lin.cmd[LIN_SE_LINE_WIDTH] = (1 << 4);
1132
1133 rmesa->hw.msk.cmd[MSK_RB3D_STENCILREFMASK] =
1134 ((0x00 << R200_STENCIL_REF_SHIFT) |
1135 (0xff << R200_STENCIL_MASK_SHIFT) |
1136 (0xff << R200_STENCIL_WRITEMASK_SHIFT));
1137
1138 rmesa->hw.msk.cmd[MSK_RB3D_ROPCNTL] = R200_ROP_COPY;
1139 rmesa->hw.msk.cmd[MSK_RB3D_PLANEMASK] = 0xffffffff;
1140
1141 rmesa->hw.tam.cmd[TAM_DEBUG3] = 0;
1142
1143 rmesa->hw.msc.cmd[MSC_RE_MISC] =
1144 ((0 << R200_STIPPLE_X_OFFSET_SHIFT) |
1145 (0 << R200_STIPPLE_Y_OFFSET_SHIFT) |
1146 R200_STIPPLE_BIG_BIT_ORDER);
1147
1148
1149 rmesa->hw.cst.cmd[CST_PP_CNTL_X] = 0;
1150 rmesa->hw.cst.cmd[CST_RB3D_DEPTHXY_OFFSET] = 0;
1151 rmesa->hw.cst.cmd[CST_RE_AUX_SCISSOR_CNTL] = 0x0;
1152 rmesa->hw.cst.cmd[CST_RE_SCISSOR_TL_0] = 0;
1153 rmesa->hw.cst.cmd[CST_RE_SCISSOR_BR_0] = 0;
1154 rmesa->hw.cst.cmd[CST_SE_VAP_CNTL_STATUS] =
1155 #ifdef MESA_BIG_ENDIAN
1156 R200_VC_32BIT_SWAP;
1157 #else
1158 R200_VC_NO_SWAP;
1159 #endif
1160
1161 if (!(rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL)) {
1162 /* Bypass TCL */
1163 rmesa->hw.cst.cmd[CST_SE_VAP_CNTL_STATUS] |= (1<<8);
1164 }
1165
1166 rmesa->hw.cst.cmd[CST_RE_POINTSIZE] =
1167 (((GLuint)(ctx->Const.MaxPointSize * 16.0)) << R200_MAXPOINTSIZE_SHIFT) | 0x10;
1168 rmesa->hw.cst.cmd[CST_SE_TCL_INPUT_VTX_0] =
1169 (0x0 << R200_VERTEX_POSITION_ADDR__SHIFT);
1170 rmesa->hw.cst.cmd[CST_SE_TCL_INPUT_VTX_1] =
1171 (0x02 << R200_VTX_COLOR_0_ADDR__SHIFT) |
1172 (0x03 << R200_VTX_COLOR_1_ADDR__SHIFT);
1173 rmesa->hw.cst.cmd[CST_SE_TCL_INPUT_VTX_2] =
1174 (0x06 << R200_VTX_TEX_0_ADDR__SHIFT) |
1175 (0x07 << R200_VTX_TEX_1_ADDR__SHIFT) |
1176 (0x08 << R200_VTX_TEX_2_ADDR__SHIFT) |
1177 (0x09 << R200_VTX_TEX_3_ADDR__SHIFT);
1178 rmesa->hw.cst.cmd[CST_SE_TCL_INPUT_VTX_3] =
1179 (0x0A << R200_VTX_TEX_4_ADDR__SHIFT) |
1180 (0x0B << R200_VTX_TEX_5_ADDR__SHIFT);
1181
1182
1183 rmesa->hw.vpt.cmd[VPT_SE_VPORT_XSCALE] = 0x00000000;
1184 rmesa->hw.vpt.cmd[VPT_SE_VPORT_XOFFSET] = 0x00000000;
1185 rmesa->hw.vpt.cmd[VPT_SE_VPORT_YSCALE] = 0x00000000;
1186 rmesa->hw.vpt.cmd[VPT_SE_VPORT_YOFFSET] = 0x00000000;
1187 rmesa->hw.vpt.cmd[VPT_SE_VPORT_ZSCALE] = 0x00000000;
1188 rmesa->hw.vpt.cmd[VPT_SE_VPORT_ZOFFSET] = 0x00000000;
1189
1190 for ( i = 0 ; i < ctx->Const.MaxTextureUnits ; i++ ) {
1191 rmesa->hw.tex[i].cmd[TEX_PP_TXFILTER] = R200_BORDER_MODE_OGL;
1192 rmesa->hw.tex[i].cmd[TEX_PP_TXFORMAT] =
1193 ((i << R200_TXFORMAT_ST_ROUTE_SHIFT) | /* <-- note i */
1194 (2 << R200_TXFORMAT_WIDTH_SHIFT) |
1195 (2 << R200_TXFORMAT_HEIGHT_SHIFT));
1196 rmesa->hw.tex[i].cmd[TEX_PP_BORDER_COLOR] = 0;
1197 rmesa->hw.tex[i].cmd[TEX_PP_TXFORMAT_X] =
1198 (/* R200_TEXCOORD_PROJ | */
1199 0x100000); /* Small default bias */
1200 if (rmesa->radeon.radeonScreen->drmSupportsFragShader) {
1201 rmesa->hw.tex[i].cmd[TEX_PP_TXOFFSET_NEWDRM] =
1202 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
1203 rmesa->hw.tex[i].cmd[TEX_PP_CUBIC_FACES] = 0;
1204 rmesa->hw.tex[i].cmd[TEX_PP_TXMULTI_CTL] = 0;
1205 }
1206 else {
1207 rmesa->hw.tex[i].cmd[TEX_PP_TXOFFSET_OLDDRM] =
1208 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
1209 }
1210
1211 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_FACES] = 0;
1212 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F1] =
1213 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
1214 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F2] =
1215 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
1216 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F3] =
1217 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
1218 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F4] =
1219 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
1220 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F5] =
1221 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
1222
1223 rmesa->hw.pix[i].cmd[PIX_PP_TXCBLEND] =
1224 (R200_TXC_ARG_A_ZERO |
1225 R200_TXC_ARG_B_ZERO |
1226 R200_TXC_ARG_C_DIFFUSE_COLOR |
1227 R200_TXC_OP_MADD);
1228
1229 rmesa->hw.pix[i].cmd[PIX_PP_TXCBLEND2] =
1230 ((i << R200_TXC_TFACTOR_SEL_SHIFT) |
1231 R200_TXC_SCALE_1X |
1232 R200_TXC_CLAMP_0_1 |
1233 R200_TXC_OUTPUT_REG_R0);
1234
1235 rmesa->hw.pix[i].cmd[PIX_PP_TXABLEND] =
1236 (R200_TXA_ARG_A_ZERO |
1237 R200_TXA_ARG_B_ZERO |
1238 R200_TXA_ARG_C_DIFFUSE_ALPHA |
1239 R200_TXA_OP_MADD);
1240
1241 rmesa->hw.pix[i].cmd[PIX_PP_TXABLEND2] =
1242 ((i << R200_TXA_TFACTOR_SEL_SHIFT) |
1243 R200_TXA_SCALE_1X |
1244 R200_TXA_CLAMP_0_1 |
1245 R200_TXA_OUTPUT_REG_R0);
1246 }
1247
1248 rmesa->hw.tf.cmd[TF_TFACTOR_0] = 0;
1249 rmesa->hw.tf.cmd[TF_TFACTOR_1] = 0;
1250 rmesa->hw.tf.cmd[TF_TFACTOR_2] = 0;
1251 rmesa->hw.tf.cmd[TF_TFACTOR_3] = 0;
1252 rmesa->hw.tf.cmd[TF_TFACTOR_4] = 0;
1253 rmesa->hw.tf.cmd[TF_TFACTOR_5] = 0;
1254
1255 rmesa->hw.vap.cmd[VAP_SE_VAP_CNTL] =
1256 (R200_VAP_TCL_ENABLE |
1257 (0x9 << R200_VAP_VF_MAX_VTX_NUM__SHIFT));
1258
1259 rmesa->hw.vte.cmd[VTE_SE_VTE_CNTL] =
1260 (R200_VPORT_X_SCALE_ENA |
1261 R200_VPORT_Y_SCALE_ENA |
1262 R200_VPORT_Z_SCALE_ENA |
1263 R200_VPORT_X_OFFSET_ENA |
1264 R200_VPORT_Y_OFFSET_ENA |
1265 R200_VPORT_Z_OFFSET_ENA |
1266 /* FIXME: Turn on for tex rect only */
1267 R200_VTX_ST_DENORMALIZED |
1268 R200_VTX_W0_FMT);
1269
1270
1271 rmesa->hw.vtx.cmd[VTX_VTXFMT_0] = 0;
1272 rmesa->hw.vtx.cmd[VTX_VTXFMT_1] = 0;
1273 rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_VTXFMT_0] =
1274 ((R200_VTX_Z0 | R200_VTX_W0 |
1275 (R200_VTX_FP_RGBA << R200_VTX_COLOR_0_SHIFT)));
1276 rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_VTXFMT_1] = 0;
1277 rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_COMPSEL] = (R200_OUTPUT_XYZW);
1278 rmesa->hw.vtx.cmd[VTX_STATE_CNTL] = R200_VSC_UPDATE_USER_COLOR_0_ENABLE;
1279
1280
1281 /* Matrix selection */
1282 rmesa->hw.msl.cmd[MSL_MATRIX_SELECT_0] =
1283 (R200_MTX_MV << R200_MODELVIEW_0_SHIFT);
1284
1285 rmesa->hw.msl.cmd[MSL_MATRIX_SELECT_1] =
1286 (R200_MTX_IMV << R200_IT_MODELVIEW_0_SHIFT);
1287
1288 rmesa->hw.msl.cmd[MSL_MATRIX_SELECT_2] =
1289 (R200_MTX_MVP << R200_MODELPROJECT_0_SHIFT);
1290
1291 rmesa->hw.msl.cmd[MSL_MATRIX_SELECT_3] =
1292 ((R200_MTX_TEX0 << R200_TEXMAT_0_SHIFT) |
1293 (R200_MTX_TEX1 << R200_TEXMAT_1_SHIFT) |
1294 (R200_MTX_TEX2 << R200_TEXMAT_2_SHIFT) |
1295 (R200_MTX_TEX3 << R200_TEXMAT_3_SHIFT));
1296
1297 rmesa->hw.msl.cmd[MSL_MATRIX_SELECT_4] =
1298 ((R200_MTX_TEX4 << R200_TEXMAT_4_SHIFT) |
1299 (R200_MTX_TEX5 << R200_TEXMAT_5_SHIFT));
1300
1301
1302 /* General TCL state */
1303 rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL_0] =
1304 (R200_SPECULAR_LIGHTS |
1305 R200_DIFFUSE_SPECULAR_COMBINE |
1306 R200_LOCAL_LIGHT_VEC_GL |
1307 R200_LM0_SOURCE_MATERIAL_0 << R200_FRONT_SHININESS_SOURCE_SHIFT |
1308 R200_LM0_SOURCE_MATERIAL_1 << R200_BACK_SHININESS_SOURCE_SHIFT);
1309
1310 rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL_1] =
1311 ((R200_LM1_SOURCE_MATERIAL_0 << R200_FRONT_EMISSIVE_SOURCE_SHIFT) |
1312 (R200_LM1_SOURCE_MATERIAL_0 << R200_FRONT_AMBIENT_SOURCE_SHIFT) |
1313 (R200_LM1_SOURCE_MATERIAL_0 << R200_FRONT_DIFFUSE_SOURCE_SHIFT) |
1314 (R200_LM1_SOURCE_MATERIAL_0 << R200_FRONT_SPECULAR_SOURCE_SHIFT) |
1315 (R200_LM1_SOURCE_MATERIAL_1 << R200_BACK_EMISSIVE_SOURCE_SHIFT) |
1316 (R200_LM1_SOURCE_MATERIAL_1 << R200_BACK_AMBIENT_SOURCE_SHIFT) |
1317 (R200_LM1_SOURCE_MATERIAL_1 << R200_BACK_DIFFUSE_SOURCE_SHIFT) |
1318 (R200_LM1_SOURCE_MATERIAL_1 << R200_BACK_SPECULAR_SOURCE_SHIFT));
1319
1320 rmesa->hw.tcl.cmd[TCL_PER_LIGHT_CTL_0] = 0; /* filled in via callbacks */
1321 rmesa->hw.tcl.cmd[TCL_PER_LIGHT_CTL_1] = 0;
1322 rmesa->hw.tcl.cmd[TCL_PER_LIGHT_CTL_2] = 0;
1323 rmesa->hw.tcl.cmd[TCL_PER_LIGHT_CTL_3] = 0;
1324
1325 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] =
1326 (R200_UCP_IN_CLIP_SPACE |
1327 R200_CULL_FRONT_IS_CCW);
1328
1329 /* Texgen/Texmat state */
1330 rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_2] = 0x00ffffff;
1331 rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_3] =
1332 ((0 << R200_TEXGEN_0_INPUT_TEX_SHIFT) |
1333 (1 << R200_TEXGEN_1_INPUT_TEX_SHIFT) |
1334 (2 << R200_TEXGEN_2_INPUT_TEX_SHIFT) |
1335 (3 << R200_TEXGEN_3_INPUT_TEX_SHIFT) |
1336 (4 << R200_TEXGEN_4_INPUT_TEX_SHIFT) |
1337 (5 << R200_TEXGEN_5_INPUT_TEX_SHIFT));
1338 rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_0] = 0;
1339 rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_1] =
1340 ((0 << R200_TEXGEN_0_INPUT_SHIFT) |
1341 (1 << R200_TEXGEN_1_INPUT_SHIFT) |
1342 (2 << R200_TEXGEN_2_INPUT_SHIFT) |
1343 (3 << R200_TEXGEN_3_INPUT_SHIFT) |
1344 (4 << R200_TEXGEN_4_INPUT_SHIFT) |
1345 (5 << R200_TEXGEN_5_INPUT_SHIFT));
1346 rmesa->hw.tcg.cmd[TCG_TEX_CYL_WRAP_CTL] = 0;
1347
1348
1349 for (i = 0 ; i < 8; i++) {
1350 struct gl_light *l = &ctx->Light.Light[i];
1351 GLenum p = GL_LIGHT0 + i;
1352 *(float *)&(rmesa->hw.lit[i].cmd[LIT_RANGE_CUTOFF]) = FLT_MAX;
1353
1354 ctx->Driver.Lightfv( ctx, p, GL_AMBIENT, l->Ambient );
1355 ctx->Driver.Lightfv( ctx, p, GL_DIFFUSE, l->Diffuse );
1356 ctx->Driver.Lightfv( ctx, p, GL_SPECULAR, l->Specular );
1357 ctx->Driver.Lightfv( ctx, p, GL_POSITION, NULL );
1358 ctx->Driver.Lightfv( ctx, p, GL_SPOT_DIRECTION, NULL );
1359 ctx->Driver.Lightfv( ctx, p, GL_SPOT_EXPONENT, &l->SpotExponent );
1360 ctx->Driver.Lightfv( ctx, p, GL_SPOT_CUTOFF, &l->SpotCutoff );
1361 ctx->Driver.Lightfv( ctx, p, GL_CONSTANT_ATTENUATION,
1362 &l->ConstantAttenuation );
1363 ctx->Driver.Lightfv( ctx, p, GL_LINEAR_ATTENUATION,
1364 &l->LinearAttenuation );
1365 ctx->Driver.Lightfv( ctx, p, GL_QUADRATIC_ATTENUATION,
1366 &l->QuadraticAttenuation );
1367 *(float *)&(rmesa->hw.lit[i].cmd[LIT_ATTEN_XXX]) = 0.0;
1368 }
1369
1370 ctx->Driver.LightModelfv( ctx, GL_LIGHT_MODEL_AMBIENT,
1371 ctx->Light.Model.Ambient );
1372
1373 TNL_CONTEXT(ctx)->Driver.NotifyMaterialChange( ctx );
1374
1375 for (i = 0 ; i < 6; i++) {
1376 ctx->Driver.ClipPlane( ctx, GL_CLIP_PLANE0 + i, NULL );
1377 }
1378
1379 ctx->Driver.Fogfv( ctx, GL_FOG_MODE, NULL );
1380 ctx->Driver.Fogfv( ctx, GL_FOG_DENSITY, &ctx->Fog.Density );
1381 ctx->Driver.Fogfv( ctx, GL_FOG_START, &ctx->Fog.Start );
1382 ctx->Driver.Fogfv( ctx, GL_FOG_END, &ctx->Fog.End );
1383 ctx->Driver.Fogfv( ctx, GL_FOG_COLOR, ctx->Fog.Color );
1384 ctx->Driver.Fogfv( ctx, GL_FOG_COORDINATE_SOURCE_EXT, NULL );
1385
1386 rmesa->hw.grd.cmd[GRD_VERT_GUARD_CLIP_ADJ] = IEEE_ONE;
1387 rmesa->hw.grd.cmd[GRD_VERT_GUARD_DISCARD_ADJ] = IEEE_ONE;
1388 rmesa->hw.grd.cmd[GRD_HORZ_GUARD_CLIP_ADJ] = IEEE_ONE;
1389 rmesa->hw.grd.cmd[GRD_HORZ_GUARD_DISCARD_ADJ] = IEEE_ONE;
1390
1391 rmesa->hw.eye.cmd[EYE_X] = 0;
1392 rmesa->hw.eye.cmd[EYE_Y] = 0;
1393 rmesa->hw.eye.cmd[EYE_Z] = IEEE_ONE;
1394 rmesa->hw.eye.cmd[EYE_RESCALE_FACTOR] = IEEE_ONE;
1395
1396 rmesa->hw.spr.cmd[SPR_POINT_SPRITE_CNTL] =
1397 R200_PS_SE_SEL_STATE | R200_PS_MULT_CONST;
1398
1399 /* ptp_eye is presumably used to calculate the attenuation wrt a different
1400 location? In any case, since point attenuation triggers _needeyecoords,
1401 it is constant. Probably ignored as long as R200_PS_USE_MODEL_EYE_VEC
1402 isn't set */
1403 rmesa->hw.ptp.cmd[PTP_EYE_X] = 0;
1404 rmesa->hw.ptp.cmd[PTP_EYE_Y] = 0;
1405 rmesa->hw.ptp.cmd[PTP_EYE_Z] = IEEE_ONE | 0x80000000; /* -1.0 */
1406 rmesa->hw.ptp.cmd[PTP_EYE_3] = 0;
1407 /* no idea what the ptp_vport_scale values are good for, except the
1408 PTSIZE one - hopefully doesn't matter */
1409 rmesa->hw.ptp.cmd[PTP_VPORT_SCALE_0] = IEEE_ONE;
1410 rmesa->hw.ptp.cmd[PTP_VPORT_SCALE_1] = IEEE_ONE;
1411 rmesa->hw.ptp.cmd[PTP_VPORT_SCALE_PTSIZE] = IEEE_ONE;
1412 rmesa->hw.ptp.cmd[PTP_VPORT_SCALE_3] = IEEE_ONE;
1413 rmesa->hw.ptp.cmd[PTP_ATT_CONST_QUAD] = 0;
1414 rmesa->hw.ptp.cmd[PTP_ATT_CONST_LIN] = 0;
1415 rmesa->hw.ptp.cmd[PTP_ATT_CONST_CON] = IEEE_ONE;
1416 rmesa->hw.ptp.cmd[PTP_ATT_CONST_3] = 0;
1417 rmesa->hw.ptp.cmd[PTP_CLAMP_MIN] = IEEE_ONE;
1418 rmesa->hw.ptp.cmd[PTP_CLAMP_MAX] = 0x44ffe000; /* 2047 */
1419 rmesa->hw.ptp.cmd[PTP_CLAMP_2] = 0;
1420 rmesa->hw.ptp.cmd[PTP_CLAMP_3] = 0;
1421
1422 r200LightingSpaceChange( ctx );
1423
1424 rmesa->radeon.hw.all_dirty = GL_TRUE;
1425
1426 rcommonInitCmdBuf(&rmesa->radeon);
1427 }