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r200: fix another section size mismatch
[mesa.git] / src / mesa / drivers / dri / r200 / r200_state_init.c
1 /*
2 Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
3
4 The Weather Channel (TM) funded Tungsten Graphics to develop the
5 initial release of the Radeon 8500 driver under the XFree86 license.
6 This notice must be preserved.
7
8 Permission is hereby granted, free of charge, to any person obtaining
9 a copy of this software and associated documentation files (the
10 "Software"), to deal in the Software without restriction, including
11 without limitation the rights to use, copy, modify, merge, publish,
12 distribute, sublicense, and/or sell copies of the Software, and to
13 permit persons to whom the Software is furnished to do so, subject to
14 the following conditions:
15
16 The above copyright notice and this permission notice (including the
17 next paragraph) shall be included in all copies or substantial
18 portions of the Software.
19
20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 */
28
29 /*
30 * Authors:
31 * Keith Whitwell <keith@tungstengraphics.com>
32 */
33
34 #include "main/glheader.h"
35 #include "main/imports.h"
36 #include "main/enums.h"
37 #include "main/colormac.h"
38 #include "main/api_arrayelt.h"
39
40 #include "swrast/swrast.h"
41 #include "vbo/vbo.h"
42 #include "tnl/tnl.h"
43 #include "tnl/t_pipeline.h"
44 #include "swrast_setup/swrast_setup.h"
45
46 #include "radeon_common.h"
47 #include "radeon_mipmap_tree.h"
48 #include "r200_context.h"
49 #include "r200_ioctl.h"
50 #include "r200_state.h"
51 #include "r200_tcl.h"
52 #include "r200_tex.h"
53 #include "r200_swtcl.h"
54
55 #include "xmlpool.h"
56
57 /* New (1.3) state mechanism. 3 commands (packet, scalar, vector) in
58 * 1.3 cmdbuffers allow all previous state to be updated as well as
59 * the tcl scalar and vector areas.
60 */
61 static struct {
62 int start;
63 int len;
64 const char *name;
65 } packet[RADEON_MAX_STATE_PACKETS] = {
66 {RADEON_PP_MISC, 7, "RADEON_PP_MISC"},
67 {RADEON_PP_CNTL, 3, "RADEON_PP_CNTL"},
68 {RADEON_RB3D_COLORPITCH, 1, "RADEON_RB3D_COLORPITCH"},
69 {RADEON_RE_LINE_PATTERN, 2, "RADEON_RE_LINE_PATTERN"},
70 {RADEON_SE_LINE_WIDTH, 1, "RADEON_SE_LINE_WIDTH"},
71 {RADEON_PP_LUM_MATRIX, 1, "RADEON_PP_LUM_MATRIX"},
72 {RADEON_PP_ROT_MATRIX_0, 2, "RADEON_PP_ROT_MATRIX_0"},
73 {RADEON_RB3D_STENCILREFMASK, 3, "RADEON_RB3D_STENCILREFMASK"},
74 {RADEON_SE_VPORT_XSCALE, 6, "RADEON_SE_VPORT_XSCALE"},
75 {RADEON_SE_CNTL, 2, "RADEON_SE_CNTL"},
76 {RADEON_SE_CNTL_STATUS, 1, "RADEON_SE_CNTL_STATUS"},
77 {RADEON_RE_MISC, 1, "RADEON_RE_MISC"},
78 {RADEON_PP_TXFILTER_0, 6, "RADEON_PP_TXFILTER_0"},
79 {RADEON_PP_BORDER_COLOR_0, 1, "RADEON_PP_BORDER_COLOR_0"},
80 {RADEON_PP_TXFILTER_1, 6, "RADEON_PP_TXFILTER_1"},
81 {RADEON_PP_BORDER_COLOR_1, 1, "RADEON_PP_BORDER_COLOR_1"},
82 {RADEON_PP_TXFILTER_2, 6, "RADEON_PP_TXFILTER_2"},
83 {RADEON_PP_BORDER_COLOR_2, 1, "RADEON_PP_BORDER_COLOR_2"},
84 {RADEON_SE_ZBIAS_FACTOR, 2, "RADEON_SE_ZBIAS_FACTOR"},
85 {RADEON_SE_TCL_OUTPUT_VTX_FMT, 11, "RADEON_SE_TCL_OUTPUT_VTX_FMT"},
86 {RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED, 17,
87 "RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED"},
88 {R200_PP_TXCBLEND_0, 4, "R200_PP_TXCBLEND_0"},
89 {R200_PP_TXCBLEND_1, 4, "R200_PP_TXCBLEND_1"},
90 {R200_PP_TXCBLEND_2, 4, "R200_PP_TXCBLEND_2"},
91 {R200_PP_TXCBLEND_3, 4, "R200_PP_TXCBLEND_3"},
92 {R200_PP_TXCBLEND_4, 4, "R200_PP_TXCBLEND_4"},
93 {R200_PP_TXCBLEND_5, 4, "R200_PP_TXCBLEND_5"},
94 {R200_PP_TXCBLEND_6, 4, "R200_PP_TXCBLEND_6"},
95 {R200_PP_TXCBLEND_7, 4, "R200_PP_TXCBLEND_7"},
96 {R200_SE_TCL_LIGHT_MODEL_CTL_0, 6, "R200_SE_TCL_LIGHT_MODEL_CTL_0"},
97 {R200_PP_TFACTOR_0, 6, "R200_PP_TFACTOR_0"},
98 {R200_SE_VTX_FMT_0, 4, "R200_SE_VTX_FMT_0"},
99 {R200_SE_VAP_CNTL, 1, "R200_SE_VAP_CNTL"},
100 {R200_SE_TCL_MATRIX_SEL_0, 5, "R200_SE_TCL_MATRIX_SEL_0"},
101 {R200_SE_TCL_TEX_PROC_CTL_2, 5, "R200_SE_TCL_TEX_PROC_CTL_2"},
102 {R200_SE_TCL_UCP_VERT_BLEND_CTL, 1, "R200_SE_TCL_UCP_VERT_BLEND_CTL"},
103 {R200_PP_TXFILTER_0, 6, "R200_PP_TXFILTER_0"},
104 {R200_PP_TXFILTER_1, 6, "R200_PP_TXFILTER_1"},
105 {R200_PP_TXFILTER_2, 6, "R200_PP_TXFILTER_2"},
106 {R200_PP_TXFILTER_3, 6, "R200_PP_TXFILTER_3"},
107 {R200_PP_TXFILTER_4, 6, "R200_PP_TXFILTER_4"},
108 {R200_PP_TXFILTER_5, 6, "R200_PP_TXFILTER_5"},
109 {R200_PP_TXOFFSET_0, 1, "R200_PP_TXOFFSET_0"},
110 {R200_PP_TXOFFSET_1, 1, "R200_PP_TXOFFSET_1"},
111 {R200_PP_TXOFFSET_2, 1, "R200_PP_TXOFFSET_2"},
112 {R200_PP_TXOFFSET_3, 1, "R200_PP_TXOFFSET_3"},
113 {R200_PP_TXOFFSET_4, 1, "R200_PP_TXOFFSET_4"},
114 {R200_PP_TXOFFSET_5, 1, "R200_PP_TXOFFSET_5"},
115 {R200_SE_VTE_CNTL, 1, "R200_SE_VTE_CNTL"},
116 {R200_SE_TCL_OUTPUT_VTX_COMP_SEL, 1,
117 "R200_SE_TCL_OUTPUT_VTX_COMP_SEL"},
118 {R200_PP_TAM_DEBUG3, 1, "R200_PP_TAM_DEBUG3"},
119 {R200_PP_CNTL_X, 1, "R200_PP_CNTL_X"},
120 {R200_RB3D_DEPTHXY_OFFSET, 1, "R200_RB3D_DEPTHXY_OFFSET"},
121 {R200_RE_AUX_SCISSOR_CNTL, 1, "R200_RE_AUX_SCISSOR_CNTL"},
122 {R200_RE_SCISSOR_TL_0, 2, "R200_RE_SCISSOR_TL_0"},
123 {R200_RE_SCISSOR_TL_1, 2, "R200_RE_SCISSOR_TL_1"},
124 {R200_RE_SCISSOR_TL_2, 2, "R200_RE_SCISSOR_TL_2"},
125 {R200_SE_VAP_CNTL_STATUS, 1, "R200_SE_VAP_CNTL_STATUS"},
126 {R200_SE_VTX_STATE_CNTL, 1, "R200_SE_VTX_STATE_CNTL"},
127 {R200_RE_POINTSIZE, 1, "R200_RE_POINTSIZE"},
128 {R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0, 4,
129 "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0"},
130 {R200_PP_CUBIC_FACES_0, 1, "R200_PP_CUBIC_FACES_0"}, /* 61 */
131 {R200_PP_CUBIC_OFFSET_F1_0, 5, "R200_PP_CUBIC_OFFSET_F1_0"}, /* 62 */
132 {R200_PP_CUBIC_FACES_1, 1, "R200_PP_CUBIC_FACES_1"},
133 {R200_PP_CUBIC_OFFSET_F1_1, 5, "R200_PP_CUBIC_OFFSET_F1_1"},
134 {R200_PP_CUBIC_FACES_2, 1, "R200_PP_CUBIC_FACES_2"},
135 {R200_PP_CUBIC_OFFSET_F1_2, 5, "R200_PP_CUBIC_OFFSET_F1_2"},
136 {R200_PP_CUBIC_FACES_3, 1, "R200_PP_CUBIC_FACES_3"},
137 {R200_PP_CUBIC_OFFSET_F1_3, 5, "R200_PP_CUBIC_OFFSET_F1_3"},
138 {R200_PP_CUBIC_FACES_4, 1, "R200_PP_CUBIC_FACES_4"},
139 {R200_PP_CUBIC_OFFSET_F1_4, 5, "R200_PP_CUBIC_OFFSET_F1_4"},
140 {R200_PP_CUBIC_FACES_5, 1, "R200_PP_CUBIC_FACES_5"},
141 {R200_PP_CUBIC_OFFSET_F1_5, 5, "R200_PP_CUBIC_OFFSET_F1_5"},
142 {RADEON_PP_TEX_SIZE_0, 2, "RADEON_PP_TEX_SIZE_0"},
143 {RADEON_PP_TEX_SIZE_1, 2, "RADEON_PP_TEX_SIZE_1"},
144 {RADEON_PP_TEX_SIZE_2, 2, "RADEON_PP_TEX_SIZE_2"},
145 {R200_RB3D_BLENDCOLOR, 3, "R200_RB3D_BLENDCOLOR"},
146 {R200_SE_TCL_POINT_SPRITE_CNTL, 1, "R200_SE_TCL_POINT_SPRITE_CNTL"},
147 {RADEON_PP_CUBIC_FACES_0, 1, "RADEON_PP_CUBIC_FACES_0"},
148 {RADEON_PP_CUBIC_OFFSET_T0_0, 5, "RADEON_PP_CUBIC_OFFSET_T0_0"},
149 {RADEON_PP_CUBIC_FACES_1, 1, "RADEON_PP_CUBIC_FACES_1"},
150 {RADEON_PP_CUBIC_OFFSET_T1_0, 5, "RADEON_PP_CUBIC_OFFSET_T1_0"},
151 {RADEON_PP_CUBIC_FACES_2, 1, "RADEON_PP_CUBIC_FACES_2"},
152 {RADEON_PP_CUBIC_OFFSET_T2_0, 5, "RADEON_PP_CUBIC_OFFSET_T2_0"},
153 {R200_PP_TRI_PERF, 2, "R200_PP_TRI_PERF"},
154 {R200_PP_TXCBLEND_8, 32, "R200_PP_AFS_0"}, /* 85 */
155 {R200_PP_TXCBLEND_0, 32, "R200_PP_AFS_1"},
156 {R200_PP_TFACTOR_0, 8, "R200_ATF_TFACTOR"},
157 {R200_PP_TXFILTER_0, 8, "R200_PP_TXCTLALL_0"},
158 {R200_PP_TXFILTER_1, 8, "R200_PP_TXCTLALL_1"},
159 {R200_PP_TXFILTER_2, 8, "R200_PP_TXCTLALL_2"},
160 {R200_PP_TXFILTER_3, 8, "R200_PP_TXCTLALL_3"},
161 {R200_PP_TXFILTER_4, 8, "R200_PP_TXCTLALL_4"},
162 {R200_PP_TXFILTER_5, 8, "R200_PP_TXCTLALL_5"},
163 {R200_VAP_PVS_CNTL_1, 2, "R200_VAP_PVS_CNTL"},
164 };
165
166 /* =============================================================
167 * State initialization
168 */
169 static int cmdpkt( r200ContextPtr rmesa, int id )
170 {
171 drm_radeon_cmd_header_t h;
172
173 if (rmesa->radeon.radeonScreen->kernel_mm) {
174 return CP_PACKET0(packet[id].start, packet[id].len - 1);
175 } else {
176 h.i = 0;
177 h.packet.cmd_type = RADEON_CMD_PACKET;
178 h.packet.packet_id = id;
179 }
180 return h.i;
181 }
182
183 static int cmdvec( int offset, int stride, int count )
184 {
185 drm_radeon_cmd_header_t h;
186 h.i = 0;
187 h.vectors.cmd_type = RADEON_CMD_VECTORS;
188 h.vectors.offset = offset;
189 h.vectors.stride = stride;
190 h.vectors.count = count;
191 return h.i;
192 }
193
194 /* warning: the count here is divided by 4 compared to other cmds
195 (so it doesn't exceed the char size)! */
196 static int cmdveclinear( int offset, int count )
197 {
198 drm_radeon_cmd_header_t h;
199 h.i = 0;
200 h.veclinear.cmd_type = RADEON_CMD_VECLINEAR;
201 h.veclinear.addr_lo = offset & 0xff;
202 h.veclinear.addr_hi = (offset & 0xff00) >> 8;
203 h.veclinear.count = count;
204 return h.i;
205 }
206
207 static int cmdscl( int offset, int stride, int count )
208 {
209 drm_radeon_cmd_header_t h;
210 h.i = 0;
211 h.scalars.cmd_type = RADEON_CMD_SCALARS;
212 h.scalars.offset = offset;
213 h.scalars.stride = stride;
214 h.scalars.count = count;
215 return h.i;
216 }
217
218 static int cmdscl2( int offset, int stride, int count )
219 {
220 drm_radeon_cmd_header_t h;
221 h.i = 0;
222 h.scalars.cmd_type = RADEON_CMD_SCALARS2;
223 h.scalars.offset = offset - 0x100;
224 h.scalars.stride = stride;
225 h.scalars.count = count;
226 return h.i;
227 }
228
229 #define CHECK( NM, FLAG ) \
230 static int check_##NM( GLcontext *ctx, struct radeon_state_atom *atom) \
231 { \
232 r200ContextPtr rmesa = R200_CONTEXT(ctx); \
233 (void) rmesa; \
234 return (FLAG) ? atom->cmd_size : 0; \
235 }
236
237 #define TCL_CHECK( NM, FLAG ) \
238 static int check_##NM( GLcontext *ctx, struct radeon_state_atom *atom) \
239 { \
240 r200ContextPtr rmesa = R200_CONTEXT(ctx); \
241 return (!rmesa->radeon.TclFallback && !ctx->VertexProgram._Enabled && (FLAG)) ? atom->cmd_size : 0; \
242 }
243
244 #define TCL_OR_VP_CHECK( NM, FLAG ) \
245 static int check_##NM( GLcontext *ctx, struct radeon_state_atom *atom ) \
246 { \
247 r200ContextPtr rmesa = R200_CONTEXT(ctx); \
248 return (!rmesa->radeon.TclFallback && (FLAG)) ? atom->cmd_size : 0; \
249 }
250
251 #define VP_CHECK( NM, FLAG ) \
252 static int check_##NM( GLcontext *ctx, struct radeon_state_atom *atom ) \
253 { \
254 r200ContextPtr rmesa = R200_CONTEXT(ctx); \
255 (void) atom; \
256 return (!rmesa->radeon.TclFallback && ctx->VertexProgram._Enabled && (FLAG)) ? atom->cmd_size : 0; \
257 }
258
259 CHECK( always, GL_TRUE )
260 CHECK( never, GL_FALSE )
261 CHECK( tex_any, ctx->Texture._EnabledUnits )
262 CHECK( tf, (ctx->Texture._EnabledUnits && !ctx->ATIFragmentShader._Enabled) );
263 CHECK( tex_pair, (rmesa->state.texture.unit[atom->idx].unitneeded | rmesa->state.texture.unit[atom->idx & ~1].unitneeded) )
264 CHECK( tex, rmesa->state.texture.unit[atom->idx].unitneeded )
265 CHECK( pix_zero, !ctx->ATIFragmentShader._Enabled )
266 CHECK( texenv, (rmesa->state.envneeded & (1 << (atom->idx)) && !ctx->ATIFragmentShader._Enabled) )
267 CHECK( afs_pass1, (ctx->ATIFragmentShader._Enabled && (ctx->ATIFragmentShader.Current->NumPasses > 1)) )
268 CHECK( afs, ctx->ATIFragmentShader._Enabled )
269 CHECK( tex_cube, rmesa->state.texture.unit[atom->idx].unitneeded & TEXTURE_CUBE_BIT )
270 TCL_CHECK( tcl_fog, ctx->Fog.Enabled )
271 TCL_CHECK( tcl, GL_TRUE )
272 TCL_CHECK( tcl_tex, rmesa->state.texture.unit[atom->idx].unitneeded )
273 TCL_CHECK( tcl_lighting, ctx->Light.Enabled )
274 TCL_CHECK( tcl_light, ctx->Light.Enabled && ctx->Light.Light[atom->idx].Enabled )
275 TCL_OR_VP_CHECK( tcl_ucp, (ctx->Transform.ClipPlanesEnabled & (1 << (atom->idx))) )
276 TCL_OR_VP_CHECK( tcl_or_vp, GL_TRUE )
277 VP_CHECK( tcl_vp, GL_TRUE )
278 VP_CHECK( tcl_vp_size, ctx->VertexProgram.Current->Base.NumNativeInstructions > 64 )
279 VP_CHECK( tcl_vpp_size, ctx->VertexProgram.Current->Base.NumNativeParameters > 96 )
280
281 #define OUT_VEC(hdr, data) do { \
282 drm_radeon_cmd_header_t h; \
283 h.i = hdr; \
284 OUT_BATCH(CP_PACKET0(RADEON_SE_TCL_STATE_FLUSH, 0)); \
285 OUT_BATCH(0); \
286 OUT_BATCH(CP_PACKET0(R200_SE_TCL_VECTOR_INDX_REG, 0)); \
287 OUT_BATCH(h.vectors.offset | (h.vectors.stride << RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT)); \
288 OUT_BATCH(CP_PACKET0_ONE(R200_SE_TCL_VECTOR_DATA_REG, h.vectors.count - 1)); \
289 OUT_BATCH_TABLE((data), h.vectors.count); \
290 } while(0)
291
292 #define OUT_VECLINEAR(hdr, data) do { \
293 drm_radeon_cmd_header_t h; \
294 uint32_t _start, _sz; \
295 h.i = hdr; \
296 _start = h.veclinear.addr_lo | (h.veclinear.addr_hi << 8); \
297 _sz = h.veclinear.count * 4; \
298 OUT_BATCH(CP_PACKET0(RADEON_SE_TCL_STATE_FLUSH, 0)); \
299 OUT_BATCH(0); \
300 OUT_BATCH(CP_PACKET0(R200_SE_TCL_VECTOR_INDX_REG, 0)); \
301 OUT_BATCH(_start | (1 << RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT)); \
302 OUT_BATCH(CP_PACKET0_ONE(R200_SE_TCL_VECTOR_DATA_REG, _sz - 1)); \
303 OUT_BATCH_TABLE((data), _sz); \
304 } while(0)
305
306 #define OUT_SCL(hdr, data) do { \
307 drm_radeon_cmd_header_t h; \
308 h.i = hdr; \
309 OUT_BATCH(CP_PACKET0(R200_SE_TCL_SCALAR_INDX_REG, 0)); \
310 OUT_BATCH((h.scalars.offset) | (h.scalars.stride << RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT)); \
311 OUT_BATCH(CP_PACKET0_ONE(R200_SE_TCL_SCALAR_DATA_REG, h.scalars.count - 1)); \
312 OUT_BATCH_TABLE((data), h.scalars.count); \
313 } while(0)
314
315 #define OUT_SCL2(hdr, data) do { \
316 drm_radeon_cmd_header_t h; \
317 h.i = hdr; \
318 OUT_BATCH(CP_PACKET0(R200_SE_TCL_SCALAR_INDX_REG, 0)); \
319 OUT_BATCH((h.scalars.offset + 0x100) | (h.scalars.stride << RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT)); \
320 OUT_BATCH(CP_PACKET0_ONE(R200_SE_TCL_SCALAR_DATA_REG, h.scalars.count - 1)); \
321 OUT_BATCH_TABLE((data), h.scalars.count); \
322 } while(0)
323
324 static void mtl_emit(GLcontext *ctx, struct radeon_state_atom *atom)
325 {
326 r200ContextPtr r200 = R200_CONTEXT(ctx);
327 BATCH_LOCALS(&r200->radeon);
328 uint32_t dwords = atom->cmd_size;
329
330 dwords += 6;
331 BEGIN_BATCH_NO_AUTOSTATE(dwords);
332 OUT_VEC(atom->cmd[MTL_CMD_0], (atom->cmd+1));
333 OUT_SCL2(atom->cmd[MTL_CMD_1], (atom->cmd + 18));
334 END_BATCH();
335 }
336
337 static void lit_emit(GLcontext *ctx, struct radeon_state_atom *atom)
338 {
339 r200ContextPtr r200 = R200_CONTEXT(ctx);
340 BATCH_LOCALS(&r200->radeon);
341 uint32_t dwords = atom->cmd_size;
342
343 dwords += 8;
344 BEGIN_BATCH_NO_AUTOSTATE(dwords);
345 OUT_VEC(atom->cmd[LIT_CMD_0], atom->cmd+1);
346 OUT_VEC(atom->cmd[LIT_CMD_1], atom->cmd+LIT_CMD_1+1);
347 END_BATCH();
348 }
349
350 static void ptp_emit(GLcontext *ctx, struct radeon_state_atom *atom)
351 {
352 r200ContextPtr r200 = R200_CONTEXT(ctx);
353 BATCH_LOCALS(&r200->radeon);
354 uint32_t dwords = atom->cmd_size;
355
356 dwords += 8;
357 BEGIN_BATCH_NO_AUTOSTATE(dwords);
358 OUT_VEC(atom->cmd[PTP_CMD_0], atom->cmd+1);
359 OUT_VEC(atom->cmd[PTP_CMD_1], atom->cmd+PTP_CMD_1+1);
360 END_BATCH();
361 }
362
363 static void veclinear_emit(GLcontext *ctx, struct radeon_state_atom *atom)
364 {
365 r200ContextPtr r200 = R200_CONTEXT(ctx);
366 BATCH_LOCALS(&r200->radeon);
367 uint32_t dwords = atom->cmd_size;
368
369 dwords += 4;
370 BEGIN_BATCH_NO_AUTOSTATE(dwords);
371 OUT_VECLINEAR(atom->cmd[0], atom->cmd+1);
372 END_BATCH();
373 }
374
375 static void scl_emit(GLcontext *ctx, struct radeon_state_atom *atom)
376 {
377 r200ContextPtr r200 = R200_CONTEXT(ctx);
378 BATCH_LOCALS(&r200->radeon);
379 uint32_t dwords = atom->cmd_size;
380
381 dwords += 2;
382 BEGIN_BATCH_NO_AUTOSTATE(dwords);
383 OUT_SCL(atom->cmd[0], atom->cmd+1);
384 END_BATCH();
385 }
386
387
388 static void vec_emit(GLcontext *ctx, struct radeon_state_atom *atom)
389 {
390 r200ContextPtr r200 = R200_CONTEXT(ctx);
391 BATCH_LOCALS(&r200->radeon);
392 uint32_t dwords = atom->cmd_size;
393
394 dwords += 4;
395 BEGIN_BATCH_NO_AUTOSTATE(dwords);
396 OUT_VEC(atom->cmd[0], atom->cmd+1);
397 END_BATCH();
398 }
399
400 static void ctx_emit(GLcontext *ctx, struct radeon_state_atom *atom)
401 {
402 r200ContextPtr r200 = R200_CONTEXT(ctx);
403 BATCH_LOCALS(&r200->radeon);
404 struct radeon_renderbuffer *rrb;
405 uint32_t cbpitch;
406 uint32_t zbpitch, depth_fmt;
407 uint32_t dwords = atom->cmd_size;
408
409 /* output the first 7 bytes of context */
410 BEGIN_BATCH_NO_AUTOSTATE(dwords+2+2);
411 OUT_BATCH_TABLE(atom->cmd, 5);
412
413 rrb = radeon_get_depthbuffer(&r200->radeon);
414 if (!rrb) {
415 OUT_BATCH(0);
416 OUT_BATCH(0);
417 } else {
418 zbpitch = (rrb->pitch / rrb->cpp);
419 if (r200->using_hyperz)
420 zbpitch |= RADEON_DEPTH_HYPERZ;
421 OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
422 OUT_BATCH(zbpitch);
423 if (rrb->cpp == 4)
424 depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
425 else
426 depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
427 atom->cmd[CTX_RB3D_ZSTENCILCNTL] &= ~RADEON_DEPTH_FORMAT_MASK;
428 atom->cmd[CTX_RB3D_ZSTENCILCNTL] |= depth_fmt;
429 }
430
431 OUT_BATCH(atom->cmd[CTX_RB3D_ZSTENCILCNTL]);
432 OUT_BATCH(atom->cmd[CTX_CMD_1]);
433 OUT_BATCH(atom->cmd[CTX_PP_CNTL]);
434
435 rrb = radeon_get_colorbuffer(&r200->radeon);
436 if (!rrb || !rrb->bo) {
437 OUT_BATCH(atom->cmd[CTX_RB3D_CNTL]);
438 OUT_BATCH(atom->cmd[CTX_RB3D_COLOROFFSET]);
439 } else {
440 atom->cmd[CTX_RB3D_CNTL] &= ~(0xf << 10);
441 if (rrb->cpp == 4)
442 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB8888;
443 else
444 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_RGB565;
445
446 OUT_BATCH(atom->cmd[CTX_RB3D_CNTL]);
447 OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
448 }
449
450 OUT_BATCH(atom->cmd[CTX_CMD_2]);
451
452 if (!rrb || !rrb->bo) {
453 OUT_BATCH(atom->cmd[CTX_RB3D_COLORPITCH]);
454 } else {
455 cbpitch = (rrb->pitch / rrb->cpp);
456 if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE)
457 cbpitch |= R200_COLOR_TILE_ENABLE;
458 OUT_BATCH(cbpitch);
459 }
460
461 if (atom->cmd_size == CTX_STATE_SIZE_NEWDRM)
462 OUT_BATCH_TABLE((atom->cmd + 14), 4);
463
464 END_BATCH();
465 }
466
467 static void ctx_emit_cs(GLcontext *ctx, struct radeon_state_atom *atom)
468 {
469 r200ContextPtr r200 = R200_CONTEXT(ctx);
470 BATCH_LOCALS(&r200->radeon);
471 struct radeon_renderbuffer *rrb, *drb;
472 uint32_t cbpitch = 0;
473 uint32_t zbpitch = 0;
474 uint32_t dwords = atom->cmd_size;
475 uint32_t depth_fmt;
476
477 rrb = radeon_get_colorbuffer(&r200->radeon);
478 if (!rrb || !rrb->bo) {
479 return;
480 }
481
482 atom->cmd[CTX_RB3D_CNTL] &= ~(0xf << 10);
483 if (rrb->cpp == 4)
484 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB8888;
485 else
486 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_RGB565;
487
488 cbpitch = (rrb->pitch / rrb->cpp);
489 if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE)
490 cbpitch |= R200_COLOR_TILE_ENABLE;
491
492 drb = radeon_get_depthbuffer(&r200->radeon);
493 if (drb) {
494 zbpitch = (drb->pitch / drb->cpp);
495 if (drb->cpp == 4)
496 depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
497 else
498 depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
499 atom->cmd[CTX_RB3D_ZSTENCILCNTL] &= ~RADEON_DEPTH_FORMAT_MASK;
500 atom->cmd[CTX_RB3D_ZSTENCILCNTL] |= depth_fmt;
501 }
502
503 dwords = 10;
504 if (drb)
505 dwords += 6;
506 if (rrb)
507 dwords += 6;
508 if (atom->cmd_size == CTX_STATE_SIZE_NEWDRM)
509 dwords += 4;
510
511 /* output the first 7 bytes of context */
512 BEGIN_BATCH_NO_AUTOSTATE(dwords);
513
514 /* In the CS case we need to split this up */
515 OUT_BATCH(CP_PACKET0(packet[0].start, 3));
516 OUT_BATCH_TABLE((atom->cmd + 1), 4);
517
518 if (drb) {
519 OUT_BATCH(CP_PACKET0(RADEON_RB3D_DEPTHOFFSET, 0));
520 OUT_BATCH_RELOC(0, drb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
521
522 OUT_BATCH(CP_PACKET0(RADEON_RB3D_DEPTHPITCH, 0));
523 OUT_BATCH(zbpitch);
524 }
525
526 OUT_BATCH(CP_PACKET0(RADEON_RB3D_ZSTENCILCNTL, 0));
527 OUT_BATCH(atom->cmd[CTX_RB3D_ZSTENCILCNTL]);
528 OUT_BATCH(CP_PACKET0(RADEON_PP_CNTL, 1));
529 OUT_BATCH(atom->cmd[CTX_PP_CNTL]);
530 OUT_BATCH(atom->cmd[CTX_RB3D_CNTL]);
531
532
533 if (rrb) {
534 OUT_BATCH(CP_PACKET0(RADEON_RB3D_COLOROFFSET, 0));
535 OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
536
537 OUT_BATCH(CP_PACKET0(RADEON_RB3D_COLORPITCH, 0));
538 OUT_BATCH(cbpitch);
539 }
540
541 if (atom->cmd_size == CTX_STATE_SIZE_NEWDRM) {
542 OUT_BATCH_TABLE((atom->cmd + 14), 4);
543 }
544
545 END_BATCH();
546 }
547
548 static void tex_emit(GLcontext *ctx, struct radeon_state_atom *atom)
549 {
550 r200ContextPtr r200 = R200_CONTEXT(ctx);
551 BATCH_LOCALS(&r200->radeon);
552 uint32_t dwords = atom->cmd_size;
553 int i = atom->idx;
554 radeonTexObj *t = r200->state.texture.unit[i].texobj;
555 radeon_mipmap_level *lvl;
556
557 if (t && t->mt && !t->image_override)
558 dwords += 2;
559 BEGIN_BATCH_NO_AUTOSTATE(dwords);
560 OUT_BATCH_TABLE(atom->cmd, 10);
561
562 if (t && t->mt && !t->image_override) {
563 if ((ctx->Texture.Unit[i]._ReallyEnabled & TEXTURE_CUBE_BIT)) {
564 lvl = &t->mt->levels[0];
565 OUT_BATCH_RELOC(lvl->faces[5].offset, t->mt->bo, lvl->faces[5].offset,
566 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
567 } else {
568 OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, 0,
569 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
570 }
571 } else if (!t) {
572 /* workaround for old CS mechanism */
573 OUT_BATCH(r200->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP]);
574 } else {
575 OUT_BATCH(t->override_offset);
576 }
577
578 END_BATCH();
579 }
580
581 static void tex_emit_cs(GLcontext *ctx, struct radeon_state_atom *atom)
582 {
583 r200ContextPtr r200 = R200_CONTEXT(ctx);
584 BATCH_LOCALS(&r200->radeon);
585 uint32_t dwords = atom->cmd_size;
586 int i = atom->idx;
587 radeonTexObj *t = r200->state.texture.unit[i].texobj;
588 radeon_mipmap_level *lvl;
589 int hastexture = 1;
590
591 if (!t)
592 hastexture = 0;
593 else {
594 if (!t->mt && !t->bo)
595 hastexture = 0;
596 }
597
598 if (hastexture)
599 dwords += 2;
600 else
601 dwords -= 2;
602 BEGIN_BATCH_NO_AUTOSTATE(dwords);
603
604 OUT_BATCH(CP_PACKET0(R200_PP_TXFILTER_0 + (24 * i), 7));
605 OUT_BATCH_TABLE((atom->cmd + 1), 8);
606
607 if (hastexture) {
608 OUT_BATCH(CP_PACKET0(R200_PP_TXOFFSET_0 + (24 * i), 0));
609 if (t->mt && !t->image_override) {
610 if ((ctx->Texture.Unit[i]._ReallyEnabled & TEXTURE_CUBE_BIT)) {
611 lvl = &t->mt->levels[0];
612 OUT_BATCH_RELOC(lvl->faces[5].offset, t->mt->bo, lvl->faces[5].offset,
613 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
614 } else {
615 OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, 0,
616 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
617 }
618 } else {
619 if (t->bo)
620 OUT_BATCH_RELOC(t->tile_bits, t->bo, 0,
621 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
622 }
623 }
624 END_BATCH();
625 }
626
627
628 static void cube_emit(GLcontext *ctx, struct radeon_state_atom *atom)
629 {
630 r200ContextPtr r200 = R200_CONTEXT(ctx);
631 BATCH_LOCALS(&r200->radeon);
632 uint32_t dwords = atom->cmd_size;
633 int i = atom->idx;
634 radeonTexObj *t = r200->state.texture.unit[i].texobj;
635 GLuint size;
636
637 BEGIN_BATCH_NO_AUTOSTATE(dwords + (2 * 5));
638 OUT_BATCH_TABLE(atom->cmd, 3);
639
640 if (t && !t->image_override) {
641 size = t->mt->totalsize / 6;
642 OUT_BATCH_RELOC(0, t->mt->bo, size, RADEON_GEM_DOMAIN_VRAM, 0, 0);
643 OUT_BATCH_RELOC(0, t->mt->bo, size * 2, RADEON_GEM_DOMAIN_VRAM, 0, 0);
644 OUT_BATCH_RELOC(0, t->mt->bo, size * 3, RADEON_GEM_DOMAIN_VRAM, 0, 0);
645 OUT_BATCH_RELOC(0, t->mt->bo, size * 4, RADEON_GEM_DOMAIN_VRAM, 0, 0);
646 OUT_BATCH_RELOC(0, t->mt->bo, size * 5, RADEON_GEM_DOMAIN_VRAM, 0, 0);
647 }
648 END_BATCH();
649 }
650
651 /* Initialize the context's hardware state.
652 */
653 void r200InitState( r200ContextPtr rmesa )
654 {
655 GLcontext *ctx = rmesa->radeon.glCtx;
656 GLuint i;
657
658 rmesa->radeon.state.color.clear = 0x00000000;
659
660 switch ( ctx->Visual.depthBits ) {
661 case 16:
662 rmesa->radeon.state.depth.clear = 0x0000ffff;
663 rmesa->radeon.state.stencil.clear = 0x00000000;
664 break;
665 case 24:
666 default:
667 rmesa->radeon.state.depth.clear = 0x00ffffff;
668 rmesa->radeon.state.stencil.clear = 0xffff0000;
669 break;
670 }
671
672 rmesa->radeon.Fallback = 0;
673
674 rmesa->radeon.hw.max_state_size = 0;
675
676 #define ALLOC_STATE( ATOM, CHK, SZ, NM, IDX ) \
677 do { \
678 rmesa->hw.ATOM.cmd_size = SZ; \
679 rmesa->hw.ATOM.cmd = (GLuint *)CALLOC(SZ * sizeof(int)); \
680 rmesa->hw.ATOM.lastcmd = (GLuint *)CALLOC(SZ * sizeof(int)); \
681 rmesa->hw.ATOM.name = NM; \
682 rmesa->hw.ATOM.idx = IDX; \
683 rmesa->hw.ATOM.check = check_##CHK; \
684 rmesa->hw.ATOM.dirty = GL_FALSE; \
685 rmesa->radeon.hw.max_state_size += SZ * sizeof(int); \
686 } while (0)
687
688
689 /* Allocate state buffers:
690 */
691 if (rmesa->radeon.radeonScreen->drmSupportsBlendColor)
692 ALLOC_STATE( ctx, always, CTX_STATE_SIZE_NEWDRM, "CTX/context", 0 );
693 else
694 ALLOC_STATE( ctx, always, CTX_STATE_SIZE_OLDDRM, "CTX/context", 0 );
695
696 if (rmesa->radeon.radeonScreen->kernel_mm)
697 rmesa->hw.ctx.emit = ctx_emit_cs;
698 else
699 rmesa->hw.ctx.emit = ctx_emit;
700 ALLOC_STATE( set, always, SET_STATE_SIZE, "SET/setup", 0 );
701 ALLOC_STATE( lin, always, LIN_STATE_SIZE, "LIN/line", 0 );
702 ALLOC_STATE( msk, always, MSK_STATE_SIZE, "MSK/mask", 0 );
703 ALLOC_STATE( vpt, always, VPT_STATE_SIZE, "VPT/viewport", 0 );
704 ALLOC_STATE( vtx, always, VTX_STATE_SIZE, "VTX/vertex", 0 );
705 ALLOC_STATE( vap, always, VAP_STATE_SIZE, "VAP/vap", 0 );
706 ALLOC_STATE( vte, always, VTE_STATE_SIZE, "VTE/vte", 0 );
707 ALLOC_STATE( msc, always, MSC_STATE_SIZE, "MSC/misc", 0 );
708 ALLOC_STATE( cst, always, CST_STATE_SIZE, "CST/constant", 0 );
709 ALLOC_STATE( zbs, always, ZBS_STATE_SIZE, "ZBS/zbias", 0 );
710 ALLOC_STATE( tf, tf, TF_STATE_SIZE, "TF/tfactor", 0 );
711 if (rmesa->radeon.radeonScreen->drmSupportsFragShader) {
712 if (rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_R200) {
713 /* make sure texture units 0/1 are emitted pair-wise for r200 t0 hang workaround */
714 ALLOC_STATE( tex[0], tex_pair, TEX_STATE_SIZE_NEWDRM, "TEX/tex-0", 0 );
715 ALLOC_STATE( tex[1], tex_pair, TEX_STATE_SIZE_NEWDRM, "TEX/tex-1", 1 );
716 ALLOC_STATE( tam, tex_any, TAM_STATE_SIZE, "TAM/tam", 0 );
717 }
718 else {
719 ALLOC_STATE( tex[0], tex, TEX_STATE_SIZE_NEWDRM, "TEX/tex-0", 0 );
720 ALLOC_STATE( tex[1], tex, TEX_STATE_SIZE_NEWDRM, "TEX/tex-1", 1 );
721 ALLOC_STATE( tam, never, TAM_STATE_SIZE, "TAM/tam", 0 );
722 }
723 ALLOC_STATE( tex[2], tex, TEX_STATE_SIZE_NEWDRM, "TEX/tex-2", 2 );
724 ALLOC_STATE( tex[3], tex, TEX_STATE_SIZE_NEWDRM, "TEX/tex-3", 3 );
725 ALLOC_STATE( tex[4], tex, TEX_STATE_SIZE_NEWDRM, "TEX/tex-4", 4 );
726 ALLOC_STATE( tex[5], tex, TEX_STATE_SIZE_NEWDRM, "TEX/tex-5", 5 );
727 ALLOC_STATE( atf, afs, ATF_STATE_SIZE, "ATF/tfactor", 0 );
728 ALLOC_STATE( afs[0], afs_pass1, AFS_STATE_SIZE, "AFS/afsinst-0", 0 );
729 ALLOC_STATE( afs[1], afs, AFS_STATE_SIZE, "AFS/afsinst-1", 1 );
730 }
731 else {
732 if (rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_R200) {
733 ALLOC_STATE( tex[0], tex_pair, TEX_STATE_SIZE_OLDDRM, "TEX/tex-0", 0 );
734 ALLOC_STATE( tex[1], tex_pair, TEX_STATE_SIZE_OLDDRM, "TEX/tex-1", 1 );
735 ALLOC_STATE( tam, tex_any, TAM_STATE_SIZE, "TAM/tam", 0 );
736 }
737 else {
738 ALLOC_STATE( tex[0], tex, TEX_STATE_SIZE_OLDDRM, "TEX/tex-0", 0 );
739 ALLOC_STATE( tex[1], tex, TEX_STATE_SIZE_OLDDRM, "TEX/tex-1", 1 );
740 ALLOC_STATE( tam, never, TAM_STATE_SIZE, "TAM/tam", 0 );
741 }
742 ALLOC_STATE( tex[2], tex, TEX_STATE_SIZE_OLDDRM, "TEX/tex-2", 2 );
743 ALLOC_STATE( tex[3], tex, TEX_STATE_SIZE_OLDDRM, "TEX/tex-3", 3 );
744 ALLOC_STATE( tex[4], tex, TEX_STATE_SIZE_OLDDRM, "TEX/tex-4", 4 );
745 ALLOC_STATE( tex[5], tex, TEX_STATE_SIZE_OLDDRM, "TEX/tex-5", 5 );
746 ALLOC_STATE( atf, never, ATF_STATE_SIZE, "TF/tfactor", 0 );
747 ALLOC_STATE( afs[0], never, AFS_STATE_SIZE, "AFS/afsinst-0", 0 );
748 ALLOC_STATE( afs[1], never, AFS_STATE_SIZE, "AFS/afsinst-1", 1 );
749 }
750
751 for (i = 0; i < 5; i++)
752 if (rmesa->radeon.radeonScreen->kernel_mm)
753 rmesa->hw.tex[i].emit = tex_emit_cs;
754 else
755 rmesa->hw.tex[i].emit = tex_emit;
756 if (rmesa->radeon.radeonScreen->drmSupportsCubeMapsR200) {
757 ALLOC_STATE( cube[0], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-0", 0 );
758 ALLOC_STATE( cube[1], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-1", 1 );
759 ALLOC_STATE( cube[2], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-2", 2 );
760 ALLOC_STATE( cube[3], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-3", 3 );
761 ALLOC_STATE( cube[4], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-4", 4 );
762 ALLOC_STATE( cube[5], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-5", 5 );
763 for (i = 0; i < 5; i++)
764 rmesa->hw.cube[i].emit = cube_emit;
765 }
766 else {
767 ALLOC_STATE( cube[0], never, CUBE_STATE_SIZE, "CUBE/tex-0", 0 );
768 ALLOC_STATE( cube[1], never, CUBE_STATE_SIZE, "CUBE/tex-1", 1 );
769 ALLOC_STATE( cube[2], never, CUBE_STATE_SIZE, "CUBE/tex-2", 2 );
770 ALLOC_STATE( cube[3], never, CUBE_STATE_SIZE, "CUBE/tex-3", 3 );
771 ALLOC_STATE( cube[4], never, CUBE_STATE_SIZE, "CUBE/tex-4", 4 );
772 ALLOC_STATE( cube[5], never, CUBE_STATE_SIZE, "CUBE/tex-5", 5 );
773 }
774
775 if (rmesa->radeon.radeonScreen->drmSupportsVertexProgram) {
776 ALLOC_STATE( pvs, tcl_vp, PVS_STATE_SIZE, "PVS/pvscntl", 0 );
777 ALLOC_STATE( vpi[0], tcl_vp, VPI_STATE_SIZE, "VP/vertexprog-0", 0 );
778 ALLOC_STATE( vpi[1], tcl_vp_size, VPI_STATE_SIZE, "VP/vertexprog-1", 1 );
779 ALLOC_STATE( vpp[0], tcl_vp, VPP_STATE_SIZE, "VPP/vertexparam-0", 0 );
780 ALLOC_STATE( vpp[1], tcl_vpp_size, VPP_STATE_SIZE, "VPP/vertexparam-1", 1 );
781 }
782 else {
783 ALLOC_STATE( pvs, never, PVS_STATE_SIZE, "PVS/pvscntl", 0 );
784 ALLOC_STATE( vpi[0], never, VPI_STATE_SIZE, "VP/vertexprog-0", 0 );
785 ALLOC_STATE( vpi[1], never, VPI_STATE_SIZE, "VP/vertexprog-1", 1 );
786 ALLOC_STATE( vpp[0], never, VPP_STATE_SIZE, "VPP/vertexparam-0", 0 );
787 ALLOC_STATE( vpp[1], never, VPP_STATE_SIZE, "VPP/vertexparam-1", 1 );
788 }
789 /* FIXME: this atom has two commands, we need only one (ucp_vert_blend) for vp */
790 ALLOC_STATE( tcl, tcl_or_vp, TCL_STATE_SIZE, "TCL/tcl", 0 );
791 ALLOC_STATE( msl, tcl, MSL_STATE_SIZE, "MSL/matrix-select", 0 );
792 ALLOC_STATE( tcg, tcl, TCG_STATE_SIZE, "TCG/texcoordgen", 0 );
793 ALLOC_STATE( mtl[0], tcl_lighting, MTL_STATE_SIZE, "MTL0/material0", 0 );
794 ALLOC_STATE( mtl[1], tcl_lighting, MTL_STATE_SIZE, "MTL1/material1", 1 );
795 ALLOC_STATE( grd, tcl_or_vp, GRD_STATE_SIZE, "GRD/guard-band", 0 );
796 ALLOC_STATE( fog, tcl_fog, FOG_STATE_SIZE, "FOG/fog", 0 );
797 ALLOC_STATE( glt, tcl_lighting, GLT_STATE_SIZE, "GLT/light-global", 0 );
798 ALLOC_STATE( eye, tcl_lighting, EYE_STATE_SIZE, "EYE/eye-vector", 0 );
799 ALLOC_STATE( mat[R200_MTX_MV], tcl, MAT_STATE_SIZE, "MAT/modelview", 0 );
800 ALLOC_STATE( mat[R200_MTX_IMV], tcl, MAT_STATE_SIZE, "MAT/it-modelview", 0 );
801 ALLOC_STATE( mat[R200_MTX_MVP], tcl, MAT_STATE_SIZE, "MAT/modelproject", 0 );
802 ALLOC_STATE( mat[R200_MTX_TEX0], tcl_tex, MAT_STATE_SIZE, "MAT/texmat0", 0 );
803 ALLOC_STATE( mat[R200_MTX_TEX1], tcl_tex, MAT_STATE_SIZE, "MAT/texmat1", 1 );
804 ALLOC_STATE( mat[R200_MTX_TEX2], tcl_tex, MAT_STATE_SIZE, "MAT/texmat2", 2 );
805 ALLOC_STATE( mat[R200_MTX_TEX3], tcl_tex, MAT_STATE_SIZE, "MAT/texmat3", 3 );
806 ALLOC_STATE( mat[R200_MTX_TEX4], tcl_tex, MAT_STATE_SIZE, "MAT/texmat4", 4 );
807 ALLOC_STATE( mat[R200_MTX_TEX5], tcl_tex, MAT_STATE_SIZE, "MAT/texmat5", 5 );
808 ALLOC_STATE( ucp[0], tcl_ucp, UCP_STATE_SIZE, "UCP/userclip-0", 0 );
809 ALLOC_STATE( ucp[1], tcl_ucp, UCP_STATE_SIZE, "UCP/userclip-1", 1 );
810 ALLOC_STATE( ucp[2], tcl_ucp, UCP_STATE_SIZE, "UCP/userclip-2", 2 );
811 ALLOC_STATE( ucp[3], tcl_ucp, UCP_STATE_SIZE, "UCP/userclip-3", 3 );
812 ALLOC_STATE( ucp[4], tcl_ucp, UCP_STATE_SIZE, "UCP/userclip-4", 4 );
813 ALLOC_STATE( ucp[5], tcl_ucp, UCP_STATE_SIZE, "UCP/userclip-5", 5 );
814 ALLOC_STATE( lit[0], tcl_light, LIT_STATE_SIZE, "LIT/light-0", 0 );
815 ALLOC_STATE( lit[1], tcl_light, LIT_STATE_SIZE, "LIT/light-1", 1 );
816 ALLOC_STATE( lit[2], tcl_light, LIT_STATE_SIZE, "LIT/light-2", 2 );
817 ALLOC_STATE( lit[3], tcl_light, LIT_STATE_SIZE, "LIT/light-3", 3 );
818 ALLOC_STATE( lit[4], tcl_light, LIT_STATE_SIZE, "LIT/light-4", 4 );
819 ALLOC_STATE( lit[5], tcl_light, LIT_STATE_SIZE, "LIT/light-5", 5 );
820 ALLOC_STATE( lit[6], tcl_light, LIT_STATE_SIZE, "LIT/light-6", 6 );
821 ALLOC_STATE( lit[7], tcl_light, LIT_STATE_SIZE, "LIT/light-7", 7 );
822 ALLOC_STATE( pix[0], pix_zero, PIX_STATE_SIZE, "PIX/pixstage-0", 0 );
823 ALLOC_STATE( pix[1], texenv, PIX_STATE_SIZE, "PIX/pixstage-1", 1 );
824 ALLOC_STATE( pix[2], texenv, PIX_STATE_SIZE, "PIX/pixstage-2", 2 );
825 ALLOC_STATE( pix[3], texenv, PIX_STATE_SIZE, "PIX/pixstage-3", 3 );
826 ALLOC_STATE( pix[4], texenv, PIX_STATE_SIZE, "PIX/pixstage-4", 4 );
827 ALLOC_STATE( pix[5], texenv, PIX_STATE_SIZE, "PIX/pixstage-5", 5 );
828 if (rmesa->radeon.radeonScreen->drmSupportsTriPerf) {
829 ALLOC_STATE( prf, always, PRF_STATE_SIZE, "PRF/performance-tri", 0 );
830 }
831 else {
832 ALLOC_STATE( prf, never, PRF_STATE_SIZE, "PRF/performance-tri", 0 );
833 }
834 if (rmesa->radeon.radeonScreen->drmSupportsPointSprites) {
835 ALLOC_STATE( spr, always, SPR_STATE_SIZE, "SPR/pointsprite", 0 );
836 ALLOC_STATE( ptp, tcl, PTP_STATE_SIZE, "PTP/pointparams", 0 );
837 }
838 else {
839 ALLOC_STATE (spr, never, SPR_STATE_SIZE, "SPR/pointsprite", 0 );
840 ALLOC_STATE (ptp, never, PTP_STATE_SIZE, "PTP/pointparams", 0 );
841 }
842
843 r200SetUpAtomList( rmesa );
844
845 /* Fill in the packet headers:
846 */
847 rmesa->hw.ctx.cmd[CTX_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_MISC);
848 rmesa->hw.ctx.cmd[CTX_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_PP_CNTL);
849 rmesa->hw.ctx.cmd[CTX_CMD_2] = cmdpkt(rmesa, RADEON_EMIT_RB3D_COLORPITCH);
850 if (rmesa->radeon.radeonScreen->drmSupportsBlendColor)
851 rmesa->hw.ctx.cmd[CTX_CMD_3] = cmdpkt(rmesa, R200_EMIT_RB3D_BLENDCOLOR);
852 rmesa->hw.lin.cmd[LIN_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_RE_LINE_PATTERN);
853 rmesa->hw.lin.cmd[LIN_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_SE_LINE_WIDTH);
854 rmesa->hw.msk.cmd[MSK_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_RB3D_STENCILREFMASK);
855 rmesa->hw.vpt.cmd[VPT_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_SE_VPORT_XSCALE);
856 rmesa->hw.set.cmd[SET_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_SE_CNTL);
857 rmesa->hw.msc.cmd[MSC_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_RE_MISC);
858 rmesa->hw.cst.cmd[CST_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_CNTL_X);
859 rmesa->hw.cst.cmd[CST_CMD_1] = cmdpkt(rmesa, R200_EMIT_RB3D_DEPTHXY_OFFSET);
860 rmesa->hw.cst.cmd[CST_CMD_2] = cmdpkt(rmesa, R200_EMIT_RE_AUX_SCISSOR_CNTL);
861 rmesa->hw.cst.cmd[CST_CMD_3] = cmdpkt(rmesa, R200_EMIT_RE_SCISSOR_TL_0);
862 rmesa->hw.cst.cmd[CST_CMD_4] = cmdpkt(rmesa, R200_EMIT_SE_VAP_CNTL_STATUS);
863 rmesa->hw.cst.cmd[CST_CMD_5] = cmdpkt(rmesa, R200_EMIT_RE_POINTSIZE);
864 rmesa->hw.cst.cmd[CST_CMD_6] = cmdpkt(rmesa, R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0);
865 rmesa->hw.tam.cmd[TAM_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TAM_DEBUG3);
866 rmesa->hw.tf.cmd[TF_CMD_0] = cmdpkt(rmesa, R200_EMIT_TFACTOR_0);
867 if (rmesa->radeon.radeonScreen->drmSupportsFragShader) {
868 rmesa->hw.atf.cmd[ATF_CMD_0] = cmdpkt(rmesa, R200_EMIT_ATF_TFACTOR);
869 rmesa->hw.tex[0].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCTLALL_0);
870 rmesa->hw.tex[0].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_0);
871 rmesa->hw.tex[1].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCTLALL_1);
872 rmesa->hw.tex[1].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_1);
873 rmesa->hw.tex[2].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCTLALL_2);
874 rmesa->hw.tex[2].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_2);
875 rmesa->hw.tex[3].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCTLALL_3);
876 rmesa->hw.tex[3].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_3);
877 rmesa->hw.tex[4].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCTLALL_4);
878 rmesa->hw.tex[4].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_4);
879 rmesa->hw.tex[5].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCTLALL_5);
880 rmesa->hw.tex[5].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_5);
881 } else {
882 rmesa->hw.tex[0].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXFILTER_0);
883 rmesa->hw.tex[0].cmd[TEX_CMD_1_OLDDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_0);
884 rmesa->hw.tex[1].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXFILTER_1);
885 rmesa->hw.tex[1].cmd[TEX_CMD_1_OLDDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_1);
886 rmesa->hw.tex[2].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXFILTER_2);
887 rmesa->hw.tex[2].cmd[TEX_CMD_1_OLDDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_2);
888 rmesa->hw.tex[3].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXFILTER_3);
889 rmesa->hw.tex[3].cmd[TEX_CMD_1_OLDDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_3);
890 rmesa->hw.tex[4].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXFILTER_4);
891 rmesa->hw.tex[4].cmd[TEX_CMD_1_OLDDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_4);
892 rmesa->hw.tex[5].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXFILTER_5);
893 rmesa->hw.tex[5].cmd[TEX_CMD_1_OLDDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_5);
894 }
895 rmesa->hw.afs[0].cmd[AFS_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_AFS_0);
896 rmesa->hw.afs[1].cmd[AFS_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_AFS_1);
897 rmesa->hw.pvs.cmd[PVS_CMD_0] = cmdpkt(rmesa, R200_EMIT_VAP_PVS_CNTL);
898 rmesa->hw.cube[0].cmd[CUBE_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_FACES_0);
899 rmesa->hw.cube[0].cmd[CUBE_CMD_1] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_OFFSETS_0);
900 rmesa->hw.cube[1].cmd[CUBE_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_FACES_1);
901 rmesa->hw.cube[1].cmd[CUBE_CMD_1] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_OFFSETS_1);
902 rmesa->hw.cube[2].cmd[CUBE_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_FACES_2);
903 rmesa->hw.cube[2].cmd[CUBE_CMD_1] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_OFFSETS_2);
904 rmesa->hw.cube[3].cmd[CUBE_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_FACES_3);
905 rmesa->hw.cube[3].cmd[CUBE_CMD_1] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_OFFSETS_3);
906 rmesa->hw.cube[4].cmd[CUBE_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_FACES_4);
907 rmesa->hw.cube[4].cmd[CUBE_CMD_1] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_OFFSETS_4);
908 rmesa->hw.cube[5].cmd[CUBE_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_FACES_5);
909 rmesa->hw.cube[5].cmd[CUBE_CMD_1] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_OFFSETS_5);
910 rmesa->hw.pix[0].cmd[PIX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCBLEND_0);
911 rmesa->hw.pix[1].cmd[PIX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCBLEND_1);
912 rmesa->hw.pix[2].cmd[PIX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCBLEND_2);
913 rmesa->hw.pix[3].cmd[PIX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCBLEND_3);
914 rmesa->hw.pix[4].cmd[PIX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCBLEND_4);
915 rmesa->hw.pix[5].cmd[PIX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCBLEND_5);
916 rmesa->hw.zbs.cmd[ZBS_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_SE_ZBIAS_FACTOR);
917 rmesa->hw.tcl.cmd[TCL_CMD_0] = cmdpkt(rmesa, R200_EMIT_TCL_LIGHT_MODEL_CTL_0);
918 rmesa->hw.tcl.cmd[TCL_CMD_1] = cmdpkt(rmesa, R200_EMIT_TCL_UCP_VERT_BLEND_CTL);
919 rmesa->hw.tcg.cmd[TCG_CMD_0] = cmdpkt(rmesa, R200_EMIT_TEX_PROC_CTL_2);
920 rmesa->hw.msl.cmd[MSL_CMD_0] = cmdpkt(rmesa, R200_EMIT_MATRIX_SELECT_0);
921 rmesa->hw.vap.cmd[VAP_CMD_0] = cmdpkt(rmesa, R200_EMIT_VAP_CTL);
922 rmesa->hw.vtx.cmd[VTX_CMD_0] = cmdpkt(rmesa, R200_EMIT_VTX_FMT_0);
923 rmesa->hw.vtx.cmd[VTX_CMD_1] = cmdpkt(rmesa, R200_EMIT_OUTPUT_VTX_COMP_SEL);
924 rmesa->hw.vtx.cmd[VTX_CMD_2] = cmdpkt(rmesa, R200_EMIT_SE_VTX_STATE_CNTL);
925 rmesa->hw.vte.cmd[VTE_CMD_0] = cmdpkt(rmesa, R200_EMIT_VTE_CNTL);
926 rmesa->hw.prf.cmd[PRF_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TRI_PERF_CNTL);
927 rmesa->hw.spr.cmd[SPR_CMD_0] = cmdpkt(rmesa, R200_EMIT_TCL_POINT_SPRITE_CNTL);
928 if (rmesa->radeon.radeonScreen->kernel_mm) {
929 rmesa->hw.mtl[0].emit = mtl_emit;
930 rmesa->hw.mtl[1].emit = mtl_emit;
931
932 rmesa->hw.vpi[0].emit = veclinear_emit;
933 rmesa->hw.vpi[1].emit = veclinear_emit;
934 rmesa->hw.vpp[0].emit = veclinear_emit;
935 rmesa->hw.vpp[1].emit = veclinear_emit;
936
937 rmesa->hw.grd.emit = scl_emit;
938 rmesa->hw.fog.emit = vec_emit;
939 rmesa->hw.glt.emit = vec_emit;
940 rmesa->hw.eye.emit = vec_emit;
941
942 for (i = R200_MTX_MV; i <= R200_MTX_TEX5; i++)
943 rmesa->hw.mat[i].emit = vec_emit;
944
945 for (i = 0; i < 8; i++)
946 rmesa->hw.lit[i].emit = lit_emit;
947
948 for (i = 0; i < 6; i++)
949 rmesa->hw.ucp[i].emit = vec_emit;
950
951 rmesa->hw.ptp.emit = ptp_emit;
952 }
953
954
955
956 rmesa->hw.mtl[0].cmd[MTL_CMD_0] =
957 cmdvec( R200_VS_MAT_0_EMISS, 1, 16 );
958 rmesa->hw.mtl[0].cmd[MTL_CMD_1] =
959 cmdscl2( R200_SS_MAT_0_SHININESS, 1, 1 );
960 rmesa->hw.mtl[1].cmd[MTL_CMD_0] =
961 cmdvec( R200_VS_MAT_1_EMISS, 1, 16 );
962 rmesa->hw.mtl[1].cmd[MTL_CMD_1] =
963 cmdscl2( R200_SS_MAT_1_SHININESS, 1, 1 );
964
965 rmesa->hw.vpi[0].cmd[VPI_CMD_0] =
966 cmdveclinear( R200_PVS_PROG0, 64 );
967 rmesa->hw.vpi[1].cmd[VPI_CMD_0] =
968 cmdveclinear( R200_PVS_PROG1, 64 );
969 rmesa->hw.vpp[0].cmd[VPP_CMD_0] =
970 cmdveclinear( R200_PVS_PARAM0, 96 );
971 rmesa->hw.vpp[1].cmd[VPP_CMD_0] =
972 cmdveclinear( R200_PVS_PARAM1, 96 );
973
974 rmesa->hw.grd.cmd[GRD_CMD_0] =
975 cmdscl( R200_SS_VERT_GUARD_CLIP_ADJ_ADDR, 1, 4 );
976 rmesa->hw.fog.cmd[FOG_CMD_0] =
977 cmdvec( R200_VS_FOG_PARAM_ADDR, 1, 4 );
978 rmesa->hw.glt.cmd[GLT_CMD_0] =
979 cmdvec( R200_VS_GLOBAL_AMBIENT_ADDR, 1, 4 );
980 rmesa->hw.eye.cmd[EYE_CMD_0] =
981 cmdvec( R200_VS_EYE_VECTOR_ADDR, 1, 4 );
982
983 rmesa->hw.mat[R200_MTX_MV].cmd[MAT_CMD_0] =
984 cmdvec( R200_VS_MATRIX_0_MV, 1, 16);
985 rmesa->hw.mat[R200_MTX_IMV].cmd[MAT_CMD_0] =
986 cmdvec( R200_VS_MATRIX_1_INV_MV, 1, 16);
987 rmesa->hw.mat[R200_MTX_MVP].cmd[MAT_CMD_0] =
988 cmdvec( R200_VS_MATRIX_2_MVP, 1, 16);
989 rmesa->hw.mat[R200_MTX_TEX0].cmd[MAT_CMD_0] =
990 cmdvec( R200_VS_MATRIX_3_TEX0, 1, 16);
991 rmesa->hw.mat[R200_MTX_TEX1].cmd[MAT_CMD_0] =
992 cmdvec( R200_VS_MATRIX_4_TEX1, 1, 16);
993 rmesa->hw.mat[R200_MTX_TEX2].cmd[MAT_CMD_0] =
994 cmdvec( R200_VS_MATRIX_5_TEX2, 1, 16);
995 rmesa->hw.mat[R200_MTX_TEX3].cmd[MAT_CMD_0] =
996 cmdvec( R200_VS_MATRIX_6_TEX3, 1, 16);
997 rmesa->hw.mat[R200_MTX_TEX4].cmd[MAT_CMD_0] =
998 cmdvec( R200_VS_MATRIX_7_TEX4, 1, 16);
999 rmesa->hw.mat[R200_MTX_TEX5].cmd[MAT_CMD_0] =
1000 cmdvec( R200_VS_MATRIX_8_TEX5, 1, 16);
1001
1002 for (i = 0 ; i < 8; i++) {
1003 rmesa->hw.lit[i].cmd[LIT_CMD_0] =
1004 cmdvec( R200_VS_LIGHT_AMBIENT_ADDR + i, 8, 24 );
1005 rmesa->hw.lit[i].cmd[LIT_CMD_1] =
1006 cmdscl( R200_SS_LIGHT_DCD_ADDR + i, 8, 7 );
1007 }
1008
1009 for (i = 0 ; i < 6; i++) {
1010 rmesa->hw.ucp[i].cmd[UCP_CMD_0] =
1011 cmdvec( R200_VS_UCP_ADDR + i, 1, 4 );
1012 }
1013
1014 rmesa->hw.ptp.cmd[PTP_CMD_0] =
1015 cmdvec( R200_VS_PNT_SPRITE_VPORT_SCALE, 1, 4 );
1016 rmesa->hw.ptp.cmd[PTP_CMD_1] =
1017 cmdvec( R200_VS_PNT_SPRITE_ATT_CONST, 1, 12 );
1018
1019 /* Initial Harware state:
1020 */
1021 rmesa->hw.ctx.cmd[CTX_PP_MISC] = (R200_ALPHA_TEST_PASS
1022 /* | R200_RIGHT_HAND_CUBE_OGL*/);
1023
1024 rmesa->hw.ctx.cmd[CTX_PP_FOG_COLOR] = (R200_FOG_VERTEX |
1025 R200_FOG_USE_SPEC_ALPHA);
1026
1027 rmesa->hw.ctx.cmd[CTX_RE_SOLID_COLOR] = 0x00000000;
1028
1029 rmesa->hw.ctx.cmd[CTX_RB3D_BLENDCNTL] = (R200_COMB_FCN_ADD_CLAMP |
1030 (R200_BLEND_GL_ONE << R200_SRC_BLEND_SHIFT) |
1031 (R200_BLEND_GL_ZERO << R200_DST_BLEND_SHIFT));
1032
1033 if (rmesa->radeon.radeonScreen->drmSupportsBlendColor) {
1034 rmesa->hw.ctx.cmd[CTX_RB3D_BLENDCOLOR] = 0x00000000;
1035 rmesa->hw.ctx.cmd[CTX_RB3D_ABLENDCNTL] = (R200_COMB_FCN_ADD_CLAMP |
1036 (R200_BLEND_GL_ONE << R200_SRC_BLEND_SHIFT) |
1037 (R200_BLEND_GL_ZERO << R200_DST_BLEND_SHIFT));
1038 rmesa->hw.ctx.cmd[CTX_RB3D_CBLENDCNTL] = (R200_COMB_FCN_ADD_CLAMP |
1039 (R200_BLEND_GL_ONE << R200_SRC_BLEND_SHIFT) |
1040 (R200_BLEND_GL_ZERO << R200_DST_BLEND_SHIFT));
1041 }
1042
1043 rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHOFFSET] =
1044 rmesa->radeon.radeonScreen->depthOffset + rmesa->radeon.radeonScreen->fbLocation;
1045
1046 rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHPITCH] =
1047 ((rmesa->radeon.radeonScreen->depthPitch &
1048 R200_DEPTHPITCH_MASK) |
1049 R200_DEPTH_ENDIAN_NO_SWAP);
1050
1051 if (rmesa->using_hyperz)
1052 rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHPITCH] |= R200_DEPTH_HYPERZ;
1053
1054 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] = (R200_Z_TEST_LESS |
1055 R200_STENCIL_TEST_ALWAYS |
1056 R200_STENCIL_FAIL_KEEP |
1057 R200_STENCIL_ZPASS_KEEP |
1058 R200_STENCIL_ZFAIL_KEEP |
1059 R200_Z_WRITE_ENABLE);
1060
1061 if (rmesa->using_hyperz) {
1062 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= R200_Z_COMPRESSION_ENABLE |
1063 R200_Z_DECOMPRESSION_ENABLE;
1064 /* if (rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_R200)
1065 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_HIERARCHY_ENABLE;*/
1066 }
1067
1068 rmesa->hw.ctx.cmd[CTX_PP_CNTL] = (R200_ANTI_ALIAS_NONE
1069 | R200_TEX_BLEND_0_ENABLE);
1070
1071 switch ( driQueryOptioni( &rmesa->radeon.optionCache, "dither_mode" ) ) {
1072 case DRI_CONF_DITHER_XERRORDIFFRESET:
1073 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= R200_DITHER_INIT;
1074 break;
1075 case DRI_CONF_DITHER_ORDERED:
1076 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= R200_SCALE_DITHER_ENABLE;
1077 break;
1078 }
1079 if ( driQueryOptioni( &rmesa->radeon.optionCache, "round_mode" ) ==
1080 DRI_CONF_ROUND_ROUND )
1081 rmesa->radeon.state.color.roundEnable = R200_ROUND_ENABLE;
1082 else
1083 rmesa->radeon.state.color.roundEnable = 0;
1084 if ( driQueryOptioni (&rmesa->radeon.optionCache, "color_reduction" ) ==
1085 DRI_CONF_COLOR_REDUCTION_DITHER )
1086 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= R200_DITHER_ENABLE;
1087 else
1088 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= rmesa->radeon.state.color.roundEnable;
1089
1090 rmesa->hw.prf.cmd[PRF_PP_TRI_PERF] = R200_TRI_CUTOFF_MASK - R200_TRI_CUTOFF_MASK *
1091 driQueryOptionf (&rmesa->radeon.optionCache,"texture_blend_quality");
1092 rmesa->hw.prf.cmd[PRF_PP_PERF_CNTL] = 0;
1093
1094 rmesa->hw.set.cmd[SET_SE_CNTL] = (R200_FFACE_CULL_CCW |
1095 R200_BFACE_SOLID |
1096 R200_FFACE_SOLID |
1097 R200_FLAT_SHADE_VTX_LAST |
1098 R200_DIFFUSE_SHADE_GOURAUD |
1099 R200_ALPHA_SHADE_GOURAUD |
1100 R200_SPECULAR_SHADE_GOURAUD |
1101 R200_FOG_SHADE_GOURAUD |
1102 R200_DISC_FOG_SHADE_GOURAUD |
1103 R200_VTX_PIX_CENTER_OGL |
1104 R200_ROUND_MODE_TRUNC |
1105 R200_ROUND_PREC_8TH_PIX);
1106
1107 rmesa->hw.set.cmd[SET_RE_CNTL] = (R200_PERSPECTIVE_ENABLE |
1108 R200_SCISSOR_ENABLE);
1109
1110 rmesa->hw.lin.cmd[LIN_RE_LINE_PATTERN] = ((1 << 16) | 0xffff);
1111
1112 rmesa->hw.lin.cmd[LIN_RE_LINE_STATE] =
1113 ((0 << R200_LINE_CURRENT_PTR_SHIFT) |
1114 (1 << R200_LINE_CURRENT_COUNT_SHIFT));
1115
1116 rmesa->hw.lin.cmd[LIN_SE_LINE_WIDTH] = (1 << 4);
1117
1118 rmesa->hw.msk.cmd[MSK_RB3D_STENCILREFMASK] =
1119 ((0x00 << R200_STENCIL_REF_SHIFT) |
1120 (0xff << R200_STENCIL_MASK_SHIFT) |
1121 (0xff << R200_STENCIL_WRITEMASK_SHIFT));
1122
1123 rmesa->hw.msk.cmd[MSK_RB3D_ROPCNTL] = R200_ROP_COPY;
1124 rmesa->hw.msk.cmd[MSK_RB3D_PLANEMASK] = 0xffffffff;
1125
1126 rmesa->hw.tam.cmd[TAM_DEBUG3] = 0;
1127
1128 rmesa->hw.msc.cmd[MSC_RE_MISC] =
1129 ((0 << R200_STIPPLE_X_OFFSET_SHIFT) |
1130 (0 << R200_STIPPLE_Y_OFFSET_SHIFT) |
1131 R200_STIPPLE_BIG_BIT_ORDER);
1132
1133
1134 rmesa->hw.cst.cmd[CST_PP_CNTL_X] = 0;
1135 rmesa->hw.cst.cmd[CST_RB3D_DEPTHXY_OFFSET] = 0;
1136 rmesa->hw.cst.cmd[CST_RE_AUX_SCISSOR_CNTL] = 0x0;
1137 rmesa->hw.cst.cmd[CST_RE_SCISSOR_TL_0] = 0;
1138 rmesa->hw.cst.cmd[CST_RE_SCISSOR_BR_0] = 0;
1139 rmesa->hw.cst.cmd[CST_SE_VAP_CNTL_STATUS] =
1140 #ifdef MESA_BIG_ENDIAN
1141 R200_VC_32BIT_SWAP;
1142 #else
1143 R200_VC_NO_SWAP;
1144 #endif
1145
1146 if (!(rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL)) {
1147 /* Bypass TCL */
1148 rmesa->hw.cst.cmd[CST_SE_VAP_CNTL_STATUS] |= (1<<8);
1149 }
1150
1151 rmesa->hw.cst.cmd[CST_RE_POINTSIZE] =
1152 (((GLuint)(ctx->Const.MaxPointSize * 16.0)) << R200_MAXPOINTSIZE_SHIFT) | 0x10;
1153 rmesa->hw.cst.cmd[CST_SE_TCL_INPUT_VTX_0] =
1154 (0x0 << R200_VERTEX_POSITION_ADDR__SHIFT);
1155 rmesa->hw.cst.cmd[CST_SE_TCL_INPUT_VTX_1] =
1156 (0x02 << R200_VTX_COLOR_0_ADDR__SHIFT) |
1157 (0x03 << R200_VTX_COLOR_1_ADDR__SHIFT);
1158 rmesa->hw.cst.cmd[CST_SE_TCL_INPUT_VTX_2] =
1159 (0x06 << R200_VTX_TEX_0_ADDR__SHIFT) |
1160 (0x07 << R200_VTX_TEX_1_ADDR__SHIFT) |
1161 (0x08 << R200_VTX_TEX_2_ADDR__SHIFT) |
1162 (0x09 << R200_VTX_TEX_3_ADDR__SHIFT);
1163 rmesa->hw.cst.cmd[CST_SE_TCL_INPUT_VTX_3] =
1164 (0x0A << R200_VTX_TEX_4_ADDR__SHIFT) |
1165 (0x0B << R200_VTX_TEX_5_ADDR__SHIFT);
1166
1167
1168 rmesa->hw.vpt.cmd[VPT_SE_VPORT_XSCALE] = 0x00000000;
1169 rmesa->hw.vpt.cmd[VPT_SE_VPORT_XOFFSET] = 0x00000000;
1170 rmesa->hw.vpt.cmd[VPT_SE_VPORT_YSCALE] = 0x00000000;
1171 rmesa->hw.vpt.cmd[VPT_SE_VPORT_YOFFSET] = 0x00000000;
1172 rmesa->hw.vpt.cmd[VPT_SE_VPORT_ZSCALE] = 0x00000000;
1173 rmesa->hw.vpt.cmd[VPT_SE_VPORT_ZOFFSET] = 0x00000000;
1174
1175 for ( i = 0 ; i < ctx->Const.MaxTextureUnits ; i++ ) {
1176 rmesa->hw.tex[i].cmd[TEX_PP_TXFILTER] = R200_BORDER_MODE_OGL;
1177 rmesa->hw.tex[i].cmd[TEX_PP_TXFORMAT] =
1178 ((i << R200_TXFORMAT_ST_ROUTE_SHIFT) | /* <-- note i */
1179 (2 << R200_TXFORMAT_WIDTH_SHIFT) |
1180 (2 << R200_TXFORMAT_HEIGHT_SHIFT));
1181 rmesa->hw.tex[i].cmd[TEX_PP_BORDER_COLOR] = 0;
1182 rmesa->hw.tex[i].cmd[TEX_PP_TXFORMAT_X] =
1183 (/* R200_TEXCOORD_PROJ | */
1184 0x100000); /* Small default bias */
1185 if (rmesa->radeon.radeonScreen->drmSupportsFragShader) {
1186 rmesa->hw.tex[i].cmd[TEX_PP_TXOFFSET_NEWDRM] =
1187 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
1188 rmesa->hw.tex[i].cmd[TEX_PP_CUBIC_FACES] = 0;
1189 rmesa->hw.tex[i].cmd[TEX_PP_TXMULTI_CTL] = 0;
1190 }
1191 else {
1192 rmesa->hw.tex[i].cmd[TEX_PP_TXOFFSET_OLDDRM] =
1193 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
1194 }
1195
1196 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_FACES] = 0;
1197 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F1] =
1198 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
1199 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F2] =
1200 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
1201 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F3] =
1202 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
1203 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F4] =
1204 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
1205 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F5] =
1206 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
1207
1208 rmesa->hw.pix[i].cmd[PIX_PP_TXCBLEND] =
1209 (R200_TXC_ARG_A_ZERO |
1210 R200_TXC_ARG_B_ZERO |
1211 R200_TXC_ARG_C_DIFFUSE_COLOR |
1212 R200_TXC_OP_MADD);
1213
1214 rmesa->hw.pix[i].cmd[PIX_PP_TXCBLEND2] =
1215 ((i << R200_TXC_TFACTOR_SEL_SHIFT) |
1216 R200_TXC_SCALE_1X |
1217 R200_TXC_CLAMP_0_1 |
1218 R200_TXC_OUTPUT_REG_R0);
1219
1220 rmesa->hw.pix[i].cmd[PIX_PP_TXABLEND] =
1221 (R200_TXA_ARG_A_ZERO |
1222 R200_TXA_ARG_B_ZERO |
1223 R200_TXA_ARG_C_DIFFUSE_ALPHA |
1224 R200_TXA_OP_MADD);
1225
1226 rmesa->hw.pix[i].cmd[PIX_PP_TXABLEND2] =
1227 ((i << R200_TXA_TFACTOR_SEL_SHIFT) |
1228 R200_TXA_SCALE_1X |
1229 R200_TXA_CLAMP_0_1 |
1230 R200_TXA_OUTPUT_REG_R0);
1231 }
1232
1233 rmesa->hw.tf.cmd[TF_TFACTOR_0] = 0;
1234 rmesa->hw.tf.cmd[TF_TFACTOR_1] = 0;
1235 rmesa->hw.tf.cmd[TF_TFACTOR_2] = 0;
1236 rmesa->hw.tf.cmd[TF_TFACTOR_3] = 0;
1237 rmesa->hw.tf.cmd[TF_TFACTOR_4] = 0;
1238 rmesa->hw.tf.cmd[TF_TFACTOR_5] = 0;
1239
1240 rmesa->hw.vap.cmd[VAP_SE_VAP_CNTL] =
1241 (R200_VAP_TCL_ENABLE |
1242 (0x9 << R200_VAP_VF_MAX_VTX_NUM__SHIFT));
1243
1244 rmesa->hw.vte.cmd[VTE_SE_VTE_CNTL] =
1245 (R200_VPORT_X_SCALE_ENA |
1246 R200_VPORT_Y_SCALE_ENA |
1247 R200_VPORT_Z_SCALE_ENA |
1248 R200_VPORT_X_OFFSET_ENA |
1249 R200_VPORT_Y_OFFSET_ENA |
1250 R200_VPORT_Z_OFFSET_ENA |
1251 /* FIXME: Turn on for tex rect only */
1252 R200_VTX_ST_DENORMALIZED |
1253 R200_VTX_W0_FMT);
1254
1255
1256 rmesa->hw.vtx.cmd[VTX_VTXFMT_0] = 0;
1257 rmesa->hw.vtx.cmd[VTX_VTXFMT_1] = 0;
1258 rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_VTXFMT_0] =
1259 ((R200_VTX_Z0 | R200_VTX_W0 |
1260 (R200_VTX_FP_RGBA << R200_VTX_COLOR_0_SHIFT)));
1261 rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_VTXFMT_1] = 0;
1262 rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_COMPSEL] = (R200_OUTPUT_XYZW);
1263 rmesa->hw.vtx.cmd[VTX_STATE_CNTL] = R200_VSC_UPDATE_USER_COLOR_0_ENABLE;
1264
1265
1266 /* Matrix selection */
1267 rmesa->hw.msl.cmd[MSL_MATRIX_SELECT_0] =
1268 (R200_MTX_MV << R200_MODELVIEW_0_SHIFT);
1269
1270 rmesa->hw.msl.cmd[MSL_MATRIX_SELECT_1] =
1271 (R200_MTX_IMV << R200_IT_MODELVIEW_0_SHIFT);
1272
1273 rmesa->hw.msl.cmd[MSL_MATRIX_SELECT_2] =
1274 (R200_MTX_MVP << R200_MODELPROJECT_0_SHIFT);
1275
1276 rmesa->hw.msl.cmd[MSL_MATRIX_SELECT_3] =
1277 ((R200_MTX_TEX0 << R200_TEXMAT_0_SHIFT) |
1278 (R200_MTX_TEX1 << R200_TEXMAT_1_SHIFT) |
1279 (R200_MTX_TEX2 << R200_TEXMAT_2_SHIFT) |
1280 (R200_MTX_TEX3 << R200_TEXMAT_3_SHIFT));
1281
1282 rmesa->hw.msl.cmd[MSL_MATRIX_SELECT_4] =
1283 ((R200_MTX_TEX4 << R200_TEXMAT_4_SHIFT) |
1284 (R200_MTX_TEX5 << R200_TEXMAT_5_SHIFT));
1285
1286
1287 /* General TCL state */
1288 rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL_0] =
1289 (R200_SPECULAR_LIGHTS |
1290 R200_DIFFUSE_SPECULAR_COMBINE |
1291 R200_LOCAL_LIGHT_VEC_GL |
1292 R200_LM0_SOURCE_MATERIAL_0 << R200_FRONT_SHININESS_SOURCE_SHIFT |
1293 R200_LM0_SOURCE_MATERIAL_1 << R200_BACK_SHININESS_SOURCE_SHIFT);
1294
1295 rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL_1] =
1296 ((R200_LM1_SOURCE_MATERIAL_0 << R200_FRONT_EMISSIVE_SOURCE_SHIFT) |
1297 (R200_LM1_SOURCE_MATERIAL_0 << R200_FRONT_AMBIENT_SOURCE_SHIFT) |
1298 (R200_LM1_SOURCE_MATERIAL_0 << R200_FRONT_DIFFUSE_SOURCE_SHIFT) |
1299 (R200_LM1_SOURCE_MATERIAL_0 << R200_FRONT_SPECULAR_SOURCE_SHIFT) |
1300 (R200_LM1_SOURCE_MATERIAL_1 << R200_BACK_EMISSIVE_SOURCE_SHIFT) |
1301 (R200_LM1_SOURCE_MATERIAL_1 << R200_BACK_AMBIENT_SOURCE_SHIFT) |
1302 (R200_LM1_SOURCE_MATERIAL_1 << R200_BACK_DIFFUSE_SOURCE_SHIFT) |
1303 (R200_LM1_SOURCE_MATERIAL_1 << R200_BACK_SPECULAR_SOURCE_SHIFT));
1304
1305 rmesa->hw.tcl.cmd[TCL_PER_LIGHT_CTL_0] = 0; /* filled in via callbacks */
1306 rmesa->hw.tcl.cmd[TCL_PER_LIGHT_CTL_1] = 0;
1307 rmesa->hw.tcl.cmd[TCL_PER_LIGHT_CTL_2] = 0;
1308 rmesa->hw.tcl.cmd[TCL_PER_LIGHT_CTL_3] = 0;
1309
1310 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] =
1311 (R200_UCP_IN_CLIP_SPACE |
1312 R200_CULL_FRONT_IS_CCW);
1313
1314 /* Texgen/Texmat state */
1315 rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_2] = 0x00ffffff;
1316 rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_3] =
1317 ((0 << R200_TEXGEN_0_INPUT_TEX_SHIFT) |
1318 (1 << R200_TEXGEN_1_INPUT_TEX_SHIFT) |
1319 (2 << R200_TEXGEN_2_INPUT_TEX_SHIFT) |
1320 (3 << R200_TEXGEN_3_INPUT_TEX_SHIFT) |
1321 (4 << R200_TEXGEN_4_INPUT_TEX_SHIFT) |
1322 (5 << R200_TEXGEN_5_INPUT_TEX_SHIFT));
1323 rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_0] = 0;
1324 rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_1] =
1325 ((0 << R200_TEXGEN_0_INPUT_SHIFT) |
1326 (1 << R200_TEXGEN_1_INPUT_SHIFT) |
1327 (2 << R200_TEXGEN_2_INPUT_SHIFT) |
1328 (3 << R200_TEXGEN_3_INPUT_SHIFT) |
1329 (4 << R200_TEXGEN_4_INPUT_SHIFT) |
1330 (5 << R200_TEXGEN_5_INPUT_SHIFT));
1331 rmesa->hw.tcg.cmd[TCG_TEX_CYL_WRAP_CTL] = 0;
1332
1333
1334 for (i = 0 ; i < 8; i++) {
1335 struct gl_light *l = &ctx->Light.Light[i];
1336 GLenum p = GL_LIGHT0 + i;
1337 *(float *)&(rmesa->hw.lit[i].cmd[LIT_RANGE_CUTOFF]) = FLT_MAX;
1338
1339 ctx->Driver.Lightfv( ctx, p, GL_AMBIENT, l->Ambient );
1340 ctx->Driver.Lightfv( ctx, p, GL_DIFFUSE, l->Diffuse );
1341 ctx->Driver.Lightfv( ctx, p, GL_SPECULAR, l->Specular );
1342 ctx->Driver.Lightfv( ctx, p, GL_POSITION, NULL );
1343 ctx->Driver.Lightfv( ctx, p, GL_SPOT_DIRECTION, NULL );
1344 ctx->Driver.Lightfv( ctx, p, GL_SPOT_EXPONENT, &l->SpotExponent );
1345 ctx->Driver.Lightfv( ctx, p, GL_SPOT_CUTOFF, &l->SpotCutoff );
1346 ctx->Driver.Lightfv( ctx, p, GL_CONSTANT_ATTENUATION,
1347 &l->ConstantAttenuation );
1348 ctx->Driver.Lightfv( ctx, p, GL_LINEAR_ATTENUATION,
1349 &l->LinearAttenuation );
1350 ctx->Driver.Lightfv( ctx, p, GL_QUADRATIC_ATTENUATION,
1351 &l->QuadraticAttenuation );
1352 *(float *)&(rmesa->hw.lit[i].cmd[LIT_ATTEN_XXX]) = 0.0;
1353 }
1354
1355 ctx->Driver.LightModelfv( ctx, GL_LIGHT_MODEL_AMBIENT,
1356 ctx->Light.Model.Ambient );
1357
1358 TNL_CONTEXT(ctx)->Driver.NotifyMaterialChange( ctx );
1359
1360 for (i = 0 ; i < 6; i++) {
1361 ctx->Driver.ClipPlane( ctx, GL_CLIP_PLANE0 + i, NULL );
1362 }
1363
1364 ctx->Driver.Fogfv( ctx, GL_FOG_MODE, NULL );
1365 ctx->Driver.Fogfv( ctx, GL_FOG_DENSITY, &ctx->Fog.Density );
1366 ctx->Driver.Fogfv( ctx, GL_FOG_START, &ctx->Fog.Start );
1367 ctx->Driver.Fogfv( ctx, GL_FOG_END, &ctx->Fog.End );
1368 ctx->Driver.Fogfv( ctx, GL_FOG_COLOR, ctx->Fog.Color );
1369 ctx->Driver.Fogfv( ctx, GL_FOG_COORDINATE_SOURCE_EXT, NULL );
1370
1371 rmesa->hw.grd.cmd[GRD_VERT_GUARD_CLIP_ADJ] = IEEE_ONE;
1372 rmesa->hw.grd.cmd[GRD_VERT_GUARD_DISCARD_ADJ] = IEEE_ONE;
1373 rmesa->hw.grd.cmd[GRD_HORZ_GUARD_CLIP_ADJ] = IEEE_ONE;
1374 rmesa->hw.grd.cmd[GRD_HORZ_GUARD_DISCARD_ADJ] = IEEE_ONE;
1375
1376 rmesa->hw.eye.cmd[EYE_X] = 0;
1377 rmesa->hw.eye.cmd[EYE_Y] = 0;
1378 rmesa->hw.eye.cmd[EYE_Z] = IEEE_ONE;
1379 rmesa->hw.eye.cmd[EYE_RESCALE_FACTOR] = IEEE_ONE;
1380
1381 rmesa->hw.spr.cmd[SPR_POINT_SPRITE_CNTL] =
1382 R200_PS_SE_SEL_STATE | R200_PS_MULT_CONST;
1383
1384 /* ptp_eye is presumably used to calculate the attenuation wrt a different
1385 location? In any case, since point attenuation triggers _needeyecoords,
1386 it is constant. Probably ignored as long as R200_PS_USE_MODEL_EYE_VEC
1387 isn't set */
1388 rmesa->hw.ptp.cmd[PTP_EYE_X] = 0;
1389 rmesa->hw.ptp.cmd[PTP_EYE_Y] = 0;
1390 rmesa->hw.ptp.cmd[PTP_EYE_Z] = IEEE_ONE | 0x80000000; /* -1.0 */
1391 rmesa->hw.ptp.cmd[PTP_EYE_3] = 0;
1392 /* no idea what the ptp_vport_scale values are good for, except the
1393 PTSIZE one - hopefully doesn't matter */
1394 rmesa->hw.ptp.cmd[PTP_VPORT_SCALE_0] = IEEE_ONE;
1395 rmesa->hw.ptp.cmd[PTP_VPORT_SCALE_1] = IEEE_ONE;
1396 rmesa->hw.ptp.cmd[PTP_VPORT_SCALE_PTSIZE] = IEEE_ONE;
1397 rmesa->hw.ptp.cmd[PTP_VPORT_SCALE_3] = IEEE_ONE;
1398 rmesa->hw.ptp.cmd[PTP_ATT_CONST_QUAD] = 0;
1399 rmesa->hw.ptp.cmd[PTP_ATT_CONST_LIN] = 0;
1400 rmesa->hw.ptp.cmd[PTP_ATT_CONST_CON] = IEEE_ONE;
1401 rmesa->hw.ptp.cmd[PTP_ATT_CONST_3] = 0;
1402 rmesa->hw.ptp.cmd[PTP_CLAMP_MIN] = IEEE_ONE;
1403 rmesa->hw.ptp.cmd[PTP_CLAMP_MAX] = 0x44ffe000; /* 2047 */
1404 rmesa->hw.ptp.cmd[PTP_CLAMP_2] = 0;
1405 rmesa->hw.ptp.cmd[PTP_CLAMP_3] = 0;
1406
1407 r200LightingSpaceChange( ctx );
1408
1409 rmesa->radeon.hw.all_dirty = GL_TRUE;
1410
1411 rcommonInitCmdBuf(&rmesa->radeon);
1412 }