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Merge branch 'mesa_7_6_branch'
[mesa.git] / src / mesa / drivers / dri / r200 / r200_state_init.c
1 /*
2 Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
3
4 The Weather Channel (TM) funded Tungsten Graphics to develop the
5 initial release of the Radeon 8500 driver under the XFree86 license.
6 This notice must be preserved.
7
8 Permission is hereby granted, free of charge, to any person obtaining
9 a copy of this software and associated documentation files (the
10 "Software"), to deal in the Software without restriction, including
11 without limitation the rights to use, copy, modify, merge, publish,
12 distribute, sublicense, and/or sell copies of the Software, and to
13 permit persons to whom the Software is furnished to do so, subject to
14 the following conditions:
15
16 The above copyright notice and this permission notice (including the
17 next paragraph) shall be included in all copies or substantial
18 portions of the Software.
19
20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 */
28
29 /*
30 * Authors:
31 * Keith Whitwell <keith@tungstengraphics.com>
32 */
33
34 #include "main/glheader.h"
35 #include "main/imports.h"
36 #include "main/enums.h"
37 #include "main/colormac.h"
38 #include "main/api_arrayelt.h"
39
40 #include "swrast/swrast.h"
41 #include "vbo/vbo.h"
42 #include "tnl/tnl.h"
43 #include "tnl/t_pipeline.h"
44 #include "swrast_setup/swrast_setup.h"
45
46 #include "radeon_common.h"
47 #include "radeon_mipmap_tree.h"
48 #include "r200_context.h"
49 #include "r200_ioctl.h"
50 #include "r200_state.h"
51 #include "r200_tcl.h"
52 #include "r200_tex.h"
53 #include "r200_swtcl.h"
54 #include "radeon_queryobj.h"
55
56 #include "xmlpool.h"
57
58 /* New (1.3) state mechanism. 3 commands (packet, scalar, vector) in
59 * 1.3 cmdbuffers allow all previous state to be updated as well as
60 * the tcl scalar and vector areas.
61 */
62 static struct {
63 int start;
64 int len;
65 const char *name;
66 } packet[RADEON_MAX_STATE_PACKETS] = {
67 {RADEON_PP_MISC, 7, "RADEON_PP_MISC"},
68 {RADEON_PP_CNTL, 3, "RADEON_PP_CNTL"},
69 {RADEON_RB3D_COLORPITCH, 1, "RADEON_RB3D_COLORPITCH"},
70 {RADEON_RE_LINE_PATTERN, 2, "RADEON_RE_LINE_PATTERN"},
71 {RADEON_SE_LINE_WIDTH, 1, "RADEON_SE_LINE_WIDTH"},
72 {RADEON_PP_LUM_MATRIX, 1, "RADEON_PP_LUM_MATRIX"},
73 {RADEON_PP_ROT_MATRIX_0, 2, "RADEON_PP_ROT_MATRIX_0"},
74 {RADEON_RB3D_STENCILREFMASK, 3, "RADEON_RB3D_STENCILREFMASK"},
75 {RADEON_SE_VPORT_XSCALE, 6, "RADEON_SE_VPORT_XSCALE"},
76 {RADEON_SE_CNTL, 2, "RADEON_SE_CNTL"},
77 {RADEON_SE_CNTL_STATUS, 1, "RADEON_SE_CNTL_STATUS"},
78 {RADEON_RE_MISC, 1, "RADEON_RE_MISC"},
79 {RADEON_PP_TXFILTER_0, 6, "RADEON_PP_TXFILTER_0"},
80 {RADEON_PP_BORDER_COLOR_0, 1, "RADEON_PP_BORDER_COLOR_0"},
81 {RADEON_PP_TXFILTER_1, 6, "RADEON_PP_TXFILTER_1"},
82 {RADEON_PP_BORDER_COLOR_1, 1, "RADEON_PP_BORDER_COLOR_1"},
83 {RADEON_PP_TXFILTER_2, 6, "RADEON_PP_TXFILTER_2"},
84 {RADEON_PP_BORDER_COLOR_2, 1, "RADEON_PP_BORDER_COLOR_2"},
85 {RADEON_SE_ZBIAS_FACTOR, 2, "RADEON_SE_ZBIAS_FACTOR"},
86 {RADEON_SE_TCL_OUTPUT_VTX_FMT, 11, "RADEON_SE_TCL_OUTPUT_VTX_FMT"},
87 {RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED, 17,
88 "RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED"},
89 {R200_PP_TXCBLEND_0, 4, "R200_PP_TXCBLEND_0"},
90 {R200_PP_TXCBLEND_1, 4, "R200_PP_TXCBLEND_1"},
91 {R200_PP_TXCBLEND_2, 4, "R200_PP_TXCBLEND_2"},
92 {R200_PP_TXCBLEND_3, 4, "R200_PP_TXCBLEND_3"},
93 {R200_PP_TXCBLEND_4, 4, "R200_PP_TXCBLEND_4"},
94 {R200_PP_TXCBLEND_5, 4, "R200_PP_TXCBLEND_5"},
95 {R200_PP_TXCBLEND_6, 4, "R200_PP_TXCBLEND_6"},
96 {R200_PP_TXCBLEND_7, 4, "R200_PP_TXCBLEND_7"},
97 {R200_SE_TCL_LIGHT_MODEL_CTL_0, 6, "R200_SE_TCL_LIGHT_MODEL_CTL_0"},
98 {R200_PP_TFACTOR_0, 6, "R200_PP_TFACTOR_0"},
99 {R200_SE_VTX_FMT_0, 4, "R200_SE_VTX_FMT_0"},
100 {R200_SE_VAP_CNTL, 1, "R200_SE_VAP_CNTL"},
101 {R200_SE_TCL_MATRIX_SEL_0, 5, "R200_SE_TCL_MATRIX_SEL_0"},
102 {R200_SE_TCL_TEX_PROC_CTL_2, 5, "R200_SE_TCL_TEX_PROC_CTL_2"},
103 {R200_SE_TCL_UCP_VERT_BLEND_CTL, 1, "R200_SE_TCL_UCP_VERT_BLEND_CTL"},
104 {R200_PP_TXFILTER_0, 6, "R200_PP_TXFILTER_0"},
105 {R200_PP_TXFILTER_1, 6, "R200_PP_TXFILTER_1"},
106 {R200_PP_TXFILTER_2, 6, "R200_PP_TXFILTER_2"},
107 {R200_PP_TXFILTER_3, 6, "R200_PP_TXFILTER_3"},
108 {R200_PP_TXFILTER_4, 6, "R200_PP_TXFILTER_4"},
109 {R200_PP_TXFILTER_5, 6, "R200_PP_TXFILTER_5"},
110 {R200_PP_TXOFFSET_0, 1, "R200_PP_TXOFFSET_0"},
111 {R200_PP_TXOFFSET_1, 1, "R200_PP_TXOFFSET_1"},
112 {R200_PP_TXOFFSET_2, 1, "R200_PP_TXOFFSET_2"},
113 {R200_PP_TXOFFSET_3, 1, "R200_PP_TXOFFSET_3"},
114 {R200_PP_TXOFFSET_4, 1, "R200_PP_TXOFFSET_4"},
115 {R200_PP_TXOFFSET_5, 1, "R200_PP_TXOFFSET_5"},
116 {R200_SE_VTE_CNTL, 1, "R200_SE_VTE_CNTL"},
117 {R200_SE_TCL_OUTPUT_VTX_COMP_SEL, 1,
118 "R200_SE_TCL_OUTPUT_VTX_COMP_SEL"},
119 {R200_PP_TAM_DEBUG3, 1, "R200_PP_TAM_DEBUG3"},
120 {R200_PP_CNTL_X, 1, "R200_PP_CNTL_X"},
121 {R200_RB3D_DEPTHXY_OFFSET, 1, "R200_RB3D_DEPTHXY_OFFSET"},
122 {R200_RE_AUX_SCISSOR_CNTL, 1, "R200_RE_AUX_SCISSOR_CNTL"},
123 {R200_RE_SCISSOR_TL_0, 2, "R200_RE_SCISSOR_TL_0"},
124 {R200_RE_SCISSOR_TL_1, 2, "R200_RE_SCISSOR_TL_1"},
125 {R200_RE_SCISSOR_TL_2, 2, "R200_RE_SCISSOR_TL_2"},
126 {R200_SE_VAP_CNTL_STATUS, 1, "R200_SE_VAP_CNTL_STATUS"},
127 {R200_SE_VTX_STATE_CNTL, 1, "R200_SE_VTX_STATE_CNTL"},
128 {R200_RE_POINTSIZE, 1, "R200_RE_POINTSIZE"},
129 {R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0, 4,
130 "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0"},
131 {R200_PP_CUBIC_FACES_0, 1, "R200_PP_CUBIC_FACES_0"}, /* 61 */
132 {R200_PP_CUBIC_OFFSET_F1_0, 5, "R200_PP_CUBIC_OFFSET_F1_0"}, /* 62 */
133 {R200_PP_CUBIC_FACES_1, 1, "R200_PP_CUBIC_FACES_1"},
134 {R200_PP_CUBIC_OFFSET_F1_1, 5, "R200_PP_CUBIC_OFFSET_F1_1"},
135 {R200_PP_CUBIC_FACES_2, 1, "R200_PP_CUBIC_FACES_2"},
136 {R200_PP_CUBIC_OFFSET_F1_2, 5, "R200_PP_CUBIC_OFFSET_F1_2"},
137 {R200_PP_CUBIC_FACES_3, 1, "R200_PP_CUBIC_FACES_3"},
138 {R200_PP_CUBIC_OFFSET_F1_3, 5, "R200_PP_CUBIC_OFFSET_F1_3"},
139 {R200_PP_CUBIC_FACES_4, 1, "R200_PP_CUBIC_FACES_4"},
140 {R200_PP_CUBIC_OFFSET_F1_4, 5, "R200_PP_CUBIC_OFFSET_F1_4"},
141 {R200_PP_CUBIC_FACES_5, 1, "R200_PP_CUBIC_FACES_5"},
142 {R200_PP_CUBIC_OFFSET_F1_5, 5, "R200_PP_CUBIC_OFFSET_F1_5"},
143 {RADEON_PP_TEX_SIZE_0, 2, "RADEON_PP_TEX_SIZE_0"},
144 {RADEON_PP_TEX_SIZE_1, 2, "RADEON_PP_TEX_SIZE_1"},
145 {RADEON_PP_TEX_SIZE_2, 2, "RADEON_PP_TEX_SIZE_2"},
146 {R200_RB3D_BLENDCOLOR, 3, "R200_RB3D_BLENDCOLOR"},
147 {R200_SE_TCL_POINT_SPRITE_CNTL, 1, "R200_SE_TCL_POINT_SPRITE_CNTL"},
148 {RADEON_PP_CUBIC_FACES_0, 1, "RADEON_PP_CUBIC_FACES_0"},
149 {RADEON_PP_CUBIC_OFFSET_T0_0, 5, "RADEON_PP_CUBIC_OFFSET_T0_0"},
150 {RADEON_PP_CUBIC_FACES_1, 1, "RADEON_PP_CUBIC_FACES_1"},
151 {RADEON_PP_CUBIC_OFFSET_T1_0, 5, "RADEON_PP_CUBIC_OFFSET_T1_0"},
152 {RADEON_PP_CUBIC_FACES_2, 1, "RADEON_PP_CUBIC_FACES_2"},
153 {RADEON_PP_CUBIC_OFFSET_T2_0, 5, "RADEON_PP_CUBIC_OFFSET_T2_0"},
154 {R200_PP_TRI_PERF, 2, "R200_PP_TRI_PERF"},
155 {R200_PP_TXCBLEND_8, 32, "R200_PP_AFS_0"}, /* 85 */
156 {R200_PP_TXCBLEND_0, 32, "R200_PP_AFS_1"},
157 {R200_PP_TFACTOR_0, 8, "R200_ATF_TFACTOR"},
158 {R200_PP_TXFILTER_0, 8, "R200_PP_TXCTLALL_0"},
159 {R200_PP_TXFILTER_1, 8, "R200_PP_TXCTLALL_1"},
160 {R200_PP_TXFILTER_2, 8, "R200_PP_TXCTLALL_2"},
161 {R200_PP_TXFILTER_3, 8, "R200_PP_TXCTLALL_3"},
162 {R200_PP_TXFILTER_4, 8, "R200_PP_TXCTLALL_4"},
163 {R200_PP_TXFILTER_5, 8, "R200_PP_TXCTLALL_5"},
164 {R200_VAP_PVS_CNTL_1, 2, "R200_VAP_PVS_CNTL"},
165 };
166
167 /* =============================================================
168 * State initialization
169 */
170 static int cmdpkt( r200ContextPtr rmesa, int id )
171 {
172 drm_radeon_cmd_header_t h;
173
174 if (rmesa->radeon.radeonScreen->kernel_mm) {
175 return CP_PACKET0(packet[id].start, packet[id].len - 1);
176 } else {
177 h.i = 0;
178 h.packet.cmd_type = RADEON_CMD_PACKET;
179 h.packet.packet_id = id;
180 }
181 return h.i;
182 }
183
184 static int cmdvec( int offset, int stride, int count )
185 {
186 drm_radeon_cmd_header_t h;
187 h.i = 0;
188 h.vectors.cmd_type = RADEON_CMD_VECTORS;
189 h.vectors.offset = offset;
190 h.vectors.stride = stride;
191 h.vectors.count = count;
192 return h.i;
193 }
194
195 /* warning: the count here is divided by 4 compared to other cmds
196 (so it doesn't exceed the char size)! */
197 static int cmdveclinear( int offset, int count )
198 {
199 drm_radeon_cmd_header_t h;
200 h.i = 0;
201 h.veclinear.cmd_type = RADEON_CMD_VECLINEAR;
202 h.veclinear.addr_lo = offset & 0xff;
203 h.veclinear.addr_hi = (offset & 0xff00) >> 8;
204 h.veclinear.count = count;
205 return h.i;
206 }
207
208 static int cmdscl( int offset, int stride, int count )
209 {
210 drm_radeon_cmd_header_t h;
211 h.i = 0;
212 h.scalars.cmd_type = RADEON_CMD_SCALARS;
213 h.scalars.offset = offset;
214 h.scalars.stride = stride;
215 h.scalars.count = count;
216 return h.i;
217 }
218
219 static int cmdscl2( int offset, int stride, int count )
220 {
221 drm_radeon_cmd_header_t h;
222 h.i = 0;
223 h.scalars.cmd_type = RADEON_CMD_SCALARS2;
224 h.scalars.offset = offset - 0x100;
225 h.scalars.stride = stride;
226 h.scalars.count = count;
227 return h.i;
228 }
229
230 /**
231 * Check functions are used to check if state is active.
232 * If it is active check function returns maximum emit size.
233 */
234 #define CHECK( NM, FLAG, ADD ) \
235 static int check_##NM( GLcontext *ctx, struct radeon_state_atom *atom) \
236 { \
237 r200ContextPtr rmesa = R200_CONTEXT(ctx); \
238 (void) rmesa; \
239 return (FLAG) ? atom->cmd_size + (ADD) : 0; \
240 }
241
242 #define TCL_CHECK( NM, FLAG, ADD ) \
243 static int check_##NM( GLcontext *ctx, struct radeon_state_atom *atom) \
244 { \
245 r200ContextPtr rmesa = R200_CONTEXT(ctx); \
246 return (!rmesa->radeon.TclFallback && !ctx->VertexProgram._Enabled && (FLAG)) ? atom->cmd_size + (ADD) : 0; \
247 }
248
249 #define TCL_OR_VP_CHECK( NM, FLAG, ADD ) \
250 static int check_##NM( GLcontext *ctx, struct radeon_state_atom *atom ) \
251 { \
252 r200ContextPtr rmesa = R200_CONTEXT(ctx); \
253 return (!rmesa->radeon.TclFallback && (FLAG)) ? atom->cmd_size + (ADD) : 0; \
254 }
255
256 #define VP_CHECK( NM, FLAG, ADD ) \
257 static int check_##NM( GLcontext *ctx, struct radeon_state_atom *atom ) \
258 { \
259 r200ContextPtr rmesa = R200_CONTEXT(ctx); \
260 (void) atom; \
261 return (!rmesa->radeon.TclFallback && ctx->VertexProgram._Enabled && (FLAG)) ? atom->cmd_size + (ADD) : 0; \
262 }
263
264 CHECK( always, GL_TRUE, 0 )
265 CHECK( always_add4, GL_TRUE, 4 )
266 CHECK( never, GL_FALSE, 0 )
267 CHECK( tex_any, ctx->Texture._EnabledUnits, 0 )
268 CHECK( tf, (ctx->Texture._EnabledUnits && !ctx->ATIFragmentShader._Enabled), 0 );
269 CHECK( pix_zero, !ctx->ATIFragmentShader._Enabled, 0 )
270 CHECK( texenv, (rmesa->state.envneeded & (1 << (atom->idx)) && !ctx->ATIFragmentShader._Enabled), 0 )
271 CHECK( afs_pass1, (ctx->ATIFragmentShader._Enabled && (ctx->ATIFragmentShader.Current->NumPasses > 1)), 0 )
272 CHECK( afs, ctx->ATIFragmentShader._Enabled, 0 )
273 CHECK( tex_cube, rmesa->state.texture.unit[atom->idx].unitneeded & TEXTURE_CUBE_BIT, 3 + 3*5 - CUBE_STATE_SIZE )
274 CHECK( tex_cube_cs, rmesa->state.texture.unit[atom->idx].unitneeded & TEXTURE_CUBE_BIT, 2 + 4*5 - CUBE_STATE_SIZE )
275 TCL_CHECK( tcl_fog, ctx->Fog.Enabled, 0 )
276 TCL_CHECK( tcl_fog_add4, ctx->Fog.Enabled, 4 )
277 TCL_CHECK( tcl, GL_TRUE, 0 )
278 TCL_CHECK( tcl_add8, GL_TRUE, 8 )
279 TCL_CHECK( tcl_add4, GL_TRUE, 4 )
280 TCL_CHECK( tcl_tex, rmesa->state.texture.unit[atom->idx].unitneeded, 0 )
281 TCL_CHECK( tcl_lighting, ctx->Light.Enabled, 0 )
282 TCL_CHECK( tcl_light, ctx->Light.Enabled && ctx->Light.Light[atom->idx].Enabled, 0 )
283 TCL_CHECK( tcl_tex_add4, rmesa->state.texture.unit[atom->idx].unitneeded, 4 )
284 TCL_CHECK( tcl_lighting_add4, ctx->Light.Enabled, 4 )
285 TCL_CHECK( tcl_lighting_add6, ctx->Light.Enabled, 6 )
286 TCL_CHECK( tcl_light_add8, ctx->Light.Enabled && ctx->Light.Light[atom->idx].Enabled, 8 )
287 TCL_OR_VP_CHECK( tcl_ucp, (ctx->Transform.ClipPlanesEnabled & (1 << (atom->idx))), 0 )
288 TCL_OR_VP_CHECK( tcl_ucp_add4, (ctx->Transform.ClipPlanesEnabled & (1 << (atom->idx))), 4 )
289 TCL_OR_VP_CHECK( tcl_or_vp, GL_TRUE, 0 )
290 TCL_OR_VP_CHECK( tcl_or_vp_add2, GL_TRUE, 2 )
291 VP_CHECK( tcl_vp, GL_TRUE, 0 )
292 VP_CHECK( tcl_vp_add4, GL_TRUE, 4 )
293 VP_CHECK( tcl_vp_size, ctx->VertexProgram.Current->Base.NumNativeInstructions > 64, 0 )
294 VP_CHECK( tcl_vpp_size, ctx->VertexProgram.Current->Base.NumNativeParameters > 96, 0 )
295 VP_CHECK( tcl_vp_size_add4, ctx->VertexProgram.Current->Base.NumNativeInstructions > 64, 4 )
296 VP_CHECK( tcl_vpp_size_add4, ctx->VertexProgram.Current->Base.NumNativeParameters > 96, 4 )
297
298 #define OUT_VEC(hdr, data) do { \
299 drm_radeon_cmd_header_t h; \
300 h.i = hdr; \
301 OUT_BATCH(CP_PACKET0(RADEON_SE_TCL_STATE_FLUSH, 0)); \
302 OUT_BATCH(0); \
303 OUT_BATCH(CP_PACKET0(R200_SE_TCL_VECTOR_INDX_REG, 0)); \
304 OUT_BATCH(h.vectors.offset | (h.vectors.stride << RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT)); \
305 OUT_BATCH(CP_PACKET0_ONE(R200_SE_TCL_VECTOR_DATA_REG, h.vectors.count - 1)); \
306 OUT_BATCH_TABLE((data), h.vectors.count); \
307 } while(0)
308
309 #define OUT_VECLINEAR(hdr, data) do { \
310 drm_radeon_cmd_header_t h; \
311 uint32_t _start, _sz; \
312 h.i = hdr; \
313 _start = h.veclinear.addr_lo | (h.veclinear.addr_hi << 8); \
314 _sz = h.veclinear.count * 4; \
315 if (r200->radeon.radeonScreen->kernel_mm && _sz) { \
316 BEGIN_BATCH_NO_AUTOSTATE(dwords); \
317 OUT_BATCH(CP_PACKET0(RADEON_SE_TCL_STATE_FLUSH, 0)); \
318 OUT_BATCH(0); \
319 OUT_BATCH(CP_PACKET0(R200_SE_TCL_VECTOR_INDX_REG, 0)); \
320 OUT_BATCH(_start | (1 << RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT)); \
321 OUT_BATCH(CP_PACKET0_ONE(R200_SE_TCL_VECTOR_DATA_REG, _sz - 1)); \
322 OUT_BATCH_TABLE((data), _sz); \
323 END_BATCH(); \
324 } \
325 } while(0)
326
327 #define OUT_SCL(hdr, data) do { \
328 drm_radeon_cmd_header_t h; \
329 h.i = hdr; \
330 OUT_BATCH(CP_PACKET0(R200_SE_TCL_SCALAR_INDX_REG, 0)); \
331 OUT_BATCH((h.scalars.offset) | (h.scalars.stride << RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT)); \
332 OUT_BATCH(CP_PACKET0_ONE(R200_SE_TCL_SCALAR_DATA_REG, h.scalars.count - 1)); \
333 OUT_BATCH_TABLE((data), h.scalars.count); \
334 } while(0)
335
336 #define OUT_SCL2(hdr, data) do { \
337 drm_radeon_cmd_header_t h; \
338 h.i = hdr; \
339 OUT_BATCH(CP_PACKET0(R200_SE_TCL_SCALAR_INDX_REG, 0)); \
340 OUT_BATCH((h.scalars.offset + 0x100) | (h.scalars.stride << RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT)); \
341 OUT_BATCH(CP_PACKET0_ONE(R200_SE_TCL_SCALAR_DATA_REG, h.scalars.count - 1)); \
342 OUT_BATCH_TABLE((data), h.scalars.count); \
343 } while(0)
344 static int check_rrb(GLcontext *ctx, struct radeon_state_atom *atom)
345 {
346 r200ContextPtr r200 = R200_CONTEXT(ctx);
347 struct radeon_renderbuffer *rrb;
348 rrb = radeon_get_colorbuffer(&r200->radeon);
349 if (!rrb || !rrb->bo)
350 return 0;
351 return atom->cmd_size;
352 }
353
354 static void mtl_emit(GLcontext *ctx, struct radeon_state_atom *atom)
355 {
356 r200ContextPtr r200 = R200_CONTEXT(ctx);
357 BATCH_LOCALS(&r200->radeon);
358 uint32_t dwords = atom->check(ctx, atom);
359
360 BEGIN_BATCH_NO_AUTOSTATE(dwords);
361 OUT_VEC(atom->cmd[MTL_CMD_0], (atom->cmd+1));
362 OUT_SCL2(atom->cmd[MTL_CMD_1], (atom->cmd + 18));
363 END_BATCH();
364 }
365
366 static void lit_emit(GLcontext *ctx, struct radeon_state_atom *atom)
367 {
368 r200ContextPtr r200 = R200_CONTEXT(ctx);
369 BATCH_LOCALS(&r200->radeon);
370 uint32_t dwords = atom->check(ctx, atom);
371
372 BEGIN_BATCH_NO_AUTOSTATE(dwords);
373 OUT_VEC(atom->cmd[LIT_CMD_0], atom->cmd+1);
374 OUT_VEC(atom->cmd[LIT_CMD_1], atom->cmd+LIT_CMD_1+1);
375 END_BATCH();
376 }
377
378 static void ptp_emit(GLcontext *ctx, struct radeon_state_atom *atom)
379 {
380 r200ContextPtr r200 = R200_CONTEXT(ctx);
381 BATCH_LOCALS(&r200->radeon);
382 uint32_t dwords = atom->check(ctx, atom);
383
384 BEGIN_BATCH_NO_AUTOSTATE(dwords);
385 OUT_VEC(atom->cmd[PTP_CMD_0], atom->cmd+1);
386 OUT_VEC(atom->cmd[PTP_CMD_1], atom->cmd+PTP_CMD_1+1);
387 END_BATCH();
388 }
389
390 static void veclinear_emit(GLcontext *ctx, struct radeon_state_atom *atom)
391 {
392 r200ContextPtr r200 = R200_CONTEXT(ctx);
393 BATCH_LOCALS(&r200->radeon);
394 uint32_t dwords = atom->check(ctx, atom);
395
396 OUT_VECLINEAR(atom->cmd[0], atom->cmd+1);
397 }
398
399 static void scl_emit(GLcontext *ctx, struct radeon_state_atom *atom)
400 {
401 r200ContextPtr r200 = R200_CONTEXT(ctx);
402 BATCH_LOCALS(&r200->radeon);
403 uint32_t dwords = atom->check(ctx, atom);
404
405 BEGIN_BATCH_NO_AUTOSTATE(dwords);
406 OUT_SCL(atom->cmd[0], atom->cmd+1);
407 END_BATCH();
408 }
409
410
411 static void vec_emit(GLcontext *ctx, struct radeon_state_atom *atom)
412 {
413 r200ContextPtr r200 = R200_CONTEXT(ctx);
414 BATCH_LOCALS(&r200->radeon);
415 uint32_t dwords = atom->check(ctx, atom);
416
417 BEGIN_BATCH_NO_AUTOSTATE(dwords);
418 OUT_VEC(atom->cmd[0], atom->cmd+1);
419 END_BATCH();
420 }
421
422 static void ctx_emit(GLcontext *ctx, struct radeon_state_atom *atom)
423 {
424 r200ContextPtr r200 = R200_CONTEXT(ctx);
425 BATCH_LOCALS(&r200->radeon);
426 struct radeon_renderbuffer *rrb;
427 uint32_t cbpitch;
428 uint32_t zbpitch, depth_fmt;
429 uint32_t dwords = atom->check(ctx, atom);
430
431 /* output the first 7 bytes of context */
432 BEGIN_BATCH_NO_AUTOSTATE(dwords);
433 OUT_BATCH_TABLE(atom->cmd, 5);
434
435 rrb = radeon_get_depthbuffer(&r200->radeon);
436 if (!rrb) {
437 OUT_BATCH(0);
438 OUT_BATCH(0);
439 } else {
440 zbpitch = (rrb->pitch / rrb->cpp);
441 if (r200->using_hyperz)
442 zbpitch |= RADEON_DEPTH_HYPERZ;
443 OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
444 OUT_BATCH(zbpitch);
445 if (rrb->cpp == 4)
446 depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
447 else
448 depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
449 atom->cmd[CTX_RB3D_ZSTENCILCNTL] &= ~RADEON_DEPTH_FORMAT_MASK;
450 atom->cmd[CTX_RB3D_ZSTENCILCNTL] |= depth_fmt;
451 }
452
453 OUT_BATCH(atom->cmd[CTX_RB3D_ZSTENCILCNTL]);
454 OUT_BATCH(atom->cmd[CTX_CMD_1]);
455 OUT_BATCH(atom->cmd[CTX_PP_CNTL]);
456
457 rrb = radeon_get_colorbuffer(&r200->radeon);
458 if (!rrb || !rrb->bo) {
459 OUT_BATCH(atom->cmd[CTX_RB3D_CNTL]);
460 OUT_BATCH(atom->cmd[CTX_RB3D_COLOROFFSET]);
461 } else {
462 atom->cmd[CTX_RB3D_CNTL] &= ~(0xf << 10);
463 if (rrb->cpp == 4)
464 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB8888;
465 else
466 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_RGB565;
467
468 OUT_BATCH(atom->cmd[CTX_RB3D_CNTL]);
469 OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
470 }
471
472 OUT_BATCH(atom->cmd[CTX_CMD_2]);
473
474 if (!rrb || !rrb->bo) {
475 OUT_BATCH(atom->cmd[CTX_RB3D_COLORPITCH]);
476 } else {
477 cbpitch = (rrb->pitch / rrb->cpp);
478 if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE)
479 cbpitch |= R200_COLOR_TILE_ENABLE;
480 OUT_BATCH(cbpitch);
481 }
482
483 if (atom->cmd_size == CTX_STATE_SIZE_NEWDRM)
484 OUT_BATCH_TABLE((atom->cmd + 14), 4);
485
486 END_BATCH();
487 }
488
489 static int check_always_ctx( GLcontext *ctx, struct radeon_state_atom *atom)
490 {
491 r200ContextPtr r200 = R200_CONTEXT(ctx);
492 struct radeon_renderbuffer *rrb, *drb;
493 uint32_t dwords;
494
495 rrb = radeon_get_colorbuffer(&r200->radeon);
496 if (!rrb || !rrb->bo) {
497 return 0;
498 }
499
500 drb = radeon_get_depthbuffer(&r200->radeon);
501
502 dwords = 10;
503 if (drb)
504 dwords += 6;
505 if (rrb)
506 dwords += 8;
507 if (atom->cmd_size == CTX_STATE_SIZE_NEWDRM)
508 dwords += 4;
509
510
511 return dwords;
512 }
513
514 static void ctx_emit_cs(GLcontext *ctx, struct radeon_state_atom *atom)
515 {
516 r200ContextPtr r200 = R200_CONTEXT(ctx);
517 BATCH_LOCALS(&r200->radeon);
518 struct radeon_renderbuffer *rrb, *drb;
519 uint32_t cbpitch = 0;
520 uint32_t zbpitch = 0;
521 uint32_t dwords = atom->check(ctx, atom);
522 uint32_t depth_fmt;
523
524 rrb = radeon_get_colorbuffer(&r200->radeon);
525 if (!rrb || !rrb->bo) {
526 return;
527 }
528
529 atom->cmd[CTX_RB3D_CNTL] &= ~(0xf << 10);
530 if (rrb->cpp == 4)
531 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB8888;
532 else switch (rrb->base.Format) {
533 case MESA_FORMAT_RGB565:
534 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_RGB565;
535 break;
536 case MESA_FORMAT_ARGB4444:
537 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB4444;
538 break;
539 case MESA_FORMAT_ARGB1555:
540 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB1555;
541 break;
542 default:
543 _mesa_problem(ctx, "Unexpected format in ctx_emit_cs");
544 }
545
546 cbpitch = (rrb->pitch / rrb->cpp);
547 if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE)
548 cbpitch |= R200_COLOR_TILE_ENABLE;
549
550 drb = radeon_get_depthbuffer(&r200->radeon);
551 if (drb) {
552 zbpitch = (drb->pitch / drb->cpp);
553 if (drb->cpp == 4)
554 depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
555 else
556 depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
557 atom->cmd[CTX_RB3D_ZSTENCILCNTL] &= ~RADEON_DEPTH_FORMAT_MASK;
558 atom->cmd[CTX_RB3D_ZSTENCILCNTL] |= depth_fmt;
559 }
560
561 /* output the first 7 bytes of context */
562 BEGIN_BATCH_NO_AUTOSTATE(dwords);
563
564 /* In the CS case we need to split this up */
565 OUT_BATCH(CP_PACKET0(packet[0].start, 3));
566 OUT_BATCH_TABLE((atom->cmd + 1), 4);
567
568 if (drb) {
569 OUT_BATCH(CP_PACKET0(RADEON_RB3D_DEPTHOFFSET, 0));
570 OUT_BATCH_RELOC(0, drb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
571
572 OUT_BATCH(CP_PACKET0(RADEON_RB3D_DEPTHPITCH, 0));
573 OUT_BATCH(zbpitch);
574 }
575
576 OUT_BATCH(CP_PACKET0(RADEON_RB3D_ZSTENCILCNTL, 0));
577 OUT_BATCH(atom->cmd[CTX_RB3D_ZSTENCILCNTL]);
578 OUT_BATCH(CP_PACKET0(RADEON_PP_CNTL, 1));
579 OUT_BATCH(atom->cmd[CTX_PP_CNTL]);
580 OUT_BATCH(atom->cmd[CTX_RB3D_CNTL]);
581
582
583 if (rrb) {
584 OUT_BATCH(CP_PACKET0(RADEON_RB3D_COLOROFFSET, 0));
585 OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
586
587 OUT_BATCH(CP_PACKET0(RADEON_RB3D_COLORPITCH, 0));
588 OUT_BATCH_RELOC(cbpitch, rrb->bo, cbpitch, 0, RADEON_GEM_DOMAIN_VRAM, 0);
589 }
590
591 if (atom->cmd_size == CTX_STATE_SIZE_NEWDRM) {
592 OUT_BATCH_TABLE((atom->cmd + 14), 4);
593 }
594
595 END_BATCH();
596 }
597
598 static int get_tex_size(GLcontext* ctx, struct radeon_state_atom *atom)
599 {
600 r200ContextPtr r200 = R200_CONTEXT(ctx);
601 uint32_t dwords = atom->cmd_size + 2;
602 int i = atom->idx;
603 radeonTexObj *t = r200->state.texture.unit[i].texobj;
604 if (!(t && t->mt && !t->image_override))
605 dwords -= 2;
606
607 return dwords;
608 }
609
610 static int check_tex_pair(GLcontext* ctx, struct radeon_state_atom *atom)
611 {
612 r200ContextPtr r200 = R200_CONTEXT(ctx);
613 /** XOR is bit flip operation so use it for finding pair */
614 if (!(r200->state.texture.unit[atom->idx].unitneeded | r200->state.texture.unit[atom->idx ^ 1].unitneeded))
615 return 0;
616
617 return get_tex_size(ctx, atom);
618 }
619
620 static int check_tex(GLcontext* ctx, struct radeon_state_atom *atom)
621 {
622 r200ContextPtr r200 = R200_CONTEXT(ctx);
623 if (!(r200->state.texture.unit[atom->idx].unitneeded))
624 return 0;
625
626 return get_tex_size(ctx, atom);
627 }
628
629
630 static void tex_emit(GLcontext *ctx, struct radeon_state_atom *atom)
631 {
632 r200ContextPtr r200 = R200_CONTEXT(ctx);
633 BATCH_LOCALS(&r200->radeon);
634 uint32_t dwords = atom->check(ctx, atom);
635 int i = atom->idx;
636 radeonTexObj *t = r200->state.texture.unit[i].texobj;
637
638 BEGIN_BATCH_NO_AUTOSTATE(dwords);
639 /* is this ok even with drm older than 1.18? */
640 OUT_BATCH_TABLE(atom->cmd, 10);
641
642 if (t && t->mt && !t->image_override) {
643 OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, 0,
644 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
645 } else if (!t) {
646 /* workaround for old CS mechanism */
647 OUT_BATCH(r200->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP]);
648 } else {
649 OUT_BATCH(t->override_offset);
650 }
651
652 END_BATCH();
653 }
654
655 static int get_tex_mm_size(GLcontext* ctx, struct radeon_state_atom *atom)
656 {
657 r200ContextPtr r200 = R200_CONTEXT(ctx);
658 uint32_t dwords = atom->cmd_size + 2;
659 int hastexture = 1;
660 int i = atom->idx;
661 radeonTexObj *t = r200->state.texture.unit[i].texobj;
662 if (!t)
663 hastexture = 0;
664 else {
665 if (!t->mt && !t->bo)
666 hastexture = 0;
667 }
668
669 if (!hastexture)
670 dwords -= 4;
671 return dwords;
672 }
673
674 static int check_tex_pair_mm(GLcontext* ctx, struct radeon_state_atom *atom)
675 {
676 r200ContextPtr r200 = R200_CONTEXT(ctx);
677 /** XOR is bit flip operation so use it for finding pair */
678 if (!(r200->state.texture.unit[atom->idx].unitneeded | r200->state.texture.unit[atom->idx ^ 1].unitneeded))
679 return 0;
680
681 return get_tex_mm_size(ctx, atom);
682 }
683
684 static int check_tex_mm(GLcontext* ctx, struct radeon_state_atom *atom)
685 {
686 r200ContextPtr r200 = R200_CONTEXT(ctx);
687 if (!(r200->state.texture.unit[atom->idx].unitneeded))
688 return 0;
689
690 return get_tex_mm_size(ctx, atom);
691 }
692
693
694 static void tex_emit_mm(GLcontext *ctx, struct radeon_state_atom *atom)
695 {
696 r200ContextPtr r200 = R200_CONTEXT(ctx);
697 BATCH_LOCALS(&r200->radeon);
698 uint32_t dwords = atom->check(ctx, atom);
699 int i = atom->idx;
700 radeonTexObj *t = r200->state.texture.unit[i].texobj;
701 if (!r200->state.texture.unit[i].unitneeded)
702 dwords -= 4;
703 BEGIN_BATCH_NO_AUTOSTATE(dwords);
704
705 OUT_BATCH(CP_PACKET0(R200_PP_TXFILTER_0 + (32 * i), 7));
706 OUT_BATCH_TABLE((atom->cmd + 1), 8);
707
708 if (dwords > atom->cmd_size) {
709 OUT_BATCH(CP_PACKET0(R200_PP_TXOFFSET_0 + (24 * i), 0));
710 if (t->mt && !t->image_override) {
711 OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, 0,
712 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
713 } else {
714 if (t->bo)
715 OUT_BATCH_RELOC(t->tile_bits, t->bo, 0,
716 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
717 }
718 }
719 END_BATCH();
720 }
721
722
723 static void cube_emit(GLcontext *ctx, struct radeon_state_atom *atom)
724 {
725 r200ContextPtr r200 = R200_CONTEXT(ctx);
726 BATCH_LOCALS(&r200->radeon);
727 uint32_t dwords = atom->check(ctx, atom);
728 int i = atom->idx, j;
729 radeonTexObj *t = r200->state.texture.unit[i].texobj;
730 radeon_mipmap_level *lvl;
731
732 if (!(t && !t->image_override))
733 dwords = 2;
734
735 BEGIN_BATCH_NO_AUTOSTATE(dwords);
736 /* XXX that size won't really match with image_override... */
737 OUT_BATCH_TABLE(atom->cmd, 2);
738
739 if (t && !t->image_override) {
740 lvl = &t->mt->levels[0];
741 OUT_BATCH_TABLE((atom->cmd + 2), 1);
742 for (j = 1; j <= 5; j++) {
743 OUT_BATCH_RELOC(lvl->faces[j].offset, t->mt->bo, lvl->faces[j].offset,
744 RADEON_GEM_DOMAIN_VRAM, 0, 0);
745 }
746 }
747 END_BATCH();
748 }
749
750 static void cube_emit_cs(GLcontext *ctx, struct radeon_state_atom *atom)
751 {
752 r200ContextPtr r200 = R200_CONTEXT(ctx);
753 BATCH_LOCALS(&r200->radeon);
754 uint32_t dwords = atom->check(ctx, atom);
755 int i = atom->idx, j;
756 radeonTexObj *t = r200->state.texture.unit[i].texobj;
757 radeon_mipmap_level *lvl;
758 if (!(t && !t->image_override))
759 dwords = 2;
760
761 BEGIN_BATCH_NO_AUTOSTATE(dwords);
762 OUT_BATCH_TABLE(atom->cmd, 2);
763
764 if (t && !t->image_override) {
765 lvl = &t->mt->levels[0];
766 for (j = 1; j <= 5; j++) {
767 OUT_BATCH(CP_PACKET0(R200_PP_CUBIC_OFFSET_F1_0 + (24*i) + (4 * (j-1)), 0));
768 OUT_BATCH_RELOC(lvl->faces[j].offset, t->mt->bo, lvl->faces[j].offset,
769 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
770 }
771 }
772 END_BATCH();
773 }
774
775 /* Initialize the context's hardware state.
776 */
777 void r200InitState( r200ContextPtr rmesa )
778 {
779 GLcontext *ctx = rmesa->radeon.glCtx;
780 GLuint i;
781
782 rmesa->radeon.state.color.clear = 0x00000000;
783
784 switch ( ctx->Visual.depthBits ) {
785 case 16:
786 rmesa->radeon.state.depth.clear = 0x0000ffff;
787 rmesa->radeon.state.stencil.clear = 0x00000000;
788 break;
789 case 24:
790 default:
791 rmesa->radeon.state.depth.clear = 0x00ffffff;
792 rmesa->radeon.state.stencil.clear = 0xffff0000;
793 break;
794 }
795
796 rmesa->radeon.Fallback = 0;
797
798 rmesa->radeon.hw.max_state_size = 0;
799
800 #define ALLOC_STATE( ATOM, CHK, SZ, NM, IDX ) \
801 do { \
802 rmesa->hw.ATOM.cmd_size = SZ; \
803 rmesa->hw.ATOM.cmd = (GLuint *)CALLOC(SZ * sizeof(int)); \
804 rmesa->hw.ATOM.lastcmd = (GLuint *)CALLOC(SZ * sizeof(int)); \
805 rmesa->hw.ATOM.name = NM; \
806 rmesa->hw.ATOM.idx = IDX; \
807 if (check_##CHK != check_never) { \
808 rmesa->hw.ATOM.check = check_##CHK; \
809 rmesa->radeon.hw.max_state_size += SZ * sizeof(int); \
810 } else { \
811 rmesa->hw.ATOM.check = NULL; \
812 } \
813 rmesa->hw.ATOM.dirty = GL_FALSE; \
814 } while (0)
815
816
817 /* Allocate state buffers:
818 */
819 if (rmesa->radeon.radeonScreen->drmSupportsBlendColor)
820 ALLOC_STATE( ctx, always_add4, CTX_STATE_SIZE_NEWDRM, "CTX/context", 0 );
821 else
822 ALLOC_STATE( ctx, always_add4, CTX_STATE_SIZE_OLDDRM, "CTX/context", 0 );
823
824 if (rmesa->radeon.radeonScreen->kernel_mm)
825 {
826 rmesa->hw.ctx.emit = ctx_emit_cs;
827 rmesa->hw.ctx.check = check_always_ctx;
828 }
829 else
830 {
831 rmesa->hw.ctx.emit = ctx_emit;
832 }
833 ALLOC_STATE( set, always, SET_STATE_SIZE, "SET/setup", 0 );
834 ALLOC_STATE( lin, always, LIN_STATE_SIZE, "LIN/line", 0 );
835 ALLOC_STATE( msk, always, MSK_STATE_SIZE, "MSK/mask", 0 );
836 ALLOC_STATE( vpt, always, VPT_STATE_SIZE, "VPT/viewport", 0 );
837 ALLOC_STATE( vtx, always, VTX_STATE_SIZE, "VTX/vertex", 0 );
838 ALLOC_STATE( vap, always, VAP_STATE_SIZE, "VAP/vap", 0 );
839 ALLOC_STATE( vte, always, VTE_STATE_SIZE, "VTE/vte", 0 );
840 ALLOC_STATE( msc, always, MSC_STATE_SIZE, "MSC/misc", 0 );
841 ALLOC_STATE( cst, always, CST_STATE_SIZE, "CST/constant", 0 );
842 ALLOC_STATE( zbs, always, ZBS_STATE_SIZE, "ZBS/zbias", 0 );
843 ALLOC_STATE( tf, tf, TF_STATE_SIZE, "TF/tfactor", 0 );
844 {
845 int state_size = TEX_STATE_SIZE_NEWDRM;
846 if (!rmesa->radeon.radeonScreen->drmSupportsFragShader) {
847 state_size = TEX_STATE_SIZE_OLDDRM;
848 }
849 if (rmesa->radeon.radeonScreen->drmSupportsFragShader) {
850 if (rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_R200) {
851 /* make sure texture units 0/1 are emitted pair-wise for r200 t0 hang workaround */
852 ALLOC_STATE( tex[0], tex_pair_mm, state_size, "TEX/tex-0", 0 );
853 ALLOC_STATE( tex[1], tex_pair_mm, state_size, "TEX/tex-1", 1 );
854 ALLOC_STATE( tam, tex_any, TAM_STATE_SIZE, "TAM/tam", 0 );
855 }
856 else {
857 ALLOC_STATE( tex[0], tex_mm, state_size, "TEX/tex-0", 0 );
858 ALLOC_STATE( tex[1], tex_mm, state_size, "TEX/tex-1", 1 );
859 ALLOC_STATE( tam, never, TAM_STATE_SIZE, "TAM/tam", 0 );
860 }
861 ALLOC_STATE( tex[2], tex_mm, state_size, "TEX/tex-2", 2 );
862 ALLOC_STATE( tex[3], tex_mm, state_size, "TEX/tex-3", 3 );
863 ALLOC_STATE( tex[4], tex_mm, state_size, "TEX/tex-4", 4 );
864 ALLOC_STATE( tex[5], tex_mm, state_size, "TEX/tex-5", 5 );
865 if (!rmesa->radeon.radeonScreen->kernel_mm)
866 {
867 if (rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_R200) {
868 rmesa->hw.tex[0].check = check_tex_pair;
869 rmesa->hw.tex[1].check = check_tex_pair;
870 } else {
871 rmesa->hw.tex[0].check = check_tex;
872 rmesa->hw.tex[1].check = check_tex;
873 }
874 rmesa->hw.tex[2].check = check_tex;
875 rmesa->hw.tex[3].check = check_tex;
876 rmesa->hw.tex[4].check = check_tex;
877 rmesa->hw.tex[5].check = check_tex;
878 }
879 if (rmesa->radeon.radeonScreen->drmSupportsFragShader) {
880 ALLOC_STATE( atf, afs, ATF_STATE_SIZE, "ATF/tfactor", 0 );
881 ALLOC_STATE( afs[0], afs_pass1, AFS_STATE_SIZE, "AFS/afsinst-0", 0 );
882 ALLOC_STATE( afs[1], afs, AFS_STATE_SIZE, "AFS/afsinst-1", 1 );
883 } else {
884 ALLOC_STATE( atf, never, ATF_STATE_SIZE, "ATF/tfactor", 0 );
885 ALLOC_STATE( afs[0], never, AFS_STATE_SIZE, "AFS/afsinst-0", 0 );
886 ALLOC_STATE( afs[1], never, AFS_STATE_SIZE, "AFS/afsinst-1", 1 );
887 }
888 }
889 }
890 /* polygon stipple is done with irq for non-kms */
891 if (rmesa->radeon.radeonScreen->kernel_mm) {
892 ALLOC_STATE( stp, always, STP_STATE_SIZE, "STP/stp", 0 );
893 }
894
895 for (i = 0; i < 6; i++)
896 if (rmesa->radeon.radeonScreen->kernel_mm)
897 rmesa->hw.tex[i].emit = tex_emit_mm;
898 else
899 rmesa->hw.tex[i].emit = tex_emit;
900 if (rmesa->radeon.radeonScreen->drmSupportsCubeMapsR200) {
901 ALLOC_STATE( cube[0], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-0", 0 );
902 ALLOC_STATE( cube[1], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-1", 1 );
903 ALLOC_STATE( cube[2], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-2", 2 );
904 ALLOC_STATE( cube[3], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-3", 3 );
905 ALLOC_STATE( cube[4], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-4", 4 );
906 ALLOC_STATE( cube[5], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-5", 5 );
907 for (i = 0; i < 6; i++)
908 if (rmesa->radeon.radeonScreen->kernel_mm) {
909 rmesa->hw.cube[i].emit = cube_emit_cs;
910 rmesa->hw.cube[i].check = check_tex_cube_cs;
911 } else
912 rmesa->hw.cube[i].emit = cube_emit;
913 }
914 else {
915 ALLOC_STATE( cube[0], never, CUBE_STATE_SIZE, "CUBE/tex-0", 0 );
916 ALLOC_STATE( cube[1], never, CUBE_STATE_SIZE, "CUBE/tex-1", 1 );
917 ALLOC_STATE( cube[2], never, CUBE_STATE_SIZE, "CUBE/tex-2", 2 );
918 ALLOC_STATE( cube[3], never, CUBE_STATE_SIZE, "CUBE/tex-3", 3 );
919 ALLOC_STATE( cube[4], never, CUBE_STATE_SIZE, "CUBE/tex-4", 4 );
920 ALLOC_STATE( cube[5], never, CUBE_STATE_SIZE, "CUBE/tex-5", 5 );
921 }
922
923 if (rmesa->radeon.radeonScreen->drmSupportsVertexProgram) {
924 ALLOC_STATE( pvs, tcl_vp, PVS_STATE_SIZE, "PVS/pvscntl", 0 );
925 if (rmesa->radeon.radeonScreen->kernel_mm) {
926 ALLOC_STATE( vpi[0], tcl_vp_add4, VPI_STATE_SIZE, "VP/vertexprog-0", 0 );
927 ALLOC_STATE( vpi[1], tcl_vp_size_add4, VPI_STATE_SIZE, "VP/vertexprog-1", 1 );
928 ALLOC_STATE( vpp[0], tcl_vp_add4, VPP_STATE_SIZE, "VPP/vertexparam-0", 0 );
929 ALLOC_STATE( vpp[1], tcl_vpp_size_add4, VPP_STATE_SIZE, "VPP/vertexparam-1", 1 );
930 } else {
931 ALLOC_STATE( vpi[0], tcl_vp, VPI_STATE_SIZE, "VP/vertexprog-0", 0 );
932 ALLOC_STATE( vpi[1], tcl_vp_size, VPI_STATE_SIZE, "VP/vertexprog-1", 1 );
933 ALLOC_STATE( vpp[0], tcl_vp, VPP_STATE_SIZE, "VPP/vertexparam-0", 0 );
934 ALLOC_STATE( vpp[1], tcl_vpp_size, VPP_STATE_SIZE, "VPP/vertexparam-1", 1 );
935 }
936 }
937 else {
938 ALLOC_STATE( pvs, never, PVS_STATE_SIZE, "PVS/pvscntl", 0 );
939 ALLOC_STATE( vpi[0], never, VPI_STATE_SIZE, "VP/vertexprog-0", 0 );
940 ALLOC_STATE( vpi[1], never, VPI_STATE_SIZE, "VP/vertexprog-1", 1 );
941 ALLOC_STATE( vpp[0], never, VPP_STATE_SIZE, "VPP/vertexparam-0", 0 );
942 ALLOC_STATE( vpp[1], never, VPP_STATE_SIZE, "VPP/vertexparam-1", 1 );
943 }
944 /* FIXME: this atom has two commands, we need only one (ucp_vert_blend) for vp */
945 ALLOC_STATE( tcl, tcl_or_vp, TCL_STATE_SIZE, "TCL/tcl", 0 );
946 ALLOC_STATE( msl, tcl, MSL_STATE_SIZE, "MSL/matrix-select", 0 );
947 ALLOC_STATE( tcg, tcl, TCG_STATE_SIZE, "TCG/texcoordgen", 0 );
948 if (rmesa->radeon.radeonScreen->kernel_mm) {
949 ALLOC_STATE( mtl[0], tcl_lighting_add6, MTL_STATE_SIZE, "MTL0/material0", 0 );
950 ALLOC_STATE( mtl[1], tcl_lighting_add6, MTL_STATE_SIZE, "MTL1/material1", 1 );
951 ALLOC_STATE( grd, tcl_or_vp_add2, GRD_STATE_SIZE, "GRD/guard-band", 0 );
952 ALLOC_STATE( fog, tcl_fog_add4, FOG_STATE_SIZE, "FOG/fog", 0 );
953 ALLOC_STATE( glt, tcl_lighting_add4, GLT_STATE_SIZE, "GLT/light-global", 0 );
954 ALLOC_STATE( eye, tcl_lighting_add4, EYE_STATE_SIZE, "EYE/eye-vector", 0 );
955 ALLOC_STATE( mat[R200_MTX_MV], tcl_add4, MAT_STATE_SIZE, "MAT/modelview", 0 );
956 ALLOC_STATE( mat[R200_MTX_IMV], tcl_add4, MAT_STATE_SIZE, "MAT/it-modelview", 0 );
957 ALLOC_STATE( mat[R200_MTX_MVP], tcl_add4, MAT_STATE_SIZE, "MAT/modelproject", 0 );
958 ALLOC_STATE( mat[R200_MTX_TEX0], tcl_tex_add4, MAT_STATE_SIZE, "MAT/texmat0", 0 );
959 ALLOC_STATE( mat[R200_MTX_TEX1], tcl_tex_add4, MAT_STATE_SIZE, "MAT/texmat1", 1 );
960 ALLOC_STATE( mat[R200_MTX_TEX2], tcl_tex_add4, MAT_STATE_SIZE, "MAT/texmat2", 2 );
961 ALLOC_STATE( mat[R200_MTX_TEX3], tcl_tex_add4, MAT_STATE_SIZE, "MAT/texmat3", 3 );
962 ALLOC_STATE( mat[R200_MTX_TEX4], tcl_tex_add4, MAT_STATE_SIZE, "MAT/texmat4", 4 );
963 ALLOC_STATE( mat[R200_MTX_TEX5], tcl_tex_add4, MAT_STATE_SIZE, "MAT/texmat5", 5 );
964 ALLOC_STATE( ucp[0], tcl_ucp_add4, UCP_STATE_SIZE, "UCP/userclip-0", 0 );
965 ALLOC_STATE( ucp[1], tcl_ucp_add4, UCP_STATE_SIZE, "UCP/userclip-1", 1 );
966 ALLOC_STATE( ucp[2], tcl_ucp_add4, UCP_STATE_SIZE, "UCP/userclip-2", 2 );
967 ALLOC_STATE( ucp[3], tcl_ucp_add4, UCP_STATE_SIZE, "UCP/userclip-3", 3 );
968 ALLOC_STATE( ucp[4], tcl_ucp_add4, UCP_STATE_SIZE, "UCP/userclip-4", 4 );
969 ALLOC_STATE( ucp[5], tcl_ucp_add4, UCP_STATE_SIZE, "UCP/userclip-5", 5 );
970 ALLOC_STATE( lit[0], tcl_light_add8, LIT_STATE_SIZE, "LIT/light-0", 0 );
971 ALLOC_STATE( lit[1], tcl_light_add8, LIT_STATE_SIZE, "LIT/light-1", 1 );
972 ALLOC_STATE( lit[2], tcl_light_add8, LIT_STATE_SIZE, "LIT/light-2", 2 );
973 ALLOC_STATE( lit[3], tcl_light_add8, LIT_STATE_SIZE, "LIT/light-3", 3 );
974 ALLOC_STATE( lit[4], tcl_light_add8, LIT_STATE_SIZE, "LIT/light-4", 4 );
975 ALLOC_STATE( lit[5], tcl_light_add8, LIT_STATE_SIZE, "LIT/light-5", 5 );
976 ALLOC_STATE( lit[6], tcl_light_add8, LIT_STATE_SIZE, "LIT/light-6", 6 );
977 ALLOC_STATE( lit[7], tcl_light_add8, LIT_STATE_SIZE, "LIT/light-7", 7 );
978 ALLOC_STATE( sci, rrb, SCI_STATE_SIZE, "SCI/scissor", 0 );
979 } else {
980 ALLOC_STATE( mtl[0], tcl_lighting, MTL_STATE_SIZE, "MTL0/material0", 0 );
981 ALLOC_STATE( mtl[1], tcl_lighting, MTL_STATE_SIZE, "MTL1/material1", 1 );
982 ALLOC_STATE( grd, tcl_or_vp, GRD_STATE_SIZE, "GRD/guard-band", 0 );
983 ALLOC_STATE( fog, tcl_fog, FOG_STATE_SIZE, "FOG/fog", 0 );
984 ALLOC_STATE( glt, tcl_lighting, GLT_STATE_SIZE, "GLT/light-global", 0 );
985 ALLOC_STATE( eye, tcl_lighting, EYE_STATE_SIZE, "EYE/eye-vector", 0 );
986 ALLOC_STATE( mat[R200_MTX_MV], tcl, MAT_STATE_SIZE, "MAT/modelview", 0 );
987 ALLOC_STATE( mat[R200_MTX_IMV], tcl, MAT_STATE_SIZE, "MAT/it-modelview", 0 );
988 ALLOC_STATE( mat[R200_MTX_MVP], tcl, MAT_STATE_SIZE, "MAT/modelproject", 0 );
989 ALLOC_STATE( mat[R200_MTX_TEX0], tcl_tex, MAT_STATE_SIZE, "MAT/texmat0", 0 );
990 ALLOC_STATE( mat[R200_MTX_TEX1], tcl_tex, MAT_STATE_SIZE, "MAT/texmat1", 1 );
991 ALLOC_STATE( mat[R200_MTX_TEX2], tcl_tex, MAT_STATE_SIZE, "MAT/texmat2", 2 );
992 ALLOC_STATE( mat[R200_MTX_TEX3], tcl_tex, MAT_STATE_SIZE, "MAT/texmat3", 3 );
993 ALLOC_STATE( mat[R200_MTX_TEX4], tcl_tex, MAT_STATE_SIZE, "MAT/texmat4", 4 );
994 ALLOC_STATE( mat[R200_MTX_TEX5], tcl_tex, MAT_STATE_SIZE, "MAT/texmat5", 5 );
995 ALLOC_STATE( ucp[0], tcl_ucp, UCP_STATE_SIZE, "UCP/userclip-0", 0 );
996 ALLOC_STATE( ucp[1], tcl_ucp, UCP_STATE_SIZE, "UCP/userclip-1", 1 );
997 ALLOC_STATE( ucp[2], tcl_ucp, UCP_STATE_SIZE, "UCP/userclip-2", 2 );
998 ALLOC_STATE( ucp[3], tcl_ucp, UCP_STATE_SIZE, "UCP/userclip-3", 3 );
999 ALLOC_STATE( ucp[4], tcl_ucp, UCP_STATE_SIZE, "UCP/userclip-4", 4 );
1000 ALLOC_STATE( ucp[5], tcl_ucp, UCP_STATE_SIZE, "UCP/userclip-5", 5 );
1001 ALLOC_STATE( lit[0], tcl_light, LIT_STATE_SIZE, "LIT/light-0", 0 );
1002 ALLOC_STATE( lit[1], tcl_light, LIT_STATE_SIZE, "LIT/light-1", 1 );
1003 ALLOC_STATE( lit[2], tcl_light, LIT_STATE_SIZE, "LIT/light-2", 2 );
1004 ALLOC_STATE( lit[3], tcl_light, LIT_STATE_SIZE, "LIT/light-3", 3 );
1005 ALLOC_STATE( lit[4], tcl_light, LIT_STATE_SIZE, "LIT/light-4", 4 );
1006 ALLOC_STATE( lit[5], tcl_light, LIT_STATE_SIZE, "LIT/light-5", 5 );
1007 ALLOC_STATE( lit[6], tcl_light, LIT_STATE_SIZE, "LIT/light-6", 6 );
1008 ALLOC_STATE( lit[7], tcl_light, LIT_STATE_SIZE, "LIT/light-7", 7 );
1009 ALLOC_STATE( sci, never, SCI_STATE_SIZE, "SCI/scissor", 0 );
1010 }
1011 ALLOC_STATE( pix[0], pix_zero, PIX_STATE_SIZE, "PIX/pixstage-0", 0 );
1012 ALLOC_STATE( pix[1], texenv, PIX_STATE_SIZE, "PIX/pixstage-1", 1 );
1013 ALLOC_STATE( pix[2], texenv, PIX_STATE_SIZE, "PIX/pixstage-2", 2 );
1014 ALLOC_STATE( pix[3], texenv, PIX_STATE_SIZE, "PIX/pixstage-3", 3 );
1015 ALLOC_STATE( pix[4], texenv, PIX_STATE_SIZE, "PIX/pixstage-4", 4 );
1016 ALLOC_STATE( pix[5], texenv, PIX_STATE_SIZE, "PIX/pixstage-5", 5 );
1017 if (rmesa->radeon.radeonScreen->drmSupportsTriPerf) {
1018 ALLOC_STATE( prf, always, PRF_STATE_SIZE, "PRF/performance-tri", 0 );
1019 }
1020 else {
1021 ALLOC_STATE( prf, never, PRF_STATE_SIZE, "PRF/performance-tri", 0 );
1022 }
1023 if (rmesa->radeon.radeonScreen->drmSupportsPointSprites) {
1024 ALLOC_STATE( spr, always, SPR_STATE_SIZE, "SPR/pointsprite", 0 );
1025 if (rmesa->radeon.radeonScreen->kernel_mm)
1026 ALLOC_STATE( ptp, tcl_add8, PTP_STATE_SIZE, "PTP/pointparams", 0 );
1027 else
1028 ALLOC_STATE( ptp, tcl, PTP_STATE_SIZE, "PTP/pointparams", 0 );
1029 }
1030 else {
1031 ALLOC_STATE (spr, never, SPR_STATE_SIZE, "SPR/pointsprite", 0 );
1032 ALLOC_STATE (ptp, never, PTP_STATE_SIZE, "PTP/pointparams", 0 );
1033 }
1034
1035 r200SetUpAtomList( rmesa );
1036
1037 /* Fill in the packet headers:
1038 */
1039 rmesa->hw.ctx.cmd[CTX_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_MISC);
1040 rmesa->hw.ctx.cmd[CTX_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_PP_CNTL);
1041 rmesa->hw.ctx.cmd[CTX_CMD_2] = cmdpkt(rmesa, RADEON_EMIT_RB3D_COLORPITCH);
1042 if (rmesa->radeon.radeonScreen->drmSupportsBlendColor)
1043 rmesa->hw.ctx.cmd[CTX_CMD_3] = cmdpkt(rmesa, R200_EMIT_RB3D_BLENDCOLOR);
1044 rmesa->hw.lin.cmd[LIN_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_RE_LINE_PATTERN);
1045 rmesa->hw.lin.cmd[LIN_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_SE_LINE_WIDTH);
1046 rmesa->hw.msk.cmd[MSK_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_RB3D_STENCILREFMASK);
1047 rmesa->hw.vpt.cmd[VPT_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_SE_VPORT_XSCALE);
1048 rmesa->hw.set.cmd[SET_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_SE_CNTL);
1049 rmesa->hw.msc.cmd[MSC_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_RE_MISC);
1050 rmesa->hw.cst.cmd[CST_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_CNTL_X);
1051 rmesa->hw.cst.cmd[CST_CMD_1] = cmdpkt(rmesa, R200_EMIT_RB3D_DEPTHXY_OFFSET);
1052 rmesa->hw.cst.cmd[CST_CMD_2] = cmdpkt(rmesa, R200_EMIT_RE_AUX_SCISSOR_CNTL);
1053 rmesa->hw.cst.cmd[CST_CMD_3] = cmdpkt(rmesa, R200_EMIT_RE_SCISSOR_TL_0);
1054 rmesa->hw.cst.cmd[CST_CMD_4] = cmdpkt(rmesa, R200_EMIT_SE_VAP_CNTL_STATUS);
1055 rmesa->hw.cst.cmd[CST_CMD_5] = cmdpkt(rmesa, R200_EMIT_RE_POINTSIZE);
1056 rmesa->hw.cst.cmd[CST_CMD_6] = cmdpkt(rmesa, R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0);
1057 rmesa->hw.tam.cmd[TAM_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TAM_DEBUG3);
1058 rmesa->hw.tf.cmd[TF_CMD_0] = cmdpkt(rmesa, R200_EMIT_TFACTOR_0);
1059 if (rmesa->radeon.radeonScreen->drmSupportsFragShader) {
1060 rmesa->hw.atf.cmd[ATF_CMD_0] = cmdpkt(rmesa, R200_EMIT_ATF_TFACTOR);
1061 rmesa->hw.tex[0].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCTLALL_0);
1062 rmesa->hw.tex[0].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_0);
1063 rmesa->hw.tex[1].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCTLALL_1);
1064 rmesa->hw.tex[1].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_1);
1065 rmesa->hw.tex[2].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCTLALL_2);
1066 rmesa->hw.tex[2].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_2);
1067 rmesa->hw.tex[3].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCTLALL_3);
1068 rmesa->hw.tex[3].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_3);
1069 rmesa->hw.tex[4].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCTLALL_4);
1070 rmesa->hw.tex[4].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_4);
1071 rmesa->hw.tex[5].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCTLALL_5);
1072 rmesa->hw.tex[5].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_5);
1073 } else {
1074 rmesa->hw.tex[0].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXFILTER_0);
1075 rmesa->hw.tex[0].cmd[TEX_CMD_1_OLDDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_0);
1076 rmesa->hw.tex[1].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXFILTER_1);
1077 rmesa->hw.tex[1].cmd[TEX_CMD_1_OLDDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_1);
1078 rmesa->hw.tex[2].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXFILTER_2);
1079 rmesa->hw.tex[2].cmd[TEX_CMD_1_OLDDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_2);
1080 rmesa->hw.tex[3].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXFILTER_3);
1081 rmesa->hw.tex[3].cmd[TEX_CMD_1_OLDDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_3);
1082 rmesa->hw.tex[4].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXFILTER_4);
1083 rmesa->hw.tex[4].cmd[TEX_CMD_1_OLDDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_4);
1084 rmesa->hw.tex[5].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXFILTER_5);
1085 rmesa->hw.tex[5].cmd[TEX_CMD_1_OLDDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_5);
1086 }
1087 rmesa->hw.afs[0].cmd[AFS_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_AFS_0);
1088 rmesa->hw.afs[1].cmd[AFS_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_AFS_1);
1089 rmesa->hw.pvs.cmd[PVS_CMD_0] = cmdpkt(rmesa, R200_EMIT_VAP_PVS_CNTL);
1090 rmesa->hw.cube[0].cmd[CUBE_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_FACES_0);
1091 rmesa->hw.cube[0].cmd[CUBE_CMD_1] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_OFFSETS_0);
1092 rmesa->hw.cube[1].cmd[CUBE_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_FACES_1);
1093 rmesa->hw.cube[1].cmd[CUBE_CMD_1] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_OFFSETS_1);
1094 rmesa->hw.cube[2].cmd[CUBE_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_FACES_2);
1095 rmesa->hw.cube[2].cmd[CUBE_CMD_1] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_OFFSETS_2);
1096 rmesa->hw.cube[3].cmd[CUBE_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_FACES_3);
1097 rmesa->hw.cube[3].cmd[CUBE_CMD_1] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_OFFSETS_3);
1098 rmesa->hw.cube[4].cmd[CUBE_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_FACES_4);
1099 rmesa->hw.cube[4].cmd[CUBE_CMD_1] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_OFFSETS_4);
1100 rmesa->hw.cube[5].cmd[CUBE_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_FACES_5);
1101 rmesa->hw.cube[5].cmd[CUBE_CMD_1] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_OFFSETS_5);
1102 rmesa->hw.pix[0].cmd[PIX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCBLEND_0);
1103 rmesa->hw.pix[1].cmd[PIX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCBLEND_1);
1104 rmesa->hw.pix[2].cmd[PIX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCBLEND_2);
1105 rmesa->hw.pix[3].cmd[PIX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCBLEND_3);
1106 rmesa->hw.pix[4].cmd[PIX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCBLEND_4);
1107 rmesa->hw.pix[5].cmd[PIX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCBLEND_5);
1108 rmesa->hw.zbs.cmd[ZBS_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_SE_ZBIAS_FACTOR);
1109 rmesa->hw.tcl.cmd[TCL_CMD_0] = cmdpkt(rmesa, R200_EMIT_TCL_LIGHT_MODEL_CTL_0);
1110 rmesa->hw.tcl.cmd[TCL_CMD_1] = cmdpkt(rmesa, R200_EMIT_TCL_UCP_VERT_BLEND_CTL);
1111 rmesa->hw.tcg.cmd[TCG_CMD_0] = cmdpkt(rmesa, R200_EMIT_TEX_PROC_CTL_2);
1112 rmesa->hw.msl.cmd[MSL_CMD_0] = cmdpkt(rmesa, R200_EMIT_MATRIX_SELECT_0);
1113 rmesa->hw.vap.cmd[VAP_CMD_0] = cmdpkt(rmesa, R200_EMIT_VAP_CTL);
1114 rmesa->hw.vtx.cmd[VTX_CMD_0] = cmdpkt(rmesa, R200_EMIT_VTX_FMT_0);
1115 rmesa->hw.vtx.cmd[VTX_CMD_1] = cmdpkt(rmesa, R200_EMIT_OUTPUT_VTX_COMP_SEL);
1116 rmesa->hw.vtx.cmd[VTX_CMD_2] = cmdpkt(rmesa, R200_EMIT_SE_VTX_STATE_CNTL);
1117 rmesa->hw.vte.cmd[VTE_CMD_0] = cmdpkt(rmesa, R200_EMIT_VTE_CNTL);
1118 rmesa->hw.prf.cmd[PRF_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TRI_PERF_CNTL);
1119 rmesa->hw.spr.cmd[SPR_CMD_0] = cmdpkt(rmesa, R200_EMIT_TCL_POINT_SPRITE_CNTL);
1120
1121 rmesa->hw.sci.cmd[SCI_CMD_0] = CP_PACKET0(R200_RE_AUX_SCISSOR_CNTL, 0);
1122 rmesa->hw.sci.cmd[SCI_CMD_1] = CP_PACKET0(R200_RE_TOP_LEFT, 0);
1123 rmesa->hw.sci.cmd[SCI_CMD_2] = CP_PACKET0(R200_RE_WIDTH_HEIGHT, 0);
1124
1125 if (rmesa->radeon.radeonScreen->kernel_mm) {
1126
1127 rmesa->hw.stp.cmd[STP_CMD_0] = CP_PACKET0(RADEON_RE_STIPPLE_ADDR, 0);
1128 rmesa->hw.stp.cmd[STP_DATA_0] = 0;
1129 rmesa->hw.stp.cmd[STP_CMD_1] = CP_PACKET0_ONE(RADEON_RE_STIPPLE_DATA, 31);
1130
1131 rmesa->hw.mtl[0].emit = mtl_emit;
1132 rmesa->hw.mtl[1].emit = mtl_emit;
1133
1134 rmesa->hw.vpi[0].emit = veclinear_emit;
1135 rmesa->hw.vpi[1].emit = veclinear_emit;
1136 rmesa->hw.vpp[0].emit = veclinear_emit;
1137 rmesa->hw.vpp[1].emit = veclinear_emit;
1138
1139 rmesa->hw.grd.emit = scl_emit;
1140 rmesa->hw.fog.emit = vec_emit;
1141 rmesa->hw.glt.emit = vec_emit;
1142 rmesa->hw.eye.emit = vec_emit;
1143
1144 for (i = R200_MTX_MV; i <= R200_MTX_TEX5; i++)
1145 rmesa->hw.mat[i].emit = vec_emit;
1146
1147 for (i = 0; i < 8; i++)
1148 rmesa->hw.lit[i].emit = lit_emit;
1149
1150 for (i = 0; i < 6; i++)
1151 rmesa->hw.ucp[i].emit = vec_emit;
1152
1153 rmesa->hw.ptp.emit = ptp_emit;
1154 }
1155
1156
1157
1158 rmesa->hw.mtl[0].cmd[MTL_CMD_0] =
1159 cmdvec( R200_VS_MAT_0_EMISS, 1, 16 );
1160 rmesa->hw.mtl[0].cmd[MTL_CMD_1] =
1161 cmdscl2( R200_SS_MAT_0_SHININESS, 1, 1 );
1162 rmesa->hw.mtl[1].cmd[MTL_CMD_0] =
1163 cmdvec( R200_VS_MAT_1_EMISS, 1, 16 );
1164 rmesa->hw.mtl[1].cmd[MTL_CMD_1] =
1165 cmdscl2( R200_SS_MAT_1_SHININESS, 1, 1 );
1166
1167 rmesa->hw.vpi[0].cmd[VPI_CMD_0] =
1168 cmdveclinear( R200_PVS_PROG0, 64 );
1169 rmesa->hw.vpi[1].cmd[VPI_CMD_0] =
1170 cmdveclinear( R200_PVS_PROG1, 64 );
1171 rmesa->hw.vpp[0].cmd[VPP_CMD_0] =
1172 cmdveclinear( R200_PVS_PARAM0, 96 );
1173 rmesa->hw.vpp[1].cmd[VPP_CMD_0] =
1174 cmdveclinear( R200_PVS_PARAM1, 96 );
1175
1176 rmesa->hw.grd.cmd[GRD_CMD_0] =
1177 cmdscl( R200_SS_VERT_GUARD_CLIP_ADJ_ADDR, 1, 4 );
1178 rmesa->hw.fog.cmd[FOG_CMD_0] =
1179 cmdvec( R200_VS_FOG_PARAM_ADDR, 1, 4 );
1180 rmesa->hw.glt.cmd[GLT_CMD_0] =
1181 cmdvec( R200_VS_GLOBAL_AMBIENT_ADDR, 1, 4 );
1182 rmesa->hw.eye.cmd[EYE_CMD_0] =
1183 cmdvec( R200_VS_EYE_VECTOR_ADDR, 1, 4 );
1184
1185 rmesa->hw.mat[R200_MTX_MV].cmd[MAT_CMD_0] =
1186 cmdvec( R200_VS_MATRIX_0_MV, 1, 16);
1187 rmesa->hw.mat[R200_MTX_IMV].cmd[MAT_CMD_0] =
1188 cmdvec( R200_VS_MATRIX_1_INV_MV, 1, 16);
1189 rmesa->hw.mat[R200_MTX_MVP].cmd[MAT_CMD_0] =
1190 cmdvec( R200_VS_MATRIX_2_MVP, 1, 16);
1191 rmesa->hw.mat[R200_MTX_TEX0].cmd[MAT_CMD_0] =
1192 cmdvec( R200_VS_MATRIX_3_TEX0, 1, 16);
1193 rmesa->hw.mat[R200_MTX_TEX1].cmd[MAT_CMD_0] =
1194 cmdvec( R200_VS_MATRIX_4_TEX1, 1, 16);
1195 rmesa->hw.mat[R200_MTX_TEX2].cmd[MAT_CMD_0] =
1196 cmdvec( R200_VS_MATRIX_5_TEX2, 1, 16);
1197 rmesa->hw.mat[R200_MTX_TEX3].cmd[MAT_CMD_0] =
1198 cmdvec( R200_VS_MATRIX_6_TEX3, 1, 16);
1199 rmesa->hw.mat[R200_MTX_TEX4].cmd[MAT_CMD_0] =
1200 cmdvec( R200_VS_MATRIX_7_TEX4, 1, 16);
1201 rmesa->hw.mat[R200_MTX_TEX5].cmd[MAT_CMD_0] =
1202 cmdvec( R200_VS_MATRIX_8_TEX5, 1, 16);
1203
1204 for (i = 0 ; i < 8; i++) {
1205 rmesa->hw.lit[i].cmd[LIT_CMD_0] =
1206 cmdvec( R200_VS_LIGHT_AMBIENT_ADDR + i, 8, 24 );
1207 rmesa->hw.lit[i].cmd[LIT_CMD_1] =
1208 cmdscl( R200_SS_LIGHT_DCD_ADDR + i, 8, 7 );
1209 }
1210
1211 for (i = 0 ; i < 6; i++) {
1212 rmesa->hw.ucp[i].cmd[UCP_CMD_0] =
1213 cmdvec( R200_VS_UCP_ADDR + i, 1, 4 );
1214 }
1215
1216 rmesa->hw.ptp.cmd[PTP_CMD_0] =
1217 cmdvec( R200_VS_PNT_SPRITE_VPORT_SCALE, 1, 4 );
1218 rmesa->hw.ptp.cmd[PTP_CMD_1] =
1219 cmdvec( R200_VS_PNT_SPRITE_ATT_CONST, 1, 12 );
1220
1221 /* Initial Harware state:
1222 */
1223 rmesa->hw.ctx.cmd[CTX_PP_MISC] = (R200_ALPHA_TEST_PASS
1224 /* | R200_RIGHT_HAND_CUBE_OGL*/);
1225
1226 rmesa->hw.ctx.cmd[CTX_PP_FOG_COLOR] = (R200_FOG_VERTEX |
1227 R200_FOG_USE_SPEC_ALPHA);
1228
1229 rmesa->hw.ctx.cmd[CTX_RE_SOLID_COLOR] = 0x00000000;
1230
1231 rmesa->hw.ctx.cmd[CTX_RB3D_BLENDCNTL] = (R200_COMB_FCN_ADD_CLAMP |
1232 (R200_BLEND_GL_ONE << R200_SRC_BLEND_SHIFT) |
1233 (R200_BLEND_GL_ZERO << R200_DST_BLEND_SHIFT));
1234
1235 if (rmesa->radeon.radeonScreen->drmSupportsBlendColor) {
1236 rmesa->hw.ctx.cmd[CTX_RB3D_BLENDCOLOR] = 0x00000000;
1237 rmesa->hw.ctx.cmd[CTX_RB3D_ABLENDCNTL] = (R200_COMB_FCN_ADD_CLAMP |
1238 (R200_BLEND_GL_ONE << R200_SRC_BLEND_SHIFT) |
1239 (R200_BLEND_GL_ZERO << R200_DST_BLEND_SHIFT));
1240 rmesa->hw.ctx.cmd[CTX_RB3D_CBLENDCNTL] = (R200_COMB_FCN_ADD_CLAMP |
1241 (R200_BLEND_GL_ONE << R200_SRC_BLEND_SHIFT) |
1242 (R200_BLEND_GL_ZERO << R200_DST_BLEND_SHIFT));
1243 }
1244
1245 rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHOFFSET] =
1246 rmesa->radeon.radeonScreen->depthOffset + rmesa->radeon.radeonScreen->fbLocation;
1247
1248 rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHPITCH] =
1249 ((rmesa->radeon.radeonScreen->depthPitch &
1250 R200_DEPTHPITCH_MASK) |
1251 R200_DEPTH_ENDIAN_NO_SWAP);
1252
1253 if (rmesa->using_hyperz)
1254 rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHPITCH] |= R200_DEPTH_HYPERZ;
1255
1256 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] = (R200_Z_TEST_LESS |
1257 R200_STENCIL_TEST_ALWAYS |
1258 R200_STENCIL_FAIL_KEEP |
1259 R200_STENCIL_ZPASS_KEEP |
1260 R200_STENCIL_ZFAIL_KEEP |
1261 R200_Z_WRITE_ENABLE);
1262
1263 if (rmesa->using_hyperz) {
1264 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= R200_Z_COMPRESSION_ENABLE |
1265 R200_Z_DECOMPRESSION_ENABLE;
1266 /* if (rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_R200)
1267 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_HIERARCHY_ENABLE;*/
1268 }
1269
1270 rmesa->hw.ctx.cmd[CTX_PP_CNTL] = (R200_ANTI_ALIAS_NONE
1271 | R200_TEX_BLEND_0_ENABLE);
1272
1273 switch ( driQueryOptioni( &rmesa->radeon.optionCache, "dither_mode" ) ) {
1274 case DRI_CONF_DITHER_XERRORDIFFRESET:
1275 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= R200_DITHER_INIT;
1276 break;
1277 case DRI_CONF_DITHER_ORDERED:
1278 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= R200_SCALE_DITHER_ENABLE;
1279 break;
1280 }
1281 if ( driQueryOptioni( &rmesa->radeon.optionCache, "round_mode" ) ==
1282 DRI_CONF_ROUND_ROUND )
1283 rmesa->radeon.state.color.roundEnable = R200_ROUND_ENABLE;
1284 else
1285 rmesa->radeon.state.color.roundEnable = 0;
1286 if ( driQueryOptioni (&rmesa->radeon.optionCache, "color_reduction" ) ==
1287 DRI_CONF_COLOR_REDUCTION_DITHER )
1288 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= R200_DITHER_ENABLE;
1289 else
1290 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= rmesa->radeon.state.color.roundEnable;
1291
1292 rmesa->hw.prf.cmd[PRF_PP_TRI_PERF] = R200_TRI_CUTOFF_MASK - R200_TRI_CUTOFF_MASK *
1293 driQueryOptionf (&rmesa->radeon.optionCache,"texture_blend_quality");
1294 rmesa->hw.prf.cmd[PRF_PP_PERF_CNTL] = 0;
1295
1296 rmesa->hw.set.cmd[SET_SE_CNTL] = (R200_FFACE_CULL_CCW |
1297 R200_BFACE_SOLID |
1298 R200_FFACE_SOLID |
1299 R200_FLAT_SHADE_VTX_LAST |
1300 R200_DIFFUSE_SHADE_GOURAUD |
1301 R200_ALPHA_SHADE_GOURAUD |
1302 R200_SPECULAR_SHADE_GOURAUD |
1303 R200_FOG_SHADE_GOURAUD |
1304 R200_DISC_FOG_SHADE_GOURAUD |
1305 R200_VTX_PIX_CENTER_OGL |
1306 R200_ROUND_MODE_TRUNC |
1307 R200_ROUND_PREC_8TH_PIX);
1308
1309 rmesa->hw.set.cmd[SET_RE_CNTL] = (R200_PERSPECTIVE_ENABLE |
1310 R200_SCISSOR_ENABLE);
1311
1312 rmesa->hw.lin.cmd[LIN_RE_LINE_PATTERN] = ((1 << 16) | 0xffff);
1313
1314 rmesa->hw.lin.cmd[LIN_RE_LINE_STATE] =
1315 ((0 << R200_LINE_CURRENT_PTR_SHIFT) |
1316 (1 << R200_LINE_CURRENT_COUNT_SHIFT));
1317
1318 rmesa->hw.lin.cmd[LIN_SE_LINE_WIDTH] = (1 << 4);
1319
1320 rmesa->hw.msk.cmd[MSK_RB3D_STENCILREFMASK] =
1321 ((0x00 << R200_STENCIL_REF_SHIFT) |
1322 (0xff << R200_STENCIL_MASK_SHIFT) |
1323 (0xff << R200_STENCIL_WRITEMASK_SHIFT));
1324
1325 rmesa->hw.msk.cmd[MSK_RB3D_ROPCNTL] = R200_ROP_COPY;
1326 rmesa->hw.msk.cmd[MSK_RB3D_PLANEMASK] = 0xffffffff;
1327
1328 rmesa->hw.tam.cmd[TAM_DEBUG3] = 0;
1329
1330 rmesa->hw.msc.cmd[MSC_RE_MISC] =
1331 ((0 << R200_STIPPLE_X_OFFSET_SHIFT) |
1332 (0 << R200_STIPPLE_Y_OFFSET_SHIFT) |
1333 R200_STIPPLE_BIG_BIT_ORDER);
1334
1335
1336 rmesa->hw.cst.cmd[CST_PP_CNTL_X] = 0;
1337 rmesa->hw.cst.cmd[CST_RB3D_DEPTHXY_OFFSET] = 0;
1338 rmesa->hw.cst.cmd[CST_RE_AUX_SCISSOR_CNTL] = 0x0;
1339 rmesa->hw.cst.cmd[CST_RE_SCISSOR_TL_0] = 0;
1340 rmesa->hw.cst.cmd[CST_RE_SCISSOR_BR_0] = 0;
1341 rmesa->hw.cst.cmd[CST_SE_VAP_CNTL_STATUS] =
1342 #ifdef MESA_BIG_ENDIAN
1343 R200_VC_32BIT_SWAP;
1344 #else
1345 R200_VC_NO_SWAP;
1346 #endif
1347
1348 if (!(rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL)) {
1349 /* Bypass TCL */
1350 rmesa->hw.cst.cmd[CST_SE_VAP_CNTL_STATUS] |= (1<<8);
1351 }
1352
1353 rmesa->hw.cst.cmd[CST_RE_POINTSIZE] =
1354 (((GLuint)(ctx->Const.MaxPointSize * 16.0)) << R200_MAXPOINTSIZE_SHIFT) | 0x10;
1355 rmesa->hw.cst.cmd[CST_SE_TCL_INPUT_VTX_0] =
1356 (0x0 << R200_VERTEX_POSITION_ADDR__SHIFT);
1357 rmesa->hw.cst.cmd[CST_SE_TCL_INPUT_VTX_1] =
1358 (0x02 << R200_VTX_COLOR_0_ADDR__SHIFT) |
1359 (0x03 << R200_VTX_COLOR_1_ADDR__SHIFT);
1360 rmesa->hw.cst.cmd[CST_SE_TCL_INPUT_VTX_2] =
1361 (0x06 << R200_VTX_TEX_0_ADDR__SHIFT) |
1362 (0x07 << R200_VTX_TEX_1_ADDR__SHIFT) |
1363 (0x08 << R200_VTX_TEX_2_ADDR__SHIFT) |
1364 (0x09 << R200_VTX_TEX_3_ADDR__SHIFT);
1365 rmesa->hw.cst.cmd[CST_SE_TCL_INPUT_VTX_3] =
1366 (0x0A << R200_VTX_TEX_4_ADDR__SHIFT) |
1367 (0x0B << R200_VTX_TEX_5_ADDR__SHIFT);
1368
1369
1370 rmesa->hw.vpt.cmd[VPT_SE_VPORT_XSCALE] = 0x00000000;
1371 rmesa->hw.vpt.cmd[VPT_SE_VPORT_XOFFSET] = 0x00000000;
1372 rmesa->hw.vpt.cmd[VPT_SE_VPORT_YSCALE] = 0x00000000;
1373 rmesa->hw.vpt.cmd[VPT_SE_VPORT_YOFFSET] = 0x00000000;
1374 rmesa->hw.vpt.cmd[VPT_SE_VPORT_ZSCALE] = 0x00000000;
1375 rmesa->hw.vpt.cmd[VPT_SE_VPORT_ZOFFSET] = 0x00000000;
1376
1377 for ( i = 0 ; i < ctx->Const.MaxTextureUnits ; i++ ) {
1378 rmesa->hw.tex[i].cmd[TEX_PP_TXFILTER] = R200_BORDER_MODE_OGL;
1379 rmesa->hw.tex[i].cmd[TEX_PP_TXFORMAT] =
1380 ((i << R200_TXFORMAT_ST_ROUTE_SHIFT) | /* <-- note i */
1381 (2 << R200_TXFORMAT_WIDTH_SHIFT) |
1382 (2 << R200_TXFORMAT_HEIGHT_SHIFT));
1383 rmesa->hw.tex[i].cmd[TEX_PP_BORDER_COLOR] = 0;
1384 rmesa->hw.tex[i].cmd[TEX_PP_TXFORMAT_X] =
1385 (/* R200_TEXCOORD_PROJ | */
1386 0x100000); /* Small default bias */
1387 if (rmesa->radeon.radeonScreen->drmSupportsFragShader) {
1388 rmesa->hw.tex[i].cmd[TEX_PP_TXOFFSET_NEWDRM] =
1389 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
1390 rmesa->hw.tex[i].cmd[TEX_PP_CUBIC_FACES] = 0;
1391 rmesa->hw.tex[i].cmd[TEX_PP_TXMULTI_CTL] = 0;
1392 }
1393 else {
1394 rmesa->hw.tex[i].cmd[TEX_PP_TXOFFSET_OLDDRM] =
1395 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
1396 }
1397
1398 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_FACES] = 0;
1399 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F1] =
1400 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
1401 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F2] =
1402 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
1403 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F3] =
1404 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
1405 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F4] =
1406 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
1407 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F5] =
1408 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
1409
1410 rmesa->hw.pix[i].cmd[PIX_PP_TXCBLEND] =
1411 (R200_TXC_ARG_A_ZERO |
1412 R200_TXC_ARG_B_ZERO |
1413 R200_TXC_ARG_C_DIFFUSE_COLOR |
1414 R200_TXC_OP_MADD);
1415
1416 rmesa->hw.pix[i].cmd[PIX_PP_TXCBLEND2] =
1417 ((i << R200_TXC_TFACTOR_SEL_SHIFT) |
1418 R200_TXC_SCALE_1X |
1419 R200_TXC_CLAMP_0_1 |
1420 R200_TXC_OUTPUT_REG_R0);
1421
1422 rmesa->hw.pix[i].cmd[PIX_PP_TXABLEND] =
1423 (R200_TXA_ARG_A_ZERO |
1424 R200_TXA_ARG_B_ZERO |
1425 R200_TXA_ARG_C_DIFFUSE_ALPHA |
1426 R200_TXA_OP_MADD);
1427
1428 rmesa->hw.pix[i].cmd[PIX_PP_TXABLEND2] =
1429 ((i << R200_TXA_TFACTOR_SEL_SHIFT) |
1430 R200_TXA_SCALE_1X |
1431 R200_TXA_CLAMP_0_1 |
1432 R200_TXA_OUTPUT_REG_R0);
1433 }
1434
1435 rmesa->hw.tf.cmd[TF_TFACTOR_0] = 0;
1436 rmesa->hw.tf.cmd[TF_TFACTOR_1] = 0;
1437 rmesa->hw.tf.cmd[TF_TFACTOR_2] = 0;
1438 rmesa->hw.tf.cmd[TF_TFACTOR_3] = 0;
1439 rmesa->hw.tf.cmd[TF_TFACTOR_4] = 0;
1440 rmesa->hw.tf.cmd[TF_TFACTOR_5] = 0;
1441
1442 rmesa->hw.vap.cmd[VAP_SE_VAP_CNTL] =
1443 (R200_VAP_TCL_ENABLE |
1444 (0x9 << R200_VAP_VF_MAX_VTX_NUM__SHIFT));
1445
1446 rmesa->hw.vte.cmd[VTE_SE_VTE_CNTL] =
1447 (R200_VPORT_X_SCALE_ENA |
1448 R200_VPORT_Y_SCALE_ENA |
1449 R200_VPORT_Z_SCALE_ENA |
1450 R200_VPORT_X_OFFSET_ENA |
1451 R200_VPORT_Y_OFFSET_ENA |
1452 R200_VPORT_Z_OFFSET_ENA |
1453 /* FIXME: Turn on for tex rect only */
1454 R200_VTX_ST_DENORMALIZED |
1455 R200_VTX_W0_FMT);
1456
1457
1458 rmesa->hw.vtx.cmd[VTX_VTXFMT_0] = 0;
1459 rmesa->hw.vtx.cmd[VTX_VTXFMT_1] = 0;
1460 rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_VTXFMT_0] =
1461 ((R200_VTX_Z0 | R200_VTX_W0 |
1462 (R200_VTX_FP_RGBA << R200_VTX_COLOR_0_SHIFT)));
1463 rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_VTXFMT_1] = 0;
1464 rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_COMPSEL] = (R200_OUTPUT_XYZW);
1465 rmesa->hw.vtx.cmd[VTX_STATE_CNTL] = R200_VSC_UPDATE_USER_COLOR_0_ENABLE;
1466
1467
1468 /* Matrix selection */
1469 rmesa->hw.msl.cmd[MSL_MATRIX_SELECT_0] =
1470 (R200_MTX_MV << R200_MODELVIEW_0_SHIFT);
1471
1472 rmesa->hw.msl.cmd[MSL_MATRIX_SELECT_1] =
1473 (R200_MTX_IMV << R200_IT_MODELVIEW_0_SHIFT);
1474
1475 rmesa->hw.msl.cmd[MSL_MATRIX_SELECT_2] =
1476 (R200_MTX_MVP << R200_MODELPROJECT_0_SHIFT);
1477
1478 rmesa->hw.msl.cmd[MSL_MATRIX_SELECT_3] =
1479 ((R200_MTX_TEX0 << R200_TEXMAT_0_SHIFT) |
1480 (R200_MTX_TEX1 << R200_TEXMAT_1_SHIFT) |
1481 (R200_MTX_TEX2 << R200_TEXMAT_2_SHIFT) |
1482 (R200_MTX_TEX3 << R200_TEXMAT_3_SHIFT));
1483
1484 rmesa->hw.msl.cmd[MSL_MATRIX_SELECT_4] =
1485 ((R200_MTX_TEX4 << R200_TEXMAT_4_SHIFT) |
1486 (R200_MTX_TEX5 << R200_TEXMAT_5_SHIFT));
1487
1488
1489 /* General TCL state */
1490 rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL_0] =
1491 (R200_SPECULAR_LIGHTS |
1492 R200_DIFFUSE_SPECULAR_COMBINE |
1493 R200_LOCAL_LIGHT_VEC_GL |
1494 R200_LM0_SOURCE_MATERIAL_0 << R200_FRONT_SHININESS_SOURCE_SHIFT |
1495 R200_LM0_SOURCE_MATERIAL_1 << R200_BACK_SHININESS_SOURCE_SHIFT);
1496
1497 rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL_1] =
1498 ((R200_LM1_SOURCE_MATERIAL_0 << R200_FRONT_EMISSIVE_SOURCE_SHIFT) |
1499 (R200_LM1_SOURCE_MATERIAL_0 << R200_FRONT_AMBIENT_SOURCE_SHIFT) |
1500 (R200_LM1_SOURCE_MATERIAL_0 << R200_FRONT_DIFFUSE_SOURCE_SHIFT) |
1501 (R200_LM1_SOURCE_MATERIAL_0 << R200_FRONT_SPECULAR_SOURCE_SHIFT) |
1502 (R200_LM1_SOURCE_MATERIAL_1 << R200_BACK_EMISSIVE_SOURCE_SHIFT) |
1503 (R200_LM1_SOURCE_MATERIAL_1 << R200_BACK_AMBIENT_SOURCE_SHIFT) |
1504 (R200_LM1_SOURCE_MATERIAL_1 << R200_BACK_DIFFUSE_SOURCE_SHIFT) |
1505 (R200_LM1_SOURCE_MATERIAL_1 << R200_BACK_SPECULAR_SOURCE_SHIFT));
1506
1507 rmesa->hw.tcl.cmd[TCL_PER_LIGHT_CTL_0] = 0; /* filled in via callbacks */
1508 rmesa->hw.tcl.cmd[TCL_PER_LIGHT_CTL_1] = 0;
1509 rmesa->hw.tcl.cmd[TCL_PER_LIGHT_CTL_2] = 0;
1510 rmesa->hw.tcl.cmd[TCL_PER_LIGHT_CTL_3] = 0;
1511
1512 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] =
1513 (R200_UCP_IN_CLIP_SPACE |
1514 R200_CULL_FRONT_IS_CCW);
1515
1516 /* Texgen/Texmat state */
1517 rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_2] = 0x00ffffff;
1518 rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_3] =
1519 ((0 << R200_TEXGEN_0_INPUT_TEX_SHIFT) |
1520 (1 << R200_TEXGEN_1_INPUT_TEX_SHIFT) |
1521 (2 << R200_TEXGEN_2_INPUT_TEX_SHIFT) |
1522 (3 << R200_TEXGEN_3_INPUT_TEX_SHIFT) |
1523 (4 << R200_TEXGEN_4_INPUT_TEX_SHIFT) |
1524 (5 << R200_TEXGEN_5_INPUT_TEX_SHIFT));
1525 rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_0] = 0;
1526 rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_1] =
1527 ((0 << R200_TEXGEN_0_INPUT_SHIFT) |
1528 (1 << R200_TEXGEN_1_INPUT_SHIFT) |
1529 (2 << R200_TEXGEN_2_INPUT_SHIFT) |
1530 (3 << R200_TEXGEN_3_INPUT_SHIFT) |
1531 (4 << R200_TEXGEN_4_INPUT_SHIFT) |
1532 (5 << R200_TEXGEN_5_INPUT_SHIFT));
1533 rmesa->hw.tcg.cmd[TCG_TEX_CYL_WRAP_CTL] = 0;
1534
1535
1536 for (i = 0 ; i < 8; i++) {
1537 struct gl_light *l = &ctx->Light.Light[i];
1538 GLenum p = GL_LIGHT0 + i;
1539 *(float *)&(rmesa->hw.lit[i].cmd[LIT_RANGE_CUTOFF]) = FLT_MAX;
1540
1541 ctx->Driver.Lightfv( ctx, p, GL_AMBIENT, l->Ambient );
1542 ctx->Driver.Lightfv( ctx, p, GL_DIFFUSE, l->Diffuse );
1543 ctx->Driver.Lightfv( ctx, p, GL_SPECULAR, l->Specular );
1544 ctx->Driver.Lightfv( ctx, p, GL_POSITION, NULL );
1545 ctx->Driver.Lightfv( ctx, p, GL_SPOT_DIRECTION, NULL );
1546 ctx->Driver.Lightfv( ctx, p, GL_SPOT_EXPONENT, &l->SpotExponent );
1547 ctx->Driver.Lightfv( ctx, p, GL_SPOT_CUTOFF, &l->SpotCutoff );
1548 ctx->Driver.Lightfv( ctx, p, GL_CONSTANT_ATTENUATION,
1549 &l->ConstantAttenuation );
1550 ctx->Driver.Lightfv( ctx, p, GL_LINEAR_ATTENUATION,
1551 &l->LinearAttenuation );
1552 ctx->Driver.Lightfv( ctx, p, GL_QUADRATIC_ATTENUATION,
1553 &l->QuadraticAttenuation );
1554 *(float *)&(rmesa->hw.lit[i].cmd[LIT_ATTEN_XXX]) = 0.0;
1555 }
1556
1557 ctx->Driver.LightModelfv( ctx, GL_LIGHT_MODEL_AMBIENT,
1558 ctx->Light.Model.Ambient );
1559
1560 TNL_CONTEXT(ctx)->Driver.NotifyMaterialChange( ctx );
1561
1562 for (i = 0 ; i < 6; i++) {
1563 ctx->Driver.ClipPlane( ctx, GL_CLIP_PLANE0 + i, NULL );
1564 }
1565
1566 ctx->Driver.Fogfv( ctx, GL_FOG_MODE, NULL );
1567 ctx->Driver.Fogfv( ctx, GL_FOG_DENSITY, &ctx->Fog.Density );
1568 ctx->Driver.Fogfv( ctx, GL_FOG_START, &ctx->Fog.Start );
1569 ctx->Driver.Fogfv( ctx, GL_FOG_END, &ctx->Fog.End );
1570 ctx->Driver.Fogfv( ctx, GL_FOG_COLOR, ctx->Fog.Color );
1571 ctx->Driver.Fogfv( ctx, GL_FOG_COORDINATE_SOURCE_EXT, NULL );
1572
1573 rmesa->hw.grd.cmd[GRD_VERT_GUARD_CLIP_ADJ] = IEEE_ONE;
1574 rmesa->hw.grd.cmd[GRD_VERT_GUARD_DISCARD_ADJ] = IEEE_ONE;
1575 rmesa->hw.grd.cmd[GRD_HORZ_GUARD_CLIP_ADJ] = IEEE_ONE;
1576 rmesa->hw.grd.cmd[GRD_HORZ_GUARD_DISCARD_ADJ] = IEEE_ONE;
1577
1578 rmesa->hw.eye.cmd[EYE_X] = 0;
1579 rmesa->hw.eye.cmd[EYE_Y] = 0;
1580 rmesa->hw.eye.cmd[EYE_Z] = IEEE_ONE;
1581 rmesa->hw.eye.cmd[EYE_RESCALE_FACTOR] = IEEE_ONE;
1582
1583 rmesa->hw.spr.cmd[SPR_POINT_SPRITE_CNTL] =
1584 R200_PS_SE_SEL_STATE | R200_PS_MULT_CONST;
1585
1586 /* ptp_eye is presumably used to calculate the attenuation wrt a different
1587 location? In any case, since point attenuation triggers _needeyecoords,
1588 it is constant. Probably ignored as long as R200_PS_USE_MODEL_EYE_VEC
1589 isn't set */
1590 rmesa->hw.ptp.cmd[PTP_EYE_X] = 0;
1591 rmesa->hw.ptp.cmd[PTP_EYE_Y] = 0;
1592 rmesa->hw.ptp.cmd[PTP_EYE_Z] = IEEE_ONE | 0x80000000; /* -1.0 */
1593 rmesa->hw.ptp.cmd[PTP_EYE_3] = 0;
1594 /* no idea what the ptp_vport_scale values are good for, except the
1595 PTSIZE one - hopefully doesn't matter */
1596 rmesa->hw.ptp.cmd[PTP_VPORT_SCALE_0] = IEEE_ONE;
1597 rmesa->hw.ptp.cmd[PTP_VPORT_SCALE_1] = IEEE_ONE;
1598 rmesa->hw.ptp.cmd[PTP_VPORT_SCALE_PTSIZE] = IEEE_ONE;
1599 rmesa->hw.ptp.cmd[PTP_VPORT_SCALE_3] = IEEE_ONE;
1600 rmesa->hw.ptp.cmd[PTP_ATT_CONST_QUAD] = 0;
1601 rmesa->hw.ptp.cmd[PTP_ATT_CONST_LIN] = 0;
1602 rmesa->hw.ptp.cmd[PTP_ATT_CONST_CON] = IEEE_ONE;
1603 rmesa->hw.ptp.cmd[PTP_ATT_CONST_3] = 0;
1604 rmesa->hw.ptp.cmd[PTP_CLAMP_MIN] = IEEE_ONE;
1605 rmesa->hw.ptp.cmd[PTP_CLAMP_MAX] = 0x44ffe000; /* 2047 */
1606 rmesa->hw.ptp.cmd[PTP_CLAMP_2] = 0;
1607 rmesa->hw.ptp.cmd[PTP_CLAMP_3] = 0;
1608
1609 r200LightingSpaceChange( ctx );
1610
1611 if (rmesa->radeon.radeonScreen->kernel_mm) {
1612 radeon_init_query_stateobj(&rmesa->radeon, R200_QUERYOBJ_CMDSIZE);
1613 rmesa->radeon.query.queryobj.cmd[R200_QUERYOBJ_CMD_0] = CP_PACKET0(RADEON_RB3D_ZPASS_DATA, 0);
1614 rmesa->radeon.query.queryobj.cmd[R200_QUERYOBJ_DATA_0] = 0;
1615 }
1616
1617 rmesa->radeon.hw.all_dirty = GL_TRUE;
1618
1619 rcommonInitCmdBuf(&rmesa->radeon);
1620 }