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radeon/r200: drop dirty state from texture object + pp_txoffset
[mesa.git] / src / mesa / drivers / dri / r200 / r200_state_init.c
1 /*
2 Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
3
4 The Weather Channel (TM) funded Tungsten Graphics to develop the
5 initial release of the Radeon 8500 driver under the XFree86 license.
6 This notice must be preserved.
7
8 Permission is hereby granted, free of charge, to any person obtaining
9 a copy of this software and associated documentation files (the
10 "Software"), to deal in the Software without restriction, including
11 without limitation the rights to use, copy, modify, merge, publish,
12 distribute, sublicense, and/or sell copies of the Software, and to
13 permit persons to whom the Software is furnished to do so, subject to
14 the following conditions:
15
16 The above copyright notice and this permission notice (including the
17 next paragraph) shall be included in all copies or substantial
18 portions of the Software.
19
20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 */
28
29 /*
30 * Authors:
31 * Keith Whitwell <keith@tungstengraphics.com>
32 */
33
34 #include "main/glheader.h"
35 #include "main/imports.h"
36 #include "main/enums.h"
37 #include "main/colormac.h"
38 #include "main/api_arrayelt.h"
39
40 #include "swrast/swrast.h"
41 #include "vbo/vbo.h"
42 #include "tnl/tnl.h"
43 #include "tnl/t_pipeline.h"
44 #include "swrast_setup/swrast_setup.h"
45
46 #include "radeon_common.h"
47 #include "radeon_mipmap_tree.h"
48 #include "r200_context.h"
49 #include "r200_ioctl.h"
50 #include "r200_state.h"
51 #include "r200_tcl.h"
52 #include "r200_tex.h"
53 #include "r200_swtcl.h"
54
55 #include "xmlpool.h"
56
57 /* New (1.3) state mechanism. 3 commands (packet, scalar, vector) in
58 * 1.3 cmdbuffers allow all previous state to be updated as well as
59 * the tcl scalar and vector areas.
60 */
61 static struct {
62 int start;
63 int len;
64 const char *name;
65 } packet[RADEON_MAX_STATE_PACKETS] = {
66 {RADEON_PP_MISC, 7, "RADEON_PP_MISC"},
67 {RADEON_PP_CNTL, 3, "RADEON_PP_CNTL"},
68 {RADEON_RB3D_COLORPITCH, 1, "RADEON_RB3D_COLORPITCH"},
69 {RADEON_RE_LINE_PATTERN, 2, "RADEON_RE_LINE_PATTERN"},
70 {RADEON_SE_LINE_WIDTH, 1, "RADEON_SE_LINE_WIDTH"},
71 {RADEON_PP_LUM_MATRIX, 1, "RADEON_PP_LUM_MATRIX"},
72 {RADEON_PP_ROT_MATRIX_0, 2, "RADEON_PP_ROT_MATRIX_0"},
73 {RADEON_RB3D_STENCILREFMASK, 3, "RADEON_RB3D_STENCILREFMASK"},
74 {RADEON_SE_VPORT_XSCALE, 6, "RADEON_SE_VPORT_XSCALE"},
75 {RADEON_SE_CNTL, 2, "RADEON_SE_CNTL"},
76 {RADEON_SE_CNTL_STATUS, 1, "RADEON_SE_CNTL_STATUS"},
77 {RADEON_RE_MISC, 1, "RADEON_RE_MISC"},
78 {RADEON_PP_TXFILTER_0, 6, "RADEON_PP_TXFILTER_0"},
79 {RADEON_PP_BORDER_COLOR_0, 1, "RADEON_PP_BORDER_COLOR_0"},
80 {RADEON_PP_TXFILTER_1, 6, "RADEON_PP_TXFILTER_1"},
81 {RADEON_PP_BORDER_COLOR_1, 1, "RADEON_PP_BORDER_COLOR_1"},
82 {RADEON_PP_TXFILTER_2, 6, "RADEON_PP_TXFILTER_2"},
83 {RADEON_PP_BORDER_COLOR_2, 1, "RADEON_PP_BORDER_COLOR_2"},
84 {RADEON_SE_ZBIAS_FACTOR, 2, "RADEON_SE_ZBIAS_FACTOR"},
85 {RADEON_SE_TCL_OUTPUT_VTX_FMT, 11, "RADEON_SE_TCL_OUTPUT_VTX_FMT"},
86 {RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED, 17,
87 "RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED"},
88 {R200_PP_TXCBLEND_0, 4, "R200_PP_TXCBLEND_0"},
89 {R200_PP_TXCBLEND_1, 4, "R200_PP_TXCBLEND_1"},
90 {R200_PP_TXCBLEND_2, 4, "R200_PP_TXCBLEND_2"},
91 {R200_PP_TXCBLEND_3, 4, "R200_PP_TXCBLEND_3"},
92 {R200_PP_TXCBLEND_4, 4, "R200_PP_TXCBLEND_4"},
93 {R200_PP_TXCBLEND_5, 4, "R200_PP_TXCBLEND_5"},
94 {R200_PP_TXCBLEND_6, 4, "R200_PP_TXCBLEND_6"},
95 {R200_PP_TXCBLEND_7, 4, "R200_PP_TXCBLEND_7"},
96 {R200_SE_TCL_LIGHT_MODEL_CTL_0, 6, "R200_SE_TCL_LIGHT_MODEL_CTL_0"},
97 {R200_PP_TFACTOR_0, 6, "R200_PP_TFACTOR_0"},
98 {R200_SE_VTX_FMT_0, 4, "R200_SE_VTX_FMT_0"},
99 {R200_SE_VAP_CNTL, 1, "R200_SE_VAP_CNTL"},
100 {R200_SE_TCL_MATRIX_SEL_0, 5, "R200_SE_TCL_MATRIX_SEL_0"},
101 {R200_SE_TCL_TEX_PROC_CTL_2, 5, "R200_SE_TCL_TEX_PROC_CTL_2"},
102 {R200_SE_TCL_UCP_VERT_BLEND_CTL, 1, "R200_SE_TCL_UCP_VERT_BLEND_CTL"},
103 {R200_PP_TXFILTER_0, 6, "R200_PP_TXFILTER_0"},
104 {R200_PP_TXFILTER_1, 6, "R200_PP_TXFILTER_1"},
105 {R200_PP_TXFILTER_2, 6, "R200_PP_TXFILTER_2"},
106 {R200_PP_TXFILTER_3, 6, "R200_PP_TXFILTER_3"},
107 {R200_PP_TXFILTER_4, 6, "R200_PP_TXFILTER_4"},
108 {R200_PP_TXFILTER_5, 6, "R200_PP_TXFILTER_5"},
109 {R200_PP_TXOFFSET_0, 1, "R200_PP_TXOFFSET_0"},
110 {R200_PP_TXOFFSET_1, 1, "R200_PP_TXOFFSET_1"},
111 {R200_PP_TXOFFSET_2, 1, "R200_PP_TXOFFSET_2"},
112 {R200_PP_TXOFFSET_3, 1, "R200_PP_TXOFFSET_3"},
113 {R200_PP_TXOFFSET_4, 1, "R200_PP_TXOFFSET_4"},
114 {R200_PP_TXOFFSET_5, 1, "R200_PP_TXOFFSET_5"},
115 {R200_SE_VTE_CNTL, 1, "R200_SE_VTE_CNTL"},
116 {R200_SE_TCL_OUTPUT_VTX_COMP_SEL, 1,
117 "R200_SE_TCL_OUTPUT_VTX_COMP_SEL"},
118 {R200_PP_TAM_DEBUG3, 1, "R200_PP_TAM_DEBUG3"},
119 {R200_PP_CNTL_X, 1, "R200_PP_CNTL_X"},
120 {R200_RB3D_DEPTHXY_OFFSET, 1, "R200_RB3D_DEPTHXY_OFFSET"},
121 {R200_RE_AUX_SCISSOR_CNTL, 1, "R200_RE_AUX_SCISSOR_CNTL"},
122 {R200_RE_SCISSOR_TL_0, 2, "R200_RE_SCISSOR_TL_0"},
123 {R200_RE_SCISSOR_TL_1, 2, "R200_RE_SCISSOR_TL_1"},
124 {R200_RE_SCISSOR_TL_2, 2, "R200_RE_SCISSOR_TL_2"},
125 {R200_SE_VAP_CNTL_STATUS, 1, "R200_SE_VAP_CNTL_STATUS"},
126 {R200_SE_VTX_STATE_CNTL, 1, "R200_SE_VTX_STATE_CNTL"},
127 {R200_RE_POINTSIZE, 1, "R200_RE_POINTSIZE"},
128 {R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0, 4,
129 "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0"},
130 {R200_PP_CUBIC_FACES_0, 1, "R200_PP_CUBIC_FACES_0"}, /* 61 */
131 {R200_PP_CUBIC_OFFSET_F1_0, 5, "R200_PP_CUBIC_OFFSET_F1_0"}, /* 62 */
132 {R200_PP_CUBIC_FACES_1, 1, "R200_PP_CUBIC_FACES_1"},
133 {R200_PP_CUBIC_OFFSET_F1_1, 5, "R200_PP_CUBIC_OFFSET_F1_1"},
134 {R200_PP_CUBIC_FACES_2, 1, "R200_PP_CUBIC_FACES_2"},
135 {R200_PP_CUBIC_OFFSET_F1_2, 5, "R200_PP_CUBIC_OFFSET_F1_2"},
136 {R200_PP_CUBIC_FACES_3, 1, "R200_PP_CUBIC_FACES_3"},
137 {R200_PP_CUBIC_OFFSET_F1_3, 5, "R200_PP_CUBIC_OFFSET_F1_3"},
138 {R200_PP_CUBIC_FACES_4, 1, "R200_PP_CUBIC_FACES_4"},
139 {R200_PP_CUBIC_OFFSET_F1_4, 5, "R200_PP_CUBIC_OFFSET_F1_4"},
140 {R200_PP_CUBIC_FACES_5, 1, "R200_PP_CUBIC_FACES_5"},
141 {R200_PP_CUBIC_OFFSET_F1_5, 5, "R200_PP_CUBIC_OFFSET_F1_5"},
142 {RADEON_PP_TEX_SIZE_0, 2, "RADEON_PP_TEX_SIZE_0"},
143 {RADEON_PP_TEX_SIZE_1, 2, "RADEON_PP_TEX_SIZE_1"},
144 {RADEON_PP_TEX_SIZE_2, 2, "RADEON_PP_TEX_SIZE_2"},
145 {R200_RB3D_BLENDCOLOR, 3, "R200_RB3D_BLENDCOLOR"},
146 {R200_SE_TCL_POINT_SPRITE_CNTL, 1, "R200_SE_TCL_POINT_SPRITE_CNTL"},
147 {RADEON_PP_CUBIC_FACES_0, 1, "RADEON_PP_CUBIC_FACES_0"},
148 {RADEON_PP_CUBIC_OFFSET_T0_0, 5, "RADEON_PP_CUBIC_OFFSET_T0_0"},
149 {RADEON_PP_CUBIC_FACES_1, 1, "RADEON_PP_CUBIC_FACES_1"},
150 {RADEON_PP_CUBIC_OFFSET_T1_0, 5, "RADEON_PP_CUBIC_OFFSET_T1_0"},
151 {RADEON_PP_CUBIC_FACES_2, 1, "RADEON_PP_CUBIC_FACES_2"},
152 {RADEON_PP_CUBIC_OFFSET_T2_0, 5, "RADEON_PP_CUBIC_OFFSET_T2_0"},
153 {R200_PP_TRI_PERF, 2, "R200_PP_TRI_PERF"},
154 {R200_PP_TXCBLEND_8, 32, "R200_PP_AFS_0"}, /* 85 */
155 {R200_PP_TXCBLEND_0, 32, "R200_PP_AFS_1"},
156 {R200_PP_TFACTOR_0, 8, "R200_ATF_TFACTOR"},
157 {R200_PP_TXFILTER_0, 8, "R200_PP_TXCTLALL_0"},
158 {R200_PP_TXFILTER_1, 8, "R200_PP_TXCTLALL_1"},
159 {R200_PP_TXFILTER_2, 8, "R200_PP_TXCTLALL_2"},
160 {R200_PP_TXFILTER_3, 8, "R200_PP_TXCTLALL_3"},
161 {R200_PP_TXFILTER_4, 8, "R200_PP_TXCTLALL_4"},
162 {R200_PP_TXFILTER_5, 8, "R200_PP_TXCTLALL_5"},
163 {R200_VAP_PVS_CNTL_1, 2, "R200_VAP_PVS_CNTL"},
164 };
165
166 /* =============================================================
167 * State initialization
168 */
169
170 void r200PrintDirty( r200ContextPtr rmesa, const char *msg )
171 {
172 struct radeon_state_atom *l;
173
174 fprintf(stderr, msg);
175 fprintf(stderr, ": ");
176
177 foreach(l, &rmesa->radeon.hw.atomlist) {
178 if (l->dirty || rmesa->radeon.hw.all_dirty)
179 fprintf(stderr, "%s, ", l->name);
180 }
181
182 fprintf(stderr, "\n");
183 }
184
185 static int cmdpkt( r200ContextPtr rmesa, int id )
186 {
187 drm_radeon_cmd_header_t h;
188
189 if (rmesa->radeon.radeonScreen->kernel_mm) {
190 return CP_PACKET0(packet[id].start, packet[id].len - 1);
191 } else {
192 h.i = 0;
193 h.packet.cmd_type = RADEON_CMD_PACKET;
194 h.packet.packet_id = id;
195 }
196 return h.i;
197 }
198
199 static int cmdvec( int offset, int stride, int count )
200 {
201 drm_radeon_cmd_header_t h;
202 h.i = 0;
203 h.vectors.cmd_type = RADEON_CMD_VECTORS;
204 h.vectors.offset = offset;
205 h.vectors.stride = stride;
206 h.vectors.count = count;
207 return h.i;
208 }
209
210 /* warning: the count here is divided by 4 compared to other cmds
211 (so it doesn't exceed the char size)! */
212 static int cmdveclinear( int offset, int count )
213 {
214 drm_radeon_cmd_header_t h;
215 h.i = 0;
216 h.veclinear.cmd_type = RADEON_CMD_VECLINEAR;
217 h.veclinear.addr_lo = offset & 0xff;
218 h.veclinear.addr_hi = (offset & 0xff00) >> 8;
219 h.veclinear.count = count;
220 return h.i;
221 }
222
223 static int cmdscl( int offset, int stride, int count )
224 {
225 drm_radeon_cmd_header_t h;
226 h.i = 0;
227 h.scalars.cmd_type = RADEON_CMD_SCALARS;
228 h.scalars.offset = offset;
229 h.scalars.stride = stride;
230 h.scalars.count = count;
231 return h.i;
232 }
233
234 static int cmdscl2( int offset, int stride, int count )
235 {
236 drm_radeon_cmd_header_t h;
237 h.i = 0;
238 h.scalars.cmd_type = RADEON_CMD_SCALARS2;
239 h.scalars.offset = offset - 0x100;
240 h.scalars.stride = stride;
241 h.scalars.count = count;
242 return h.i;
243 }
244
245 #define CHECK( NM, FLAG ) \
246 static int check_##NM( GLcontext *ctx, struct radeon_state_atom *atom) \
247 { \
248 r200ContextPtr rmesa = R200_CONTEXT(ctx); \
249 (void) rmesa; \
250 return (FLAG) ? atom->cmd_size : 0; \
251 }
252
253 #define TCL_CHECK( NM, FLAG ) \
254 static int check_##NM( GLcontext *ctx, struct radeon_state_atom *atom) \
255 { \
256 r200ContextPtr rmesa = R200_CONTEXT(ctx); \
257 return (!rmesa->radeon.TclFallback && !ctx->VertexProgram._Enabled && (FLAG)) ? atom->cmd_size : 0; \
258 }
259
260 #define TCL_OR_VP_CHECK( NM, FLAG ) \
261 static int check_##NM( GLcontext *ctx, struct radeon_state_atom *atom ) \
262 { \
263 r200ContextPtr rmesa = R200_CONTEXT(ctx); \
264 return (!rmesa->radeon.TclFallback && (FLAG)) ? atom->cmd_size : 0; \
265 }
266
267 #define VP_CHECK( NM, FLAG ) \
268 static int check_##NM( GLcontext *ctx, struct radeon_state_atom *atom ) \
269 { \
270 r200ContextPtr rmesa = R200_CONTEXT(ctx); \
271 (void) atom; \
272 return (!rmesa->radeon.TclFallback && ctx->VertexProgram._Enabled && (FLAG)) ? atom->cmd_size : 0; \
273 }
274
275 CHECK( always, GL_TRUE )
276 CHECK( never, GL_FALSE )
277 CHECK( tex_any, ctx->Texture._EnabledUnits )
278 CHECK( tf, (ctx->Texture._EnabledUnits && !ctx->ATIFragmentShader._Enabled) );
279 CHECK( tex_pair, (rmesa->state.texture.unit[atom->idx].unitneeded | rmesa->state.texture.unit[atom->idx & ~1].unitneeded) )
280 CHECK( tex, rmesa->state.texture.unit[atom->idx].unitneeded )
281 CHECK( pix_zero, !ctx->ATIFragmentShader._Enabled )
282 CHECK( texenv, (rmesa->state.envneeded & (1 << (atom->idx)) && !ctx->ATIFragmentShader._Enabled) )
283 CHECK( afs_pass1, (ctx->ATIFragmentShader._Enabled && (ctx->ATIFragmentShader.Current->NumPasses > 1)) )
284 CHECK( afs, ctx->ATIFragmentShader._Enabled )
285 CHECK( tex_cube, rmesa->state.texture.unit[atom->idx].unitneeded & TEXTURE_CUBE_BIT )
286 TCL_CHECK( tcl_fog, ctx->Fog.Enabled )
287 TCL_CHECK( tcl, GL_TRUE )
288 TCL_CHECK( tcl_tex, rmesa->state.texture.unit[atom->idx].unitneeded )
289 TCL_CHECK( tcl_lighting, ctx->Light.Enabled )
290 TCL_CHECK( tcl_light, ctx->Light.Enabled && ctx->Light.Light[atom->idx].Enabled )
291 TCL_OR_VP_CHECK( tcl_ucp, (ctx->Transform.ClipPlanesEnabled & (1 << (atom->idx))) )
292 TCL_OR_VP_CHECK( tcl_or_vp, GL_TRUE )
293 VP_CHECK( tcl_vp, GL_TRUE )
294 VP_CHECK( tcl_vp_size, ctx->VertexProgram.Current->Base.NumNativeInstructions > 64 )
295 VP_CHECK( tcl_vpp_size, ctx->VertexProgram.Current->Base.NumNativeParameters > 96 )
296
297 #define OUT_VEC(hdr, data) do { \
298 drm_radeon_cmd_header_t h; \
299 h.i = hdr; \
300 OUT_BATCH(CP_PACKET0(RADEON_SE_TCL_STATE_FLUSH, 0)); \
301 OUT_BATCH(0); \
302 OUT_BATCH(CP_PACKET0(R200_SE_TCL_VECTOR_INDX_REG, 0)); \
303 OUT_BATCH(h.vectors.offset | (h.vectors.stride << RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT)); \
304 OUT_BATCH(CP_PACKET0_ONE(R200_SE_TCL_VECTOR_DATA_REG, h.vectors.count - 1)); \
305 OUT_BATCH_TABLE((data), h.vectors.count); \
306 } while(0)
307
308 #define OUT_VECLINEAR(hdr, data) do { \
309 drm_radeon_cmd_header_t h; \
310 uint32_t _start = h.veclinear.addr_lo | (h.veclinear.addr_hi << 8); \
311 uint32_t _sz = h.veclinear.count * 4; \
312 h.i = hdr; \
313 OUT_BATCH(CP_PACKET0(RADEON_SE_TCL_STATE_FLUSH, 0)); \
314 OUT_BATCH(0); \
315 OUT_BATCH(CP_PACKET0(R200_SE_TCL_VECTOR_INDX_REG, 0)); \
316 OUT_BATCH(_start | (1 << RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT)); \
317 OUT_BATCH(CP_PACKET0_ONE(R200_SE_TCL_VECTOR_DATA_REG, _sz - 1)); \
318 OUT_BATCH_TABLE((data), _sz); \
319 } while(0)
320
321 #define OUT_SCL(hdr, data) do { \
322 drm_radeon_cmd_header_t h; \
323 h.i = hdr; \
324 OUT_BATCH(CP_PACKET0(R200_SE_TCL_SCALAR_INDX_REG, 0)); \
325 OUT_BATCH((h.scalars.offset) | (h.scalars.stride << RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT)); \
326 OUT_BATCH(CP_PACKET0_ONE(R200_SE_TCL_SCALAR_DATA_REG, h.scalars.count - 1)); \
327 OUT_BATCH_TABLE((data), h.scalars.count); \
328 } while(0)
329
330 #define OUT_SCL2(hdr, data) do { \
331 drm_radeon_cmd_header_t h; \
332 h.i = hdr; \
333 OUT_BATCH(CP_PACKET0(R200_SE_TCL_SCALAR_INDX_REG, 0)); \
334 OUT_BATCH((h.scalars.offset + 0x100) | (h.scalars.stride << RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT)); \
335 OUT_BATCH(CP_PACKET0_ONE(R200_SE_TCL_SCALAR_DATA_REG, h.scalars.count - 1)); \
336 OUT_BATCH_TABLE((data), h.scalars.count); \
337 } while(0)
338
339 static void mtl_emit(GLcontext *ctx, struct radeon_state_atom *atom)
340 {
341 r200ContextPtr r200 = R200_CONTEXT(ctx);
342 BATCH_LOCALS(&r200->radeon);
343 uint32_t dwords = atom->cmd_size;
344
345 BEGIN_BATCH_NO_AUTOSTATE(dwords);
346 OUT_VEC(atom->cmd[MTL_CMD_0], (atom->cmd+1));
347 OUT_SCL2(atom->cmd[MTL_CMD_1], (atom->cmd + 18));
348 END_BATCH();
349 }
350
351 static void lit_emit(GLcontext *ctx, struct radeon_state_atom *atom)
352 {
353 r200ContextPtr r200 = R200_CONTEXT(ctx);
354 BATCH_LOCALS(&r200->radeon);
355 uint32_t dwords = atom->cmd_size;
356
357 BEGIN_BATCH_NO_AUTOSTATE(dwords);
358 OUT_VEC(atom->cmd[LIT_CMD_0], atom->cmd+1);
359 OUT_VEC(atom->cmd[LIT_CMD_1], atom->cmd+LIT_CMD_1+1);
360 END_BATCH();
361 }
362
363 static void ptp_emit(GLcontext *ctx, struct radeon_state_atom *atom)
364 {
365 r200ContextPtr r200 = R200_CONTEXT(ctx);
366 BATCH_LOCALS(&r200->radeon);
367 uint32_t dwords = atom->cmd_size;
368
369 BEGIN_BATCH_NO_AUTOSTATE(dwords);
370 OUT_VEC(atom->cmd[PTP_CMD_0], atom->cmd+1);
371 OUT_VEC(atom->cmd[PTP_CMD_1], atom->cmd+PTP_CMD_1+1);
372 END_BATCH();
373 }
374
375 static void veclinear_emit(GLcontext *ctx, struct radeon_state_atom *atom)
376 {
377 r200ContextPtr r200 = R200_CONTEXT(ctx);
378 BATCH_LOCALS(&r200->radeon);
379 uint32_t dwords = atom->cmd_size;
380
381 BEGIN_BATCH_NO_AUTOSTATE(dwords);
382 OUT_VECLINEAR(atom->cmd[0], atom->cmd+1);
383 END_BATCH();
384 }
385
386 static void scl_emit(GLcontext *ctx, struct radeon_state_atom *atom)
387 {
388 r200ContextPtr r200 = R200_CONTEXT(ctx);
389 BATCH_LOCALS(&r200->radeon);
390 uint32_t dwords = atom->cmd_size;
391
392 BEGIN_BATCH_NO_AUTOSTATE(dwords);
393 OUT_SCL(atom->cmd[0], atom->cmd+1);
394 END_BATCH();
395 }
396
397
398 static void vec_emit(GLcontext *ctx, struct radeon_state_atom *atom)
399 {
400 r200ContextPtr r200 = R200_CONTEXT(ctx);
401 BATCH_LOCALS(&r200->radeon);
402 uint32_t dwords = atom->cmd_size;
403
404 BEGIN_BATCH_NO_AUTOSTATE(dwords);
405 OUT_VEC(atom->cmd[0], atom->cmd+1);
406 END_BATCH();
407 }
408
409 static void ctx_emit(GLcontext *ctx, struct radeon_state_atom *atom)
410 {
411 r200ContextPtr r200 = R200_CONTEXT(ctx);
412 BATCH_LOCALS(&r200->radeon);
413 struct radeon_renderbuffer *rrb;
414 uint32_t cbpitch;
415 uint32_t zbpitch;
416 uint32_t dwords = atom->cmd_size;
417 GLframebuffer *fb = r200->radeon.dri.drawable->driverPrivate;
418
419 /* output the first 7 bytes of context */
420 BEGIN_BATCH_NO_AUTOSTATE(dwords+2+2);
421 OUT_BATCH_TABLE(atom->cmd, 5);
422
423 rrb = r200->radeon.state.depth.rrb;
424 if (!rrb) {
425 OUT_BATCH(0);
426 OUT_BATCH(0);
427 } else {
428 zbpitch = (rrb->pitch / rrb->cpp);
429 OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
430 OUT_BATCH(zbpitch);
431 }
432
433 OUT_BATCH(atom->cmd[CTX_RB3D_ZSTENCILCNTL]);
434 OUT_BATCH(atom->cmd[CTX_CMD_1]);
435 OUT_BATCH(atom->cmd[CTX_PP_CNTL]);
436 OUT_BATCH(atom->cmd[CTX_RB3D_CNTL]);
437
438 rrb = r200->radeon.state.color.rrb;
439 if (r200->radeon.radeonScreen->driScreen->dri2.enabled) {
440 rrb = (struct radeon_renderbuffer *)fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer;
441 }
442 if (!rrb || !rrb->bo) {
443 OUT_BATCH(atom->cmd[CTX_RB3D_COLOROFFSET]);
444 } else {
445 OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
446 }
447
448 OUT_BATCH(atom->cmd[CTX_CMD_2]);
449
450 if (!rrb || !rrb->bo) {
451 OUT_BATCH(atom->cmd[CTX_RB3D_COLORPITCH]);
452 } else {
453 cbpitch = (rrb->pitch / rrb->cpp);
454 if (rrb->cpp == 4)
455 ;
456 else
457 ;
458 if (r200->radeon.sarea->tiling_enabled)
459 cbpitch |= R200_COLOR_TILE_ENABLE;
460 OUT_BATCH(cbpitch);
461 }
462
463 if (atom->cmd_size == CTX_STATE_SIZE_NEWDRM)
464 OUT_BATCH_TABLE((atom->cmd + 14), 4);
465
466 END_BATCH();
467 }
468
469 static void ctx_emit_cs(GLcontext *ctx, struct radeon_state_atom *atom)
470 {
471 r200ContextPtr r200 = R200_CONTEXT(ctx);
472 BATCH_LOCALS(&r200->radeon);
473 struct radeon_renderbuffer *rrb, *drb;
474 uint32_t cbpitch = 0;
475 uint32_t zbpitch = 0;
476 uint32_t dwords = atom->cmd_size;
477 GLframebuffer *fb = r200->radeon.dri.drawable->driverPrivate;
478
479 rrb = r200->radeon.state.color.rrb;
480 if (r200->radeon.radeonScreen->driScreen->dri2.enabled) {
481 rrb = (struct radeon_renderbuffer *)fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer;
482 }
483 if (rrb) {
484 assert(rrb->bo != NULL);
485 cbpitch = (rrb->pitch / rrb->cpp);
486 if (r200->radeon.sarea->tiling_enabled)
487 cbpitch |= R200_COLOR_TILE_ENABLE;
488 }
489
490 drb = r200->radeon.state.depth.rrb;
491 if (drb)
492 zbpitch = (drb->pitch / drb->cpp);
493
494 /* output the first 7 bytes of context */
495 BEGIN_BATCH_NO_AUTOSTATE(dwords);
496
497 /* In the CS case we need to split this up */
498 OUT_BATCH(CP_PACKET0(packet[0].start, 3));
499 OUT_BATCH_TABLE((atom->cmd + 1), 4);
500
501 if (drb) {
502 OUT_BATCH(CP_PACKET0(RADEON_RB3D_DEPTHOFFSET, 0));
503 OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
504
505 OUT_BATCH(CP_PACKET0(RADEON_RB3D_DEPTHPITCH, 0));
506 OUT_BATCH(zbpitch);
507 }
508
509 OUT_BATCH(CP_PACKET0(RADEON_RB3D_ZSTENCILCNTL, 0));
510 OUT_BATCH(atom->cmd[CTX_RB3D_ZSTENCILCNTL]);
511 OUT_BATCH(CP_PACKET0(RADEON_PP_CNTL, 1));
512 OUT_BATCH(atom->cmd[CTX_PP_CNTL]);
513 OUT_BATCH(atom->cmd[CTX_RB3D_CNTL]);
514
515
516 if (rrb) {
517 OUT_BATCH(CP_PACKET0(RADEON_RB3D_COLOROFFSET, 0));
518 OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
519 }
520
521 if (rrb) {
522 if (rrb->cpp == 4)
523 ;
524 else
525 ;
526 OUT_BATCH(CP_PACKET0(RADEON_RB3D_COLORPITCH, 0));
527 OUT_BATCH(cbpitch);
528 }
529
530 if (atom->cmd_size == CTX_STATE_SIZE_NEWDRM) {
531 OUT_BATCH_TABLE((atom->cmd + 14), 4);
532 }
533
534 END_BATCH();
535 }
536
537 static void tex_emit(GLcontext *ctx, struct radeon_state_atom *atom)
538 {
539 r200ContextPtr r200 = R200_CONTEXT(ctx);
540 BATCH_LOCALS(&r200->radeon);
541 uint32_t dwords = atom->cmd_size;
542 int i = atom->idx;
543 radeonTexObj *t = r200->state.texture.unit[i].texobj;
544
545 if (t && t->mt && !t->image_override)
546 dwords += 2;
547 BEGIN_BATCH_NO_AUTOSTATE(dwords);
548 OUT_BATCH_TABLE(atom->cmd, 10);
549 if (t && !t->image_override) {
550 OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, 0,
551 RADEON_GEM_DOMAIN_VRAM, 0, 0);
552 } else if (!t) {
553 /* workaround for old CS mechanism */
554 OUT_BATCH(r200->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP]);
555 } else if (t->image_override)
556 OUT_BATCH(t->override_offset);
557
558 END_BATCH();
559 }
560
561 static void cube_emit(GLcontext *ctx, struct radeon_state_atom *atom)
562 {
563 r200ContextPtr r200 = R200_CONTEXT(ctx);
564 BATCH_LOCALS(&r200->radeon);
565 uint32_t dwords = atom->cmd_size;
566 int i = atom->idx;
567 radeonTexObj *t = r200->state.texture.unit[i].texobj;
568 GLuint size;
569
570 BEGIN_BATCH_NO_AUTOSTATE(dwords + (2 * 5));
571 OUT_BATCH_TABLE(atom->cmd, 3);
572
573 if (t && !t->image_override) {
574 size = t->mt->totalsize / 6;
575 OUT_BATCH_RELOC(0, t->mt->bo, size, RADEON_GEM_DOMAIN_VRAM, 0, 0);
576 OUT_BATCH_RELOC(0, t->mt->bo, size * 2, RADEON_GEM_DOMAIN_VRAM, 0, 0);
577 OUT_BATCH_RELOC(0, t->mt->bo, size * 3, RADEON_GEM_DOMAIN_VRAM, 0, 0);
578 OUT_BATCH_RELOC(0, t->mt->bo, size * 4, RADEON_GEM_DOMAIN_VRAM, 0, 0);
579 OUT_BATCH_RELOC(0, t->mt->bo, size * 5, RADEON_GEM_DOMAIN_VRAM, 0, 0);
580 }
581 END_BATCH();
582 }
583
584 /* Initialize the context's hardware state.
585 */
586 void r200InitState( r200ContextPtr rmesa )
587 {
588 GLcontext *ctx = rmesa->radeon.glCtx;
589 GLuint color_fmt, depth_fmt, i;
590 GLint drawPitch, drawOffset;
591
592 switch ( rmesa->radeon.radeonScreen->cpp ) {
593 case 2:
594 color_fmt = R200_COLOR_FORMAT_RGB565;
595 break;
596 case 4:
597 color_fmt = R200_COLOR_FORMAT_ARGB8888;
598 break;
599 default:
600 fprintf( stderr, "Error: Unsupported pixel depth... exiting\n" );
601 exit( -1 );
602 }
603
604 rmesa->radeon.state.color.clear = 0x00000000;
605
606 switch ( ctx->Visual.depthBits ) {
607 case 16:
608 rmesa->radeon.state.depth.clear = 0x0000ffff;
609 rmesa->radeon.state.depth.scale = 1.0 / (GLfloat)0xffff;
610 depth_fmt = R200_DEPTH_FORMAT_16BIT_INT_Z;
611 rmesa->radeon.state.stencil.clear = 0x00000000;
612 break;
613 case 24:
614 rmesa->radeon.state.depth.clear = 0x00ffffff;
615 rmesa->radeon.state.depth.scale = 1.0 / (GLfloat)0xffffff;
616 depth_fmt = R200_DEPTH_FORMAT_24BIT_INT_Z;
617 rmesa->radeon.state.stencil.clear = 0xffff0000;
618 break;
619 default:
620 fprintf( stderr, "Error: Unsupported depth %d... exiting\n",
621 ctx->Visual.depthBits );
622 exit( -1 );
623 }
624
625 /* Only have hw stencil when depth buffer is 24 bits deep */
626 rmesa->radeon.state.stencil.hwBuffer = ( ctx->Visual.stencilBits > 0 &&
627 ctx->Visual.depthBits == 24 );
628
629 rmesa->radeon.Fallback = 0;
630
631 if ( ctx->Visual.doubleBufferMode && rmesa->radeon.sarea->pfCurrentPage == 0 ) {
632 drawOffset = rmesa->radeon.radeonScreen->backOffset;
633 drawPitch = rmesa->radeon.radeonScreen->backPitch;
634 } else {
635 drawOffset = rmesa->radeon.radeonScreen->frontOffset;
636 drawPitch = rmesa->radeon.radeonScreen->frontPitch;
637 }
638 #if 000
639 if ( ctx->Visual.doubleBufferMode && rmesa->sarea->pfCurrentPage == 0 ) {
640 rmesa->radeon.state.color.drawOffset = rmesa->radeon.radeonScreen->backOffset;
641 rmesa->radeon.state.color.drawPitch = rmesa->radeon.radeonScreen->backPitch;
642 } else {
643 rmesa->radeon.state.color.drawOffset = rmesa->radeon.radeonScreen->frontOffset;
644 rmesa->radeon.state.color.drawPitch = rmesa->radeon.radeonScreen->frontPitch;
645 }
646
647 rmesa->state.pixel.readOffset = rmesa->radeon.state.color.drawOffset;
648 rmesa->state.pixel.readPitch = rmesa->radeon.state.color.drawPitch;
649 #endif
650
651 rmesa->radeon.hw.max_state_size = 0;
652
653 #define ALLOC_STATE( ATOM, CHK, SZ, NM, IDX ) \
654 do { \
655 rmesa->hw.ATOM.cmd_size = SZ; \
656 rmesa->hw.ATOM.cmd = (GLuint *)CALLOC(SZ * sizeof(int)); \
657 rmesa->hw.ATOM.lastcmd = (GLuint *)CALLOC(SZ * sizeof(int)); \
658 rmesa->hw.ATOM.name = NM; \
659 rmesa->hw.ATOM.idx = IDX; \
660 rmesa->hw.ATOM.check = check_##CHK; \
661 rmesa->hw.ATOM.dirty = GL_FALSE; \
662 rmesa->radeon.hw.max_state_size += SZ * sizeof(int); \
663 } while (0)
664
665
666 /* Allocate state buffers:
667 */
668 if (rmesa->radeon.radeonScreen->drmSupportsBlendColor)
669 ALLOC_STATE( ctx, always, CTX_STATE_SIZE_NEWDRM, "CTX/context", 0 );
670 else
671 ALLOC_STATE( ctx, always, CTX_STATE_SIZE_OLDDRM, "CTX/context", 0 );
672
673 if (rmesa->radeon.radeonScreen->kernel_mm)
674 rmesa->hw.ctx.emit = ctx_emit_cs;
675 else
676 rmesa->hw.ctx.emit = ctx_emit;
677 ALLOC_STATE( set, always, SET_STATE_SIZE, "SET/setup", 0 );
678 ALLOC_STATE( lin, always, LIN_STATE_SIZE, "LIN/line", 0 );
679 ALLOC_STATE( msk, always, MSK_STATE_SIZE, "MSK/mask", 0 );
680 ALLOC_STATE( vpt, always, VPT_STATE_SIZE, "VPT/viewport", 0 );
681 ALLOC_STATE( vtx, always, VTX_STATE_SIZE, "VTX/vertex", 0 );
682 ALLOC_STATE( vap, always, VAP_STATE_SIZE, "VAP/vap", 0 );
683 ALLOC_STATE( vte, always, VTE_STATE_SIZE, "VTE/vte", 0 );
684 ALLOC_STATE( msc, always, MSC_STATE_SIZE, "MSC/misc", 0 );
685 ALLOC_STATE( cst, always, CST_STATE_SIZE, "CST/constant", 0 );
686 ALLOC_STATE( zbs, always, ZBS_STATE_SIZE, "ZBS/zbias", 0 );
687 ALLOC_STATE( tf, tf, TF_STATE_SIZE, "TF/tfactor", 0 );
688 if (rmesa->radeon.radeonScreen->drmSupportsFragShader) {
689 if (rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_R200) {
690 /* make sure texture units 0/1 are emitted pair-wise for r200 t0 hang workaround */
691 ALLOC_STATE( tex[0], tex_pair, TEX_STATE_SIZE_NEWDRM, "TEX/tex-0", 0 );
692 ALLOC_STATE( tex[1], tex_pair, TEX_STATE_SIZE_NEWDRM, "TEX/tex-1", 1 );
693 ALLOC_STATE( tam, tex_any, TAM_STATE_SIZE, "TAM/tam", 0 );
694 }
695 else {
696 ALLOC_STATE( tex[0], tex, TEX_STATE_SIZE_NEWDRM, "TEX/tex-0", 0 );
697 ALLOC_STATE( tex[1], tex, TEX_STATE_SIZE_NEWDRM, "TEX/tex-1", 1 );
698 ALLOC_STATE( tam, never, TAM_STATE_SIZE, "TAM/tam", 0 );
699 }
700 ALLOC_STATE( tex[2], tex, TEX_STATE_SIZE_NEWDRM, "TEX/tex-2", 2 );
701 ALLOC_STATE( tex[3], tex, TEX_STATE_SIZE_NEWDRM, "TEX/tex-3", 3 );
702 ALLOC_STATE( tex[4], tex, TEX_STATE_SIZE_NEWDRM, "TEX/tex-4", 4 );
703 ALLOC_STATE( tex[5], tex, TEX_STATE_SIZE_NEWDRM, "TEX/tex-5", 5 );
704 ALLOC_STATE( atf, afs, ATF_STATE_SIZE, "ATF/tfactor", 0 );
705 ALLOC_STATE( afs[0], afs_pass1, AFS_STATE_SIZE, "AFS/afsinst-0", 0 );
706 ALLOC_STATE( afs[1], afs, AFS_STATE_SIZE, "AFS/afsinst-1", 1 );
707 }
708 else {
709 if (rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_R200) {
710 ALLOC_STATE( tex[0], tex_pair, TEX_STATE_SIZE_OLDDRM, "TEX/tex-0", 0 );
711 ALLOC_STATE( tex[1], tex_pair, TEX_STATE_SIZE_OLDDRM, "TEX/tex-1", 1 );
712 ALLOC_STATE( tam, tex_any, TAM_STATE_SIZE, "TAM/tam", 0 );
713 }
714 else {
715 ALLOC_STATE( tex[0], tex, TEX_STATE_SIZE_OLDDRM, "TEX/tex-0", 0 );
716 ALLOC_STATE( tex[1], tex, TEX_STATE_SIZE_OLDDRM, "TEX/tex-1", 1 );
717 ALLOC_STATE( tam, never, TAM_STATE_SIZE, "TAM/tam", 0 );
718 }
719 ALLOC_STATE( tex[2], tex, TEX_STATE_SIZE_OLDDRM, "TEX/tex-2", 2 );
720 ALLOC_STATE( tex[3], tex, TEX_STATE_SIZE_OLDDRM, "TEX/tex-3", 3 );
721 ALLOC_STATE( tex[4], tex, TEX_STATE_SIZE_OLDDRM, "TEX/tex-4", 4 );
722 ALLOC_STATE( tex[5], tex, TEX_STATE_SIZE_OLDDRM, "TEX/tex-5", 5 );
723 ALLOC_STATE( atf, never, ATF_STATE_SIZE, "TF/tfactor", 0 );
724 ALLOC_STATE( afs[0], never, AFS_STATE_SIZE, "AFS/afsinst-0", 0 );
725 ALLOC_STATE( afs[1], never, AFS_STATE_SIZE, "AFS/afsinst-1", 1 );
726 }
727
728 for (i = 0; i < 5; i++)
729 rmesa->hw.tex[i].emit = tex_emit;
730 if (rmesa->radeon.radeonScreen->drmSupportsCubeMapsR200) {
731 ALLOC_STATE( cube[0], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-0", 0 );
732 ALLOC_STATE( cube[1], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-1", 1 );
733 ALLOC_STATE( cube[2], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-2", 2 );
734 ALLOC_STATE( cube[3], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-3", 3 );
735 ALLOC_STATE( cube[4], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-4", 4 );
736 ALLOC_STATE( cube[5], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-5", 5 );
737 for (i = 0; i < 5; i++)
738 rmesa->hw.cube[i].emit = cube_emit;
739 }
740 else {
741 ALLOC_STATE( cube[0], never, CUBE_STATE_SIZE, "CUBE/tex-0", 0 );
742 ALLOC_STATE( cube[1], never, CUBE_STATE_SIZE, "CUBE/tex-1", 1 );
743 ALLOC_STATE( cube[2], never, CUBE_STATE_SIZE, "CUBE/tex-2", 2 );
744 ALLOC_STATE( cube[3], never, CUBE_STATE_SIZE, "CUBE/tex-3", 3 );
745 ALLOC_STATE( cube[4], never, CUBE_STATE_SIZE, "CUBE/tex-4", 4 );
746 ALLOC_STATE( cube[5], never, CUBE_STATE_SIZE, "CUBE/tex-5", 5 );
747 }
748
749 if (rmesa->radeon.radeonScreen->drmSupportsVertexProgram) {
750 ALLOC_STATE( pvs, tcl_vp, PVS_STATE_SIZE, "PVS/pvscntl", 0 );
751 ALLOC_STATE( vpi[0], tcl_vp, VPI_STATE_SIZE, "VP/vertexprog-0", 0 );
752 ALLOC_STATE( vpi[1], tcl_vp_size, VPI_STATE_SIZE, "VP/vertexprog-1", 1 );
753 ALLOC_STATE( vpp[0], tcl_vp, VPP_STATE_SIZE, "VPP/vertexparam-0", 0 );
754 ALLOC_STATE( vpp[1], tcl_vpp_size, VPP_STATE_SIZE, "VPP/vertexparam-1", 1 );
755 }
756 else {
757 ALLOC_STATE( pvs, never, PVS_STATE_SIZE, "PVS/pvscntl", 0 );
758 ALLOC_STATE( vpi[0], never, VPI_STATE_SIZE, "VP/vertexprog-0", 0 );
759 ALLOC_STATE( vpi[1], never, VPI_STATE_SIZE, "VP/vertexprog-1", 1 );
760 ALLOC_STATE( vpp[0], never, VPP_STATE_SIZE, "VPP/vertexparam-0", 0 );
761 ALLOC_STATE( vpp[1], never, VPP_STATE_SIZE, "VPP/vertexparam-1", 1 );
762 }
763 /* FIXME: this atom has two commands, we need only one (ucp_vert_blend) for vp */
764 ALLOC_STATE( tcl, tcl_or_vp, TCL_STATE_SIZE, "TCL/tcl", 0 );
765 ALLOC_STATE( msl, tcl, MSL_STATE_SIZE, "MSL/matrix-select", 0 );
766 ALLOC_STATE( tcg, tcl, TCG_STATE_SIZE, "TCG/texcoordgen", 0 );
767 ALLOC_STATE( mtl[0], tcl_lighting, MTL_STATE_SIZE, "MTL0/material0", 0 );
768 ALLOC_STATE( mtl[1], tcl_lighting, MTL_STATE_SIZE, "MTL1/material1", 1 );
769 ALLOC_STATE( grd, tcl_or_vp, GRD_STATE_SIZE, "GRD/guard-band", 0 );
770 ALLOC_STATE( fog, tcl_fog, FOG_STATE_SIZE, "FOG/fog", 0 );
771 ALLOC_STATE( glt, tcl_lighting, GLT_STATE_SIZE, "GLT/light-global", 0 );
772 ALLOC_STATE( eye, tcl_lighting, EYE_STATE_SIZE, "EYE/eye-vector", 0 );
773 ALLOC_STATE( mat[R200_MTX_MV], tcl, MAT_STATE_SIZE, "MAT/modelview", 0 );
774 ALLOC_STATE( mat[R200_MTX_IMV], tcl, MAT_STATE_SIZE, "MAT/it-modelview", 0 );
775 ALLOC_STATE( mat[R200_MTX_MVP], tcl, MAT_STATE_SIZE, "MAT/modelproject", 0 );
776 ALLOC_STATE( mat[R200_MTX_TEX0], tcl_tex, MAT_STATE_SIZE, "MAT/texmat0", 0 );
777 ALLOC_STATE( mat[R200_MTX_TEX1], tcl_tex, MAT_STATE_SIZE, "MAT/texmat1", 1 );
778 ALLOC_STATE( mat[R200_MTX_TEX2], tcl_tex, MAT_STATE_SIZE, "MAT/texmat2", 2 );
779 ALLOC_STATE( mat[R200_MTX_TEX3], tcl_tex, MAT_STATE_SIZE, "MAT/texmat3", 3 );
780 ALLOC_STATE( mat[R200_MTX_TEX4], tcl_tex, MAT_STATE_SIZE, "MAT/texmat4", 4 );
781 ALLOC_STATE( mat[R200_MTX_TEX5], tcl_tex, MAT_STATE_SIZE, "MAT/texmat5", 5 );
782 ALLOC_STATE( ucp[0], tcl_ucp, UCP_STATE_SIZE, "UCP/userclip-0", 0 );
783 ALLOC_STATE( ucp[1], tcl_ucp, UCP_STATE_SIZE, "UCP/userclip-1", 1 );
784 ALLOC_STATE( ucp[2], tcl_ucp, UCP_STATE_SIZE, "UCP/userclip-2", 2 );
785 ALLOC_STATE( ucp[3], tcl_ucp, UCP_STATE_SIZE, "UCP/userclip-3", 3 );
786 ALLOC_STATE( ucp[4], tcl_ucp, UCP_STATE_SIZE, "UCP/userclip-4", 4 );
787 ALLOC_STATE( ucp[5], tcl_ucp, UCP_STATE_SIZE, "UCP/userclip-5", 5 );
788 ALLOC_STATE( lit[0], tcl_light, LIT_STATE_SIZE, "LIT/light-0", 0 );
789 ALLOC_STATE( lit[1], tcl_light, LIT_STATE_SIZE, "LIT/light-1", 1 );
790 ALLOC_STATE( lit[2], tcl_light, LIT_STATE_SIZE, "LIT/light-2", 2 );
791 ALLOC_STATE( lit[3], tcl_light, LIT_STATE_SIZE, "LIT/light-3", 3 );
792 ALLOC_STATE( lit[4], tcl_light, LIT_STATE_SIZE, "LIT/light-4", 4 );
793 ALLOC_STATE( lit[5], tcl_light, LIT_STATE_SIZE, "LIT/light-5", 5 );
794 ALLOC_STATE( lit[6], tcl_light, LIT_STATE_SIZE, "LIT/light-6", 6 );
795 ALLOC_STATE( lit[7], tcl_light, LIT_STATE_SIZE, "LIT/light-7", 7 );
796 ALLOC_STATE( pix[0], pix_zero, PIX_STATE_SIZE, "PIX/pixstage-0", 0 );
797 ALLOC_STATE( pix[1], texenv, PIX_STATE_SIZE, "PIX/pixstage-1", 1 );
798 ALLOC_STATE( pix[2], texenv, PIX_STATE_SIZE, "PIX/pixstage-2", 2 );
799 ALLOC_STATE( pix[3], texenv, PIX_STATE_SIZE, "PIX/pixstage-3", 3 );
800 ALLOC_STATE( pix[4], texenv, PIX_STATE_SIZE, "PIX/pixstage-4", 4 );
801 ALLOC_STATE( pix[5], texenv, PIX_STATE_SIZE, "PIX/pixstage-5", 5 );
802 if (rmesa->radeon.radeonScreen->drmSupportsTriPerf) {
803 ALLOC_STATE( prf, always, PRF_STATE_SIZE, "PRF/performance-tri", 0 );
804 }
805 else {
806 ALLOC_STATE( prf, never, PRF_STATE_SIZE, "PRF/performance-tri", 0 );
807 }
808 if (rmesa->radeon.radeonScreen->drmSupportsPointSprites) {
809 ALLOC_STATE( spr, always, SPR_STATE_SIZE, "SPR/pointsprite", 0 );
810 ALLOC_STATE( ptp, tcl, PTP_STATE_SIZE, "PTP/pointparams", 0 );
811 }
812 else {
813 ALLOC_STATE (spr, never, SPR_STATE_SIZE, "SPR/pointsprite", 0 );
814 ALLOC_STATE (ptp, never, PTP_STATE_SIZE, "PTP/pointparams", 0 );
815 }
816
817 r200SetUpAtomList( rmesa );
818
819 /* Fill in the packet headers:
820 */
821 rmesa->hw.ctx.cmd[CTX_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_MISC);
822 rmesa->hw.ctx.cmd[CTX_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_PP_CNTL);
823 rmesa->hw.ctx.cmd[CTX_CMD_2] = cmdpkt(rmesa, RADEON_EMIT_RB3D_COLORPITCH);
824 if (rmesa->radeon.radeonScreen->drmSupportsBlendColor)
825 rmesa->hw.ctx.cmd[CTX_CMD_3] = cmdpkt(rmesa, R200_EMIT_RB3D_BLENDCOLOR);
826 rmesa->hw.lin.cmd[LIN_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_RE_LINE_PATTERN);
827 rmesa->hw.lin.cmd[LIN_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_SE_LINE_WIDTH);
828 rmesa->hw.msk.cmd[MSK_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_RB3D_STENCILREFMASK);
829 rmesa->hw.vpt.cmd[VPT_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_SE_VPORT_XSCALE);
830 rmesa->hw.set.cmd[SET_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_SE_CNTL);
831 rmesa->hw.msc.cmd[MSC_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_RE_MISC);
832 rmesa->hw.cst.cmd[CST_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_CNTL_X);
833 rmesa->hw.cst.cmd[CST_CMD_1] = cmdpkt(rmesa, R200_EMIT_RB3D_DEPTHXY_OFFSET);
834 rmesa->hw.cst.cmd[CST_CMD_2] = cmdpkt(rmesa, R200_EMIT_RE_AUX_SCISSOR_CNTL);
835 rmesa->hw.cst.cmd[CST_CMD_3] = cmdpkt(rmesa, R200_EMIT_RE_SCISSOR_TL_0);
836 rmesa->hw.cst.cmd[CST_CMD_4] = cmdpkt(rmesa, R200_EMIT_SE_VAP_CNTL_STATUS);
837 rmesa->hw.cst.cmd[CST_CMD_5] = cmdpkt(rmesa, R200_EMIT_RE_POINTSIZE);
838 rmesa->hw.cst.cmd[CST_CMD_6] = cmdpkt(rmesa, R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0);
839 rmesa->hw.tam.cmd[TAM_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TAM_DEBUG3);
840 rmesa->hw.tf.cmd[TF_CMD_0] = cmdpkt(rmesa, R200_EMIT_TFACTOR_0);
841 if (rmesa->radeon.radeonScreen->drmSupportsFragShader) {
842 rmesa->hw.atf.cmd[ATF_CMD_0] = cmdpkt(rmesa, R200_EMIT_ATF_TFACTOR);
843 rmesa->hw.tex[0].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCTLALL_0);
844 rmesa->hw.tex[0].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_0);
845 rmesa->hw.tex[1].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCTLALL_1);
846 rmesa->hw.tex[1].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_1);
847 rmesa->hw.tex[2].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCTLALL_2);
848 rmesa->hw.tex[2].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_2);
849 rmesa->hw.tex[3].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCTLALL_3);
850 rmesa->hw.tex[3].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_3);
851 rmesa->hw.tex[4].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCTLALL_4);
852 rmesa->hw.tex[4].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_4);
853 rmesa->hw.tex[5].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCTLALL_5);
854 rmesa->hw.tex[5].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_5);
855 } else {
856 rmesa->hw.tex[0].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXFILTER_0);
857 rmesa->hw.tex[0].cmd[TEX_CMD_1_OLDDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_0);
858 rmesa->hw.tex[1].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXFILTER_1);
859 rmesa->hw.tex[1].cmd[TEX_CMD_1_OLDDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_1);
860 rmesa->hw.tex[2].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXFILTER_2);
861 rmesa->hw.tex[2].cmd[TEX_CMD_1_OLDDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_2);
862 rmesa->hw.tex[3].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXFILTER_3);
863 rmesa->hw.tex[3].cmd[TEX_CMD_1_OLDDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_3);
864 rmesa->hw.tex[4].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXFILTER_4);
865 rmesa->hw.tex[4].cmd[TEX_CMD_1_OLDDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_4);
866 rmesa->hw.tex[5].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXFILTER_5);
867 rmesa->hw.tex[5].cmd[TEX_CMD_1_OLDDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_5);
868 }
869 rmesa->hw.afs[0].cmd[AFS_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_AFS_0);
870 rmesa->hw.afs[1].cmd[AFS_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_AFS_1);
871 rmesa->hw.pvs.cmd[PVS_CMD_0] = cmdpkt(rmesa, R200_EMIT_VAP_PVS_CNTL);
872 rmesa->hw.cube[0].cmd[CUBE_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_FACES_0);
873 rmesa->hw.cube[0].cmd[CUBE_CMD_1] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_OFFSETS_0);
874 rmesa->hw.cube[1].cmd[CUBE_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_FACES_1);
875 rmesa->hw.cube[1].cmd[CUBE_CMD_1] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_OFFSETS_1);
876 rmesa->hw.cube[2].cmd[CUBE_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_FACES_2);
877 rmesa->hw.cube[2].cmd[CUBE_CMD_1] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_OFFSETS_2);
878 rmesa->hw.cube[3].cmd[CUBE_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_FACES_3);
879 rmesa->hw.cube[3].cmd[CUBE_CMD_1] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_OFFSETS_3);
880 rmesa->hw.cube[4].cmd[CUBE_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_FACES_4);
881 rmesa->hw.cube[4].cmd[CUBE_CMD_1] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_OFFSETS_4);
882 rmesa->hw.cube[5].cmd[CUBE_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_FACES_5);
883 rmesa->hw.cube[5].cmd[CUBE_CMD_1] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_OFFSETS_5);
884 rmesa->hw.pix[0].cmd[PIX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCBLEND_0);
885 rmesa->hw.pix[1].cmd[PIX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCBLEND_1);
886 rmesa->hw.pix[2].cmd[PIX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCBLEND_2);
887 rmesa->hw.pix[3].cmd[PIX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCBLEND_3);
888 rmesa->hw.pix[4].cmd[PIX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCBLEND_4);
889 rmesa->hw.pix[5].cmd[PIX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCBLEND_5);
890 rmesa->hw.zbs.cmd[ZBS_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_SE_ZBIAS_FACTOR);
891 rmesa->hw.tcl.cmd[TCL_CMD_0] = cmdpkt(rmesa, R200_EMIT_TCL_LIGHT_MODEL_CTL_0);
892 rmesa->hw.tcl.cmd[TCL_CMD_1] = cmdpkt(rmesa, R200_EMIT_TCL_UCP_VERT_BLEND_CTL);
893 rmesa->hw.tcg.cmd[TCG_CMD_0] = cmdpkt(rmesa, R200_EMIT_TEX_PROC_CTL_2);
894 rmesa->hw.msl.cmd[MSL_CMD_0] = cmdpkt(rmesa, R200_EMIT_MATRIX_SELECT_0);
895 rmesa->hw.vap.cmd[VAP_CMD_0] = cmdpkt(rmesa, R200_EMIT_VAP_CTL);
896 rmesa->hw.vtx.cmd[VTX_CMD_0] = cmdpkt(rmesa, R200_EMIT_VTX_FMT_0);
897 rmesa->hw.vtx.cmd[VTX_CMD_1] = cmdpkt(rmesa, R200_EMIT_OUTPUT_VTX_COMP_SEL);
898 rmesa->hw.vtx.cmd[VTX_CMD_2] = cmdpkt(rmesa, R200_EMIT_SE_VTX_STATE_CNTL);
899 rmesa->hw.vte.cmd[VTE_CMD_0] = cmdpkt(rmesa, R200_EMIT_VTE_CNTL);
900 rmesa->hw.prf.cmd[PRF_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TRI_PERF_CNTL);
901 rmesa->hw.spr.cmd[SPR_CMD_0] = cmdpkt(rmesa, R200_EMIT_TCL_POINT_SPRITE_CNTL);
902 if (rmesa->radeon.radeonScreen->kernel_mm) {
903 rmesa->hw.mtl[0].emit = mtl_emit;
904 rmesa->hw.mtl[1].emit = mtl_emit;
905
906 rmesa->hw.vpi[0].emit = veclinear_emit;
907 rmesa->hw.vpi[1].emit = veclinear_emit;
908 rmesa->hw.vpp[0].emit = veclinear_emit;
909 rmesa->hw.vpp[1].emit = veclinear_emit;
910
911 rmesa->hw.grd.emit = scl_emit;
912 rmesa->hw.fog.emit = vec_emit;
913 rmesa->hw.glt.emit = vec_emit;
914 rmesa->hw.eye.emit = vec_emit;
915
916 for (i = R200_MTX_MV; i <= R200_MTX_TEX5; i++)
917 rmesa->hw.mat[i].emit = vec_emit;
918
919 for (i = 0; i < 8; i++)
920 rmesa->hw.lit[i].emit = lit_emit;
921
922 for (i = 0; i < 6; i++)
923 rmesa->hw.ucp[i].emit = vec_emit;
924
925 rmesa->hw.ptp.emit = ptp_emit;
926 }
927
928
929
930 rmesa->hw.mtl[0].cmd[MTL_CMD_0] =
931 cmdvec( R200_VS_MAT_0_EMISS, 1, 16 );
932 rmesa->hw.mtl[0].cmd[MTL_CMD_1] =
933 cmdscl2( R200_SS_MAT_0_SHININESS, 1, 1 );
934 rmesa->hw.mtl[1].cmd[MTL_CMD_0] =
935 cmdvec( R200_VS_MAT_1_EMISS, 1, 16 );
936 rmesa->hw.mtl[1].cmd[MTL_CMD_1] =
937 cmdscl2( R200_SS_MAT_1_SHININESS, 1, 1 );
938
939 rmesa->hw.vpi[0].cmd[VPI_CMD_0] =
940 cmdveclinear( R200_PVS_PROG0, 64 );
941 rmesa->hw.vpi[1].cmd[VPI_CMD_0] =
942 cmdveclinear( R200_PVS_PROG1, 64 );
943 rmesa->hw.vpp[0].cmd[VPP_CMD_0] =
944 cmdveclinear( R200_PVS_PARAM0, 96 );
945 rmesa->hw.vpp[1].cmd[VPP_CMD_0] =
946 cmdveclinear( R200_PVS_PARAM1, 96 );
947
948 rmesa->hw.grd.cmd[GRD_CMD_0] =
949 cmdscl( R200_SS_VERT_GUARD_CLIP_ADJ_ADDR, 1, 4 );
950 rmesa->hw.fog.cmd[FOG_CMD_0] =
951 cmdvec( R200_VS_FOG_PARAM_ADDR, 1, 4 );
952 rmesa->hw.glt.cmd[GLT_CMD_0] =
953 cmdvec( R200_VS_GLOBAL_AMBIENT_ADDR, 1, 4 );
954 rmesa->hw.eye.cmd[EYE_CMD_0] =
955 cmdvec( R200_VS_EYE_VECTOR_ADDR, 1, 4 );
956
957 rmesa->hw.mat[R200_MTX_MV].cmd[MAT_CMD_0] =
958 cmdvec( R200_VS_MATRIX_0_MV, 1, 16);
959 rmesa->hw.mat[R200_MTX_IMV].cmd[MAT_CMD_0] =
960 cmdvec( R200_VS_MATRIX_1_INV_MV, 1, 16);
961 rmesa->hw.mat[R200_MTX_MVP].cmd[MAT_CMD_0] =
962 cmdvec( R200_VS_MATRIX_2_MVP, 1, 16);
963 rmesa->hw.mat[R200_MTX_TEX0].cmd[MAT_CMD_0] =
964 cmdvec( R200_VS_MATRIX_3_TEX0, 1, 16);
965 rmesa->hw.mat[R200_MTX_TEX1].cmd[MAT_CMD_0] =
966 cmdvec( R200_VS_MATRIX_4_TEX1, 1, 16);
967 rmesa->hw.mat[R200_MTX_TEX2].cmd[MAT_CMD_0] =
968 cmdvec( R200_VS_MATRIX_5_TEX2, 1, 16);
969 rmesa->hw.mat[R200_MTX_TEX3].cmd[MAT_CMD_0] =
970 cmdvec( R200_VS_MATRIX_6_TEX3, 1, 16);
971 rmesa->hw.mat[R200_MTX_TEX4].cmd[MAT_CMD_0] =
972 cmdvec( R200_VS_MATRIX_7_TEX4, 1, 16);
973 rmesa->hw.mat[R200_MTX_TEX5].cmd[MAT_CMD_0] =
974 cmdvec( R200_VS_MATRIX_8_TEX5, 1, 16);
975
976 for (i = 0 ; i < 8; i++) {
977 rmesa->hw.lit[i].cmd[LIT_CMD_0] =
978 cmdvec( R200_VS_LIGHT_AMBIENT_ADDR + i, 8, 24 );
979 rmesa->hw.lit[i].cmd[LIT_CMD_1] =
980 cmdscl( R200_SS_LIGHT_DCD_ADDR + i, 8, 7 );
981 }
982
983 for (i = 0 ; i < 6; i++) {
984 rmesa->hw.ucp[i].cmd[UCP_CMD_0] =
985 cmdvec( R200_VS_UCP_ADDR + i, 1, 4 );
986 }
987
988 rmesa->hw.ptp.cmd[PTP_CMD_0] =
989 cmdvec( R200_VS_PNT_SPRITE_VPORT_SCALE, 1, 4 );
990 rmesa->hw.ptp.cmd[PTP_CMD_1] =
991 cmdvec( R200_VS_PNT_SPRITE_ATT_CONST, 1, 12 );
992
993 /* Initial Harware state:
994 */
995 rmesa->hw.ctx.cmd[CTX_PP_MISC] = (R200_ALPHA_TEST_PASS
996 /* | R200_RIGHT_HAND_CUBE_OGL*/);
997
998 rmesa->hw.ctx.cmd[CTX_PP_FOG_COLOR] = (R200_FOG_VERTEX |
999 R200_FOG_USE_SPEC_ALPHA);
1000
1001 rmesa->hw.ctx.cmd[CTX_RE_SOLID_COLOR] = 0x00000000;
1002
1003 rmesa->hw.ctx.cmd[CTX_RB3D_BLENDCNTL] = (R200_COMB_FCN_ADD_CLAMP |
1004 (R200_BLEND_GL_ONE << R200_SRC_BLEND_SHIFT) |
1005 (R200_BLEND_GL_ZERO << R200_DST_BLEND_SHIFT));
1006
1007 if (rmesa->radeon.radeonScreen->drmSupportsBlendColor) {
1008 rmesa->hw.ctx.cmd[CTX_RB3D_BLENDCOLOR] = 0x00000000;
1009 rmesa->hw.ctx.cmd[CTX_RB3D_ABLENDCNTL] = (R200_COMB_FCN_ADD_CLAMP |
1010 (R200_BLEND_GL_ONE << R200_SRC_BLEND_SHIFT) |
1011 (R200_BLEND_GL_ZERO << R200_DST_BLEND_SHIFT));
1012 rmesa->hw.ctx.cmd[CTX_RB3D_CBLENDCNTL] = (R200_COMB_FCN_ADD_CLAMP |
1013 (R200_BLEND_GL_ONE << R200_SRC_BLEND_SHIFT) |
1014 (R200_BLEND_GL_ZERO << R200_DST_BLEND_SHIFT));
1015 }
1016
1017 rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHOFFSET] =
1018 rmesa->radeon.radeonScreen->depthOffset + rmesa->radeon.radeonScreen->fbLocation;
1019
1020 rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHPITCH] =
1021 ((rmesa->radeon.radeonScreen->depthPitch &
1022 R200_DEPTHPITCH_MASK) |
1023 R200_DEPTH_ENDIAN_NO_SWAP);
1024
1025 if (rmesa->using_hyperz)
1026 rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHPITCH] |= R200_DEPTH_HYPERZ;
1027
1028 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] = (depth_fmt |
1029 R200_Z_TEST_LESS |
1030 R200_STENCIL_TEST_ALWAYS |
1031 R200_STENCIL_FAIL_KEEP |
1032 R200_STENCIL_ZPASS_KEEP |
1033 R200_STENCIL_ZFAIL_KEEP |
1034 R200_Z_WRITE_ENABLE);
1035
1036 if (rmesa->using_hyperz) {
1037 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= R200_Z_COMPRESSION_ENABLE |
1038 R200_Z_DECOMPRESSION_ENABLE;
1039 /* if (rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_R200)
1040 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_HIERARCHY_ENABLE;*/
1041 }
1042
1043 rmesa->hw.ctx.cmd[CTX_PP_CNTL] = (R200_ANTI_ALIAS_NONE
1044 | R200_TEX_BLEND_0_ENABLE);
1045
1046 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] = color_fmt;
1047 switch ( driQueryOptioni( &rmesa->radeon.optionCache, "dither_mode" ) ) {
1048 case DRI_CONF_DITHER_XERRORDIFFRESET:
1049 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= R200_DITHER_INIT;
1050 break;
1051 case DRI_CONF_DITHER_ORDERED:
1052 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= R200_SCALE_DITHER_ENABLE;
1053 break;
1054 }
1055 if ( driQueryOptioni( &rmesa->radeon.optionCache, "round_mode" ) ==
1056 DRI_CONF_ROUND_ROUND )
1057 rmesa->radeon.state.color.roundEnable = R200_ROUND_ENABLE;
1058 else
1059 rmesa->radeon.state.color.roundEnable = 0;
1060 if ( driQueryOptioni (&rmesa->radeon.optionCache, "color_reduction" ) ==
1061 DRI_CONF_COLOR_REDUCTION_DITHER )
1062 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= R200_DITHER_ENABLE;
1063 else
1064 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= rmesa->radeon.state.color.roundEnable;
1065
1066 #if 000
1067 rmesa->hw.ctx.cmd[CTX_RB3D_COLOROFFSET] = ((rmesa->radeon.state.color.drawOffset +
1068 rmesa->radeon.radeonScreen->fbLocation)
1069 & R200_COLOROFFSET_MASK);
1070
1071 rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] = ((rmesa->radeon.state.color.drawPitch &
1072 R200_COLORPITCH_MASK) |
1073 R200_COLOR_ENDIAN_NO_SWAP);
1074 #else
1075 rmesa->hw.ctx.cmd[CTX_RB3D_COLOROFFSET] = ((drawOffset +
1076 rmesa->radeon.radeonScreen->fbLocation)
1077 & R200_COLOROFFSET_MASK);
1078
1079 rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] = ((drawPitch &
1080 R200_COLORPITCH_MASK) |
1081 R200_COLOR_ENDIAN_NO_SWAP);
1082 #endif
1083 /* (fixed size) sarea is initialized to zero afaics so can omit version check. Phew! */
1084 if (rmesa->radeon.sarea->tiling_enabled) {
1085 rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] |= R200_COLOR_TILE_ENABLE;
1086 }
1087
1088 rmesa->hw.prf.cmd[PRF_PP_TRI_PERF] = R200_TRI_CUTOFF_MASK - R200_TRI_CUTOFF_MASK *
1089 driQueryOptionf (&rmesa->radeon.optionCache,"texture_blend_quality");
1090 rmesa->hw.prf.cmd[PRF_PP_PERF_CNTL] = 0;
1091
1092 rmesa->hw.set.cmd[SET_SE_CNTL] = (R200_FFACE_CULL_CCW |
1093 R200_BFACE_SOLID |
1094 R200_FFACE_SOLID |
1095 R200_FLAT_SHADE_VTX_LAST |
1096 R200_DIFFUSE_SHADE_GOURAUD |
1097 R200_ALPHA_SHADE_GOURAUD |
1098 R200_SPECULAR_SHADE_GOURAUD |
1099 R200_FOG_SHADE_GOURAUD |
1100 R200_DISC_FOG_SHADE_GOURAUD |
1101 R200_VTX_PIX_CENTER_OGL |
1102 R200_ROUND_MODE_TRUNC |
1103 R200_ROUND_PREC_8TH_PIX);
1104
1105 rmesa->hw.set.cmd[SET_RE_CNTL] = (R200_PERSPECTIVE_ENABLE |
1106 R200_SCISSOR_ENABLE);
1107
1108 rmesa->hw.lin.cmd[LIN_RE_LINE_PATTERN] = ((1 << 16) | 0xffff);
1109
1110 rmesa->hw.lin.cmd[LIN_RE_LINE_STATE] =
1111 ((0 << R200_LINE_CURRENT_PTR_SHIFT) |
1112 (1 << R200_LINE_CURRENT_COUNT_SHIFT));
1113
1114 rmesa->hw.lin.cmd[LIN_SE_LINE_WIDTH] = (1 << 4);
1115
1116 rmesa->hw.msk.cmd[MSK_RB3D_STENCILREFMASK] =
1117 ((0x00 << R200_STENCIL_REF_SHIFT) |
1118 (0xff << R200_STENCIL_MASK_SHIFT) |
1119 (0xff << R200_STENCIL_WRITEMASK_SHIFT));
1120
1121 rmesa->hw.msk.cmd[MSK_RB3D_ROPCNTL] = R200_ROP_COPY;
1122 rmesa->hw.msk.cmd[MSK_RB3D_PLANEMASK] = 0xffffffff;
1123
1124 rmesa->hw.tam.cmd[TAM_DEBUG3] = 0;
1125
1126 rmesa->hw.msc.cmd[MSC_RE_MISC] =
1127 ((0 << R200_STIPPLE_X_OFFSET_SHIFT) |
1128 (0 << R200_STIPPLE_Y_OFFSET_SHIFT) |
1129 R200_STIPPLE_BIG_BIT_ORDER);
1130
1131
1132 rmesa->hw.cst.cmd[CST_PP_CNTL_X] = 0;
1133 rmesa->hw.cst.cmd[CST_RB3D_DEPTHXY_OFFSET] = 0;
1134 rmesa->hw.cst.cmd[CST_RE_AUX_SCISSOR_CNTL] = 0x0;
1135 rmesa->hw.cst.cmd[CST_RE_SCISSOR_TL_0] = 0;
1136 rmesa->hw.cst.cmd[CST_RE_SCISSOR_BR_0] = 0;
1137 rmesa->hw.cst.cmd[CST_SE_VAP_CNTL_STATUS] =
1138 #ifdef MESA_BIG_ENDIAN
1139 R200_VC_32BIT_SWAP;
1140 #else
1141 R200_VC_NO_SWAP;
1142 #endif
1143
1144 if (!(rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL)) {
1145 /* Bypass TCL */
1146 rmesa->hw.cst.cmd[CST_SE_VAP_CNTL_STATUS] |= (1<<8);
1147 }
1148
1149 rmesa->hw.cst.cmd[CST_RE_POINTSIZE] =
1150 (((GLuint)(ctx->Const.MaxPointSize * 16.0)) << R200_MAXPOINTSIZE_SHIFT) | 0x10;
1151 rmesa->hw.cst.cmd[CST_SE_TCL_INPUT_VTX_0] =
1152 (0x0 << R200_VERTEX_POSITION_ADDR__SHIFT);
1153 rmesa->hw.cst.cmd[CST_SE_TCL_INPUT_VTX_1] =
1154 (0x02 << R200_VTX_COLOR_0_ADDR__SHIFT) |
1155 (0x03 << R200_VTX_COLOR_1_ADDR__SHIFT);
1156 rmesa->hw.cst.cmd[CST_SE_TCL_INPUT_VTX_2] =
1157 (0x06 << R200_VTX_TEX_0_ADDR__SHIFT) |
1158 (0x07 << R200_VTX_TEX_1_ADDR__SHIFT) |
1159 (0x08 << R200_VTX_TEX_2_ADDR__SHIFT) |
1160 (0x09 << R200_VTX_TEX_3_ADDR__SHIFT);
1161 rmesa->hw.cst.cmd[CST_SE_TCL_INPUT_VTX_3] =
1162 (0x0A << R200_VTX_TEX_4_ADDR__SHIFT) |
1163 (0x0B << R200_VTX_TEX_5_ADDR__SHIFT);
1164
1165
1166 rmesa->hw.vpt.cmd[VPT_SE_VPORT_XSCALE] = 0x00000000;
1167 rmesa->hw.vpt.cmd[VPT_SE_VPORT_XOFFSET] = 0x00000000;
1168 rmesa->hw.vpt.cmd[VPT_SE_VPORT_YSCALE] = 0x00000000;
1169 rmesa->hw.vpt.cmd[VPT_SE_VPORT_YOFFSET] = 0x00000000;
1170 rmesa->hw.vpt.cmd[VPT_SE_VPORT_ZSCALE] = 0x00000000;
1171 rmesa->hw.vpt.cmd[VPT_SE_VPORT_ZOFFSET] = 0x00000000;
1172
1173 for ( i = 0 ; i < ctx->Const.MaxTextureUnits ; i++ ) {
1174 rmesa->hw.tex[i].cmd[TEX_PP_TXFILTER] = R200_BORDER_MODE_OGL;
1175 rmesa->hw.tex[i].cmd[TEX_PP_TXFORMAT] =
1176 ((i << R200_TXFORMAT_ST_ROUTE_SHIFT) | /* <-- note i */
1177 (2 << R200_TXFORMAT_WIDTH_SHIFT) |
1178 (2 << R200_TXFORMAT_HEIGHT_SHIFT));
1179 rmesa->hw.tex[i].cmd[TEX_PP_BORDER_COLOR] = 0;
1180 rmesa->hw.tex[i].cmd[TEX_PP_TXFORMAT_X] =
1181 (/* R200_TEXCOORD_PROJ | */
1182 0x100000); /* Small default bias */
1183 if (rmesa->radeon.radeonScreen->drmSupportsFragShader) {
1184 rmesa->hw.tex[i].cmd[TEX_PP_TXOFFSET_NEWDRM] =
1185 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
1186 rmesa->hw.tex[i].cmd[TEX_PP_CUBIC_FACES] = 0;
1187 rmesa->hw.tex[i].cmd[TEX_PP_TXMULTI_CTL] = 0;
1188 }
1189 else {
1190 rmesa->hw.tex[i].cmd[TEX_PP_TXOFFSET_OLDDRM] =
1191 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
1192 }
1193
1194 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_FACES] = 0;
1195 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F1] =
1196 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
1197 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F2] =
1198 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
1199 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F3] =
1200 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
1201 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F4] =
1202 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
1203 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F5] =
1204 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
1205
1206 rmesa->hw.pix[i].cmd[PIX_PP_TXCBLEND] =
1207 (R200_TXC_ARG_A_ZERO |
1208 R200_TXC_ARG_B_ZERO |
1209 R200_TXC_ARG_C_DIFFUSE_COLOR |
1210 R200_TXC_OP_MADD);
1211
1212 rmesa->hw.pix[i].cmd[PIX_PP_TXCBLEND2] =
1213 ((i << R200_TXC_TFACTOR_SEL_SHIFT) |
1214 R200_TXC_SCALE_1X |
1215 R200_TXC_CLAMP_0_1 |
1216 R200_TXC_OUTPUT_REG_R0);
1217
1218 rmesa->hw.pix[i].cmd[PIX_PP_TXABLEND] =
1219 (R200_TXA_ARG_A_ZERO |
1220 R200_TXA_ARG_B_ZERO |
1221 R200_TXA_ARG_C_DIFFUSE_ALPHA |
1222 R200_TXA_OP_MADD);
1223
1224 rmesa->hw.pix[i].cmd[PIX_PP_TXABLEND2] =
1225 ((i << R200_TXA_TFACTOR_SEL_SHIFT) |
1226 R200_TXA_SCALE_1X |
1227 R200_TXA_CLAMP_0_1 |
1228 R200_TXA_OUTPUT_REG_R0);
1229 }
1230
1231 rmesa->hw.tf.cmd[TF_TFACTOR_0] = 0;
1232 rmesa->hw.tf.cmd[TF_TFACTOR_1] = 0;
1233 rmesa->hw.tf.cmd[TF_TFACTOR_2] = 0;
1234 rmesa->hw.tf.cmd[TF_TFACTOR_3] = 0;
1235 rmesa->hw.tf.cmd[TF_TFACTOR_4] = 0;
1236 rmesa->hw.tf.cmd[TF_TFACTOR_5] = 0;
1237
1238 rmesa->hw.vap.cmd[VAP_SE_VAP_CNTL] =
1239 (R200_VAP_TCL_ENABLE |
1240 (0x9 << R200_VAP_VF_MAX_VTX_NUM__SHIFT));
1241
1242 rmesa->hw.vte.cmd[VTE_SE_VTE_CNTL] =
1243 (R200_VPORT_X_SCALE_ENA |
1244 R200_VPORT_Y_SCALE_ENA |
1245 R200_VPORT_Z_SCALE_ENA |
1246 R200_VPORT_X_OFFSET_ENA |
1247 R200_VPORT_Y_OFFSET_ENA |
1248 R200_VPORT_Z_OFFSET_ENA |
1249 /* FIXME: Turn on for tex rect only */
1250 R200_VTX_ST_DENORMALIZED |
1251 R200_VTX_W0_FMT);
1252
1253
1254 rmesa->hw.vtx.cmd[VTX_VTXFMT_0] = 0;
1255 rmesa->hw.vtx.cmd[VTX_VTXFMT_1] = 0;
1256 rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_VTXFMT_0] =
1257 ((R200_VTX_Z0 | R200_VTX_W0 |
1258 (R200_VTX_FP_RGBA << R200_VTX_COLOR_0_SHIFT)));
1259 rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_VTXFMT_1] = 0;
1260 rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_COMPSEL] = (R200_OUTPUT_XYZW);
1261 rmesa->hw.vtx.cmd[VTX_STATE_CNTL] = R200_VSC_UPDATE_USER_COLOR_0_ENABLE;
1262
1263
1264 /* Matrix selection */
1265 rmesa->hw.msl.cmd[MSL_MATRIX_SELECT_0] =
1266 (R200_MTX_MV << R200_MODELVIEW_0_SHIFT);
1267
1268 rmesa->hw.msl.cmd[MSL_MATRIX_SELECT_1] =
1269 (R200_MTX_IMV << R200_IT_MODELVIEW_0_SHIFT);
1270
1271 rmesa->hw.msl.cmd[MSL_MATRIX_SELECT_2] =
1272 (R200_MTX_MVP << R200_MODELPROJECT_0_SHIFT);
1273
1274 rmesa->hw.msl.cmd[MSL_MATRIX_SELECT_3] =
1275 ((R200_MTX_TEX0 << R200_TEXMAT_0_SHIFT) |
1276 (R200_MTX_TEX1 << R200_TEXMAT_1_SHIFT) |
1277 (R200_MTX_TEX2 << R200_TEXMAT_2_SHIFT) |
1278 (R200_MTX_TEX3 << R200_TEXMAT_3_SHIFT));
1279
1280 rmesa->hw.msl.cmd[MSL_MATRIX_SELECT_4] =
1281 ((R200_MTX_TEX4 << R200_TEXMAT_4_SHIFT) |
1282 (R200_MTX_TEX5 << R200_TEXMAT_5_SHIFT));
1283
1284
1285 /* General TCL state */
1286 rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL_0] =
1287 (R200_SPECULAR_LIGHTS |
1288 R200_DIFFUSE_SPECULAR_COMBINE |
1289 R200_LOCAL_LIGHT_VEC_GL |
1290 R200_LM0_SOURCE_MATERIAL_0 << R200_FRONT_SHININESS_SOURCE_SHIFT |
1291 R200_LM0_SOURCE_MATERIAL_1 << R200_BACK_SHININESS_SOURCE_SHIFT);
1292
1293 rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL_1] =
1294 ((R200_LM1_SOURCE_MATERIAL_0 << R200_FRONT_EMISSIVE_SOURCE_SHIFT) |
1295 (R200_LM1_SOURCE_MATERIAL_0 << R200_FRONT_AMBIENT_SOURCE_SHIFT) |
1296 (R200_LM1_SOURCE_MATERIAL_0 << R200_FRONT_DIFFUSE_SOURCE_SHIFT) |
1297 (R200_LM1_SOURCE_MATERIAL_0 << R200_FRONT_SPECULAR_SOURCE_SHIFT) |
1298 (R200_LM1_SOURCE_MATERIAL_1 << R200_BACK_EMISSIVE_SOURCE_SHIFT) |
1299 (R200_LM1_SOURCE_MATERIAL_1 << R200_BACK_AMBIENT_SOURCE_SHIFT) |
1300 (R200_LM1_SOURCE_MATERIAL_1 << R200_BACK_DIFFUSE_SOURCE_SHIFT) |
1301 (R200_LM1_SOURCE_MATERIAL_1 << R200_BACK_SPECULAR_SOURCE_SHIFT));
1302
1303 rmesa->hw.tcl.cmd[TCL_PER_LIGHT_CTL_0] = 0; /* filled in via callbacks */
1304 rmesa->hw.tcl.cmd[TCL_PER_LIGHT_CTL_1] = 0;
1305 rmesa->hw.tcl.cmd[TCL_PER_LIGHT_CTL_2] = 0;
1306 rmesa->hw.tcl.cmd[TCL_PER_LIGHT_CTL_3] = 0;
1307
1308 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] =
1309 (R200_UCP_IN_CLIP_SPACE |
1310 R200_CULL_FRONT_IS_CCW);
1311
1312 /* Texgen/Texmat state */
1313 rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_2] = 0x00ffffff;
1314 rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_3] =
1315 ((0 << R200_TEXGEN_0_INPUT_TEX_SHIFT) |
1316 (1 << R200_TEXGEN_1_INPUT_TEX_SHIFT) |
1317 (2 << R200_TEXGEN_2_INPUT_TEX_SHIFT) |
1318 (3 << R200_TEXGEN_3_INPUT_TEX_SHIFT) |
1319 (4 << R200_TEXGEN_4_INPUT_TEX_SHIFT) |
1320 (5 << R200_TEXGEN_5_INPUT_TEX_SHIFT));
1321 rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_0] = 0;
1322 rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_1] =
1323 ((0 << R200_TEXGEN_0_INPUT_SHIFT) |
1324 (1 << R200_TEXGEN_1_INPUT_SHIFT) |
1325 (2 << R200_TEXGEN_2_INPUT_SHIFT) |
1326 (3 << R200_TEXGEN_3_INPUT_SHIFT) |
1327 (4 << R200_TEXGEN_4_INPUT_SHIFT) |
1328 (5 << R200_TEXGEN_5_INPUT_SHIFT));
1329 rmesa->hw.tcg.cmd[TCG_TEX_CYL_WRAP_CTL] = 0;
1330
1331
1332 for (i = 0 ; i < 8; i++) {
1333 struct gl_light *l = &ctx->Light.Light[i];
1334 GLenum p = GL_LIGHT0 + i;
1335 *(float *)&(rmesa->hw.lit[i].cmd[LIT_RANGE_CUTOFF]) = FLT_MAX;
1336
1337 ctx->Driver.Lightfv( ctx, p, GL_AMBIENT, l->Ambient );
1338 ctx->Driver.Lightfv( ctx, p, GL_DIFFUSE, l->Diffuse );
1339 ctx->Driver.Lightfv( ctx, p, GL_SPECULAR, l->Specular );
1340 ctx->Driver.Lightfv( ctx, p, GL_POSITION, NULL );
1341 ctx->Driver.Lightfv( ctx, p, GL_SPOT_DIRECTION, NULL );
1342 ctx->Driver.Lightfv( ctx, p, GL_SPOT_EXPONENT, &l->SpotExponent );
1343 ctx->Driver.Lightfv( ctx, p, GL_SPOT_CUTOFF, &l->SpotCutoff );
1344 ctx->Driver.Lightfv( ctx, p, GL_CONSTANT_ATTENUATION,
1345 &l->ConstantAttenuation );
1346 ctx->Driver.Lightfv( ctx, p, GL_LINEAR_ATTENUATION,
1347 &l->LinearAttenuation );
1348 ctx->Driver.Lightfv( ctx, p, GL_QUADRATIC_ATTENUATION,
1349 &l->QuadraticAttenuation );
1350 *(float *)&(rmesa->hw.lit[i].cmd[LIT_ATTEN_XXX]) = 0.0;
1351 }
1352
1353 ctx->Driver.LightModelfv( ctx, GL_LIGHT_MODEL_AMBIENT,
1354 ctx->Light.Model.Ambient );
1355
1356 TNL_CONTEXT(ctx)->Driver.NotifyMaterialChange( ctx );
1357
1358 for (i = 0 ; i < 6; i++) {
1359 ctx->Driver.ClipPlane( ctx, GL_CLIP_PLANE0 + i, NULL );
1360 }
1361
1362 ctx->Driver.Fogfv( ctx, GL_FOG_MODE, NULL );
1363 ctx->Driver.Fogfv( ctx, GL_FOG_DENSITY, &ctx->Fog.Density );
1364 ctx->Driver.Fogfv( ctx, GL_FOG_START, &ctx->Fog.Start );
1365 ctx->Driver.Fogfv( ctx, GL_FOG_END, &ctx->Fog.End );
1366 ctx->Driver.Fogfv( ctx, GL_FOG_COLOR, ctx->Fog.Color );
1367 ctx->Driver.Fogfv( ctx, GL_FOG_COORDINATE_SOURCE_EXT, NULL );
1368
1369 rmesa->hw.grd.cmd[GRD_VERT_GUARD_CLIP_ADJ] = IEEE_ONE;
1370 rmesa->hw.grd.cmd[GRD_VERT_GUARD_DISCARD_ADJ] = IEEE_ONE;
1371 rmesa->hw.grd.cmd[GRD_HORZ_GUARD_CLIP_ADJ] = IEEE_ONE;
1372 rmesa->hw.grd.cmd[GRD_HORZ_GUARD_DISCARD_ADJ] = IEEE_ONE;
1373
1374 rmesa->hw.eye.cmd[EYE_X] = 0;
1375 rmesa->hw.eye.cmd[EYE_Y] = 0;
1376 rmesa->hw.eye.cmd[EYE_Z] = IEEE_ONE;
1377 rmesa->hw.eye.cmd[EYE_RESCALE_FACTOR] = IEEE_ONE;
1378
1379 rmesa->hw.spr.cmd[SPR_POINT_SPRITE_CNTL] =
1380 R200_PS_SE_SEL_STATE | R200_PS_MULT_CONST;
1381
1382 /* ptp_eye is presumably used to calculate the attenuation wrt a different
1383 location? In any case, since point attenuation triggers _needeyecoords,
1384 it is constant. Probably ignored as long as R200_PS_USE_MODEL_EYE_VEC
1385 isn't set */
1386 rmesa->hw.ptp.cmd[PTP_EYE_X] = 0;
1387 rmesa->hw.ptp.cmd[PTP_EYE_Y] = 0;
1388 rmesa->hw.ptp.cmd[PTP_EYE_Z] = IEEE_ONE | 0x80000000; /* -1.0 */
1389 rmesa->hw.ptp.cmd[PTP_EYE_3] = 0;
1390 /* no idea what the ptp_vport_scale values are good for, except the
1391 PTSIZE one - hopefully doesn't matter */
1392 rmesa->hw.ptp.cmd[PTP_VPORT_SCALE_0] = IEEE_ONE;
1393 rmesa->hw.ptp.cmd[PTP_VPORT_SCALE_1] = IEEE_ONE;
1394 rmesa->hw.ptp.cmd[PTP_VPORT_SCALE_PTSIZE] = IEEE_ONE;
1395 rmesa->hw.ptp.cmd[PTP_VPORT_SCALE_3] = IEEE_ONE;
1396 rmesa->hw.ptp.cmd[PTP_ATT_CONST_QUAD] = 0;
1397 rmesa->hw.ptp.cmd[PTP_ATT_CONST_LIN] = 0;
1398 rmesa->hw.ptp.cmd[PTP_ATT_CONST_CON] = IEEE_ONE;
1399 rmesa->hw.ptp.cmd[PTP_ATT_CONST_3] = 0;
1400 rmesa->hw.ptp.cmd[PTP_CLAMP_MIN] = IEEE_ONE;
1401 rmesa->hw.ptp.cmd[PTP_CLAMP_MAX] = 0x44ffe000; /* 2047 */
1402 rmesa->hw.ptp.cmd[PTP_CLAMP_2] = 0;
1403 rmesa->hw.ptp.cmd[PTP_CLAMP_3] = 0;
1404
1405 r200LightingSpaceChange( ctx );
1406
1407 rmesa->radeon.hw.all_dirty = GL_TRUE;
1408
1409 rcommonInitCmdBuf(&rmesa->radeon);
1410 }