1 /* $XFree86: xc/lib/GL/mesa/src/drv/r200/r200_state_init.c,v 1.4 2003/02/22 06:21:11 dawes Exp $ */
3 Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
5 The Weather Channel (TM) funded Tungsten Graphics to develop the
6 initial release of the Radeon 8500 driver under the XFree86 license.
7 This notice must be preserved.
9 Permission is hereby granted, free of charge, to any person obtaining
10 a copy of this software and associated documentation files (the
11 "Software"), to deal in the Software without restriction, including
12 without limitation the rights to use, copy, modify, merge, publish,
13 distribute, sublicense, and/or sell copies of the Software, and to
14 permit persons to whom the Software is furnished to do so, subject to
15 the following conditions:
17 The above copyright notice and this permission notice (including the
18 next paragraph) shall be included in all copies or substantial
19 portions of the Software.
21 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
22 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
23 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
24 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
25 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
26 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
27 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
32 * Keith Whitwell <keith@tungstengraphics.com>
39 #include "api_arrayelt.h"
41 #include "swrast/swrast.h"
44 #include "tnl/t_pipeline.h"
45 #include "swrast_setup/swrast_setup.h"
47 #include "r200_context.h"
48 #include "r200_ioctl.h"
49 #include "r200_state.h"
52 #include "r200_swtcl.h"
56 /* =============================================================
57 * State initialization
60 void r200PrintDirty( r200ContextPtr rmesa
, const char *msg
)
62 struct r200_state_atom
*l
;
65 fprintf(stderr
, ": ");
67 foreach(l
, &rmesa
->hw
.atomlist
) {
68 if (l
->dirty
|| rmesa
->hw
.all_dirty
)
69 fprintf(stderr
, "%s, ", l
->name
);
72 fprintf(stderr
, "\n");
75 static int cmdpkt( int id
)
77 drm_radeon_cmd_header_t h
;
79 h
.packet
.cmd_type
= RADEON_CMD_PACKET
;
80 h
.packet
.packet_id
= id
;
84 static int cmdvec( int offset
, int stride
, int count
)
86 drm_radeon_cmd_header_t h
;
88 h
.vectors
.cmd_type
= RADEON_CMD_VECTORS
;
89 h
.vectors
.offset
= offset
;
90 h
.vectors
.stride
= stride
;
91 h
.vectors
.count
= count
;
95 /* warning: the count here is divided by 4 compared to other cmds
96 (so it doesn't exceed the char size)! */
97 static int cmdveclinear( int offset
, int count
)
99 drm_radeon_cmd_header_t h
;
101 h
.veclinear
.cmd_type
= RADEON_CMD_VECLINEAR
;
102 h
.veclinear
.addr_lo
= offset
& 0xff;
103 h
.veclinear
.addr_hi
= (offset
& 0xff00) >> 8;
104 h
.veclinear
.count
= count
;
108 static int cmdscl( int offset
, int stride
, int count
)
110 drm_radeon_cmd_header_t h
;
112 h
.scalars
.cmd_type
= RADEON_CMD_SCALARS
;
113 h
.scalars
.offset
= offset
;
114 h
.scalars
.stride
= stride
;
115 h
.scalars
.count
= count
;
119 static int cmdscl2( int offset
, int stride
, int count
)
121 drm_radeon_cmd_header_t h
;
123 h
.scalars
.cmd_type
= RADEON_CMD_SCALARS2
;
124 h
.scalars
.offset
= offset
- 0x100;
125 h
.scalars
.stride
= stride
;
126 h
.scalars
.count
= count
;
130 #define CHECK( NM, FLAG ) \
131 static GLboolean check_##NM( GLcontext *ctx, int idx ) \
133 r200ContextPtr rmesa = R200_CONTEXT(ctx); \
139 #define TCL_CHECK( NM, FLAG ) \
140 static GLboolean check_##NM( GLcontext *ctx, int idx ) \
142 r200ContextPtr rmesa = R200_CONTEXT(ctx); \
144 return !rmesa->TclFallback && !ctx->VertexProgram._Enabled && (FLAG); \
147 #define TCL_OR_VP_CHECK( NM, FLAG ) \
148 static GLboolean check_##NM( GLcontext *ctx, int idx ) \
150 r200ContextPtr rmesa = R200_CONTEXT(ctx); \
152 return !rmesa->TclFallback && (FLAG); \
155 #define VP_CHECK( NM, FLAG ) \
156 static GLboolean check_##NM( GLcontext *ctx, int idx ) \
158 r200ContextPtr rmesa = R200_CONTEXT(ctx); \
160 return !rmesa->TclFallback && ctx->VertexProgram._Enabled && (FLAG); \
164 CHECK( always
, GL_TRUE
)
165 CHECK( never
, GL_FALSE
)
166 CHECK( tex_any
, ctx
->Texture
._EnabledUnits
)
167 CHECK( tf
, (ctx
->Texture
._EnabledUnits
&& !ctx
->ATIFragmentShader
._Enabled
) );
168 CHECK( tex_pair
, (rmesa
->state
.texture
.unit
[idx
].unitneeded
| rmesa
->state
.texture
.unit
[idx
& ~1].unitneeded
) )
169 CHECK( tex
, rmesa
->state
.texture
.unit
[idx
].unitneeded
)
170 CHECK( pix_zero
, !ctx
->ATIFragmentShader
._Enabled
)
171 CHECK( texenv
, (rmesa
->state
.envneeded
& (1 << idx
) && !ctx
->ATIFragmentShader
._Enabled
) )
172 CHECK( afs_pass1
, (ctx
->ATIFragmentShader
._Enabled
&& (ctx
->ATIFragmentShader
.Current
->NumPasses
> 1)) )
173 CHECK( afs
, ctx
->ATIFragmentShader
._Enabled
)
174 CHECK( tex_cube
, rmesa
->state
.texture
.unit
[idx
].unitneeded
& TEXTURE_CUBE_BIT
)
175 TCL_CHECK( tcl_fog
, ctx
->Fog
.Enabled
)
176 TCL_CHECK( tcl
, GL_TRUE
)
177 TCL_CHECK( tcl_tex
, rmesa
->state
.texture
.unit
[idx
].unitneeded
)
178 TCL_CHECK( tcl_lighting
, ctx
->Light
.Enabled
)
179 TCL_CHECK( tcl_light
, ctx
->Light
.Enabled
&& ctx
->Light
.Light
[idx
].Enabled
)
180 TCL_OR_VP_CHECK( tcl_ucp
, (ctx
->Transform
.ClipPlanesEnabled
& (1 << idx
)) )
181 TCL_OR_VP_CHECK( tcl_or_vp
, GL_TRUE
)
182 VP_CHECK( tcl_vp
, GL_TRUE
)
183 VP_CHECK( tcl_vp_size
, ctx
->VertexProgram
.Current
->Base
.NumNativeInstructions
> 64 )
184 VP_CHECK( tcl_vpp_size
, ctx
->VertexProgram
.Current
->Base
.NumNativeParameters
> 96 )
187 /* Initialize the context's hardware state.
189 void r200InitState( r200ContextPtr rmesa
)
191 GLcontext
*ctx
= rmesa
->glCtx
;
192 GLuint color_fmt
, depth_fmt
, i
;
193 GLint drawPitch
, drawOffset
;
195 switch ( rmesa
->r200Screen
->cpp
) {
197 color_fmt
= R200_COLOR_FORMAT_RGB565
;
200 color_fmt
= R200_COLOR_FORMAT_ARGB8888
;
203 fprintf( stderr
, "Error: Unsupported pixel depth... exiting\n" );
207 rmesa
->state
.color
.clear
= 0x00000000;
209 switch ( ctx
->Visual
.depthBits
) {
211 rmesa
->state
.depth
.clear
= 0x0000ffff;
212 rmesa
->state
.depth
.scale
= 1.0 / (GLfloat
)0xffff;
213 depth_fmt
= R200_DEPTH_FORMAT_16BIT_INT_Z
;
214 rmesa
->state
.stencil
.clear
= 0x00000000;
217 rmesa
->state
.depth
.clear
= 0x00ffffff;
218 rmesa
->state
.depth
.scale
= 1.0 / (GLfloat
)0xffffff;
219 depth_fmt
= R200_DEPTH_FORMAT_24BIT_INT_Z
;
220 rmesa
->state
.stencil
.clear
= 0xffff0000;
223 fprintf( stderr
, "Error: Unsupported depth %d... exiting\n",
224 ctx
->Visual
.depthBits
);
228 /* Only have hw stencil when depth buffer is 24 bits deep */
229 rmesa
->state
.stencil
.hwBuffer
= ( ctx
->Visual
.stencilBits
> 0 &&
230 ctx
->Visual
.depthBits
== 24 );
234 if ( ctx
->Visual
.doubleBufferMode
&& rmesa
->sarea
->pfCurrentPage
== 0 ) {
235 drawOffset
= rmesa
->r200Screen
->backOffset
;
236 drawPitch
= rmesa
->r200Screen
->backPitch
;
238 drawOffset
= rmesa
->r200Screen
->frontOffset
;
239 drawPitch
= rmesa
->r200Screen
->frontPitch
;
242 if ( ctx
->Visual
.doubleBufferMode
&& rmesa
->sarea
->pfCurrentPage
== 0 ) {
243 rmesa
->state
.color
.drawOffset
= rmesa
->r200Screen
->backOffset
;
244 rmesa
->state
.color
.drawPitch
= rmesa
->r200Screen
->backPitch
;
246 rmesa
->state
.color
.drawOffset
= rmesa
->r200Screen
->frontOffset
;
247 rmesa
->state
.color
.drawPitch
= rmesa
->r200Screen
->frontPitch
;
250 rmesa
->state
.pixel
.readOffset
= rmesa
->state
.color
.drawOffset
;
251 rmesa
->state
.pixel
.readPitch
= rmesa
->state
.color
.drawPitch
;
254 rmesa
->hw
.max_state_size
= 0;
256 #define ALLOC_STATE( ATOM, CHK, SZ, NM, IDX ) \
258 rmesa->hw.ATOM.cmd_size = SZ; \
259 rmesa->hw.ATOM.cmd = (int *)CALLOC(SZ * sizeof(int)); \
260 rmesa->hw.ATOM.lastcmd = (int *)CALLOC(SZ * sizeof(int)); \
261 rmesa->hw.ATOM.name = NM; \
262 rmesa->hw.ATOM.idx = IDX; \
263 rmesa->hw.ATOM.check = check_##CHK; \
264 rmesa->hw.ATOM.dirty = GL_FALSE; \
265 rmesa->hw.max_state_size += SZ * sizeof(int); \
269 /* Allocate state buffers:
271 if (rmesa
->r200Screen
->drmSupportsBlendColor
)
272 ALLOC_STATE( ctx
, always
, CTX_STATE_SIZE_NEWDRM
, "CTX/context", 0 );
274 ALLOC_STATE( ctx
, always
, CTX_STATE_SIZE_OLDDRM
, "CTX/context", 0 );
275 ALLOC_STATE( set
, always
, SET_STATE_SIZE
, "SET/setup", 0 );
276 ALLOC_STATE( lin
, always
, LIN_STATE_SIZE
, "LIN/line", 0 );
277 ALLOC_STATE( msk
, always
, MSK_STATE_SIZE
, "MSK/mask", 0 );
278 ALLOC_STATE( vpt
, always
, VPT_STATE_SIZE
, "VPT/viewport", 0 );
279 ALLOC_STATE( vtx
, always
, VTX_STATE_SIZE
, "VTX/vertex", 0 );
280 ALLOC_STATE( vap
, always
, VAP_STATE_SIZE
, "VAP/vap", 0 );
281 ALLOC_STATE( vte
, always
, VTE_STATE_SIZE
, "VTE/vte", 0 );
282 ALLOC_STATE( msc
, always
, MSC_STATE_SIZE
, "MSC/misc", 0 );
283 ALLOC_STATE( cst
, always
, CST_STATE_SIZE
, "CST/constant", 0 );
284 ALLOC_STATE( zbs
, always
, ZBS_STATE_SIZE
, "ZBS/zbias", 0 );
285 ALLOC_STATE( tf
, tf
, TF_STATE_SIZE
, "TF/tfactor", 0 );
286 if (rmesa
->r200Screen
->drmSupportsFragShader
) {
287 if (rmesa
->r200Screen
->chip_family
== CHIP_FAMILY_R200
) {
288 /* make sure texture units 0/1 are emitted pair-wise for r200 t0 hang workaround */
289 ALLOC_STATE( tex
[0], tex_pair
, TEX_STATE_SIZE_NEWDRM
, "TEX/tex-0", 0 );
290 ALLOC_STATE( tex
[1], tex_pair
, TEX_STATE_SIZE_NEWDRM
, "TEX/tex-1", 1 );
291 ALLOC_STATE( tam
, tex_any
, TAM_STATE_SIZE
, "TAM/tam", 0 );
294 ALLOC_STATE( tex
[0], tex
, TEX_STATE_SIZE_NEWDRM
, "TEX/tex-0", 0 );
295 ALLOC_STATE( tex
[1], tex
, TEX_STATE_SIZE_NEWDRM
, "TEX/tex-1", 1 );
296 ALLOC_STATE( tam
, never
, TAM_STATE_SIZE
, "TAM/tam", 0 );
298 ALLOC_STATE( tex
[2], tex
, TEX_STATE_SIZE_NEWDRM
, "TEX/tex-2", 2 );
299 ALLOC_STATE( tex
[3], tex
, TEX_STATE_SIZE_NEWDRM
, "TEX/tex-3", 3 );
300 ALLOC_STATE( tex
[4], tex
, TEX_STATE_SIZE_NEWDRM
, "TEX/tex-4", 4 );
301 ALLOC_STATE( tex
[5], tex
, TEX_STATE_SIZE_NEWDRM
, "TEX/tex-5", 5 );
302 ALLOC_STATE( atf
, afs
, ATF_STATE_SIZE
, "ATF/tfactor", 0 );
303 ALLOC_STATE( afs
[0], afs_pass1
, AFS_STATE_SIZE
, "AFS/afsinst-0", 0 );
304 ALLOC_STATE( afs
[1], afs
, AFS_STATE_SIZE
, "AFS/afsinst-1", 1 );
307 if (rmesa
->r200Screen
->chip_family
== CHIP_FAMILY_R200
) {
308 ALLOC_STATE( tex
[0], tex_pair
, TEX_STATE_SIZE_OLDDRM
, "TEX/tex-0", 0 );
309 ALLOC_STATE( tex
[1], tex_pair
, TEX_STATE_SIZE_OLDDRM
, "TEX/tex-1", 1 );
310 ALLOC_STATE( tam
, tex_any
, TAM_STATE_SIZE
, "TAM/tam", 0 );
313 ALLOC_STATE( tex
[0], tex
, TEX_STATE_SIZE_OLDDRM
, "TEX/tex-0", 0 );
314 ALLOC_STATE( tex
[1], tex
, TEX_STATE_SIZE_OLDDRM
, "TEX/tex-1", 1 );
315 ALLOC_STATE( tam
, never
, TAM_STATE_SIZE
, "TAM/tam", 0 );
317 ALLOC_STATE( tex
[2], tex
, TEX_STATE_SIZE_OLDDRM
, "TEX/tex-2", 2 );
318 ALLOC_STATE( tex
[3], tex
, TEX_STATE_SIZE_OLDDRM
, "TEX/tex-3", 3 );
319 ALLOC_STATE( tex
[4], tex
, TEX_STATE_SIZE_OLDDRM
, "TEX/tex-4", 4 );
320 ALLOC_STATE( tex
[5], tex
, TEX_STATE_SIZE_OLDDRM
, "TEX/tex-5", 5 );
321 ALLOC_STATE( atf
, never
, ATF_STATE_SIZE
, "TF/tfactor", 0 );
322 ALLOC_STATE( afs
[0], never
, AFS_STATE_SIZE
, "AFS/afsinst-0", 0 );
323 ALLOC_STATE( afs
[1], never
, AFS_STATE_SIZE
, "AFS/afsinst-1", 1 );
325 if (rmesa
->r200Screen
->drmSupportsCubeMapsR200
) {
326 ALLOC_STATE( cube
[0], tex_cube
, CUBE_STATE_SIZE
, "CUBE/tex-0", 0 );
327 ALLOC_STATE( cube
[1], tex_cube
, CUBE_STATE_SIZE
, "CUBE/tex-1", 1 );
328 ALLOC_STATE( cube
[2], tex_cube
, CUBE_STATE_SIZE
, "CUBE/tex-2", 2 );
329 ALLOC_STATE( cube
[3], tex_cube
, CUBE_STATE_SIZE
, "CUBE/tex-3", 3 );
330 ALLOC_STATE( cube
[4], tex_cube
, CUBE_STATE_SIZE
, "CUBE/tex-4", 4 );
331 ALLOC_STATE( cube
[5], tex_cube
, CUBE_STATE_SIZE
, "CUBE/tex-5", 5 );
334 ALLOC_STATE( cube
[0], never
, CUBE_STATE_SIZE
, "CUBE/tex-0", 0 );
335 ALLOC_STATE( cube
[1], never
, CUBE_STATE_SIZE
, "CUBE/tex-1", 1 );
336 ALLOC_STATE( cube
[2], never
, CUBE_STATE_SIZE
, "CUBE/tex-2", 2 );
337 ALLOC_STATE( cube
[3], never
, CUBE_STATE_SIZE
, "CUBE/tex-3", 3 );
338 ALLOC_STATE( cube
[4], never
, CUBE_STATE_SIZE
, "CUBE/tex-4", 4 );
339 ALLOC_STATE( cube
[5], never
, CUBE_STATE_SIZE
, "CUBE/tex-5", 5 );
341 if (rmesa
->r200Screen
->drmSupportsVertexProgram
) {
342 ALLOC_STATE( pvs
, tcl_vp
, PVS_STATE_SIZE
, "PVS/pvscntl", 0 );
343 ALLOC_STATE( vpi
[0], tcl_vp
, VPI_STATE_SIZE
, "VP/vertexprog-0", 0 );
344 ALLOC_STATE( vpi
[1], tcl_vp_size
, VPI_STATE_SIZE
, "VP/vertexprog-1", 1 );
345 ALLOC_STATE( vpp
[0], tcl_vp
, VPP_STATE_SIZE
, "VPP/vertexparam-0", 0 );
346 ALLOC_STATE( vpp
[1], tcl_vpp_size
, VPP_STATE_SIZE
, "VPP/vertexparam-1", 1 );
349 ALLOC_STATE( pvs
, never
, PVS_STATE_SIZE
, "PVS/pvscntl", 0 );
350 ALLOC_STATE( vpi
[0], never
, VPI_STATE_SIZE
, "VP/vertexprog-0", 0 );
351 ALLOC_STATE( vpi
[1], never
, VPI_STATE_SIZE
, "VP/vertexprog-1", 1 );
352 ALLOC_STATE( vpp
[0], never
, VPP_STATE_SIZE
, "VPP/vertexparam-0", 0 );
353 ALLOC_STATE( vpp
[1], never
, VPP_STATE_SIZE
, "VPP/vertexparam-1", 1 );
355 /* FIXME: this atom has two commands, we need only one (ucp_vert_blend) for vp */
356 ALLOC_STATE( tcl
, tcl_or_vp
, TCL_STATE_SIZE
, "TCL/tcl", 0 );
357 ALLOC_STATE( msl
, tcl
, MSL_STATE_SIZE
, "MSL/matrix-select", 0 );
358 ALLOC_STATE( tcg
, tcl
, TCG_STATE_SIZE
, "TCG/texcoordgen", 0 );
359 ALLOC_STATE( mtl
[0], tcl_lighting
, MTL_STATE_SIZE
, "MTL0/material0", 0 );
360 ALLOC_STATE( mtl
[1], tcl_lighting
, MTL_STATE_SIZE
, "MTL1/material1", 1 );
361 ALLOC_STATE( grd
, tcl_or_vp
, GRD_STATE_SIZE
, "GRD/guard-band", 0 );
362 ALLOC_STATE( fog
, tcl_fog
, FOG_STATE_SIZE
, "FOG/fog", 0 );
363 ALLOC_STATE( glt
, tcl_lighting
, GLT_STATE_SIZE
, "GLT/light-global", 0 );
364 ALLOC_STATE( eye
, tcl_lighting
, EYE_STATE_SIZE
, "EYE/eye-vector", 0 );
365 ALLOC_STATE( mat
[R200_MTX_MV
], tcl
, MAT_STATE_SIZE
, "MAT/modelview", 0 );
366 ALLOC_STATE( mat
[R200_MTX_IMV
], tcl
, MAT_STATE_SIZE
, "MAT/it-modelview", 0 );
367 ALLOC_STATE( mat
[R200_MTX_MVP
], tcl
, MAT_STATE_SIZE
, "MAT/modelproject", 0 );
368 ALLOC_STATE( mat
[R200_MTX_TEX0
], tcl_tex
, MAT_STATE_SIZE
, "MAT/texmat0", 0 );
369 ALLOC_STATE( mat
[R200_MTX_TEX1
], tcl_tex
, MAT_STATE_SIZE
, "MAT/texmat1", 1 );
370 ALLOC_STATE( mat
[R200_MTX_TEX2
], tcl_tex
, MAT_STATE_SIZE
, "MAT/texmat2", 2 );
371 ALLOC_STATE( mat
[R200_MTX_TEX3
], tcl_tex
, MAT_STATE_SIZE
, "MAT/texmat3", 3 );
372 ALLOC_STATE( mat
[R200_MTX_TEX4
], tcl_tex
, MAT_STATE_SIZE
, "MAT/texmat4", 4 );
373 ALLOC_STATE( mat
[R200_MTX_TEX5
], tcl_tex
, MAT_STATE_SIZE
, "MAT/texmat5", 5 );
374 ALLOC_STATE( ucp
[0], tcl_ucp
, UCP_STATE_SIZE
, "UCP/userclip-0", 0 );
375 ALLOC_STATE( ucp
[1], tcl_ucp
, UCP_STATE_SIZE
, "UCP/userclip-1", 1 );
376 ALLOC_STATE( ucp
[2], tcl_ucp
, UCP_STATE_SIZE
, "UCP/userclip-2", 2 );
377 ALLOC_STATE( ucp
[3], tcl_ucp
, UCP_STATE_SIZE
, "UCP/userclip-3", 3 );
378 ALLOC_STATE( ucp
[4], tcl_ucp
, UCP_STATE_SIZE
, "UCP/userclip-4", 4 );
379 ALLOC_STATE( ucp
[5], tcl_ucp
, UCP_STATE_SIZE
, "UCP/userclip-5", 5 );
380 ALLOC_STATE( lit
[0], tcl_light
, LIT_STATE_SIZE
, "LIT/light-0", 0 );
381 ALLOC_STATE( lit
[1], tcl_light
, LIT_STATE_SIZE
, "LIT/light-1", 1 );
382 ALLOC_STATE( lit
[2], tcl_light
, LIT_STATE_SIZE
, "LIT/light-2", 2 );
383 ALLOC_STATE( lit
[3], tcl_light
, LIT_STATE_SIZE
, "LIT/light-3", 3 );
384 ALLOC_STATE( lit
[4], tcl_light
, LIT_STATE_SIZE
, "LIT/light-4", 4 );
385 ALLOC_STATE( lit
[5], tcl_light
, LIT_STATE_SIZE
, "LIT/light-5", 5 );
386 ALLOC_STATE( lit
[6], tcl_light
, LIT_STATE_SIZE
, "LIT/light-6", 6 );
387 ALLOC_STATE( lit
[7], tcl_light
, LIT_STATE_SIZE
, "LIT/light-7", 7 );
388 ALLOC_STATE( pix
[0], pix_zero
, PIX_STATE_SIZE
, "PIX/pixstage-0", 0 );
389 ALLOC_STATE( pix
[1], texenv
, PIX_STATE_SIZE
, "PIX/pixstage-1", 1 );
390 ALLOC_STATE( pix
[2], texenv
, PIX_STATE_SIZE
, "PIX/pixstage-2", 2 );
391 ALLOC_STATE( pix
[3], texenv
, PIX_STATE_SIZE
, "PIX/pixstage-3", 3 );
392 ALLOC_STATE( pix
[4], texenv
, PIX_STATE_SIZE
, "PIX/pixstage-4", 4 );
393 ALLOC_STATE( pix
[5], texenv
, PIX_STATE_SIZE
, "PIX/pixstage-5", 5 );
394 if (rmesa
->r200Screen
->drmSupportsTriPerf
) {
395 ALLOC_STATE( prf
, always
, PRF_STATE_SIZE
, "PRF/performance-tri", 0 );
398 ALLOC_STATE( prf
, never
, PRF_STATE_SIZE
, "PRF/performance-tri", 0 );
400 if (rmesa
->r200Screen
->drmSupportsPointSprites
) {
401 ALLOC_STATE( spr
, always
, SPR_STATE_SIZE
, "SPR/pointsprite", 0 );
402 ALLOC_STATE( ptp
, tcl
, PTP_STATE_SIZE
, "PTP/pointparams", 0 );
405 ALLOC_STATE (spr
, never
, SPR_STATE_SIZE
, "SPR/pointsprite", 0 );
406 ALLOC_STATE (ptp
, never
, PTP_STATE_SIZE
, "PTP/pointparams", 0 );
409 r200SetUpAtomList( rmesa
);
411 /* Fill in the packet headers:
413 rmesa
->hw
.ctx
.cmd
[CTX_CMD_0
] = cmdpkt(RADEON_EMIT_PP_MISC
);
414 rmesa
->hw
.ctx
.cmd
[CTX_CMD_1
] = cmdpkt(RADEON_EMIT_PP_CNTL
);
415 rmesa
->hw
.ctx
.cmd
[CTX_CMD_2
] = cmdpkt(RADEON_EMIT_RB3D_COLORPITCH
);
416 if (rmesa
->r200Screen
->drmSupportsBlendColor
)
417 rmesa
->hw
.ctx
.cmd
[CTX_CMD_3
] = cmdpkt(R200_EMIT_RB3D_BLENDCOLOR
);
418 rmesa
->hw
.lin
.cmd
[LIN_CMD_0
] = cmdpkt(RADEON_EMIT_RE_LINE_PATTERN
);
419 rmesa
->hw
.lin
.cmd
[LIN_CMD_1
] = cmdpkt(RADEON_EMIT_SE_LINE_WIDTH
);
420 rmesa
->hw
.msk
.cmd
[MSK_CMD_0
] = cmdpkt(RADEON_EMIT_RB3D_STENCILREFMASK
);
421 rmesa
->hw
.vpt
.cmd
[VPT_CMD_0
] = cmdpkt(RADEON_EMIT_SE_VPORT_XSCALE
);
422 rmesa
->hw
.set
.cmd
[SET_CMD_0
] = cmdpkt(RADEON_EMIT_SE_CNTL
);
423 rmesa
->hw
.msc
.cmd
[MSC_CMD_0
] = cmdpkt(RADEON_EMIT_RE_MISC
);
424 rmesa
->hw
.cst
.cmd
[CST_CMD_0
] = cmdpkt(R200_EMIT_PP_CNTL_X
);
425 rmesa
->hw
.cst
.cmd
[CST_CMD_1
] = cmdpkt(R200_EMIT_RB3D_DEPTHXY_OFFSET
);
426 rmesa
->hw
.cst
.cmd
[CST_CMD_2
] = cmdpkt(R200_EMIT_RE_AUX_SCISSOR_CNTL
);
427 rmesa
->hw
.cst
.cmd
[CST_CMD_3
] = cmdpkt(R200_EMIT_RE_SCISSOR_TL_0
);
428 rmesa
->hw
.cst
.cmd
[CST_CMD_4
] = cmdpkt(R200_EMIT_SE_VAP_CNTL_STATUS
);
429 rmesa
->hw
.cst
.cmd
[CST_CMD_5
] = cmdpkt(R200_EMIT_RE_POINTSIZE
);
430 rmesa
->hw
.cst
.cmd
[CST_CMD_6
] = cmdpkt(R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0
);
431 rmesa
->hw
.tam
.cmd
[TAM_CMD_0
] = cmdpkt(R200_EMIT_PP_TAM_DEBUG3
);
432 rmesa
->hw
.tf
.cmd
[TF_CMD_0
] = cmdpkt(R200_EMIT_TFACTOR_0
);
433 if (rmesa
->r200Screen
->drmSupportsFragShader
) {
434 rmesa
->hw
.atf
.cmd
[ATF_CMD_0
] = cmdpkt(R200_EMIT_ATF_TFACTOR
);
435 rmesa
->hw
.tex
[0].cmd
[TEX_CMD_0
] = cmdpkt(R200_EMIT_PP_TXCTLALL_0
);
436 rmesa
->hw
.tex
[0].cmd
[TEX_CMD_1_NEWDRM
] = cmdpkt(R200_EMIT_PP_TXOFFSET_0
);
437 rmesa
->hw
.tex
[1].cmd
[TEX_CMD_0
] = cmdpkt(R200_EMIT_PP_TXCTLALL_1
);
438 rmesa
->hw
.tex
[1].cmd
[TEX_CMD_1_NEWDRM
] = cmdpkt(R200_EMIT_PP_TXOFFSET_1
);
439 rmesa
->hw
.tex
[2].cmd
[TEX_CMD_0
] = cmdpkt(R200_EMIT_PP_TXCTLALL_2
);
440 rmesa
->hw
.tex
[2].cmd
[TEX_CMD_1_NEWDRM
] = cmdpkt(R200_EMIT_PP_TXOFFSET_2
);
441 rmesa
->hw
.tex
[3].cmd
[TEX_CMD_0
] = cmdpkt(R200_EMIT_PP_TXCTLALL_3
);
442 rmesa
->hw
.tex
[3].cmd
[TEX_CMD_1_NEWDRM
] = cmdpkt(R200_EMIT_PP_TXOFFSET_3
);
443 rmesa
->hw
.tex
[4].cmd
[TEX_CMD_0
] = cmdpkt(R200_EMIT_PP_TXCTLALL_4
);
444 rmesa
->hw
.tex
[4].cmd
[TEX_CMD_1_NEWDRM
] = cmdpkt(R200_EMIT_PP_TXOFFSET_4
);
445 rmesa
->hw
.tex
[5].cmd
[TEX_CMD_0
] = cmdpkt(R200_EMIT_PP_TXCTLALL_5
);
446 rmesa
->hw
.tex
[5].cmd
[TEX_CMD_1_NEWDRM
] = cmdpkt(R200_EMIT_PP_TXOFFSET_5
);
448 rmesa
->hw
.tex
[0].cmd
[TEX_CMD_0
] = cmdpkt(R200_EMIT_PP_TXFILTER_0
);
449 rmesa
->hw
.tex
[0].cmd
[TEX_CMD_1_OLDDRM
] = cmdpkt(R200_EMIT_PP_TXOFFSET_0
);
450 rmesa
->hw
.tex
[1].cmd
[TEX_CMD_0
] = cmdpkt(R200_EMIT_PP_TXFILTER_1
);
451 rmesa
->hw
.tex
[1].cmd
[TEX_CMD_1_OLDDRM
] = cmdpkt(R200_EMIT_PP_TXOFFSET_1
);
452 rmesa
->hw
.tex
[2].cmd
[TEX_CMD_0
] = cmdpkt(R200_EMIT_PP_TXFILTER_2
);
453 rmesa
->hw
.tex
[2].cmd
[TEX_CMD_1_OLDDRM
] = cmdpkt(R200_EMIT_PP_TXOFFSET_2
);
454 rmesa
->hw
.tex
[3].cmd
[TEX_CMD_0
] = cmdpkt(R200_EMIT_PP_TXFILTER_3
);
455 rmesa
->hw
.tex
[3].cmd
[TEX_CMD_1_OLDDRM
] = cmdpkt(R200_EMIT_PP_TXOFFSET_3
);
456 rmesa
->hw
.tex
[4].cmd
[TEX_CMD_0
] = cmdpkt(R200_EMIT_PP_TXFILTER_4
);
457 rmesa
->hw
.tex
[4].cmd
[TEX_CMD_1_OLDDRM
] = cmdpkt(R200_EMIT_PP_TXOFFSET_4
);
458 rmesa
->hw
.tex
[5].cmd
[TEX_CMD_0
] = cmdpkt(R200_EMIT_PP_TXFILTER_5
);
459 rmesa
->hw
.tex
[5].cmd
[TEX_CMD_1_OLDDRM
] = cmdpkt(R200_EMIT_PP_TXOFFSET_5
);
461 rmesa
->hw
.afs
[0].cmd
[AFS_CMD_0
] = cmdpkt(R200_EMIT_PP_AFS_0
);
462 rmesa
->hw
.afs
[1].cmd
[AFS_CMD_0
] = cmdpkt(R200_EMIT_PP_AFS_1
);
463 rmesa
->hw
.pvs
.cmd
[PVS_CMD_0
] = cmdpkt(R200_EMIT_VAP_PVS_CNTL
);
464 rmesa
->hw
.cube
[0].cmd
[CUBE_CMD_0
] = cmdpkt(R200_EMIT_PP_CUBIC_FACES_0
);
465 rmesa
->hw
.cube
[0].cmd
[CUBE_CMD_1
] = cmdpkt(R200_EMIT_PP_CUBIC_OFFSETS_0
);
466 rmesa
->hw
.cube
[1].cmd
[CUBE_CMD_0
] = cmdpkt(R200_EMIT_PP_CUBIC_FACES_1
);
467 rmesa
->hw
.cube
[1].cmd
[CUBE_CMD_1
] = cmdpkt(R200_EMIT_PP_CUBIC_OFFSETS_1
);
468 rmesa
->hw
.cube
[2].cmd
[CUBE_CMD_0
] = cmdpkt(R200_EMIT_PP_CUBIC_FACES_2
);
469 rmesa
->hw
.cube
[2].cmd
[CUBE_CMD_1
] = cmdpkt(R200_EMIT_PP_CUBIC_OFFSETS_2
);
470 rmesa
->hw
.cube
[3].cmd
[CUBE_CMD_0
] = cmdpkt(R200_EMIT_PP_CUBIC_FACES_3
);
471 rmesa
->hw
.cube
[3].cmd
[CUBE_CMD_1
] = cmdpkt(R200_EMIT_PP_CUBIC_OFFSETS_3
);
472 rmesa
->hw
.cube
[4].cmd
[CUBE_CMD_0
] = cmdpkt(R200_EMIT_PP_CUBIC_FACES_4
);
473 rmesa
->hw
.cube
[4].cmd
[CUBE_CMD_1
] = cmdpkt(R200_EMIT_PP_CUBIC_OFFSETS_4
);
474 rmesa
->hw
.cube
[5].cmd
[CUBE_CMD_0
] = cmdpkt(R200_EMIT_PP_CUBIC_FACES_5
);
475 rmesa
->hw
.cube
[5].cmd
[CUBE_CMD_1
] = cmdpkt(R200_EMIT_PP_CUBIC_OFFSETS_5
);
476 rmesa
->hw
.pix
[0].cmd
[PIX_CMD_0
] = cmdpkt(R200_EMIT_PP_TXCBLEND_0
);
477 rmesa
->hw
.pix
[1].cmd
[PIX_CMD_0
] = cmdpkt(R200_EMIT_PP_TXCBLEND_1
);
478 rmesa
->hw
.pix
[2].cmd
[PIX_CMD_0
] = cmdpkt(R200_EMIT_PP_TXCBLEND_2
);
479 rmesa
->hw
.pix
[3].cmd
[PIX_CMD_0
] = cmdpkt(R200_EMIT_PP_TXCBLEND_3
);
480 rmesa
->hw
.pix
[4].cmd
[PIX_CMD_0
] = cmdpkt(R200_EMIT_PP_TXCBLEND_4
);
481 rmesa
->hw
.pix
[5].cmd
[PIX_CMD_0
] = cmdpkt(R200_EMIT_PP_TXCBLEND_5
);
482 rmesa
->hw
.zbs
.cmd
[ZBS_CMD_0
] = cmdpkt(RADEON_EMIT_SE_ZBIAS_FACTOR
);
483 rmesa
->hw
.tcl
.cmd
[TCL_CMD_0
] = cmdpkt(R200_EMIT_TCL_LIGHT_MODEL_CTL_0
);
484 rmesa
->hw
.tcl
.cmd
[TCL_CMD_1
] = cmdpkt(R200_EMIT_TCL_UCP_VERT_BLEND_CTL
);
485 rmesa
->hw
.tcg
.cmd
[TCG_CMD_0
] = cmdpkt(R200_EMIT_TEX_PROC_CTL_2
);
486 rmesa
->hw
.msl
.cmd
[MSL_CMD_0
] = cmdpkt(R200_EMIT_MATRIX_SELECT_0
);
487 rmesa
->hw
.vap
.cmd
[VAP_CMD_0
] = cmdpkt(R200_EMIT_VAP_CTL
);
488 rmesa
->hw
.vtx
.cmd
[VTX_CMD_0
] = cmdpkt(R200_EMIT_VTX_FMT_0
);
489 rmesa
->hw
.vtx
.cmd
[VTX_CMD_1
] = cmdpkt(R200_EMIT_OUTPUT_VTX_COMP_SEL
);
490 rmesa
->hw
.vtx
.cmd
[VTX_CMD_2
] = cmdpkt(R200_EMIT_SE_VTX_STATE_CNTL
);
491 rmesa
->hw
.vte
.cmd
[VTE_CMD_0
] = cmdpkt(R200_EMIT_VTE_CNTL
);
492 rmesa
->hw
.prf
.cmd
[PRF_CMD_0
] = cmdpkt(R200_EMIT_PP_TRI_PERF_CNTL
);
493 rmesa
->hw
.spr
.cmd
[SPR_CMD_0
] = cmdpkt(R200_EMIT_TCL_POINT_SPRITE_CNTL
);
494 rmesa
->hw
.mtl
[0].cmd
[MTL_CMD_0
] =
495 cmdvec( R200_VS_MAT_0_EMISS
, 1, 16 );
496 rmesa
->hw
.mtl
[0].cmd
[MTL_CMD_1
] =
497 cmdscl2( R200_SS_MAT_0_SHININESS
, 1, 1 );
498 rmesa
->hw
.mtl
[1].cmd
[MTL_CMD_0
] =
499 cmdvec( R200_VS_MAT_1_EMISS
, 1, 16 );
500 rmesa
->hw
.mtl
[1].cmd
[MTL_CMD_1
] =
501 cmdscl2( R200_SS_MAT_1_SHININESS
, 1, 1 );
503 rmesa
->hw
.vpi
[0].cmd
[VPI_CMD_0
] =
504 cmdveclinear( R200_PVS_PROG0
, 64 );
505 rmesa
->hw
.vpi
[1].cmd
[VPI_CMD_0
] =
506 cmdveclinear( R200_PVS_PROG1
, 64 );
507 rmesa
->hw
.vpp
[0].cmd
[VPP_CMD_0
] =
508 cmdveclinear( R200_PVS_PARAM0
, 96 );
509 rmesa
->hw
.vpp
[1].cmd
[VPP_CMD_0
] =
510 cmdveclinear( R200_PVS_PARAM1
, 96 );
512 rmesa
->hw
.grd
.cmd
[GRD_CMD_0
] =
513 cmdscl( R200_SS_VERT_GUARD_CLIP_ADJ_ADDR
, 1, 4 );
514 rmesa
->hw
.fog
.cmd
[FOG_CMD_0
] =
515 cmdvec( R200_VS_FOG_PARAM_ADDR
, 1, 4 );
516 rmesa
->hw
.glt
.cmd
[GLT_CMD_0
] =
517 cmdvec( R200_VS_GLOBAL_AMBIENT_ADDR
, 1, 4 );
518 rmesa
->hw
.eye
.cmd
[EYE_CMD_0
] =
519 cmdvec( R200_VS_EYE_VECTOR_ADDR
, 1, 4 );
521 rmesa
->hw
.mat
[R200_MTX_MV
].cmd
[MAT_CMD_0
] =
522 cmdvec( R200_VS_MATRIX_0_MV
, 1, 16);
523 rmesa
->hw
.mat
[R200_MTX_IMV
].cmd
[MAT_CMD_0
] =
524 cmdvec( R200_VS_MATRIX_1_INV_MV
, 1, 16);
525 rmesa
->hw
.mat
[R200_MTX_MVP
].cmd
[MAT_CMD_0
] =
526 cmdvec( R200_VS_MATRIX_2_MVP
, 1, 16);
527 rmesa
->hw
.mat
[R200_MTX_TEX0
].cmd
[MAT_CMD_0
] =
528 cmdvec( R200_VS_MATRIX_3_TEX0
, 1, 16);
529 rmesa
->hw
.mat
[R200_MTX_TEX1
].cmd
[MAT_CMD_0
] =
530 cmdvec( R200_VS_MATRIX_4_TEX1
, 1, 16);
531 rmesa
->hw
.mat
[R200_MTX_TEX2
].cmd
[MAT_CMD_0
] =
532 cmdvec( R200_VS_MATRIX_5_TEX2
, 1, 16);
533 rmesa
->hw
.mat
[R200_MTX_TEX3
].cmd
[MAT_CMD_0
] =
534 cmdvec( R200_VS_MATRIX_6_TEX3
, 1, 16);
535 rmesa
->hw
.mat
[R200_MTX_TEX4
].cmd
[MAT_CMD_0
] =
536 cmdvec( R200_VS_MATRIX_7_TEX4
, 1, 16);
537 rmesa
->hw
.mat
[R200_MTX_TEX5
].cmd
[MAT_CMD_0
] =
538 cmdvec( R200_VS_MATRIX_8_TEX5
, 1, 16);
540 for (i
= 0 ; i
< 8; i
++) {
541 rmesa
->hw
.lit
[i
].cmd
[LIT_CMD_0
] =
542 cmdvec( R200_VS_LIGHT_AMBIENT_ADDR
+ i
, 8, 24 );
543 rmesa
->hw
.lit
[i
].cmd
[LIT_CMD_1
] =
544 cmdscl( R200_SS_LIGHT_DCD_ADDR
+ i
, 8, 7 );
547 for (i
= 0 ; i
< 6; i
++) {
548 rmesa
->hw
.ucp
[i
].cmd
[UCP_CMD_0
] =
549 cmdvec( R200_VS_UCP_ADDR
+ i
, 1, 4 );
552 rmesa
->hw
.ptp
.cmd
[PTP_CMD_0
] =
553 cmdvec( R200_VS_PNT_SPRITE_VPORT_SCALE
, 1, 4 );
554 rmesa
->hw
.ptp
.cmd
[PTP_CMD_1
] =
555 cmdvec( R200_VS_PNT_SPRITE_ATT_CONST
, 1, 12 );
557 /* Initial Harware state:
559 rmesa
->hw
.ctx
.cmd
[CTX_PP_MISC
] = (R200_ALPHA_TEST_PASS
560 /* | R200_RIGHT_HAND_CUBE_OGL*/);
562 rmesa
->hw
.ctx
.cmd
[CTX_PP_FOG_COLOR
] = (R200_FOG_VERTEX
|
563 R200_FOG_USE_SPEC_ALPHA
);
565 rmesa
->hw
.ctx
.cmd
[CTX_RE_SOLID_COLOR
] = 0x00000000;
567 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_BLENDCNTL
] = (R200_COMB_FCN_ADD_CLAMP
|
568 (R200_BLEND_GL_ONE
<< R200_SRC_BLEND_SHIFT
) |
569 (R200_BLEND_GL_ZERO
<< R200_DST_BLEND_SHIFT
));
571 if (rmesa
->r200Screen
->drmSupportsBlendColor
) {
572 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_BLENDCOLOR
] = 0x00000000;
573 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ABLENDCNTL
] = (R200_COMB_FCN_ADD_CLAMP
|
574 (R200_BLEND_GL_ONE
<< R200_SRC_BLEND_SHIFT
) |
575 (R200_BLEND_GL_ZERO
<< R200_DST_BLEND_SHIFT
));
576 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_CBLENDCNTL
] = (R200_COMB_FCN_ADD_CLAMP
|
577 (R200_BLEND_GL_ONE
<< R200_SRC_BLEND_SHIFT
) |
578 (R200_BLEND_GL_ZERO
<< R200_DST_BLEND_SHIFT
));
581 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_DEPTHOFFSET
] =
582 rmesa
->r200Screen
->depthOffset
+ rmesa
->r200Screen
->fbLocation
;
584 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_DEPTHPITCH
] =
585 ((rmesa
->r200Screen
->depthPitch
&
586 R200_DEPTHPITCH_MASK
) |
587 R200_DEPTH_ENDIAN_NO_SWAP
);
589 if (rmesa
->using_hyperz
)
590 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_DEPTHPITCH
] |= R200_DEPTH_HYPERZ
;
592 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] = (depth_fmt
|
594 R200_STENCIL_TEST_ALWAYS
|
595 R200_STENCIL_FAIL_KEEP
|
596 R200_STENCIL_ZPASS_KEEP
|
597 R200_STENCIL_ZFAIL_KEEP
|
598 R200_Z_WRITE_ENABLE
);
600 if (rmesa
->using_hyperz
) {
601 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= R200_Z_COMPRESSION_ENABLE
|
602 R200_Z_DECOMPRESSION_ENABLE
;
603 /* if (rmesa->r200Screen->chip_family == CHIP_FAMILY_R200)
604 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_HIERARCHY_ENABLE;*/
607 rmesa
->hw
.ctx
.cmd
[CTX_PP_CNTL
] = (R200_ANTI_ALIAS_NONE
608 | R200_TEX_BLEND_0_ENABLE
);
610 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_CNTL
] = color_fmt
;
611 switch ( driQueryOptioni( &rmesa
->optionCache
, "dither_mode" ) ) {
612 case DRI_CONF_DITHER_XERRORDIFFRESET
:
613 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_CNTL
] |= R200_DITHER_INIT
;
615 case DRI_CONF_DITHER_ORDERED
:
616 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_CNTL
] |= R200_SCALE_DITHER_ENABLE
;
619 if ( driQueryOptioni( &rmesa
->optionCache
, "round_mode" ) ==
620 DRI_CONF_ROUND_ROUND
)
621 rmesa
->state
.color
.roundEnable
= R200_ROUND_ENABLE
;
623 rmesa
->state
.color
.roundEnable
= 0;
624 if ( driQueryOptioni (&rmesa
->optionCache
, "color_reduction" ) ==
625 DRI_CONF_COLOR_REDUCTION_DITHER
)
626 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_CNTL
] |= R200_DITHER_ENABLE
;
628 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_CNTL
] |= rmesa
->state
.color
.roundEnable
;
631 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_COLOROFFSET
] = ((rmesa
->state
.color
.drawOffset
+
632 rmesa
->r200Screen
->fbLocation
)
633 & R200_COLOROFFSET_MASK
);
635 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_COLORPITCH
] = ((rmesa
->state
.color
.drawPitch
&
636 R200_COLORPITCH_MASK
) |
637 R200_COLOR_ENDIAN_NO_SWAP
);
639 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_COLOROFFSET
] = ((drawOffset
+
640 rmesa
->r200Screen
->fbLocation
)
641 & R200_COLOROFFSET_MASK
);
643 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_COLORPITCH
] = ((drawPitch
&
644 R200_COLORPITCH_MASK
) |
645 R200_COLOR_ENDIAN_NO_SWAP
);
647 /* (fixed size) sarea is initialized to zero afaics so can omit version check. Phew! */
648 if (rmesa
->sarea
->tiling_enabled
) {
649 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_COLORPITCH
] |= R200_COLOR_TILE_ENABLE
;
652 rmesa
->hw
.prf
.cmd
[PRF_PP_TRI_PERF
] = R200_TRI_CUTOFF_MASK
- R200_TRI_CUTOFF_MASK
*
653 driQueryOptionf (&rmesa
->optionCache
,"texture_blend_quality");
654 rmesa
->hw
.prf
.cmd
[PRF_PP_PERF_CNTL
] = 0;
656 rmesa
->hw
.set
.cmd
[SET_SE_CNTL
] = (R200_FFACE_CULL_CCW
|
659 R200_FLAT_SHADE_VTX_LAST
|
660 R200_DIFFUSE_SHADE_GOURAUD
|
661 R200_ALPHA_SHADE_GOURAUD
|
662 R200_SPECULAR_SHADE_GOURAUD
|
663 R200_FOG_SHADE_GOURAUD
|
664 R200_DISC_FOG_SHADE_GOURAUD
|
665 R200_VTX_PIX_CENTER_OGL
|
666 R200_ROUND_MODE_TRUNC
|
667 R200_ROUND_PREC_8TH_PIX
);
669 rmesa
->hw
.set
.cmd
[SET_RE_CNTL
] = (R200_PERSPECTIVE_ENABLE
|
670 R200_SCISSOR_ENABLE
);
672 rmesa
->hw
.lin
.cmd
[LIN_RE_LINE_PATTERN
] = ((1 << 16) | 0xffff);
674 rmesa
->hw
.lin
.cmd
[LIN_RE_LINE_STATE
] =
675 ((0 << R200_LINE_CURRENT_PTR_SHIFT
) |
676 (1 << R200_LINE_CURRENT_COUNT_SHIFT
));
678 rmesa
->hw
.lin
.cmd
[LIN_SE_LINE_WIDTH
] = (1 << 4);
680 rmesa
->hw
.msk
.cmd
[MSK_RB3D_STENCILREFMASK
] =
681 ((0x00 << R200_STENCIL_REF_SHIFT
) |
682 (0xff << R200_STENCIL_MASK_SHIFT
) |
683 (0xff << R200_STENCIL_WRITEMASK_SHIFT
));
685 rmesa
->hw
.msk
.cmd
[MSK_RB3D_ROPCNTL
] = R200_ROP_COPY
;
686 rmesa
->hw
.msk
.cmd
[MSK_RB3D_PLANEMASK
] = 0xffffffff;
688 rmesa
->hw
.tam
.cmd
[TAM_DEBUG3
] = 0;
690 rmesa
->hw
.msc
.cmd
[MSC_RE_MISC
] =
691 ((0 << R200_STIPPLE_X_OFFSET_SHIFT
) |
692 (0 << R200_STIPPLE_Y_OFFSET_SHIFT
) |
693 R200_STIPPLE_BIG_BIT_ORDER
);
696 rmesa
->hw
.cst
.cmd
[CST_PP_CNTL_X
] = 0;
697 rmesa
->hw
.cst
.cmd
[CST_RB3D_DEPTHXY_OFFSET
] = 0;
698 rmesa
->hw
.cst
.cmd
[CST_RE_AUX_SCISSOR_CNTL
] = 0x0;
699 rmesa
->hw
.cst
.cmd
[CST_RE_SCISSOR_TL_0
] = 0;
700 rmesa
->hw
.cst
.cmd
[CST_RE_SCISSOR_BR_0
] = 0;
701 rmesa
->hw
.cst
.cmd
[CST_SE_VAP_CNTL_STATUS
] =
702 #ifdef MESA_BIG_ENDIAN
708 if (!(rmesa
->r200Screen
->chip_flags
& RADEON_CHIPSET_TCL
)) {
710 rmesa
->hw
.cst
.cmd
[CST_SE_VAP_CNTL_STATUS
] |= (1<<8);
713 rmesa
->hw
.cst
.cmd
[CST_RE_POINTSIZE
] =
714 (((GLuint
)(ctx
->Const
.MaxPointSize
* 16.0)) << R200_MAXPOINTSIZE_SHIFT
) | 0x10;
715 rmesa
->hw
.cst
.cmd
[CST_SE_TCL_INPUT_VTX_0
] =
716 (0x0 << R200_VERTEX_POSITION_ADDR__SHIFT
);
717 rmesa
->hw
.cst
.cmd
[CST_SE_TCL_INPUT_VTX_1
] =
718 (0x02 << R200_VTX_COLOR_0_ADDR__SHIFT
) |
719 (0x03 << R200_VTX_COLOR_1_ADDR__SHIFT
);
720 rmesa
->hw
.cst
.cmd
[CST_SE_TCL_INPUT_VTX_2
] =
721 (0x06 << R200_VTX_TEX_0_ADDR__SHIFT
) |
722 (0x07 << R200_VTX_TEX_1_ADDR__SHIFT
) |
723 (0x08 << R200_VTX_TEX_2_ADDR__SHIFT
) |
724 (0x09 << R200_VTX_TEX_3_ADDR__SHIFT
);
725 rmesa
->hw
.cst
.cmd
[CST_SE_TCL_INPUT_VTX_3
] =
726 (0x0A << R200_VTX_TEX_4_ADDR__SHIFT
) |
727 (0x0B << R200_VTX_TEX_5_ADDR__SHIFT
);
730 rmesa
->hw
.vpt
.cmd
[VPT_SE_VPORT_XSCALE
] = 0x00000000;
731 rmesa
->hw
.vpt
.cmd
[VPT_SE_VPORT_XOFFSET
] = 0x00000000;
732 rmesa
->hw
.vpt
.cmd
[VPT_SE_VPORT_YSCALE
] = 0x00000000;
733 rmesa
->hw
.vpt
.cmd
[VPT_SE_VPORT_YOFFSET
] = 0x00000000;
734 rmesa
->hw
.vpt
.cmd
[VPT_SE_VPORT_ZSCALE
] = 0x00000000;
735 rmesa
->hw
.vpt
.cmd
[VPT_SE_VPORT_ZOFFSET
] = 0x00000000;
737 for ( i
= 0 ; i
< ctx
->Const
.MaxTextureUnits
; i
++ ) {
738 rmesa
->hw
.tex
[i
].cmd
[TEX_PP_TXFILTER
] = R200_BORDER_MODE_OGL
;
739 rmesa
->hw
.tex
[i
].cmd
[TEX_PP_TXFORMAT
] =
740 ((i
<< R200_TXFORMAT_ST_ROUTE_SHIFT
) | /* <-- note i */
741 (2 << R200_TXFORMAT_WIDTH_SHIFT
) |
742 (2 << R200_TXFORMAT_HEIGHT_SHIFT
));
743 rmesa
->hw
.tex
[i
].cmd
[TEX_PP_BORDER_COLOR
] = 0;
744 rmesa
->hw
.tex
[i
].cmd
[TEX_PP_TXFORMAT_X
] =
745 (/* R200_TEXCOORD_PROJ | */
746 0x100000); /* Small default bias */
747 if (rmesa
->r200Screen
->drmSupportsFragShader
) {
748 rmesa
->hw
.tex
[i
].cmd
[TEX_PP_TXOFFSET_NEWDRM
] =
749 rmesa
->r200Screen
->texOffset
[RADEON_LOCAL_TEX_HEAP
];
750 rmesa
->hw
.tex
[i
].cmd
[TEX_PP_CUBIC_FACES
] = 0;
751 rmesa
->hw
.tex
[i
].cmd
[TEX_PP_TXMULTI_CTL
] = 0;
754 rmesa
->hw
.tex
[i
].cmd
[TEX_PP_TXOFFSET_OLDDRM
] =
755 rmesa
->r200Screen
->texOffset
[RADEON_LOCAL_TEX_HEAP
];
758 rmesa
->hw
.cube
[i
].cmd
[CUBE_PP_CUBIC_FACES
] = 0;
759 rmesa
->hw
.cube
[i
].cmd
[CUBE_PP_CUBIC_OFFSET_F1
] =
760 rmesa
->r200Screen
->texOffset
[RADEON_LOCAL_TEX_HEAP
];
761 rmesa
->hw
.cube
[i
].cmd
[CUBE_PP_CUBIC_OFFSET_F2
] =
762 rmesa
->r200Screen
->texOffset
[RADEON_LOCAL_TEX_HEAP
];
763 rmesa
->hw
.cube
[i
].cmd
[CUBE_PP_CUBIC_OFFSET_F3
] =
764 rmesa
->r200Screen
->texOffset
[RADEON_LOCAL_TEX_HEAP
];
765 rmesa
->hw
.cube
[i
].cmd
[CUBE_PP_CUBIC_OFFSET_F4
] =
766 rmesa
->r200Screen
->texOffset
[RADEON_LOCAL_TEX_HEAP
];
767 rmesa
->hw
.cube
[i
].cmd
[CUBE_PP_CUBIC_OFFSET_F5
] =
768 rmesa
->r200Screen
->texOffset
[RADEON_LOCAL_TEX_HEAP
];
770 rmesa
->hw
.pix
[i
].cmd
[PIX_PP_TXCBLEND
] =
771 (R200_TXC_ARG_A_ZERO
|
772 R200_TXC_ARG_B_ZERO
|
773 R200_TXC_ARG_C_DIFFUSE_COLOR
|
776 rmesa
->hw
.pix
[i
].cmd
[PIX_PP_TXCBLEND2
] =
777 ((i
<< R200_TXC_TFACTOR_SEL_SHIFT
) |
780 R200_TXC_OUTPUT_REG_R0
);
782 rmesa
->hw
.pix
[i
].cmd
[PIX_PP_TXABLEND
] =
783 (R200_TXA_ARG_A_ZERO
|
784 R200_TXA_ARG_B_ZERO
|
785 R200_TXA_ARG_C_DIFFUSE_ALPHA
|
788 rmesa
->hw
.pix
[i
].cmd
[PIX_PP_TXABLEND2
] =
789 ((i
<< R200_TXA_TFACTOR_SEL_SHIFT
) |
792 R200_TXA_OUTPUT_REG_R0
);
795 rmesa
->hw
.tf
.cmd
[TF_TFACTOR_0
] = 0;
796 rmesa
->hw
.tf
.cmd
[TF_TFACTOR_1
] = 0;
797 rmesa
->hw
.tf
.cmd
[TF_TFACTOR_2
] = 0;
798 rmesa
->hw
.tf
.cmd
[TF_TFACTOR_3
] = 0;
799 rmesa
->hw
.tf
.cmd
[TF_TFACTOR_4
] = 0;
800 rmesa
->hw
.tf
.cmd
[TF_TFACTOR_5
] = 0;
802 rmesa
->hw
.vap
.cmd
[VAP_SE_VAP_CNTL
] =
803 (R200_VAP_TCL_ENABLE
|
804 (0x9 << R200_VAP_VF_MAX_VTX_NUM__SHIFT
));
806 rmesa
->hw
.vte
.cmd
[VTE_SE_VTE_CNTL
] =
807 (R200_VPORT_X_SCALE_ENA
|
808 R200_VPORT_Y_SCALE_ENA
|
809 R200_VPORT_Z_SCALE_ENA
|
810 R200_VPORT_X_OFFSET_ENA
|
811 R200_VPORT_Y_OFFSET_ENA
|
812 R200_VPORT_Z_OFFSET_ENA
|
813 /* FIXME: Turn on for tex rect only */
814 R200_VTX_ST_DENORMALIZED
|
818 rmesa
->hw
.vtx
.cmd
[VTX_VTXFMT_0
] = 0;
819 rmesa
->hw
.vtx
.cmd
[VTX_VTXFMT_1
] = 0;
820 rmesa
->hw
.vtx
.cmd
[VTX_TCL_OUTPUT_VTXFMT_0
] =
821 ((R200_VTX_Z0
| R200_VTX_W0
|
822 (R200_VTX_FP_RGBA
<< R200_VTX_COLOR_0_SHIFT
)));
823 rmesa
->hw
.vtx
.cmd
[VTX_TCL_OUTPUT_VTXFMT_1
] = 0;
824 rmesa
->hw
.vtx
.cmd
[VTX_TCL_OUTPUT_COMPSEL
] = (R200_OUTPUT_XYZW
);
825 rmesa
->hw
.vtx
.cmd
[VTX_STATE_CNTL
] = R200_VSC_UPDATE_USER_COLOR_0_ENABLE
;
828 /* Matrix selection */
829 rmesa
->hw
.msl
.cmd
[MSL_MATRIX_SELECT_0
] =
830 (R200_MTX_MV
<< R200_MODELVIEW_0_SHIFT
);
832 rmesa
->hw
.msl
.cmd
[MSL_MATRIX_SELECT_1
] =
833 (R200_MTX_IMV
<< R200_IT_MODELVIEW_0_SHIFT
);
835 rmesa
->hw
.msl
.cmd
[MSL_MATRIX_SELECT_2
] =
836 (R200_MTX_MVP
<< R200_MODELPROJECT_0_SHIFT
);
838 rmesa
->hw
.msl
.cmd
[MSL_MATRIX_SELECT_3
] =
839 ((R200_MTX_TEX0
<< R200_TEXMAT_0_SHIFT
) |
840 (R200_MTX_TEX1
<< R200_TEXMAT_1_SHIFT
) |
841 (R200_MTX_TEX2
<< R200_TEXMAT_2_SHIFT
) |
842 (R200_MTX_TEX3
<< R200_TEXMAT_3_SHIFT
));
844 rmesa
->hw
.msl
.cmd
[MSL_MATRIX_SELECT_4
] =
845 ((R200_MTX_TEX4
<< R200_TEXMAT_4_SHIFT
) |
846 (R200_MTX_TEX5
<< R200_TEXMAT_5_SHIFT
));
849 /* General TCL state */
850 rmesa
->hw
.tcl
.cmd
[TCL_LIGHT_MODEL_CTL_0
] =
851 (R200_SPECULAR_LIGHTS
|
852 R200_DIFFUSE_SPECULAR_COMBINE
|
853 R200_LOCAL_LIGHT_VEC_GL
|
854 R200_LM0_SOURCE_MATERIAL_0
<< R200_FRONT_SHININESS_SOURCE_SHIFT
|
855 R200_LM0_SOURCE_MATERIAL_1
<< R200_BACK_SHININESS_SOURCE_SHIFT
);
857 rmesa
->hw
.tcl
.cmd
[TCL_LIGHT_MODEL_CTL_1
] =
858 ((R200_LM1_SOURCE_MATERIAL_0
<< R200_FRONT_EMISSIVE_SOURCE_SHIFT
) |
859 (R200_LM1_SOURCE_MATERIAL_0
<< R200_FRONT_AMBIENT_SOURCE_SHIFT
) |
860 (R200_LM1_SOURCE_MATERIAL_0
<< R200_FRONT_DIFFUSE_SOURCE_SHIFT
) |
861 (R200_LM1_SOURCE_MATERIAL_0
<< R200_FRONT_SPECULAR_SOURCE_SHIFT
) |
862 (R200_LM1_SOURCE_MATERIAL_1
<< R200_BACK_EMISSIVE_SOURCE_SHIFT
) |
863 (R200_LM1_SOURCE_MATERIAL_1
<< R200_BACK_AMBIENT_SOURCE_SHIFT
) |
864 (R200_LM1_SOURCE_MATERIAL_1
<< R200_BACK_DIFFUSE_SOURCE_SHIFT
) |
865 (R200_LM1_SOURCE_MATERIAL_1
<< R200_BACK_SPECULAR_SOURCE_SHIFT
));
867 rmesa
->hw
.tcl
.cmd
[TCL_PER_LIGHT_CTL_0
] = 0; /* filled in via callbacks */
868 rmesa
->hw
.tcl
.cmd
[TCL_PER_LIGHT_CTL_1
] = 0;
869 rmesa
->hw
.tcl
.cmd
[TCL_PER_LIGHT_CTL_2
] = 0;
870 rmesa
->hw
.tcl
.cmd
[TCL_PER_LIGHT_CTL_3
] = 0;
872 rmesa
->hw
.tcl
.cmd
[TCL_UCP_VERT_BLEND_CTL
] =
873 (R200_UCP_IN_CLIP_SPACE
|
874 R200_CULL_FRONT_IS_CCW
);
876 /* Texgen/Texmat state */
877 rmesa
->hw
.tcg
.cmd
[TCG_TEX_PROC_CTL_2
] = 0x00ffffff;
878 rmesa
->hw
.tcg
.cmd
[TCG_TEX_PROC_CTL_3
] =
879 ((0 << R200_TEXGEN_0_INPUT_TEX_SHIFT
) |
880 (1 << R200_TEXGEN_1_INPUT_TEX_SHIFT
) |
881 (2 << R200_TEXGEN_2_INPUT_TEX_SHIFT
) |
882 (3 << R200_TEXGEN_3_INPUT_TEX_SHIFT
) |
883 (4 << R200_TEXGEN_4_INPUT_TEX_SHIFT
) |
884 (5 << R200_TEXGEN_5_INPUT_TEX_SHIFT
));
885 rmesa
->hw
.tcg
.cmd
[TCG_TEX_PROC_CTL_0
] = 0;
886 rmesa
->hw
.tcg
.cmd
[TCG_TEX_PROC_CTL_1
] =
887 ((0 << R200_TEXGEN_0_INPUT_SHIFT
) |
888 (1 << R200_TEXGEN_1_INPUT_SHIFT
) |
889 (2 << R200_TEXGEN_2_INPUT_SHIFT
) |
890 (3 << R200_TEXGEN_3_INPUT_SHIFT
) |
891 (4 << R200_TEXGEN_4_INPUT_SHIFT
) |
892 (5 << R200_TEXGEN_5_INPUT_SHIFT
));
893 rmesa
->hw
.tcg
.cmd
[TCG_TEX_CYL_WRAP_CTL
] = 0;
896 for (i
= 0 ; i
< 8; i
++) {
897 struct gl_light
*l
= &ctx
->Light
.Light
[i
];
898 GLenum p
= GL_LIGHT0
+ i
;
899 *(float *)&(rmesa
->hw
.lit
[i
].cmd
[LIT_RANGE_CUTOFF
]) = FLT_MAX
;
901 ctx
->Driver
.Lightfv( ctx
, p
, GL_AMBIENT
, l
->Ambient
);
902 ctx
->Driver
.Lightfv( ctx
, p
, GL_DIFFUSE
, l
->Diffuse
);
903 ctx
->Driver
.Lightfv( ctx
, p
, GL_SPECULAR
, l
->Specular
);
904 ctx
->Driver
.Lightfv( ctx
, p
, GL_POSITION
, NULL
);
905 ctx
->Driver
.Lightfv( ctx
, p
, GL_SPOT_DIRECTION
, NULL
);
906 ctx
->Driver
.Lightfv( ctx
, p
, GL_SPOT_EXPONENT
, &l
->SpotExponent
);
907 ctx
->Driver
.Lightfv( ctx
, p
, GL_SPOT_CUTOFF
, &l
->SpotCutoff
);
908 ctx
->Driver
.Lightfv( ctx
, p
, GL_CONSTANT_ATTENUATION
,
909 &l
->ConstantAttenuation
);
910 ctx
->Driver
.Lightfv( ctx
, p
, GL_LINEAR_ATTENUATION
,
911 &l
->LinearAttenuation
);
912 ctx
->Driver
.Lightfv( ctx
, p
, GL_QUADRATIC_ATTENUATION
,
913 &l
->QuadraticAttenuation
);
914 *(float *)&(rmesa
->hw
.lit
[i
].cmd
[LIT_ATTEN_XXX
]) = 0.0;
917 ctx
->Driver
.LightModelfv( ctx
, GL_LIGHT_MODEL_AMBIENT
,
918 ctx
->Light
.Model
.Ambient
);
920 TNL_CONTEXT(ctx
)->Driver
.NotifyMaterialChange( ctx
);
922 for (i
= 0 ; i
< 6; i
++) {
923 ctx
->Driver
.ClipPlane( ctx
, GL_CLIP_PLANE0
+ i
, NULL
);
926 ctx
->Driver
.Fogfv( ctx
, GL_FOG_MODE
, NULL
);
927 ctx
->Driver
.Fogfv( ctx
, GL_FOG_DENSITY
, &ctx
->Fog
.Density
);
928 ctx
->Driver
.Fogfv( ctx
, GL_FOG_START
, &ctx
->Fog
.Start
);
929 ctx
->Driver
.Fogfv( ctx
, GL_FOG_END
, &ctx
->Fog
.End
);
930 ctx
->Driver
.Fogfv( ctx
, GL_FOG_COLOR
, ctx
->Fog
.Color
);
931 ctx
->Driver
.Fogfv( ctx
, GL_FOG_COORDINATE_SOURCE_EXT
, NULL
);
933 rmesa
->hw
.grd
.cmd
[GRD_VERT_GUARD_CLIP_ADJ
] = IEEE_ONE
;
934 rmesa
->hw
.grd
.cmd
[GRD_VERT_GUARD_DISCARD_ADJ
] = IEEE_ONE
;
935 rmesa
->hw
.grd
.cmd
[GRD_HORZ_GUARD_CLIP_ADJ
] = IEEE_ONE
;
936 rmesa
->hw
.grd
.cmd
[GRD_HORZ_GUARD_DISCARD_ADJ
] = IEEE_ONE
;
938 rmesa
->hw
.eye
.cmd
[EYE_X
] = 0;
939 rmesa
->hw
.eye
.cmd
[EYE_Y
] = 0;
940 rmesa
->hw
.eye
.cmd
[EYE_Z
] = IEEE_ONE
;
941 rmesa
->hw
.eye
.cmd
[EYE_RESCALE_FACTOR
] = IEEE_ONE
;
943 rmesa
->hw
.spr
.cmd
[SPR_POINT_SPRITE_CNTL
] =
944 R200_PS_SE_SEL_STATE
| R200_PS_MULT_CONST
;
946 /* ptp_eye is presumably used to calculate the attenuation wrt a different
947 location? In any case, since point attenuation triggers _needeyecoords,
948 it is constant. Probably ignored as long as R200_PS_USE_MODEL_EYE_VEC
950 rmesa
->hw
.ptp
.cmd
[PTP_EYE_X
] = 0;
951 rmesa
->hw
.ptp
.cmd
[PTP_EYE_Y
] = 0;
952 rmesa
->hw
.ptp
.cmd
[PTP_EYE_Z
] = IEEE_ONE
| 0x80000000; /* -1.0 */
953 rmesa
->hw
.ptp
.cmd
[PTP_EYE_3
] = 0;
954 /* no idea what the ptp_vport_scale values are good for, except the
955 PTSIZE one - hopefully doesn't matter */
956 rmesa
->hw
.ptp
.cmd
[PTP_VPORT_SCALE_0
] = IEEE_ONE
;
957 rmesa
->hw
.ptp
.cmd
[PTP_VPORT_SCALE_1
] = IEEE_ONE
;
958 rmesa
->hw
.ptp
.cmd
[PTP_VPORT_SCALE_PTSIZE
] = IEEE_ONE
;
959 rmesa
->hw
.ptp
.cmd
[PTP_VPORT_SCALE_3
] = IEEE_ONE
;
960 rmesa
->hw
.ptp
.cmd
[PTP_ATT_CONST_QUAD
] = 0;
961 rmesa
->hw
.ptp
.cmd
[PTP_ATT_CONST_LIN
] = 0;
962 rmesa
->hw
.ptp
.cmd
[PTP_ATT_CONST_CON
] = IEEE_ONE
;
963 rmesa
->hw
.ptp
.cmd
[PTP_ATT_CONST_3
] = 0;
964 rmesa
->hw
.ptp
.cmd
[PTP_CLAMP_MIN
] = IEEE_ONE
;
965 rmesa
->hw
.ptp
.cmd
[PTP_CLAMP_MAX
] = 0x44ffe000; /* 2047 */
966 rmesa
->hw
.ptp
.cmd
[PTP_CLAMP_2
] = 0;
967 rmesa
->hw
.ptp
.cmd
[PTP_CLAMP_3
] = 0;
969 r200LightingSpaceChange( ctx
);
971 rmesa
->hw
.all_dirty
= GL_TRUE
;