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Merge branch 'ext-provoking-vertex'
[mesa.git] / src / mesa / drivers / dri / r200 / r200_state_init.c
1 /*
2 Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
3
4 The Weather Channel (TM) funded Tungsten Graphics to develop the
5 initial release of the Radeon 8500 driver under the XFree86 license.
6 This notice must be preserved.
7
8 Permission is hereby granted, free of charge, to any person obtaining
9 a copy of this software and associated documentation files (the
10 "Software"), to deal in the Software without restriction, including
11 without limitation the rights to use, copy, modify, merge, publish,
12 distribute, sublicense, and/or sell copies of the Software, and to
13 permit persons to whom the Software is furnished to do so, subject to
14 the following conditions:
15
16 The above copyright notice and this permission notice (including the
17 next paragraph) shall be included in all copies or substantial
18 portions of the Software.
19
20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 */
28
29 /*
30 * Authors:
31 * Keith Whitwell <keith@tungstengraphics.com>
32 */
33
34 #include "main/glheader.h"
35 #include "main/imports.h"
36 #include "main/enums.h"
37 #include "main/colormac.h"
38 #include "main/api_arrayelt.h"
39
40 #include "swrast/swrast.h"
41 #include "vbo/vbo.h"
42 #include "tnl/tnl.h"
43 #include "tnl/t_pipeline.h"
44 #include "swrast_setup/swrast_setup.h"
45
46 #include "radeon_common.h"
47 #include "radeon_mipmap_tree.h"
48 #include "r200_context.h"
49 #include "r200_ioctl.h"
50 #include "r200_state.h"
51 #include "r200_tcl.h"
52 #include "r200_tex.h"
53 #include "r200_swtcl.h"
54
55 #include "xmlpool.h"
56
57 /* New (1.3) state mechanism. 3 commands (packet, scalar, vector) in
58 * 1.3 cmdbuffers allow all previous state to be updated as well as
59 * the tcl scalar and vector areas.
60 */
61 static struct {
62 int start;
63 int len;
64 const char *name;
65 } packet[RADEON_MAX_STATE_PACKETS] = {
66 {RADEON_PP_MISC, 7, "RADEON_PP_MISC"},
67 {RADEON_PP_CNTL, 3, "RADEON_PP_CNTL"},
68 {RADEON_RB3D_COLORPITCH, 1, "RADEON_RB3D_COLORPITCH"},
69 {RADEON_RE_LINE_PATTERN, 2, "RADEON_RE_LINE_PATTERN"},
70 {RADEON_SE_LINE_WIDTH, 1, "RADEON_SE_LINE_WIDTH"},
71 {RADEON_PP_LUM_MATRIX, 1, "RADEON_PP_LUM_MATRIX"},
72 {RADEON_PP_ROT_MATRIX_0, 2, "RADEON_PP_ROT_MATRIX_0"},
73 {RADEON_RB3D_STENCILREFMASK, 3, "RADEON_RB3D_STENCILREFMASK"},
74 {RADEON_SE_VPORT_XSCALE, 6, "RADEON_SE_VPORT_XSCALE"},
75 {RADEON_SE_CNTL, 2, "RADEON_SE_CNTL"},
76 {RADEON_SE_CNTL_STATUS, 1, "RADEON_SE_CNTL_STATUS"},
77 {RADEON_RE_MISC, 1, "RADEON_RE_MISC"},
78 {RADEON_PP_TXFILTER_0, 6, "RADEON_PP_TXFILTER_0"},
79 {RADEON_PP_BORDER_COLOR_0, 1, "RADEON_PP_BORDER_COLOR_0"},
80 {RADEON_PP_TXFILTER_1, 6, "RADEON_PP_TXFILTER_1"},
81 {RADEON_PP_BORDER_COLOR_1, 1, "RADEON_PP_BORDER_COLOR_1"},
82 {RADEON_PP_TXFILTER_2, 6, "RADEON_PP_TXFILTER_2"},
83 {RADEON_PP_BORDER_COLOR_2, 1, "RADEON_PP_BORDER_COLOR_2"},
84 {RADEON_SE_ZBIAS_FACTOR, 2, "RADEON_SE_ZBIAS_FACTOR"},
85 {RADEON_SE_TCL_OUTPUT_VTX_FMT, 11, "RADEON_SE_TCL_OUTPUT_VTX_FMT"},
86 {RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED, 17,
87 "RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED"},
88 {R200_PP_TXCBLEND_0, 4, "R200_PP_TXCBLEND_0"},
89 {R200_PP_TXCBLEND_1, 4, "R200_PP_TXCBLEND_1"},
90 {R200_PP_TXCBLEND_2, 4, "R200_PP_TXCBLEND_2"},
91 {R200_PP_TXCBLEND_3, 4, "R200_PP_TXCBLEND_3"},
92 {R200_PP_TXCBLEND_4, 4, "R200_PP_TXCBLEND_4"},
93 {R200_PP_TXCBLEND_5, 4, "R200_PP_TXCBLEND_5"},
94 {R200_PP_TXCBLEND_6, 4, "R200_PP_TXCBLEND_6"},
95 {R200_PP_TXCBLEND_7, 4, "R200_PP_TXCBLEND_7"},
96 {R200_SE_TCL_LIGHT_MODEL_CTL_0, 6, "R200_SE_TCL_LIGHT_MODEL_CTL_0"},
97 {R200_PP_TFACTOR_0, 6, "R200_PP_TFACTOR_0"},
98 {R200_SE_VTX_FMT_0, 4, "R200_SE_VTX_FMT_0"},
99 {R200_SE_VAP_CNTL, 1, "R200_SE_VAP_CNTL"},
100 {R200_SE_TCL_MATRIX_SEL_0, 5, "R200_SE_TCL_MATRIX_SEL_0"},
101 {R200_SE_TCL_TEX_PROC_CTL_2, 5, "R200_SE_TCL_TEX_PROC_CTL_2"},
102 {R200_SE_TCL_UCP_VERT_BLEND_CTL, 1, "R200_SE_TCL_UCP_VERT_BLEND_CTL"},
103 {R200_PP_TXFILTER_0, 6, "R200_PP_TXFILTER_0"},
104 {R200_PP_TXFILTER_1, 6, "R200_PP_TXFILTER_1"},
105 {R200_PP_TXFILTER_2, 6, "R200_PP_TXFILTER_2"},
106 {R200_PP_TXFILTER_3, 6, "R200_PP_TXFILTER_3"},
107 {R200_PP_TXFILTER_4, 6, "R200_PP_TXFILTER_4"},
108 {R200_PP_TXFILTER_5, 6, "R200_PP_TXFILTER_5"},
109 {R200_PP_TXOFFSET_0, 1, "R200_PP_TXOFFSET_0"},
110 {R200_PP_TXOFFSET_1, 1, "R200_PP_TXOFFSET_1"},
111 {R200_PP_TXOFFSET_2, 1, "R200_PP_TXOFFSET_2"},
112 {R200_PP_TXOFFSET_3, 1, "R200_PP_TXOFFSET_3"},
113 {R200_PP_TXOFFSET_4, 1, "R200_PP_TXOFFSET_4"},
114 {R200_PP_TXOFFSET_5, 1, "R200_PP_TXOFFSET_5"},
115 {R200_SE_VTE_CNTL, 1, "R200_SE_VTE_CNTL"},
116 {R200_SE_TCL_OUTPUT_VTX_COMP_SEL, 1,
117 "R200_SE_TCL_OUTPUT_VTX_COMP_SEL"},
118 {R200_PP_TAM_DEBUG3, 1, "R200_PP_TAM_DEBUG3"},
119 {R200_PP_CNTL_X, 1, "R200_PP_CNTL_X"},
120 {R200_RB3D_DEPTHXY_OFFSET, 1, "R200_RB3D_DEPTHXY_OFFSET"},
121 {R200_RE_AUX_SCISSOR_CNTL, 1, "R200_RE_AUX_SCISSOR_CNTL"},
122 {R200_RE_SCISSOR_TL_0, 2, "R200_RE_SCISSOR_TL_0"},
123 {R200_RE_SCISSOR_TL_1, 2, "R200_RE_SCISSOR_TL_1"},
124 {R200_RE_SCISSOR_TL_2, 2, "R200_RE_SCISSOR_TL_2"},
125 {R200_SE_VAP_CNTL_STATUS, 1, "R200_SE_VAP_CNTL_STATUS"},
126 {R200_SE_VTX_STATE_CNTL, 1, "R200_SE_VTX_STATE_CNTL"},
127 {R200_RE_POINTSIZE, 1, "R200_RE_POINTSIZE"},
128 {R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0, 4,
129 "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0"},
130 {R200_PP_CUBIC_FACES_0, 1, "R200_PP_CUBIC_FACES_0"}, /* 61 */
131 {R200_PP_CUBIC_OFFSET_F1_0, 5, "R200_PP_CUBIC_OFFSET_F1_0"}, /* 62 */
132 {R200_PP_CUBIC_FACES_1, 1, "R200_PP_CUBIC_FACES_1"},
133 {R200_PP_CUBIC_OFFSET_F1_1, 5, "R200_PP_CUBIC_OFFSET_F1_1"},
134 {R200_PP_CUBIC_FACES_2, 1, "R200_PP_CUBIC_FACES_2"},
135 {R200_PP_CUBIC_OFFSET_F1_2, 5, "R200_PP_CUBIC_OFFSET_F1_2"},
136 {R200_PP_CUBIC_FACES_3, 1, "R200_PP_CUBIC_FACES_3"},
137 {R200_PP_CUBIC_OFFSET_F1_3, 5, "R200_PP_CUBIC_OFFSET_F1_3"},
138 {R200_PP_CUBIC_FACES_4, 1, "R200_PP_CUBIC_FACES_4"},
139 {R200_PP_CUBIC_OFFSET_F1_4, 5, "R200_PP_CUBIC_OFFSET_F1_4"},
140 {R200_PP_CUBIC_FACES_5, 1, "R200_PP_CUBIC_FACES_5"},
141 {R200_PP_CUBIC_OFFSET_F1_5, 5, "R200_PP_CUBIC_OFFSET_F1_5"},
142 {RADEON_PP_TEX_SIZE_0, 2, "RADEON_PP_TEX_SIZE_0"},
143 {RADEON_PP_TEX_SIZE_1, 2, "RADEON_PP_TEX_SIZE_1"},
144 {RADEON_PP_TEX_SIZE_2, 2, "RADEON_PP_TEX_SIZE_2"},
145 {R200_RB3D_BLENDCOLOR, 3, "R200_RB3D_BLENDCOLOR"},
146 {R200_SE_TCL_POINT_SPRITE_CNTL, 1, "R200_SE_TCL_POINT_SPRITE_CNTL"},
147 {RADEON_PP_CUBIC_FACES_0, 1, "RADEON_PP_CUBIC_FACES_0"},
148 {RADEON_PP_CUBIC_OFFSET_T0_0, 5, "RADEON_PP_CUBIC_OFFSET_T0_0"},
149 {RADEON_PP_CUBIC_FACES_1, 1, "RADEON_PP_CUBIC_FACES_1"},
150 {RADEON_PP_CUBIC_OFFSET_T1_0, 5, "RADEON_PP_CUBIC_OFFSET_T1_0"},
151 {RADEON_PP_CUBIC_FACES_2, 1, "RADEON_PP_CUBIC_FACES_2"},
152 {RADEON_PP_CUBIC_OFFSET_T2_0, 5, "RADEON_PP_CUBIC_OFFSET_T2_0"},
153 {R200_PP_TRI_PERF, 2, "R200_PP_TRI_PERF"},
154 {R200_PP_TXCBLEND_8, 32, "R200_PP_AFS_0"}, /* 85 */
155 {R200_PP_TXCBLEND_0, 32, "R200_PP_AFS_1"},
156 {R200_PP_TFACTOR_0, 8, "R200_ATF_TFACTOR"},
157 {R200_PP_TXFILTER_0, 8, "R200_PP_TXCTLALL_0"},
158 {R200_PP_TXFILTER_1, 8, "R200_PP_TXCTLALL_1"},
159 {R200_PP_TXFILTER_2, 8, "R200_PP_TXCTLALL_2"},
160 {R200_PP_TXFILTER_3, 8, "R200_PP_TXCTLALL_3"},
161 {R200_PP_TXFILTER_4, 8, "R200_PP_TXCTLALL_4"},
162 {R200_PP_TXFILTER_5, 8, "R200_PP_TXCTLALL_5"},
163 {R200_VAP_PVS_CNTL_1, 2, "R200_VAP_PVS_CNTL"},
164 };
165
166 /* =============================================================
167 * State initialization
168 */
169 static int cmdpkt( r200ContextPtr rmesa, int id )
170 {
171 drm_radeon_cmd_header_t h;
172
173 if (rmesa->radeon.radeonScreen->kernel_mm) {
174 return CP_PACKET0(packet[id].start, packet[id].len - 1);
175 } else {
176 h.i = 0;
177 h.packet.cmd_type = RADEON_CMD_PACKET;
178 h.packet.packet_id = id;
179 }
180 return h.i;
181 }
182
183 static int cmdvec( int offset, int stride, int count )
184 {
185 drm_radeon_cmd_header_t h;
186 h.i = 0;
187 h.vectors.cmd_type = RADEON_CMD_VECTORS;
188 h.vectors.offset = offset;
189 h.vectors.stride = stride;
190 h.vectors.count = count;
191 return h.i;
192 }
193
194 /* warning: the count here is divided by 4 compared to other cmds
195 (so it doesn't exceed the char size)! */
196 static int cmdveclinear( int offset, int count )
197 {
198 drm_radeon_cmd_header_t h;
199 h.i = 0;
200 h.veclinear.cmd_type = RADEON_CMD_VECLINEAR;
201 h.veclinear.addr_lo = offset & 0xff;
202 h.veclinear.addr_hi = (offset & 0xff00) >> 8;
203 h.veclinear.count = count;
204 return h.i;
205 }
206
207 static int cmdscl( int offset, int stride, int count )
208 {
209 drm_radeon_cmd_header_t h;
210 h.i = 0;
211 h.scalars.cmd_type = RADEON_CMD_SCALARS;
212 h.scalars.offset = offset;
213 h.scalars.stride = stride;
214 h.scalars.count = count;
215 return h.i;
216 }
217
218 static int cmdscl2( int offset, int stride, int count )
219 {
220 drm_radeon_cmd_header_t h;
221 h.i = 0;
222 h.scalars.cmd_type = RADEON_CMD_SCALARS2;
223 h.scalars.offset = offset - 0x100;
224 h.scalars.stride = stride;
225 h.scalars.count = count;
226 return h.i;
227 }
228
229 #define CHECK( NM, FLAG ) \
230 static int check_##NM( GLcontext *ctx, struct radeon_state_atom *atom) \
231 { \
232 r200ContextPtr rmesa = R200_CONTEXT(ctx); \
233 (void) rmesa; \
234 return (FLAG) ? atom->cmd_size : 0; \
235 }
236
237 #define TCL_CHECK( NM, FLAG ) \
238 static int check_##NM( GLcontext *ctx, struct radeon_state_atom *atom) \
239 { \
240 r200ContextPtr rmesa = R200_CONTEXT(ctx); \
241 return (!rmesa->radeon.TclFallback && !ctx->VertexProgram._Enabled && (FLAG)) ? atom->cmd_size : 0; \
242 }
243
244 #define TCL_OR_VP_CHECK( NM, FLAG ) \
245 static int check_##NM( GLcontext *ctx, struct radeon_state_atom *atom ) \
246 { \
247 r200ContextPtr rmesa = R200_CONTEXT(ctx); \
248 return (!rmesa->radeon.TclFallback && (FLAG)) ? atom->cmd_size : 0; \
249 }
250
251 #define VP_CHECK( NM, FLAG ) \
252 static int check_##NM( GLcontext *ctx, struct radeon_state_atom *atom ) \
253 { \
254 r200ContextPtr rmesa = R200_CONTEXT(ctx); \
255 (void) atom; \
256 return (!rmesa->radeon.TclFallback && ctx->VertexProgram._Enabled && (FLAG)) ? atom->cmd_size : 0; \
257 }
258
259 CHECK( always, GL_TRUE )
260 CHECK( never, GL_FALSE )
261 CHECK( tex_any, ctx->Texture._EnabledUnits )
262 CHECK( tf, (ctx->Texture._EnabledUnits && !ctx->ATIFragmentShader._Enabled) );
263 CHECK( tex_pair, (rmesa->state.texture.unit[atom->idx].unitneeded | rmesa->state.texture.unit[atom->idx & ~1].unitneeded) )
264 CHECK( tex, rmesa->state.texture.unit[atom->idx].unitneeded )
265 CHECK( pix_zero, !ctx->ATIFragmentShader._Enabled )
266 CHECK( texenv, (rmesa->state.envneeded & (1 << (atom->idx)) && !ctx->ATIFragmentShader._Enabled) )
267 CHECK( afs_pass1, (ctx->ATIFragmentShader._Enabled && (ctx->ATIFragmentShader.Current->NumPasses > 1)) )
268 CHECK( afs, ctx->ATIFragmentShader._Enabled )
269 CHECK( tex_cube, rmesa->state.texture.unit[atom->idx].unitneeded & TEXTURE_CUBE_BIT )
270 TCL_CHECK( tcl_fog, ctx->Fog.Enabled )
271 TCL_CHECK( tcl, GL_TRUE )
272 TCL_CHECK( tcl_tex, rmesa->state.texture.unit[atom->idx].unitneeded )
273 TCL_CHECK( tcl_lighting, ctx->Light.Enabled )
274 TCL_CHECK( tcl_light, ctx->Light.Enabled && ctx->Light.Light[atom->idx].Enabled )
275 TCL_OR_VP_CHECK( tcl_ucp, (ctx->Transform.ClipPlanesEnabled & (1 << (atom->idx))) )
276 TCL_OR_VP_CHECK( tcl_or_vp, GL_TRUE )
277 VP_CHECK( tcl_vp, GL_TRUE )
278 VP_CHECK( tcl_vp_size, ctx->VertexProgram.Current->Base.NumNativeInstructions > 64 )
279 VP_CHECK( tcl_vpp_size, ctx->VertexProgram.Current->Base.NumNativeParameters > 96 )
280
281 #define OUT_VEC(hdr, data) do { \
282 drm_radeon_cmd_header_t h; \
283 h.i = hdr; \
284 OUT_BATCH(CP_PACKET0(RADEON_SE_TCL_STATE_FLUSH, 0)); \
285 OUT_BATCH(0); \
286 OUT_BATCH(CP_PACKET0(R200_SE_TCL_VECTOR_INDX_REG, 0)); \
287 OUT_BATCH(h.vectors.offset | (h.vectors.stride << RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT)); \
288 OUT_BATCH(CP_PACKET0_ONE(R200_SE_TCL_VECTOR_DATA_REG, h.vectors.count - 1)); \
289 OUT_BATCH_TABLE((data), h.vectors.count); \
290 } while(0)
291
292 #define OUT_VECLINEAR(hdr, data) do { \
293 drm_radeon_cmd_header_t h; \
294 uint32_t _start, _sz; \
295 h.i = hdr; \
296 _start = h.veclinear.addr_lo | (h.veclinear.addr_hi << 8); \
297 _sz = h.veclinear.count * 4; \
298 if (r200->radeon.radeonScreen->kernel_mm && _sz) { \
299 BEGIN_BATCH_NO_AUTOSTATE(dwords); \
300 OUT_BATCH(CP_PACKET0(RADEON_SE_TCL_STATE_FLUSH, 0)); \
301 OUT_BATCH(0); \
302 OUT_BATCH(CP_PACKET0(R200_SE_TCL_VECTOR_INDX_REG, 0)); \
303 OUT_BATCH(_start | (1 << RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT)); \
304 OUT_BATCH(CP_PACKET0_ONE(R200_SE_TCL_VECTOR_DATA_REG, _sz - 1)); \
305 OUT_BATCH_TABLE((data), _sz); \
306 END_BATCH(); \
307 } \
308 } while(0)
309
310 #define OUT_SCL(hdr, data) do { \
311 drm_radeon_cmd_header_t h; \
312 h.i = hdr; \
313 OUT_BATCH(CP_PACKET0(R200_SE_TCL_SCALAR_INDX_REG, 0)); \
314 OUT_BATCH((h.scalars.offset) | (h.scalars.stride << RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT)); \
315 OUT_BATCH(CP_PACKET0_ONE(R200_SE_TCL_SCALAR_DATA_REG, h.scalars.count - 1)); \
316 OUT_BATCH_TABLE((data), h.scalars.count); \
317 } while(0)
318
319 #define OUT_SCL2(hdr, data) do { \
320 drm_radeon_cmd_header_t h; \
321 h.i = hdr; \
322 OUT_BATCH(CP_PACKET0(R200_SE_TCL_SCALAR_INDX_REG, 0)); \
323 OUT_BATCH((h.scalars.offset + 0x100) | (h.scalars.stride << RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT)); \
324 OUT_BATCH(CP_PACKET0_ONE(R200_SE_TCL_SCALAR_DATA_REG, h.scalars.count - 1)); \
325 OUT_BATCH_TABLE((data), h.scalars.count); \
326 } while(0)
327
328 static void mtl_emit(GLcontext *ctx, struct radeon_state_atom *atom)
329 {
330 r200ContextPtr r200 = R200_CONTEXT(ctx);
331 BATCH_LOCALS(&r200->radeon);
332 uint32_t dwords = atom->cmd_size;
333
334 dwords += 6;
335 BEGIN_BATCH_NO_AUTOSTATE(dwords);
336 OUT_VEC(atom->cmd[MTL_CMD_0], (atom->cmd+1));
337 OUT_SCL2(atom->cmd[MTL_CMD_1], (atom->cmd + 18));
338 END_BATCH();
339 }
340
341 static void lit_emit(GLcontext *ctx, struct radeon_state_atom *atom)
342 {
343 r200ContextPtr r200 = R200_CONTEXT(ctx);
344 BATCH_LOCALS(&r200->radeon);
345 uint32_t dwords = atom->cmd_size;
346
347 dwords += 8;
348 BEGIN_BATCH_NO_AUTOSTATE(dwords);
349 OUT_VEC(atom->cmd[LIT_CMD_0], atom->cmd+1);
350 OUT_VEC(atom->cmd[LIT_CMD_1], atom->cmd+LIT_CMD_1+1);
351 END_BATCH();
352 }
353
354 static void ptp_emit(GLcontext *ctx, struct radeon_state_atom *atom)
355 {
356 r200ContextPtr r200 = R200_CONTEXT(ctx);
357 BATCH_LOCALS(&r200->radeon);
358 uint32_t dwords = atom->cmd_size;
359
360 dwords += 8;
361 BEGIN_BATCH_NO_AUTOSTATE(dwords);
362 OUT_VEC(atom->cmd[PTP_CMD_0], atom->cmd+1);
363 OUT_VEC(atom->cmd[PTP_CMD_1], atom->cmd+PTP_CMD_1+1);
364 END_BATCH();
365 }
366
367 static void veclinear_emit(GLcontext *ctx, struct radeon_state_atom *atom)
368 {
369 r200ContextPtr r200 = R200_CONTEXT(ctx);
370 BATCH_LOCALS(&r200->radeon);
371 uint32_t dwords = atom->cmd_size;
372
373 dwords += 4;
374 OUT_VECLINEAR(atom->cmd[0], atom->cmd+1);
375 }
376
377 static void scl_emit(GLcontext *ctx, struct radeon_state_atom *atom)
378 {
379 r200ContextPtr r200 = R200_CONTEXT(ctx);
380 BATCH_LOCALS(&r200->radeon);
381 uint32_t dwords = atom->cmd_size;
382
383 dwords += 2;
384 BEGIN_BATCH_NO_AUTOSTATE(dwords);
385 OUT_SCL(atom->cmd[0], atom->cmd+1);
386 END_BATCH();
387 }
388
389
390 static void vec_emit(GLcontext *ctx, struct radeon_state_atom *atom)
391 {
392 r200ContextPtr r200 = R200_CONTEXT(ctx);
393 BATCH_LOCALS(&r200->radeon);
394 uint32_t dwords = atom->cmd_size;
395
396 dwords += 4;
397 BEGIN_BATCH_NO_AUTOSTATE(dwords);
398 OUT_VEC(atom->cmd[0], atom->cmd+1);
399 END_BATCH();
400 }
401
402 static void ctx_emit(GLcontext *ctx, struct radeon_state_atom *atom)
403 {
404 r200ContextPtr r200 = R200_CONTEXT(ctx);
405 BATCH_LOCALS(&r200->radeon);
406 struct radeon_renderbuffer *rrb;
407 uint32_t cbpitch;
408 uint32_t zbpitch, depth_fmt;
409 uint32_t dwords = atom->cmd_size;
410
411 /* output the first 7 bytes of context */
412 BEGIN_BATCH_NO_AUTOSTATE(dwords+2+2);
413 OUT_BATCH_TABLE(atom->cmd, 5);
414
415 rrb = radeon_get_depthbuffer(&r200->radeon);
416 if (!rrb) {
417 OUT_BATCH(0);
418 OUT_BATCH(0);
419 } else {
420 zbpitch = (rrb->pitch / rrb->cpp);
421 if (r200->using_hyperz)
422 zbpitch |= RADEON_DEPTH_HYPERZ;
423 OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
424 OUT_BATCH(zbpitch);
425 if (rrb->cpp == 4)
426 depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
427 else
428 depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
429 atom->cmd[CTX_RB3D_ZSTENCILCNTL] &= ~RADEON_DEPTH_FORMAT_MASK;
430 atom->cmd[CTX_RB3D_ZSTENCILCNTL] |= depth_fmt;
431 }
432
433 OUT_BATCH(atom->cmd[CTX_RB3D_ZSTENCILCNTL]);
434 OUT_BATCH(atom->cmd[CTX_CMD_1]);
435 OUT_BATCH(atom->cmd[CTX_PP_CNTL]);
436
437 rrb = radeon_get_colorbuffer(&r200->radeon);
438 if (!rrb || !rrb->bo) {
439 OUT_BATCH(atom->cmd[CTX_RB3D_CNTL]);
440 OUT_BATCH(atom->cmd[CTX_RB3D_COLOROFFSET]);
441 } else {
442 atom->cmd[CTX_RB3D_CNTL] &= ~(0xf << 10);
443 if (rrb->cpp == 4)
444 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB8888;
445 else
446 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_RGB565;
447
448 OUT_BATCH(atom->cmd[CTX_RB3D_CNTL]);
449 OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
450 }
451
452 OUT_BATCH(atom->cmd[CTX_CMD_2]);
453
454 if (!rrb || !rrb->bo) {
455 OUT_BATCH(atom->cmd[CTX_RB3D_COLORPITCH]);
456 } else {
457 cbpitch = (rrb->pitch / rrb->cpp);
458 if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE)
459 cbpitch |= R200_COLOR_TILE_ENABLE;
460 OUT_BATCH(cbpitch);
461 }
462
463 if (atom->cmd_size == CTX_STATE_SIZE_NEWDRM)
464 OUT_BATCH_TABLE((atom->cmd + 14), 4);
465
466 END_BATCH();
467 }
468
469 static void ctx_emit_cs(GLcontext *ctx, struct radeon_state_atom *atom)
470 {
471 r200ContextPtr r200 = R200_CONTEXT(ctx);
472 BATCH_LOCALS(&r200->radeon);
473 struct radeon_renderbuffer *rrb, *drb;
474 uint32_t cbpitch = 0;
475 uint32_t zbpitch = 0;
476 uint32_t dwords = atom->cmd_size;
477 uint32_t depth_fmt;
478
479 rrb = radeon_get_colorbuffer(&r200->radeon);
480 if (!rrb || !rrb->bo) {
481 return;
482 }
483
484 atom->cmd[CTX_RB3D_CNTL] &= ~(0xf << 10);
485 if (rrb->cpp == 4)
486 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB8888;
487 else
488 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_RGB565;
489
490 cbpitch = (rrb->pitch / rrb->cpp);
491 if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE)
492 cbpitch |= R200_COLOR_TILE_ENABLE;
493
494 drb = radeon_get_depthbuffer(&r200->radeon);
495 if (drb) {
496 zbpitch = (drb->pitch / drb->cpp);
497 if (drb->cpp == 4)
498 depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
499 else
500 depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
501 atom->cmd[CTX_RB3D_ZSTENCILCNTL] &= ~RADEON_DEPTH_FORMAT_MASK;
502 atom->cmd[CTX_RB3D_ZSTENCILCNTL] |= depth_fmt;
503 }
504
505 dwords = 10;
506 if (drb)
507 dwords += 6;
508 if (rrb)
509 dwords += 6;
510 if (atom->cmd_size == CTX_STATE_SIZE_NEWDRM)
511 dwords += 4;
512
513 /* output the first 7 bytes of context */
514 BEGIN_BATCH_NO_AUTOSTATE(dwords);
515
516 /* In the CS case we need to split this up */
517 OUT_BATCH(CP_PACKET0(packet[0].start, 3));
518 OUT_BATCH_TABLE((atom->cmd + 1), 4);
519
520 if (drb) {
521 OUT_BATCH(CP_PACKET0(RADEON_RB3D_DEPTHOFFSET, 0));
522 OUT_BATCH_RELOC(0, drb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
523
524 OUT_BATCH(CP_PACKET0(RADEON_RB3D_DEPTHPITCH, 0));
525 OUT_BATCH(zbpitch);
526 }
527
528 OUT_BATCH(CP_PACKET0(RADEON_RB3D_ZSTENCILCNTL, 0));
529 OUT_BATCH(atom->cmd[CTX_RB3D_ZSTENCILCNTL]);
530 OUT_BATCH(CP_PACKET0(RADEON_PP_CNTL, 1));
531 OUT_BATCH(atom->cmd[CTX_PP_CNTL]);
532 OUT_BATCH(atom->cmd[CTX_RB3D_CNTL]);
533
534
535 if (rrb) {
536 OUT_BATCH(CP_PACKET0(RADEON_RB3D_COLOROFFSET, 0));
537 OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
538
539 OUT_BATCH(CP_PACKET0(RADEON_RB3D_COLORPITCH, 0));
540 OUT_BATCH(cbpitch);
541 }
542
543 if (atom->cmd_size == CTX_STATE_SIZE_NEWDRM) {
544 OUT_BATCH_TABLE((atom->cmd + 14), 4);
545 }
546
547 END_BATCH();
548 }
549
550 static void tex_emit(GLcontext *ctx, struct radeon_state_atom *atom)
551 {
552 r200ContextPtr r200 = R200_CONTEXT(ctx);
553 BATCH_LOCALS(&r200->radeon);
554 uint32_t dwords = atom->cmd_size;
555 int i = atom->idx;
556 radeonTexObj *t = r200->state.texture.unit[i].texobj;
557 radeon_mipmap_level *lvl;
558
559 if (t && t->mt && !t->image_override)
560 dwords += 2;
561 BEGIN_BATCH_NO_AUTOSTATE(dwords);
562 /* is this ok even with drm older than 1.18? */
563 OUT_BATCH_TABLE(atom->cmd, 10);
564
565 if (t && t->mt && !t->image_override) {
566 OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, 0,
567 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
568 } else if (!t) {
569 /* workaround for old CS mechanism */
570 OUT_BATCH(r200->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP]);
571 } else {
572 OUT_BATCH(t->override_offset);
573 }
574
575 END_BATCH();
576 }
577
578 static void tex_emit_cs(GLcontext *ctx, struct radeon_state_atom *atom)
579 {
580 r200ContextPtr r200 = R200_CONTEXT(ctx);
581 BATCH_LOCALS(&r200->radeon);
582 uint32_t dwords = atom->cmd_size;
583 int i = atom->idx;
584 radeonTexObj *t = r200->state.texture.unit[i].texobj;
585 radeon_mipmap_level *lvl;
586 int hastexture = 1;
587
588 if (!t)
589 hastexture = 0;
590 else {
591 if (!t->mt && !t->bo)
592 hastexture = 0;
593 }
594
595 if (hastexture)
596 dwords += 2;
597 else
598 dwords -= 2;
599 BEGIN_BATCH_NO_AUTOSTATE(dwords);
600
601 OUT_BATCH(CP_PACKET0(R200_PP_TXFILTER_0 + (32 * i), 7));
602 OUT_BATCH_TABLE((atom->cmd + 1), 8);
603
604 if (hastexture) {
605 OUT_BATCH(CP_PACKET0(R200_PP_TXOFFSET_0 + (24 * i), 0));
606 if (t->mt && !t->image_override) {
607 OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, 0,
608 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
609 } else {
610 if (t->bo)
611 OUT_BATCH_RELOC(t->tile_bits, t->bo, 0,
612 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
613 }
614 }
615 END_BATCH();
616 }
617
618
619 static void cube_emit(GLcontext *ctx, struct radeon_state_atom *atom)
620 {
621 r200ContextPtr r200 = R200_CONTEXT(ctx);
622 BATCH_LOCALS(&r200->radeon);
623 uint32_t dwords = 2;
624 int i = atom->idx, j;
625 radeonTexObj *t = r200->state.texture.unit[i].texobj;
626 radeon_mipmap_level *lvl;
627
628 BEGIN_BATCH_NO_AUTOSTATE(dwords + (4 * 5));
629 OUT_BATCH_TABLE(atom->cmd, 2);
630
631 if (t && !t->image_override) {
632 lvl = &t->mt->levels[0];
633 for (j = 1; j <= 5; j++) {
634 OUT_BATCH(CP_PACKET0(R200_PP_CUBIC_OFFSET_F1_0 + (24*i) + (4 * (j-1)), 0));
635 OUT_BATCH_RELOC(lvl->faces[j].offset, t->mt->bo, lvl->faces[j].offset,
636 RADEON_GEM_DOMAIN_VRAM, 0, 0);
637 }
638 }
639 END_BATCH();
640 }
641
642 /* Initialize the context's hardware state.
643 */
644 void r200InitState( r200ContextPtr rmesa )
645 {
646 GLcontext *ctx = rmesa->radeon.glCtx;
647 GLuint i;
648
649 rmesa->radeon.state.color.clear = 0x00000000;
650
651 switch ( ctx->Visual.depthBits ) {
652 case 16:
653 rmesa->radeon.state.depth.clear = 0x0000ffff;
654 rmesa->radeon.state.stencil.clear = 0x00000000;
655 break;
656 case 24:
657 default:
658 rmesa->radeon.state.depth.clear = 0x00ffffff;
659 rmesa->radeon.state.stencil.clear = 0xffff0000;
660 break;
661 }
662
663 rmesa->radeon.Fallback = 0;
664
665 rmesa->radeon.hw.max_state_size = 0;
666
667 #define ALLOC_STATE( ATOM, CHK, SZ, NM, IDX ) \
668 do { \
669 rmesa->hw.ATOM.cmd_size = SZ; \
670 rmesa->hw.ATOM.cmd = (GLuint *)CALLOC(SZ * sizeof(int)); \
671 rmesa->hw.ATOM.lastcmd = (GLuint *)CALLOC(SZ * sizeof(int)); \
672 rmesa->hw.ATOM.name = NM; \
673 rmesa->hw.ATOM.idx = IDX; \
674 rmesa->hw.ATOM.check = check_##CHK; \
675 rmesa->hw.ATOM.dirty = GL_FALSE; \
676 rmesa->radeon.hw.max_state_size += SZ * sizeof(int); \
677 } while (0)
678
679
680 /* Allocate state buffers:
681 */
682 if (rmesa->radeon.radeonScreen->drmSupportsBlendColor)
683 ALLOC_STATE( ctx, always, CTX_STATE_SIZE_NEWDRM, "CTX/context", 0 );
684 else
685 ALLOC_STATE( ctx, always, CTX_STATE_SIZE_OLDDRM, "CTX/context", 0 );
686
687 if (rmesa->radeon.radeonScreen->kernel_mm)
688 rmesa->hw.ctx.emit = ctx_emit_cs;
689 else
690 rmesa->hw.ctx.emit = ctx_emit;
691 ALLOC_STATE( set, always, SET_STATE_SIZE, "SET/setup", 0 );
692 ALLOC_STATE( lin, always, LIN_STATE_SIZE, "LIN/line", 0 );
693 ALLOC_STATE( msk, always, MSK_STATE_SIZE, "MSK/mask", 0 );
694 ALLOC_STATE( vpt, always, VPT_STATE_SIZE, "VPT/viewport", 0 );
695 ALLOC_STATE( vtx, always, VTX_STATE_SIZE, "VTX/vertex", 0 );
696 ALLOC_STATE( vap, always, VAP_STATE_SIZE, "VAP/vap", 0 );
697 ALLOC_STATE( vte, always, VTE_STATE_SIZE, "VTE/vte", 0 );
698 ALLOC_STATE( msc, always, MSC_STATE_SIZE, "MSC/misc", 0 );
699 ALLOC_STATE( cst, always, CST_STATE_SIZE, "CST/constant", 0 );
700 ALLOC_STATE( zbs, always, ZBS_STATE_SIZE, "ZBS/zbias", 0 );
701 ALLOC_STATE( tf, tf, TF_STATE_SIZE, "TF/tfactor", 0 );
702 if (rmesa->radeon.radeonScreen->drmSupportsFragShader) {
703 if (rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_R200) {
704 /* make sure texture units 0/1 are emitted pair-wise for r200 t0 hang workaround */
705 ALLOC_STATE( tex[0], tex_pair, TEX_STATE_SIZE_NEWDRM, "TEX/tex-0", 0 );
706 ALLOC_STATE( tex[1], tex_pair, TEX_STATE_SIZE_NEWDRM, "TEX/tex-1", 1 );
707 ALLOC_STATE( tam, tex_any, TAM_STATE_SIZE, "TAM/tam", 0 );
708 }
709 else {
710 ALLOC_STATE( tex[0], tex, TEX_STATE_SIZE_NEWDRM, "TEX/tex-0", 0 );
711 ALLOC_STATE( tex[1], tex, TEX_STATE_SIZE_NEWDRM, "TEX/tex-1", 1 );
712 ALLOC_STATE( tam, never, TAM_STATE_SIZE, "TAM/tam", 0 );
713 }
714 ALLOC_STATE( tex[2], tex, TEX_STATE_SIZE_NEWDRM, "TEX/tex-2", 2 );
715 ALLOC_STATE( tex[3], tex, TEX_STATE_SIZE_NEWDRM, "TEX/tex-3", 3 );
716 ALLOC_STATE( tex[4], tex, TEX_STATE_SIZE_NEWDRM, "TEX/tex-4", 4 );
717 ALLOC_STATE( tex[5], tex, TEX_STATE_SIZE_NEWDRM, "TEX/tex-5", 5 );
718 ALLOC_STATE( atf, afs, ATF_STATE_SIZE, "ATF/tfactor", 0 );
719 ALLOC_STATE( afs[0], afs_pass1, AFS_STATE_SIZE, "AFS/afsinst-0", 0 );
720 ALLOC_STATE( afs[1], afs, AFS_STATE_SIZE, "AFS/afsinst-1", 1 );
721 }
722 else {
723 if (rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_R200) {
724 ALLOC_STATE( tex[0], tex_pair, TEX_STATE_SIZE_OLDDRM, "TEX/tex-0", 0 );
725 ALLOC_STATE( tex[1], tex_pair, TEX_STATE_SIZE_OLDDRM, "TEX/tex-1", 1 );
726 ALLOC_STATE( tam, tex_any, TAM_STATE_SIZE, "TAM/tam", 0 );
727 }
728 else {
729 ALLOC_STATE( tex[0], tex, TEX_STATE_SIZE_OLDDRM, "TEX/tex-0", 0 );
730 ALLOC_STATE( tex[1], tex, TEX_STATE_SIZE_OLDDRM, "TEX/tex-1", 1 );
731 ALLOC_STATE( tam, never, TAM_STATE_SIZE, "TAM/tam", 0 );
732 }
733 ALLOC_STATE( tex[2], tex, TEX_STATE_SIZE_OLDDRM, "TEX/tex-2", 2 );
734 ALLOC_STATE( tex[3], tex, TEX_STATE_SIZE_OLDDRM, "TEX/tex-3", 3 );
735 ALLOC_STATE( tex[4], tex, TEX_STATE_SIZE_OLDDRM, "TEX/tex-4", 4 );
736 ALLOC_STATE( tex[5], tex, TEX_STATE_SIZE_OLDDRM, "TEX/tex-5", 5 );
737 ALLOC_STATE( atf, never, ATF_STATE_SIZE, "TF/tfactor", 0 );
738 ALLOC_STATE( afs[0], never, AFS_STATE_SIZE, "AFS/afsinst-0", 0 );
739 ALLOC_STATE( afs[1], never, AFS_STATE_SIZE, "AFS/afsinst-1", 1 );
740 }
741
742 for (i = 0; i < 5; i++)
743 if (rmesa->radeon.radeonScreen->kernel_mm)
744 rmesa->hw.tex[i].emit = tex_emit_cs;
745 else
746 rmesa->hw.tex[i].emit = tex_emit;
747 if (rmesa->radeon.radeonScreen->drmSupportsCubeMapsR200) {
748 ALLOC_STATE( cube[0], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-0", 0 );
749 ALLOC_STATE( cube[1], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-1", 1 );
750 ALLOC_STATE( cube[2], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-2", 2 );
751 ALLOC_STATE( cube[3], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-3", 3 );
752 ALLOC_STATE( cube[4], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-4", 4 );
753 ALLOC_STATE( cube[5], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-5", 5 );
754 for (i = 0; i < 5; i++)
755 rmesa->hw.cube[i].emit = cube_emit;
756 }
757 else {
758 ALLOC_STATE( cube[0], never, CUBE_STATE_SIZE, "CUBE/tex-0", 0 );
759 ALLOC_STATE( cube[1], never, CUBE_STATE_SIZE, "CUBE/tex-1", 1 );
760 ALLOC_STATE( cube[2], never, CUBE_STATE_SIZE, "CUBE/tex-2", 2 );
761 ALLOC_STATE( cube[3], never, CUBE_STATE_SIZE, "CUBE/tex-3", 3 );
762 ALLOC_STATE( cube[4], never, CUBE_STATE_SIZE, "CUBE/tex-4", 4 );
763 ALLOC_STATE( cube[5], never, CUBE_STATE_SIZE, "CUBE/tex-5", 5 );
764 }
765
766 if (rmesa->radeon.radeonScreen->drmSupportsVertexProgram) {
767 ALLOC_STATE( pvs, tcl_vp, PVS_STATE_SIZE, "PVS/pvscntl", 0 );
768 ALLOC_STATE( vpi[0], tcl_vp, VPI_STATE_SIZE, "VP/vertexprog-0", 0 );
769 ALLOC_STATE( vpi[1], tcl_vp_size, VPI_STATE_SIZE, "VP/vertexprog-1", 1 );
770 ALLOC_STATE( vpp[0], tcl_vp, VPP_STATE_SIZE, "VPP/vertexparam-0", 0 );
771 ALLOC_STATE( vpp[1], tcl_vpp_size, VPP_STATE_SIZE, "VPP/vertexparam-1", 1 );
772 }
773 else {
774 ALLOC_STATE( pvs, never, PVS_STATE_SIZE, "PVS/pvscntl", 0 );
775 ALLOC_STATE( vpi[0], never, VPI_STATE_SIZE, "VP/vertexprog-0", 0 );
776 ALLOC_STATE( vpi[1], never, VPI_STATE_SIZE, "VP/vertexprog-1", 1 );
777 ALLOC_STATE( vpp[0], never, VPP_STATE_SIZE, "VPP/vertexparam-0", 0 );
778 ALLOC_STATE( vpp[1], never, VPP_STATE_SIZE, "VPP/vertexparam-1", 1 );
779 }
780 /* FIXME: this atom has two commands, we need only one (ucp_vert_blend) for vp */
781 ALLOC_STATE( tcl, tcl_or_vp, TCL_STATE_SIZE, "TCL/tcl", 0 );
782 ALLOC_STATE( msl, tcl, MSL_STATE_SIZE, "MSL/matrix-select", 0 );
783 ALLOC_STATE( tcg, tcl, TCG_STATE_SIZE, "TCG/texcoordgen", 0 );
784 ALLOC_STATE( mtl[0], tcl_lighting, MTL_STATE_SIZE, "MTL0/material0", 0 );
785 ALLOC_STATE( mtl[1], tcl_lighting, MTL_STATE_SIZE, "MTL1/material1", 1 );
786 ALLOC_STATE( grd, tcl_or_vp, GRD_STATE_SIZE, "GRD/guard-band", 0 );
787 ALLOC_STATE( fog, tcl_fog, FOG_STATE_SIZE, "FOG/fog", 0 );
788 ALLOC_STATE( glt, tcl_lighting, GLT_STATE_SIZE, "GLT/light-global", 0 );
789 ALLOC_STATE( eye, tcl_lighting, EYE_STATE_SIZE, "EYE/eye-vector", 0 );
790 ALLOC_STATE( mat[R200_MTX_MV], tcl, MAT_STATE_SIZE, "MAT/modelview", 0 );
791 ALLOC_STATE( mat[R200_MTX_IMV], tcl, MAT_STATE_SIZE, "MAT/it-modelview", 0 );
792 ALLOC_STATE( mat[R200_MTX_MVP], tcl, MAT_STATE_SIZE, "MAT/modelproject", 0 );
793 ALLOC_STATE( mat[R200_MTX_TEX0], tcl_tex, MAT_STATE_SIZE, "MAT/texmat0", 0 );
794 ALLOC_STATE( mat[R200_MTX_TEX1], tcl_tex, MAT_STATE_SIZE, "MAT/texmat1", 1 );
795 ALLOC_STATE( mat[R200_MTX_TEX2], tcl_tex, MAT_STATE_SIZE, "MAT/texmat2", 2 );
796 ALLOC_STATE( mat[R200_MTX_TEX3], tcl_tex, MAT_STATE_SIZE, "MAT/texmat3", 3 );
797 ALLOC_STATE( mat[R200_MTX_TEX4], tcl_tex, MAT_STATE_SIZE, "MAT/texmat4", 4 );
798 ALLOC_STATE( mat[R200_MTX_TEX5], tcl_tex, MAT_STATE_SIZE, "MAT/texmat5", 5 );
799 ALLOC_STATE( ucp[0], tcl_ucp, UCP_STATE_SIZE, "UCP/userclip-0", 0 );
800 ALLOC_STATE( ucp[1], tcl_ucp, UCP_STATE_SIZE, "UCP/userclip-1", 1 );
801 ALLOC_STATE( ucp[2], tcl_ucp, UCP_STATE_SIZE, "UCP/userclip-2", 2 );
802 ALLOC_STATE( ucp[3], tcl_ucp, UCP_STATE_SIZE, "UCP/userclip-3", 3 );
803 ALLOC_STATE( ucp[4], tcl_ucp, UCP_STATE_SIZE, "UCP/userclip-4", 4 );
804 ALLOC_STATE( ucp[5], tcl_ucp, UCP_STATE_SIZE, "UCP/userclip-5", 5 );
805 ALLOC_STATE( lit[0], tcl_light, LIT_STATE_SIZE, "LIT/light-0", 0 );
806 ALLOC_STATE( lit[1], tcl_light, LIT_STATE_SIZE, "LIT/light-1", 1 );
807 ALLOC_STATE( lit[2], tcl_light, LIT_STATE_SIZE, "LIT/light-2", 2 );
808 ALLOC_STATE( lit[3], tcl_light, LIT_STATE_SIZE, "LIT/light-3", 3 );
809 ALLOC_STATE( lit[4], tcl_light, LIT_STATE_SIZE, "LIT/light-4", 4 );
810 ALLOC_STATE( lit[5], tcl_light, LIT_STATE_SIZE, "LIT/light-5", 5 );
811 ALLOC_STATE( lit[6], tcl_light, LIT_STATE_SIZE, "LIT/light-6", 6 );
812 ALLOC_STATE( lit[7], tcl_light, LIT_STATE_SIZE, "LIT/light-7", 7 );
813 ALLOC_STATE( pix[0], pix_zero, PIX_STATE_SIZE, "PIX/pixstage-0", 0 );
814 ALLOC_STATE( pix[1], texenv, PIX_STATE_SIZE, "PIX/pixstage-1", 1 );
815 ALLOC_STATE( pix[2], texenv, PIX_STATE_SIZE, "PIX/pixstage-2", 2 );
816 ALLOC_STATE( pix[3], texenv, PIX_STATE_SIZE, "PIX/pixstage-3", 3 );
817 ALLOC_STATE( pix[4], texenv, PIX_STATE_SIZE, "PIX/pixstage-4", 4 );
818 ALLOC_STATE( pix[5], texenv, PIX_STATE_SIZE, "PIX/pixstage-5", 5 );
819 if (rmesa->radeon.radeonScreen->drmSupportsTriPerf) {
820 ALLOC_STATE( prf, always, PRF_STATE_SIZE, "PRF/performance-tri", 0 );
821 }
822 else {
823 ALLOC_STATE( prf, never, PRF_STATE_SIZE, "PRF/performance-tri", 0 );
824 }
825 if (rmesa->radeon.radeonScreen->drmSupportsPointSprites) {
826 ALLOC_STATE( spr, always, SPR_STATE_SIZE, "SPR/pointsprite", 0 );
827 ALLOC_STATE( ptp, tcl, PTP_STATE_SIZE, "PTP/pointparams", 0 );
828 }
829 else {
830 ALLOC_STATE (spr, never, SPR_STATE_SIZE, "SPR/pointsprite", 0 );
831 ALLOC_STATE (ptp, never, PTP_STATE_SIZE, "PTP/pointparams", 0 );
832 }
833
834 r200SetUpAtomList( rmesa );
835
836 /* Fill in the packet headers:
837 */
838 rmesa->hw.ctx.cmd[CTX_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_MISC);
839 rmesa->hw.ctx.cmd[CTX_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_PP_CNTL);
840 rmesa->hw.ctx.cmd[CTX_CMD_2] = cmdpkt(rmesa, RADEON_EMIT_RB3D_COLORPITCH);
841 if (rmesa->radeon.radeonScreen->drmSupportsBlendColor)
842 rmesa->hw.ctx.cmd[CTX_CMD_3] = cmdpkt(rmesa, R200_EMIT_RB3D_BLENDCOLOR);
843 rmesa->hw.lin.cmd[LIN_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_RE_LINE_PATTERN);
844 rmesa->hw.lin.cmd[LIN_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_SE_LINE_WIDTH);
845 rmesa->hw.msk.cmd[MSK_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_RB3D_STENCILREFMASK);
846 rmesa->hw.vpt.cmd[VPT_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_SE_VPORT_XSCALE);
847 rmesa->hw.set.cmd[SET_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_SE_CNTL);
848 rmesa->hw.msc.cmd[MSC_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_RE_MISC);
849 rmesa->hw.cst.cmd[CST_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_CNTL_X);
850 rmesa->hw.cst.cmd[CST_CMD_1] = cmdpkt(rmesa, R200_EMIT_RB3D_DEPTHXY_OFFSET);
851 rmesa->hw.cst.cmd[CST_CMD_2] = cmdpkt(rmesa, R200_EMIT_RE_AUX_SCISSOR_CNTL);
852 rmesa->hw.cst.cmd[CST_CMD_3] = cmdpkt(rmesa, R200_EMIT_RE_SCISSOR_TL_0);
853 rmesa->hw.cst.cmd[CST_CMD_4] = cmdpkt(rmesa, R200_EMIT_SE_VAP_CNTL_STATUS);
854 rmesa->hw.cst.cmd[CST_CMD_5] = cmdpkt(rmesa, R200_EMIT_RE_POINTSIZE);
855 rmesa->hw.cst.cmd[CST_CMD_6] = cmdpkt(rmesa, R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0);
856 rmesa->hw.tam.cmd[TAM_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TAM_DEBUG3);
857 rmesa->hw.tf.cmd[TF_CMD_0] = cmdpkt(rmesa, R200_EMIT_TFACTOR_0);
858 if (rmesa->radeon.radeonScreen->drmSupportsFragShader) {
859 rmesa->hw.atf.cmd[ATF_CMD_0] = cmdpkt(rmesa, R200_EMIT_ATF_TFACTOR);
860 rmesa->hw.tex[0].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCTLALL_0);
861 rmesa->hw.tex[0].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_0);
862 rmesa->hw.tex[1].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCTLALL_1);
863 rmesa->hw.tex[1].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_1);
864 rmesa->hw.tex[2].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCTLALL_2);
865 rmesa->hw.tex[2].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_2);
866 rmesa->hw.tex[3].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCTLALL_3);
867 rmesa->hw.tex[3].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_3);
868 rmesa->hw.tex[4].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCTLALL_4);
869 rmesa->hw.tex[4].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_4);
870 rmesa->hw.tex[5].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCTLALL_5);
871 rmesa->hw.tex[5].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_5);
872 } else {
873 rmesa->hw.tex[0].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXFILTER_0);
874 rmesa->hw.tex[0].cmd[TEX_CMD_1_OLDDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_0);
875 rmesa->hw.tex[1].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXFILTER_1);
876 rmesa->hw.tex[1].cmd[TEX_CMD_1_OLDDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_1);
877 rmesa->hw.tex[2].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXFILTER_2);
878 rmesa->hw.tex[2].cmd[TEX_CMD_1_OLDDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_2);
879 rmesa->hw.tex[3].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXFILTER_3);
880 rmesa->hw.tex[3].cmd[TEX_CMD_1_OLDDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_3);
881 rmesa->hw.tex[4].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXFILTER_4);
882 rmesa->hw.tex[4].cmd[TEX_CMD_1_OLDDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_4);
883 rmesa->hw.tex[5].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXFILTER_5);
884 rmesa->hw.tex[5].cmd[TEX_CMD_1_OLDDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_5);
885 }
886 rmesa->hw.afs[0].cmd[AFS_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_AFS_0);
887 rmesa->hw.afs[1].cmd[AFS_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_AFS_1);
888 rmesa->hw.pvs.cmd[PVS_CMD_0] = cmdpkt(rmesa, R200_EMIT_VAP_PVS_CNTL);
889 rmesa->hw.cube[0].cmd[CUBE_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_FACES_0);
890 rmesa->hw.cube[0].cmd[CUBE_CMD_1] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_OFFSETS_0);
891 rmesa->hw.cube[1].cmd[CUBE_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_FACES_1);
892 rmesa->hw.cube[1].cmd[CUBE_CMD_1] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_OFFSETS_1);
893 rmesa->hw.cube[2].cmd[CUBE_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_FACES_2);
894 rmesa->hw.cube[2].cmd[CUBE_CMD_1] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_OFFSETS_2);
895 rmesa->hw.cube[3].cmd[CUBE_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_FACES_3);
896 rmesa->hw.cube[3].cmd[CUBE_CMD_1] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_OFFSETS_3);
897 rmesa->hw.cube[4].cmd[CUBE_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_FACES_4);
898 rmesa->hw.cube[4].cmd[CUBE_CMD_1] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_OFFSETS_4);
899 rmesa->hw.cube[5].cmd[CUBE_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_FACES_5);
900 rmesa->hw.cube[5].cmd[CUBE_CMD_1] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_OFFSETS_5);
901 rmesa->hw.pix[0].cmd[PIX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCBLEND_0);
902 rmesa->hw.pix[1].cmd[PIX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCBLEND_1);
903 rmesa->hw.pix[2].cmd[PIX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCBLEND_2);
904 rmesa->hw.pix[3].cmd[PIX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCBLEND_3);
905 rmesa->hw.pix[4].cmd[PIX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCBLEND_4);
906 rmesa->hw.pix[5].cmd[PIX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCBLEND_5);
907 rmesa->hw.zbs.cmd[ZBS_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_SE_ZBIAS_FACTOR);
908 rmesa->hw.tcl.cmd[TCL_CMD_0] = cmdpkt(rmesa, R200_EMIT_TCL_LIGHT_MODEL_CTL_0);
909 rmesa->hw.tcl.cmd[TCL_CMD_1] = cmdpkt(rmesa, R200_EMIT_TCL_UCP_VERT_BLEND_CTL);
910 rmesa->hw.tcg.cmd[TCG_CMD_0] = cmdpkt(rmesa, R200_EMIT_TEX_PROC_CTL_2);
911 rmesa->hw.msl.cmd[MSL_CMD_0] = cmdpkt(rmesa, R200_EMIT_MATRIX_SELECT_0);
912 rmesa->hw.vap.cmd[VAP_CMD_0] = cmdpkt(rmesa, R200_EMIT_VAP_CTL);
913 rmesa->hw.vtx.cmd[VTX_CMD_0] = cmdpkt(rmesa, R200_EMIT_VTX_FMT_0);
914 rmesa->hw.vtx.cmd[VTX_CMD_1] = cmdpkt(rmesa, R200_EMIT_OUTPUT_VTX_COMP_SEL);
915 rmesa->hw.vtx.cmd[VTX_CMD_2] = cmdpkt(rmesa, R200_EMIT_SE_VTX_STATE_CNTL);
916 rmesa->hw.vte.cmd[VTE_CMD_0] = cmdpkt(rmesa, R200_EMIT_VTE_CNTL);
917 rmesa->hw.prf.cmd[PRF_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TRI_PERF_CNTL);
918 rmesa->hw.spr.cmd[SPR_CMD_0] = cmdpkt(rmesa, R200_EMIT_TCL_POINT_SPRITE_CNTL);
919 if (rmesa->radeon.radeonScreen->kernel_mm) {
920 rmesa->hw.mtl[0].emit = mtl_emit;
921 rmesa->hw.mtl[1].emit = mtl_emit;
922
923 rmesa->hw.vpi[0].emit = veclinear_emit;
924 rmesa->hw.vpi[1].emit = veclinear_emit;
925 rmesa->hw.vpp[0].emit = veclinear_emit;
926 rmesa->hw.vpp[1].emit = veclinear_emit;
927
928 rmesa->hw.grd.emit = scl_emit;
929 rmesa->hw.fog.emit = vec_emit;
930 rmesa->hw.glt.emit = vec_emit;
931 rmesa->hw.eye.emit = vec_emit;
932
933 for (i = R200_MTX_MV; i <= R200_MTX_TEX5; i++)
934 rmesa->hw.mat[i].emit = vec_emit;
935
936 for (i = 0; i < 8; i++)
937 rmesa->hw.lit[i].emit = lit_emit;
938
939 for (i = 0; i < 6; i++)
940 rmesa->hw.ucp[i].emit = vec_emit;
941
942 rmesa->hw.ptp.emit = ptp_emit;
943 }
944
945
946
947 rmesa->hw.mtl[0].cmd[MTL_CMD_0] =
948 cmdvec( R200_VS_MAT_0_EMISS, 1, 16 );
949 rmesa->hw.mtl[0].cmd[MTL_CMD_1] =
950 cmdscl2( R200_SS_MAT_0_SHININESS, 1, 1 );
951 rmesa->hw.mtl[1].cmd[MTL_CMD_0] =
952 cmdvec( R200_VS_MAT_1_EMISS, 1, 16 );
953 rmesa->hw.mtl[1].cmd[MTL_CMD_1] =
954 cmdscl2( R200_SS_MAT_1_SHININESS, 1, 1 );
955
956 rmesa->hw.vpi[0].cmd[VPI_CMD_0] =
957 cmdveclinear( R200_PVS_PROG0, 64 );
958 rmesa->hw.vpi[1].cmd[VPI_CMD_0] =
959 cmdveclinear( R200_PVS_PROG1, 64 );
960 rmesa->hw.vpp[0].cmd[VPP_CMD_0] =
961 cmdveclinear( R200_PVS_PARAM0, 96 );
962 rmesa->hw.vpp[1].cmd[VPP_CMD_0] =
963 cmdveclinear( R200_PVS_PARAM1, 96 );
964
965 rmesa->hw.grd.cmd[GRD_CMD_0] =
966 cmdscl( R200_SS_VERT_GUARD_CLIP_ADJ_ADDR, 1, 4 );
967 rmesa->hw.fog.cmd[FOG_CMD_0] =
968 cmdvec( R200_VS_FOG_PARAM_ADDR, 1, 4 );
969 rmesa->hw.glt.cmd[GLT_CMD_0] =
970 cmdvec( R200_VS_GLOBAL_AMBIENT_ADDR, 1, 4 );
971 rmesa->hw.eye.cmd[EYE_CMD_0] =
972 cmdvec( R200_VS_EYE_VECTOR_ADDR, 1, 4 );
973
974 rmesa->hw.mat[R200_MTX_MV].cmd[MAT_CMD_0] =
975 cmdvec( R200_VS_MATRIX_0_MV, 1, 16);
976 rmesa->hw.mat[R200_MTX_IMV].cmd[MAT_CMD_0] =
977 cmdvec( R200_VS_MATRIX_1_INV_MV, 1, 16);
978 rmesa->hw.mat[R200_MTX_MVP].cmd[MAT_CMD_0] =
979 cmdvec( R200_VS_MATRIX_2_MVP, 1, 16);
980 rmesa->hw.mat[R200_MTX_TEX0].cmd[MAT_CMD_0] =
981 cmdvec( R200_VS_MATRIX_3_TEX0, 1, 16);
982 rmesa->hw.mat[R200_MTX_TEX1].cmd[MAT_CMD_0] =
983 cmdvec( R200_VS_MATRIX_4_TEX1, 1, 16);
984 rmesa->hw.mat[R200_MTX_TEX2].cmd[MAT_CMD_0] =
985 cmdvec( R200_VS_MATRIX_5_TEX2, 1, 16);
986 rmesa->hw.mat[R200_MTX_TEX3].cmd[MAT_CMD_0] =
987 cmdvec( R200_VS_MATRIX_6_TEX3, 1, 16);
988 rmesa->hw.mat[R200_MTX_TEX4].cmd[MAT_CMD_0] =
989 cmdvec( R200_VS_MATRIX_7_TEX4, 1, 16);
990 rmesa->hw.mat[R200_MTX_TEX5].cmd[MAT_CMD_0] =
991 cmdvec( R200_VS_MATRIX_8_TEX5, 1, 16);
992
993 for (i = 0 ; i < 8; i++) {
994 rmesa->hw.lit[i].cmd[LIT_CMD_0] =
995 cmdvec( R200_VS_LIGHT_AMBIENT_ADDR + i, 8, 24 );
996 rmesa->hw.lit[i].cmd[LIT_CMD_1] =
997 cmdscl( R200_SS_LIGHT_DCD_ADDR + i, 8, 7 );
998 }
999
1000 for (i = 0 ; i < 6; i++) {
1001 rmesa->hw.ucp[i].cmd[UCP_CMD_0] =
1002 cmdvec( R200_VS_UCP_ADDR + i, 1, 4 );
1003 }
1004
1005 rmesa->hw.ptp.cmd[PTP_CMD_0] =
1006 cmdvec( R200_VS_PNT_SPRITE_VPORT_SCALE, 1, 4 );
1007 rmesa->hw.ptp.cmd[PTP_CMD_1] =
1008 cmdvec( R200_VS_PNT_SPRITE_ATT_CONST, 1, 12 );
1009
1010 /* Initial Harware state:
1011 */
1012 rmesa->hw.ctx.cmd[CTX_PP_MISC] = (R200_ALPHA_TEST_PASS
1013 /* | R200_RIGHT_HAND_CUBE_OGL*/);
1014
1015 rmesa->hw.ctx.cmd[CTX_PP_FOG_COLOR] = (R200_FOG_VERTEX |
1016 R200_FOG_USE_SPEC_ALPHA);
1017
1018 rmesa->hw.ctx.cmd[CTX_RE_SOLID_COLOR] = 0x00000000;
1019
1020 rmesa->hw.ctx.cmd[CTX_RB3D_BLENDCNTL] = (R200_COMB_FCN_ADD_CLAMP |
1021 (R200_BLEND_GL_ONE << R200_SRC_BLEND_SHIFT) |
1022 (R200_BLEND_GL_ZERO << R200_DST_BLEND_SHIFT));
1023
1024 if (rmesa->radeon.radeonScreen->drmSupportsBlendColor) {
1025 rmesa->hw.ctx.cmd[CTX_RB3D_BLENDCOLOR] = 0x00000000;
1026 rmesa->hw.ctx.cmd[CTX_RB3D_ABLENDCNTL] = (R200_COMB_FCN_ADD_CLAMP |
1027 (R200_BLEND_GL_ONE << R200_SRC_BLEND_SHIFT) |
1028 (R200_BLEND_GL_ZERO << R200_DST_BLEND_SHIFT));
1029 rmesa->hw.ctx.cmd[CTX_RB3D_CBLENDCNTL] = (R200_COMB_FCN_ADD_CLAMP |
1030 (R200_BLEND_GL_ONE << R200_SRC_BLEND_SHIFT) |
1031 (R200_BLEND_GL_ZERO << R200_DST_BLEND_SHIFT));
1032 }
1033
1034 rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHOFFSET] =
1035 rmesa->radeon.radeonScreen->depthOffset + rmesa->radeon.radeonScreen->fbLocation;
1036
1037 rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHPITCH] =
1038 ((rmesa->radeon.radeonScreen->depthPitch &
1039 R200_DEPTHPITCH_MASK) |
1040 R200_DEPTH_ENDIAN_NO_SWAP);
1041
1042 if (rmesa->using_hyperz)
1043 rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHPITCH] |= R200_DEPTH_HYPERZ;
1044
1045 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] = (R200_Z_TEST_LESS |
1046 R200_STENCIL_TEST_ALWAYS |
1047 R200_STENCIL_FAIL_KEEP |
1048 R200_STENCIL_ZPASS_KEEP |
1049 R200_STENCIL_ZFAIL_KEEP |
1050 R200_Z_WRITE_ENABLE);
1051
1052 if (rmesa->using_hyperz) {
1053 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= R200_Z_COMPRESSION_ENABLE |
1054 R200_Z_DECOMPRESSION_ENABLE;
1055 /* if (rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_R200)
1056 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_HIERARCHY_ENABLE;*/
1057 }
1058
1059 rmesa->hw.ctx.cmd[CTX_PP_CNTL] = (R200_ANTI_ALIAS_NONE
1060 | R200_TEX_BLEND_0_ENABLE);
1061
1062 switch ( driQueryOptioni( &rmesa->radeon.optionCache, "dither_mode" ) ) {
1063 case DRI_CONF_DITHER_XERRORDIFFRESET:
1064 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= R200_DITHER_INIT;
1065 break;
1066 case DRI_CONF_DITHER_ORDERED:
1067 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= R200_SCALE_DITHER_ENABLE;
1068 break;
1069 }
1070 if ( driQueryOptioni( &rmesa->radeon.optionCache, "round_mode" ) ==
1071 DRI_CONF_ROUND_ROUND )
1072 rmesa->radeon.state.color.roundEnable = R200_ROUND_ENABLE;
1073 else
1074 rmesa->radeon.state.color.roundEnable = 0;
1075 if ( driQueryOptioni (&rmesa->radeon.optionCache, "color_reduction" ) ==
1076 DRI_CONF_COLOR_REDUCTION_DITHER )
1077 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= R200_DITHER_ENABLE;
1078 else
1079 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= rmesa->radeon.state.color.roundEnable;
1080
1081 rmesa->hw.prf.cmd[PRF_PP_TRI_PERF] = R200_TRI_CUTOFF_MASK - R200_TRI_CUTOFF_MASK *
1082 driQueryOptionf (&rmesa->radeon.optionCache,"texture_blend_quality");
1083 rmesa->hw.prf.cmd[PRF_PP_PERF_CNTL] = 0;
1084
1085 rmesa->hw.set.cmd[SET_SE_CNTL] = (R200_FFACE_CULL_CCW |
1086 R200_BFACE_SOLID |
1087 R200_FFACE_SOLID |
1088 R200_FLAT_SHADE_VTX_LAST |
1089 R200_DIFFUSE_SHADE_GOURAUD |
1090 R200_ALPHA_SHADE_GOURAUD |
1091 R200_SPECULAR_SHADE_GOURAUD |
1092 R200_FOG_SHADE_GOURAUD |
1093 R200_DISC_FOG_SHADE_GOURAUD |
1094 R200_VTX_PIX_CENTER_OGL |
1095 R200_ROUND_MODE_TRUNC |
1096 R200_ROUND_PREC_8TH_PIX);
1097
1098 rmesa->hw.set.cmd[SET_RE_CNTL] = (R200_PERSPECTIVE_ENABLE |
1099 R200_SCISSOR_ENABLE);
1100
1101 rmesa->hw.lin.cmd[LIN_RE_LINE_PATTERN] = ((1 << 16) | 0xffff);
1102
1103 rmesa->hw.lin.cmd[LIN_RE_LINE_STATE] =
1104 ((0 << R200_LINE_CURRENT_PTR_SHIFT) |
1105 (1 << R200_LINE_CURRENT_COUNT_SHIFT));
1106
1107 rmesa->hw.lin.cmd[LIN_SE_LINE_WIDTH] = (1 << 4);
1108
1109 rmesa->hw.msk.cmd[MSK_RB3D_STENCILREFMASK] =
1110 ((0x00 << R200_STENCIL_REF_SHIFT) |
1111 (0xff << R200_STENCIL_MASK_SHIFT) |
1112 (0xff << R200_STENCIL_WRITEMASK_SHIFT));
1113
1114 rmesa->hw.msk.cmd[MSK_RB3D_ROPCNTL] = R200_ROP_COPY;
1115 rmesa->hw.msk.cmd[MSK_RB3D_PLANEMASK] = 0xffffffff;
1116
1117 rmesa->hw.tam.cmd[TAM_DEBUG3] = 0;
1118
1119 rmesa->hw.msc.cmd[MSC_RE_MISC] =
1120 ((0 << R200_STIPPLE_X_OFFSET_SHIFT) |
1121 (0 << R200_STIPPLE_Y_OFFSET_SHIFT) |
1122 R200_STIPPLE_BIG_BIT_ORDER);
1123
1124
1125 rmesa->hw.cst.cmd[CST_PP_CNTL_X] = 0;
1126 rmesa->hw.cst.cmd[CST_RB3D_DEPTHXY_OFFSET] = 0;
1127 rmesa->hw.cst.cmd[CST_RE_AUX_SCISSOR_CNTL] = 0x0;
1128 rmesa->hw.cst.cmd[CST_RE_SCISSOR_TL_0] = 0;
1129 rmesa->hw.cst.cmd[CST_RE_SCISSOR_BR_0] = 0;
1130 rmesa->hw.cst.cmd[CST_SE_VAP_CNTL_STATUS] =
1131 #ifdef MESA_BIG_ENDIAN
1132 R200_VC_32BIT_SWAP;
1133 #else
1134 R200_VC_NO_SWAP;
1135 #endif
1136
1137 if (!(rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL)) {
1138 /* Bypass TCL */
1139 rmesa->hw.cst.cmd[CST_SE_VAP_CNTL_STATUS] |= (1<<8);
1140 }
1141
1142 rmesa->hw.cst.cmd[CST_RE_POINTSIZE] =
1143 (((GLuint)(ctx->Const.MaxPointSize * 16.0)) << R200_MAXPOINTSIZE_SHIFT) | 0x10;
1144 rmesa->hw.cst.cmd[CST_SE_TCL_INPUT_VTX_0] =
1145 (0x0 << R200_VERTEX_POSITION_ADDR__SHIFT);
1146 rmesa->hw.cst.cmd[CST_SE_TCL_INPUT_VTX_1] =
1147 (0x02 << R200_VTX_COLOR_0_ADDR__SHIFT) |
1148 (0x03 << R200_VTX_COLOR_1_ADDR__SHIFT);
1149 rmesa->hw.cst.cmd[CST_SE_TCL_INPUT_VTX_2] =
1150 (0x06 << R200_VTX_TEX_0_ADDR__SHIFT) |
1151 (0x07 << R200_VTX_TEX_1_ADDR__SHIFT) |
1152 (0x08 << R200_VTX_TEX_2_ADDR__SHIFT) |
1153 (0x09 << R200_VTX_TEX_3_ADDR__SHIFT);
1154 rmesa->hw.cst.cmd[CST_SE_TCL_INPUT_VTX_3] =
1155 (0x0A << R200_VTX_TEX_4_ADDR__SHIFT) |
1156 (0x0B << R200_VTX_TEX_5_ADDR__SHIFT);
1157
1158
1159 rmesa->hw.vpt.cmd[VPT_SE_VPORT_XSCALE] = 0x00000000;
1160 rmesa->hw.vpt.cmd[VPT_SE_VPORT_XOFFSET] = 0x00000000;
1161 rmesa->hw.vpt.cmd[VPT_SE_VPORT_YSCALE] = 0x00000000;
1162 rmesa->hw.vpt.cmd[VPT_SE_VPORT_YOFFSET] = 0x00000000;
1163 rmesa->hw.vpt.cmd[VPT_SE_VPORT_ZSCALE] = 0x00000000;
1164 rmesa->hw.vpt.cmd[VPT_SE_VPORT_ZOFFSET] = 0x00000000;
1165
1166 for ( i = 0 ; i < ctx->Const.MaxTextureUnits ; i++ ) {
1167 rmesa->hw.tex[i].cmd[TEX_PP_TXFILTER] = R200_BORDER_MODE_OGL;
1168 rmesa->hw.tex[i].cmd[TEX_PP_TXFORMAT] =
1169 ((i << R200_TXFORMAT_ST_ROUTE_SHIFT) | /* <-- note i */
1170 (2 << R200_TXFORMAT_WIDTH_SHIFT) |
1171 (2 << R200_TXFORMAT_HEIGHT_SHIFT));
1172 rmesa->hw.tex[i].cmd[TEX_PP_BORDER_COLOR] = 0;
1173 rmesa->hw.tex[i].cmd[TEX_PP_TXFORMAT_X] =
1174 (/* R200_TEXCOORD_PROJ | */
1175 0x100000); /* Small default bias */
1176 if (rmesa->radeon.radeonScreen->drmSupportsFragShader) {
1177 rmesa->hw.tex[i].cmd[TEX_PP_TXOFFSET_NEWDRM] =
1178 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
1179 rmesa->hw.tex[i].cmd[TEX_PP_CUBIC_FACES] = 0;
1180 rmesa->hw.tex[i].cmd[TEX_PP_TXMULTI_CTL] = 0;
1181 }
1182 else {
1183 rmesa->hw.tex[i].cmd[TEX_PP_TXOFFSET_OLDDRM] =
1184 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
1185 }
1186
1187 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_FACES] = 0;
1188 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F1] =
1189 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
1190 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F2] =
1191 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
1192 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F3] =
1193 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
1194 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F4] =
1195 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
1196 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F5] =
1197 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
1198
1199 rmesa->hw.pix[i].cmd[PIX_PP_TXCBLEND] =
1200 (R200_TXC_ARG_A_ZERO |
1201 R200_TXC_ARG_B_ZERO |
1202 R200_TXC_ARG_C_DIFFUSE_COLOR |
1203 R200_TXC_OP_MADD);
1204
1205 rmesa->hw.pix[i].cmd[PIX_PP_TXCBLEND2] =
1206 ((i << R200_TXC_TFACTOR_SEL_SHIFT) |
1207 R200_TXC_SCALE_1X |
1208 R200_TXC_CLAMP_0_1 |
1209 R200_TXC_OUTPUT_REG_R0);
1210
1211 rmesa->hw.pix[i].cmd[PIX_PP_TXABLEND] =
1212 (R200_TXA_ARG_A_ZERO |
1213 R200_TXA_ARG_B_ZERO |
1214 R200_TXA_ARG_C_DIFFUSE_ALPHA |
1215 R200_TXA_OP_MADD);
1216
1217 rmesa->hw.pix[i].cmd[PIX_PP_TXABLEND2] =
1218 ((i << R200_TXA_TFACTOR_SEL_SHIFT) |
1219 R200_TXA_SCALE_1X |
1220 R200_TXA_CLAMP_0_1 |
1221 R200_TXA_OUTPUT_REG_R0);
1222 }
1223
1224 rmesa->hw.tf.cmd[TF_TFACTOR_0] = 0;
1225 rmesa->hw.tf.cmd[TF_TFACTOR_1] = 0;
1226 rmesa->hw.tf.cmd[TF_TFACTOR_2] = 0;
1227 rmesa->hw.tf.cmd[TF_TFACTOR_3] = 0;
1228 rmesa->hw.tf.cmd[TF_TFACTOR_4] = 0;
1229 rmesa->hw.tf.cmd[TF_TFACTOR_5] = 0;
1230
1231 rmesa->hw.vap.cmd[VAP_SE_VAP_CNTL] =
1232 (R200_VAP_TCL_ENABLE |
1233 (0x9 << R200_VAP_VF_MAX_VTX_NUM__SHIFT));
1234
1235 rmesa->hw.vte.cmd[VTE_SE_VTE_CNTL] =
1236 (R200_VPORT_X_SCALE_ENA |
1237 R200_VPORT_Y_SCALE_ENA |
1238 R200_VPORT_Z_SCALE_ENA |
1239 R200_VPORT_X_OFFSET_ENA |
1240 R200_VPORT_Y_OFFSET_ENA |
1241 R200_VPORT_Z_OFFSET_ENA |
1242 /* FIXME: Turn on for tex rect only */
1243 R200_VTX_ST_DENORMALIZED |
1244 R200_VTX_W0_FMT);
1245
1246
1247 rmesa->hw.vtx.cmd[VTX_VTXFMT_0] = 0;
1248 rmesa->hw.vtx.cmd[VTX_VTXFMT_1] = 0;
1249 rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_VTXFMT_0] =
1250 ((R200_VTX_Z0 | R200_VTX_W0 |
1251 (R200_VTX_FP_RGBA << R200_VTX_COLOR_0_SHIFT)));
1252 rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_VTXFMT_1] = 0;
1253 rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_COMPSEL] = (R200_OUTPUT_XYZW);
1254 rmesa->hw.vtx.cmd[VTX_STATE_CNTL] = R200_VSC_UPDATE_USER_COLOR_0_ENABLE;
1255
1256
1257 /* Matrix selection */
1258 rmesa->hw.msl.cmd[MSL_MATRIX_SELECT_0] =
1259 (R200_MTX_MV << R200_MODELVIEW_0_SHIFT);
1260
1261 rmesa->hw.msl.cmd[MSL_MATRIX_SELECT_1] =
1262 (R200_MTX_IMV << R200_IT_MODELVIEW_0_SHIFT);
1263
1264 rmesa->hw.msl.cmd[MSL_MATRIX_SELECT_2] =
1265 (R200_MTX_MVP << R200_MODELPROJECT_0_SHIFT);
1266
1267 rmesa->hw.msl.cmd[MSL_MATRIX_SELECT_3] =
1268 ((R200_MTX_TEX0 << R200_TEXMAT_0_SHIFT) |
1269 (R200_MTX_TEX1 << R200_TEXMAT_1_SHIFT) |
1270 (R200_MTX_TEX2 << R200_TEXMAT_2_SHIFT) |
1271 (R200_MTX_TEX3 << R200_TEXMAT_3_SHIFT));
1272
1273 rmesa->hw.msl.cmd[MSL_MATRIX_SELECT_4] =
1274 ((R200_MTX_TEX4 << R200_TEXMAT_4_SHIFT) |
1275 (R200_MTX_TEX5 << R200_TEXMAT_5_SHIFT));
1276
1277
1278 /* General TCL state */
1279 rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL_0] =
1280 (R200_SPECULAR_LIGHTS |
1281 R200_DIFFUSE_SPECULAR_COMBINE |
1282 R200_LOCAL_LIGHT_VEC_GL |
1283 R200_LM0_SOURCE_MATERIAL_0 << R200_FRONT_SHININESS_SOURCE_SHIFT |
1284 R200_LM0_SOURCE_MATERIAL_1 << R200_BACK_SHININESS_SOURCE_SHIFT);
1285
1286 rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL_1] =
1287 ((R200_LM1_SOURCE_MATERIAL_0 << R200_FRONT_EMISSIVE_SOURCE_SHIFT) |
1288 (R200_LM1_SOURCE_MATERIAL_0 << R200_FRONT_AMBIENT_SOURCE_SHIFT) |
1289 (R200_LM1_SOURCE_MATERIAL_0 << R200_FRONT_DIFFUSE_SOURCE_SHIFT) |
1290 (R200_LM1_SOURCE_MATERIAL_0 << R200_FRONT_SPECULAR_SOURCE_SHIFT) |
1291 (R200_LM1_SOURCE_MATERIAL_1 << R200_BACK_EMISSIVE_SOURCE_SHIFT) |
1292 (R200_LM1_SOURCE_MATERIAL_1 << R200_BACK_AMBIENT_SOURCE_SHIFT) |
1293 (R200_LM1_SOURCE_MATERIAL_1 << R200_BACK_DIFFUSE_SOURCE_SHIFT) |
1294 (R200_LM1_SOURCE_MATERIAL_1 << R200_BACK_SPECULAR_SOURCE_SHIFT));
1295
1296 rmesa->hw.tcl.cmd[TCL_PER_LIGHT_CTL_0] = 0; /* filled in via callbacks */
1297 rmesa->hw.tcl.cmd[TCL_PER_LIGHT_CTL_1] = 0;
1298 rmesa->hw.tcl.cmd[TCL_PER_LIGHT_CTL_2] = 0;
1299 rmesa->hw.tcl.cmd[TCL_PER_LIGHT_CTL_3] = 0;
1300
1301 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] =
1302 (R200_UCP_IN_CLIP_SPACE |
1303 R200_CULL_FRONT_IS_CCW);
1304
1305 /* Texgen/Texmat state */
1306 rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_2] = 0x00ffffff;
1307 rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_3] =
1308 ((0 << R200_TEXGEN_0_INPUT_TEX_SHIFT) |
1309 (1 << R200_TEXGEN_1_INPUT_TEX_SHIFT) |
1310 (2 << R200_TEXGEN_2_INPUT_TEX_SHIFT) |
1311 (3 << R200_TEXGEN_3_INPUT_TEX_SHIFT) |
1312 (4 << R200_TEXGEN_4_INPUT_TEX_SHIFT) |
1313 (5 << R200_TEXGEN_5_INPUT_TEX_SHIFT));
1314 rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_0] = 0;
1315 rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_1] =
1316 ((0 << R200_TEXGEN_0_INPUT_SHIFT) |
1317 (1 << R200_TEXGEN_1_INPUT_SHIFT) |
1318 (2 << R200_TEXGEN_2_INPUT_SHIFT) |
1319 (3 << R200_TEXGEN_3_INPUT_SHIFT) |
1320 (4 << R200_TEXGEN_4_INPUT_SHIFT) |
1321 (5 << R200_TEXGEN_5_INPUT_SHIFT));
1322 rmesa->hw.tcg.cmd[TCG_TEX_CYL_WRAP_CTL] = 0;
1323
1324
1325 for (i = 0 ; i < 8; i++) {
1326 struct gl_light *l = &ctx->Light.Light[i];
1327 GLenum p = GL_LIGHT0 + i;
1328 *(float *)&(rmesa->hw.lit[i].cmd[LIT_RANGE_CUTOFF]) = FLT_MAX;
1329
1330 ctx->Driver.Lightfv( ctx, p, GL_AMBIENT, l->Ambient );
1331 ctx->Driver.Lightfv( ctx, p, GL_DIFFUSE, l->Diffuse );
1332 ctx->Driver.Lightfv( ctx, p, GL_SPECULAR, l->Specular );
1333 ctx->Driver.Lightfv( ctx, p, GL_POSITION, NULL );
1334 ctx->Driver.Lightfv( ctx, p, GL_SPOT_DIRECTION, NULL );
1335 ctx->Driver.Lightfv( ctx, p, GL_SPOT_EXPONENT, &l->SpotExponent );
1336 ctx->Driver.Lightfv( ctx, p, GL_SPOT_CUTOFF, &l->SpotCutoff );
1337 ctx->Driver.Lightfv( ctx, p, GL_CONSTANT_ATTENUATION,
1338 &l->ConstantAttenuation );
1339 ctx->Driver.Lightfv( ctx, p, GL_LINEAR_ATTENUATION,
1340 &l->LinearAttenuation );
1341 ctx->Driver.Lightfv( ctx, p, GL_QUADRATIC_ATTENUATION,
1342 &l->QuadraticAttenuation );
1343 *(float *)&(rmesa->hw.lit[i].cmd[LIT_ATTEN_XXX]) = 0.0;
1344 }
1345
1346 ctx->Driver.LightModelfv( ctx, GL_LIGHT_MODEL_AMBIENT,
1347 ctx->Light.Model.Ambient );
1348
1349 TNL_CONTEXT(ctx)->Driver.NotifyMaterialChange( ctx );
1350
1351 for (i = 0 ; i < 6; i++) {
1352 ctx->Driver.ClipPlane( ctx, GL_CLIP_PLANE0 + i, NULL );
1353 }
1354
1355 ctx->Driver.Fogfv( ctx, GL_FOG_MODE, NULL );
1356 ctx->Driver.Fogfv( ctx, GL_FOG_DENSITY, &ctx->Fog.Density );
1357 ctx->Driver.Fogfv( ctx, GL_FOG_START, &ctx->Fog.Start );
1358 ctx->Driver.Fogfv( ctx, GL_FOG_END, &ctx->Fog.End );
1359 ctx->Driver.Fogfv( ctx, GL_FOG_COLOR, ctx->Fog.Color );
1360 ctx->Driver.Fogfv( ctx, GL_FOG_COORDINATE_SOURCE_EXT, NULL );
1361
1362 rmesa->hw.grd.cmd[GRD_VERT_GUARD_CLIP_ADJ] = IEEE_ONE;
1363 rmesa->hw.grd.cmd[GRD_VERT_GUARD_DISCARD_ADJ] = IEEE_ONE;
1364 rmesa->hw.grd.cmd[GRD_HORZ_GUARD_CLIP_ADJ] = IEEE_ONE;
1365 rmesa->hw.grd.cmd[GRD_HORZ_GUARD_DISCARD_ADJ] = IEEE_ONE;
1366
1367 rmesa->hw.eye.cmd[EYE_X] = 0;
1368 rmesa->hw.eye.cmd[EYE_Y] = 0;
1369 rmesa->hw.eye.cmd[EYE_Z] = IEEE_ONE;
1370 rmesa->hw.eye.cmd[EYE_RESCALE_FACTOR] = IEEE_ONE;
1371
1372 rmesa->hw.spr.cmd[SPR_POINT_SPRITE_CNTL] =
1373 R200_PS_SE_SEL_STATE | R200_PS_MULT_CONST;
1374
1375 /* ptp_eye is presumably used to calculate the attenuation wrt a different
1376 location? In any case, since point attenuation triggers _needeyecoords,
1377 it is constant. Probably ignored as long as R200_PS_USE_MODEL_EYE_VEC
1378 isn't set */
1379 rmesa->hw.ptp.cmd[PTP_EYE_X] = 0;
1380 rmesa->hw.ptp.cmd[PTP_EYE_Y] = 0;
1381 rmesa->hw.ptp.cmd[PTP_EYE_Z] = IEEE_ONE | 0x80000000; /* -1.0 */
1382 rmesa->hw.ptp.cmd[PTP_EYE_3] = 0;
1383 /* no idea what the ptp_vport_scale values are good for, except the
1384 PTSIZE one - hopefully doesn't matter */
1385 rmesa->hw.ptp.cmd[PTP_VPORT_SCALE_0] = IEEE_ONE;
1386 rmesa->hw.ptp.cmd[PTP_VPORT_SCALE_1] = IEEE_ONE;
1387 rmesa->hw.ptp.cmd[PTP_VPORT_SCALE_PTSIZE] = IEEE_ONE;
1388 rmesa->hw.ptp.cmd[PTP_VPORT_SCALE_3] = IEEE_ONE;
1389 rmesa->hw.ptp.cmd[PTP_ATT_CONST_QUAD] = 0;
1390 rmesa->hw.ptp.cmd[PTP_ATT_CONST_LIN] = 0;
1391 rmesa->hw.ptp.cmd[PTP_ATT_CONST_CON] = IEEE_ONE;
1392 rmesa->hw.ptp.cmd[PTP_ATT_CONST_3] = 0;
1393 rmesa->hw.ptp.cmd[PTP_CLAMP_MIN] = IEEE_ONE;
1394 rmesa->hw.ptp.cmd[PTP_CLAMP_MAX] = 0x44ffe000; /* 2047 */
1395 rmesa->hw.ptp.cmd[PTP_CLAMP_2] = 0;
1396 rmesa->hw.ptp.cmd[PTP_CLAMP_3] = 0;
1397
1398 r200LightingSpaceChange( ctx );
1399
1400 rmesa->radeon.hw.all_dirty = GL_TRUE;
1401
1402 rcommonInitCmdBuf(&rmesa->radeon);
1403 }