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radeon: remove some debugging
[mesa.git] / src / mesa / drivers / dri / r200 / r200_state_init.c
1 /*
2 Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
3
4 The Weather Channel (TM) funded Tungsten Graphics to develop the
5 initial release of the Radeon 8500 driver under the XFree86 license.
6 This notice must be preserved.
7
8 Permission is hereby granted, free of charge, to any person obtaining
9 a copy of this software and associated documentation files (the
10 "Software"), to deal in the Software without restriction, including
11 without limitation the rights to use, copy, modify, merge, publish,
12 distribute, sublicense, and/or sell copies of the Software, and to
13 permit persons to whom the Software is furnished to do so, subject to
14 the following conditions:
15
16 The above copyright notice and this permission notice (including the
17 next paragraph) shall be included in all copies or substantial
18 portions of the Software.
19
20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 */
28
29 /*
30 * Authors:
31 * Keith Whitwell <keith@tungstengraphics.com>
32 */
33
34 #include "main/glheader.h"
35 #include "main/imports.h"
36 #include "main/enums.h"
37 #include "main/colormac.h"
38 #include "main/api_arrayelt.h"
39
40 #include "swrast/swrast.h"
41 #include "vbo/vbo.h"
42 #include "tnl/tnl.h"
43 #include "tnl/t_pipeline.h"
44 #include "swrast_setup/swrast_setup.h"
45
46 #include "radeon_buffer.h"
47 #include "radeon_mipmap_tree.h"
48 #include "radeon_cs.h"
49 #include "common_context.h"
50 #include "common_cmdbuf.h"
51 #include "r200_context.h"
52 #include "r200_ioctl.h"
53 #include "r200_state.h"
54 #include "r200_tcl.h"
55 #include "r200_tex.h"
56 #include "r200_swtcl.h"
57
58 #include "xmlpool.h"
59
60 /* New (1.3) state mechanism. 3 commands (packet, scalar, vector) in
61 * 1.3 cmdbuffers allow all previous state to be updated as well as
62 * the tcl scalar and vector areas.
63 */
64 static struct {
65 int start;
66 int len;
67 const char *name;
68 } packet[RADEON_MAX_STATE_PACKETS] = {
69 {RADEON_PP_MISC, 7, "RADEON_PP_MISC"},
70 {RADEON_PP_CNTL, 3, "RADEON_PP_CNTL"},
71 {RADEON_RB3D_COLORPITCH, 1, "RADEON_RB3D_COLORPITCH"},
72 {RADEON_RE_LINE_PATTERN, 2, "RADEON_RE_LINE_PATTERN"},
73 {RADEON_SE_LINE_WIDTH, 1, "RADEON_SE_LINE_WIDTH"},
74 {RADEON_PP_LUM_MATRIX, 1, "RADEON_PP_LUM_MATRIX"},
75 {RADEON_PP_ROT_MATRIX_0, 2, "RADEON_PP_ROT_MATRIX_0"},
76 {RADEON_RB3D_STENCILREFMASK, 3, "RADEON_RB3D_STENCILREFMASK"},
77 {RADEON_SE_VPORT_XSCALE, 6, "RADEON_SE_VPORT_XSCALE"},
78 {RADEON_SE_CNTL, 2, "RADEON_SE_CNTL"},
79 {RADEON_SE_CNTL_STATUS, 1, "RADEON_SE_CNTL_STATUS"},
80 {RADEON_RE_MISC, 1, "RADEON_RE_MISC"},
81 {RADEON_PP_TXFILTER_0, 6, "RADEON_PP_TXFILTER_0"},
82 {RADEON_PP_BORDER_COLOR_0, 1, "RADEON_PP_BORDER_COLOR_0"},
83 {RADEON_PP_TXFILTER_1, 6, "RADEON_PP_TXFILTER_1"},
84 {RADEON_PP_BORDER_COLOR_1, 1, "RADEON_PP_BORDER_COLOR_1"},
85 {RADEON_PP_TXFILTER_2, 6, "RADEON_PP_TXFILTER_2"},
86 {RADEON_PP_BORDER_COLOR_2, 1, "RADEON_PP_BORDER_COLOR_2"},
87 {RADEON_SE_ZBIAS_FACTOR, 2, "RADEON_SE_ZBIAS_FACTOR"},
88 {RADEON_SE_TCL_OUTPUT_VTX_FMT, 11, "RADEON_SE_TCL_OUTPUT_VTX_FMT"},
89 {RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED, 17,
90 "RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED"},
91 {R200_PP_TXCBLEND_0, 4, "R200_PP_TXCBLEND_0"},
92 {R200_PP_TXCBLEND_1, 4, "R200_PP_TXCBLEND_1"},
93 {R200_PP_TXCBLEND_2, 4, "R200_PP_TXCBLEND_2"},
94 {R200_PP_TXCBLEND_3, 4, "R200_PP_TXCBLEND_3"},
95 {R200_PP_TXCBLEND_4, 4, "R200_PP_TXCBLEND_4"},
96 {R200_PP_TXCBLEND_5, 4, "R200_PP_TXCBLEND_5"},
97 {R200_PP_TXCBLEND_6, 4, "R200_PP_TXCBLEND_6"},
98 {R200_PP_TXCBLEND_7, 4, "R200_PP_TXCBLEND_7"},
99 {R200_SE_TCL_LIGHT_MODEL_CTL_0, 6, "R200_SE_TCL_LIGHT_MODEL_CTL_0"},
100 {R200_PP_TFACTOR_0, 6, "R200_PP_TFACTOR_0"},
101 {R200_SE_VTX_FMT_0, 4, "R200_SE_VTX_FMT_0"},
102 {R200_SE_VAP_CNTL, 1, "R200_SE_VAP_CNTL"},
103 {R200_SE_TCL_MATRIX_SEL_0, 5, "R200_SE_TCL_MATRIX_SEL_0"},
104 {R200_SE_TCL_TEX_PROC_CTL_2, 5, "R200_SE_TCL_TEX_PROC_CTL_2"},
105 {R200_SE_TCL_UCP_VERT_BLEND_CTL, 1, "R200_SE_TCL_UCP_VERT_BLEND_CTL"},
106 {R200_PP_TXFILTER_0, 6, "R200_PP_TXFILTER_0"},
107 {R200_PP_TXFILTER_1, 6, "R200_PP_TXFILTER_1"},
108 {R200_PP_TXFILTER_2, 6, "R200_PP_TXFILTER_2"},
109 {R200_PP_TXFILTER_3, 6, "R200_PP_TXFILTER_3"},
110 {R200_PP_TXFILTER_4, 6, "R200_PP_TXFILTER_4"},
111 {R200_PP_TXFILTER_5, 6, "R200_PP_TXFILTER_5"},
112 {R200_PP_TXOFFSET_0, 1, "R200_PP_TXOFFSET_0"},
113 {R200_PP_TXOFFSET_1, 1, "R200_PP_TXOFFSET_1"},
114 {R200_PP_TXOFFSET_2, 1, "R200_PP_TXOFFSET_2"},
115 {R200_PP_TXOFFSET_3, 1, "R200_PP_TXOFFSET_3"},
116 {R200_PP_TXOFFSET_4, 1, "R200_PP_TXOFFSET_4"},
117 {R200_PP_TXOFFSET_5, 1, "R200_PP_TXOFFSET_5"},
118 {R200_SE_VTE_CNTL, 1, "R200_SE_VTE_CNTL"},
119 {R200_SE_TCL_OUTPUT_VTX_COMP_SEL, 1,
120 "R200_SE_TCL_OUTPUT_VTX_COMP_SEL"},
121 {R200_PP_TAM_DEBUG3, 1, "R200_PP_TAM_DEBUG3"},
122 {R200_PP_CNTL_X, 1, "R200_PP_CNTL_X"},
123 {R200_RB3D_DEPTHXY_OFFSET, 1, "R200_RB3D_DEPTHXY_OFFSET"},
124 {R200_RE_AUX_SCISSOR_CNTL, 1, "R200_RE_AUX_SCISSOR_CNTL"},
125 {R200_RE_SCISSOR_TL_0, 2, "R200_RE_SCISSOR_TL_0"},
126 {R200_RE_SCISSOR_TL_1, 2, "R200_RE_SCISSOR_TL_1"},
127 {R200_RE_SCISSOR_TL_2, 2, "R200_RE_SCISSOR_TL_2"},
128 {R200_SE_VAP_CNTL_STATUS, 1, "R200_SE_VAP_CNTL_STATUS"},
129 {R200_SE_VTX_STATE_CNTL, 1, "R200_SE_VTX_STATE_CNTL"},
130 {R200_RE_POINTSIZE, 1, "R200_RE_POINTSIZE"},
131 {R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0, 4,
132 "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0"},
133 {R200_PP_CUBIC_FACES_0, 1, "R200_PP_CUBIC_FACES_0"}, /* 61 */
134 {R200_PP_CUBIC_OFFSET_F1_0, 5, "R200_PP_CUBIC_OFFSET_F1_0"}, /* 62 */
135 {R200_PP_CUBIC_FACES_1, 1, "R200_PP_CUBIC_FACES_1"},
136 {R200_PP_CUBIC_OFFSET_F1_1, 5, "R200_PP_CUBIC_OFFSET_F1_1"},
137 {R200_PP_CUBIC_FACES_2, 1, "R200_PP_CUBIC_FACES_2"},
138 {R200_PP_CUBIC_OFFSET_F1_2, 5, "R200_PP_CUBIC_OFFSET_F1_2"},
139 {R200_PP_CUBIC_FACES_3, 1, "R200_PP_CUBIC_FACES_3"},
140 {R200_PP_CUBIC_OFFSET_F1_3, 5, "R200_PP_CUBIC_OFFSET_F1_3"},
141 {R200_PP_CUBIC_FACES_4, 1, "R200_PP_CUBIC_FACES_4"},
142 {R200_PP_CUBIC_OFFSET_F1_4, 5, "R200_PP_CUBIC_OFFSET_F1_4"},
143 {R200_PP_CUBIC_FACES_5, 1, "R200_PP_CUBIC_FACES_5"},
144 {R200_PP_CUBIC_OFFSET_F1_5, 5, "R200_PP_CUBIC_OFFSET_F1_5"},
145 {RADEON_PP_TEX_SIZE_0, 2, "RADEON_PP_TEX_SIZE_0"},
146 {RADEON_PP_TEX_SIZE_1, 2, "RADEON_PP_TEX_SIZE_1"},
147 {RADEON_PP_TEX_SIZE_2, 2, "RADEON_PP_TEX_SIZE_2"},
148 {R200_RB3D_BLENDCOLOR, 3, "R200_RB3D_BLENDCOLOR"},
149 {R200_SE_TCL_POINT_SPRITE_CNTL, 1, "R200_SE_TCL_POINT_SPRITE_CNTL"},
150 {RADEON_PP_CUBIC_FACES_0, 1, "RADEON_PP_CUBIC_FACES_0"},
151 {RADEON_PP_CUBIC_OFFSET_T0_0, 5, "RADEON_PP_CUBIC_OFFSET_T0_0"},
152 {RADEON_PP_CUBIC_FACES_1, 1, "RADEON_PP_CUBIC_FACES_1"},
153 {RADEON_PP_CUBIC_OFFSET_T1_0, 5, "RADEON_PP_CUBIC_OFFSET_T1_0"},
154 {RADEON_PP_CUBIC_FACES_2, 1, "RADEON_PP_CUBIC_FACES_2"},
155 {RADEON_PP_CUBIC_OFFSET_T2_0, 5, "RADEON_PP_CUBIC_OFFSET_T2_0"},
156 {R200_PP_TRI_PERF, 2, "R200_PP_TRI_PERF"},
157 {R200_PP_TXCBLEND_8, 32, "R200_PP_AFS_0"}, /* 85 */
158 {R200_PP_TXCBLEND_0, 32, "R200_PP_AFS_1"},
159 {R200_PP_TFACTOR_0, 8, "R200_ATF_TFACTOR"},
160 {R200_PP_TXFILTER_0, 8, "R200_PP_TXCTLALL_0"},
161 {R200_PP_TXFILTER_1, 8, "R200_PP_TXCTLALL_1"},
162 {R200_PP_TXFILTER_2, 8, "R200_PP_TXCTLALL_2"},
163 {R200_PP_TXFILTER_3, 8, "R200_PP_TXCTLALL_3"},
164 {R200_PP_TXFILTER_4, 8, "R200_PP_TXCTLALL_4"},
165 {R200_PP_TXFILTER_5, 8, "R200_PP_TXCTLALL_5"},
166 {R200_VAP_PVS_CNTL_1, 2, "R200_VAP_PVS_CNTL"},
167 };
168
169 /* =============================================================
170 * State initialization
171 */
172
173 void r200PrintDirty( r200ContextPtr rmesa, const char *msg )
174 {
175 struct radeon_state_atom *l;
176
177 fprintf(stderr, msg);
178 fprintf(stderr, ": ");
179
180 foreach(l, &rmesa->hw.atomlist) {
181 if (l->dirty || rmesa->hw.all_dirty)
182 fprintf(stderr, "%s, ", l->name);
183 }
184
185 fprintf(stderr, "\n");
186 }
187
188 static int cmdpkt( int id )
189 {
190 drm_radeon_cmd_header_t h;
191 h.i = 0;
192 h.packet.cmd_type = RADEON_CMD_PACKET;
193 h.packet.packet_id = id;
194 return h.i;
195 }
196
197 static int cmdvec( int offset, int stride, int count )
198 {
199 drm_radeon_cmd_header_t h;
200 h.i = 0;
201 h.vectors.cmd_type = RADEON_CMD_VECTORS;
202 h.vectors.offset = offset;
203 h.vectors.stride = stride;
204 h.vectors.count = count;
205 return h.i;
206 }
207
208 /* warning: the count here is divided by 4 compared to other cmds
209 (so it doesn't exceed the char size)! */
210 static int cmdveclinear( int offset, int count )
211 {
212 drm_radeon_cmd_header_t h;
213 h.i = 0;
214 h.veclinear.cmd_type = RADEON_CMD_VECLINEAR;
215 h.veclinear.addr_lo = offset & 0xff;
216 h.veclinear.addr_hi = (offset & 0xff00) >> 8;
217 h.veclinear.count = count;
218 return h.i;
219 }
220
221 static int cmdscl( int offset, int stride, int count )
222 {
223 drm_radeon_cmd_header_t h;
224 h.i = 0;
225 h.scalars.cmd_type = RADEON_CMD_SCALARS;
226 h.scalars.offset = offset;
227 h.scalars.stride = stride;
228 h.scalars.count = count;
229 return h.i;
230 }
231
232 static int cmdscl2( int offset, int stride, int count )
233 {
234 drm_radeon_cmd_header_t h;
235 h.i = 0;
236 h.scalars.cmd_type = RADEON_CMD_SCALARS2;
237 h.scalars.offset = offset - 0x100;
238 h.scalars.stride = stride;
239 h.scalars.count = count;
240 return h.i;
241 }
242
243 #define CHECK( NM, FLAG ) \
244 static int check_##NM( GLcontext *ctx, struct radeon_state_atom *atom) \
245 { \
246 r200ContextPtr rmesa = R200_CONTEXT(ctx); \
247 (void) rmesa; \
248 return (FLAG) ? atom->cmd_size : 0; \
249 }
250
251 #define TCL_CHECK( NM, FLAG ) \
252 static int check_##NM( GLcontext *ctx, struct radeon_state_atom *atom) \
253 { \
254 r200ContextPtr rmesa = R200_CONTEXT(ctx); \
255 return (!rmesa->radeon.TclFallback && !ctx->VertexProgram._Enabled && (FLAG)) ? atom->cmd_size : 0; \
256 }
257
258 #define TCL_OR_VP_CHECK( NM, FLAG ) \
259 static int check_##NM( GLcontext *ctx, struct radeon_state_atom *atom ) \
260 { \
261 r200ContextPtr rmesa = R200_CONTEXT(ctx); \
262 return (!rmesa->radeon.TclFallback && (FLAG)) ? atom->cmd_size : 0; \
263 }
264
265 #define VP_CHECK( NM, FLAG ) \
266 static int check_##NM( GLcontext *ctx, struct radeon_state_atom *atom ) \
267 { \
268 r200ContextPtr rmesa = R200_CONTEXT(ctx); \
269 (void) atom; \
270 return (!rmesa->radeon.TclFallback && ctx->VertexProgram._Enabled && (FLAG)) ? atom->cmd_size : 0; \
271 }
272
273 CHECK( always, GL_TRUE )
274 CHECK( never, GL_FALSE )
275 CHECK( tex_any, ctx->Texture._EnabledUnits )
276 CHECK( tf, (ctx->Texture._EnabledUnits && !ctx->ATIFragmentShader._Enabled) );
277 CHECK( tex_pair, (rmesa->state.texture.unit[atom->idx].unitneeded | rmesa->state.texture.unit[atom->idx & ~1].unitneeded) )
278 CHECK( tex, rmesa->state.texture.unit[atom->idx].unitneeded )
279 CHECK( pix_zero, !ctx->ATIFragmentShader._Enabled )
280 CHECK( texenv, (rmesa->state.envneeded & (1 << (atom->idx)) && !ctx->ATIFragmentShader._Enabled) )
281 CHECK( afs_pass1, (ctx->ATIFragmentShader._Enabled && (ctx->ATIFragmentShader.Current->NumPasses > 1)) )
282 CHECK( afs, ctx->ATIFragmentShader._Enabled )
283 CHECK( tex_cube, rmesa->state.texture.unit[atom->idx].unitneeded & TEXTURE_CUBE_BIT )
284 TCL_CHECK( tcl_fog, ctx->Fog.Enabled )
285 TCL_CHECK( tcl, GL_TRUE )
286 TCL_CHECK( tcl_tex, rmesa->state.texture.unit[atom->idx].unitneeded )
287 TCL_CHECK( tcl_lighting, ctx->Light.Enabled )
288 TCL_CHECK( tcl_light, ctx->Light.Enabled && ctx->Light.Light[atom->idx].Enabled )
289 TCL_OR_VP_CHECK( tcl_ucp, (ctx->Transform.ClipPlanesEnabled & (1 << (atom->idx))) )
290 TCL_OR_VP_CHECK( tcl_or_vp, GL_TRUE )
291 VP_CHECK( tcl_vp, GL_TRUE )
292 VP_CHECK( tcl_vp_size, ctx->VertexProgram.Current->Base.NumNativeInstructions > 64 )
293 VP_CHECK( tcl_vpp_size, ctx->VertexProgram.Current->Base.NumNativeParameters > 96 )
294
295
296 static void ctx_emit(GLcontext *ctx, struct radeon_state_atom *atom)
297 {
298 r200ContextPtr r200 = R200_CONTEXT(ctx);
299 BATCH_LOCALS(&r200->radeon);
300 struct radeon_renderbuffer *rrb;
301 uint32_t cbpitch;
302 uint32_t zbpitch;
303 uint32_t dwords = atom->cmd_size;
304 GLframebuffer *fb = r200->radeon.dri.drawable->driverPrivate;
305
306 /* output the first 7 bytes of context */
307 BEGIN_BATCH_NO_AUTOSTATE(dwords);
308 OUT_BATCH_TABLE(atom->cmd, 5);
309
310 rrb = r200->radeon.state.depth.rrb;
311 if (!rrb) {
312 OUT_BATCH(atom->cmd[CTX_RB3D_DEPTHOFFSET]);
313 OUT_BATCH(atom->cmd[CTX_RB3D_DEPTHPITCH]);
314 } else {
315 zbpitch = (rrb->pitch / rrb->cpp);
316 OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
317 OUT_BATCH(zbpitch);
318 }
319
320 OUT_BATCH(atom->cmd[CTX_RB3D_ZSTENCILCNTL]);
321 OUT_BATCH(atom->cmd[CTX_CMD_1]);
322 OUT_BATCH(atom->cmd[CTX_PP_CNTL]);
323 OUT_BATCH(atom->cmd[CTX_RB3D_CNTL]);
324
325 rrb = r200->radeon.state.color.rrb;
326 if (r200->radeon.radeonScreen->driScreen->dri2.enabled) {
327 rrb = (struct radeon_renderbuffer *)fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer;
328 }
329 if (!rrb || !rrb->bo) {
330 OUT_BATCH(atom->cmd[CTX_RB3D_COLOROFFSET]);
331 } else {
332 OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
333 }
334
335 OUT_BATCH(atom->cmd[CTX_CMD_2]);
336
337 if (!rrb || !rrb->bo) {
338 OUT_BATCH(atom->cmd[CTX_RB3D_COLORPITCH]);
339 } else {
340 cbpitch = (rrb->pitch / rrb->cpp);
341 if (rrb->cpp == 4)
342 ;
343 else
344 ;
345 if (r200->radeon.sarea->tiling_enabled)
346 cbpitch |= R200_COLOR_TILE_ENABLE;
347 OUT_BATCH(cbpitch);
348 }
349
350 if (atom->cmd_size == CTX_STATE_SIZE_NEWDRM)
351 OUT_BATCH_TABLE((atom->cmd + 14), 4);
352
353 END_BATCH();
354
355 }
356
357 static void tex_emit(GLcontext *ctx, struct radeon_state_atom *atom)
358 {
359 r200ContextPtr r200 = R200_CONTEXT(ctx);
360 BATCH_LOCALS(&r200->radeon);
361 uint32_t dwords = atom->cmd_size;
362 int i = atom->idx;
363 radeonTexObj *t = r200->state.texture.unit[i].texobj;
364
365 BEGIN_BATCH_NO_AUTOSTATE(dwords);
366 OUT_BATCH_TABLE(atom->cmd, 10);
367 if (t && !t->image_override) {
368 OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, 0,
369 RADEON_GEM_DOMAIN_VRAM, 0, 0);
370 } else if (!t) {
371
372 OUT_BATCH(atom->cmd[10]);
373 }
374
375 END_BATCH();
376 }
377
378 static void cube_emit(GLcontext *ctx, struct radeon_state_atom *atom)
379 {
380 r200ContextPtr r200 = R200_CONTEXT(ctx);
381 BATCH_LOCALS(&r200->radeon);
382 uint32_t dwords = atom->cmd_size;
383 int i = atom->idx;
384 radeonTexObj *t = r200->state.texture.unit[i].texobj;
385 GLuint size;
386
387 BEGIN_BATCH_NO_AUTOSTATE(dwords);
388 OUT_BATCH_TABLE(atom->cmd, 3);
389
390 fprintf(stderr,"total size is %d\n", t->mt->totalsize);
391 if (t && !t->image_override) {
392 size = t->mt->totalsize / 6;
393 OUT_BATCH_RELOC(0, t->mt->bo, size, RADEON_GEM_DOMAIN_VRAM, 0, 0);
394 OUT_BATCH_RELOC(0, t->mt->bo, size * 2, RADEON_GEM_DOMAIN_VRAM, 0, 0);
395 OUT_BATCH_RELOC(0, t->mt->bo, size * 3, RADEON_GEM_DOMAIN_VRAM, 0, 0);
396 OUT_BATCH_RELOC(0, t->mt->bo, size * 4, RADEON_GEM_DOMAIN_VRAM, 0, 0);
397 OUT_BATCH_RELOC(0, t->mt->bo, size * 5, RADEON_GEM_DOMAIN_VRAM, 0, 0);
398 }
399 END_BATCH();
400 }
401
402 /* Initialize the context's hardware state.
403 */
404 void r200InitState( r200ContextPtr rmesa )
405 {
406 GLcontext *ctx = rmesa->radeon.glCtx;
407 GLuint color_fmt, depth_fmt, i;
408 GLint drawPitch, drawOffset;
409
410 switch ( rmesa->radeon.radeonScreen->cpp ) {
411 case 2:
412 color_fmt = R200_COLOR_FORMAT_RGB565;
413 break;
414 case 4:
415 color_fmt = R200_COLOR_FORMAT_ARGB8888;
416 break;
417 default:
418 fprintf( stderr, "Error: Unsupported pixel depth... exiting\n" );
419 exit( -1 );
420 }
421
422 rmesa->radeon.state.color.clear = 0x00000000;
423
424 switch ( ctx->Visual.depthBits ) {
425 case 16:
426 rmesa->radeon.state.depth.clear = 0x0000ffff;
427 rmesa->radeon.state.depth.scale = 1.0 / (GLfloat)0xffff;
428 depth_fmt = R200_DEPTH_FORMAT_16BIT_INT_Z;
429 rmesa->radeon.state.stencil.clear = 0x00000000;
430 break;
431 case 24:
432 rmesa->radeon.state.depth.clear = 0x00ffffff;
433 rmesa->radeon.state.depth.scale = 1.0 / (GLfloat)0xffffff;
434 depth_fmt = R200_DEPTH_FORMAT_24BIT_INT_Z;
435 rmesa->radeon.state.stencil.clear = 0xffff0000;
436 break;
437 default:
438 fprintf( stderr, "Error: Unsupported depth %d... exiting\n",
439 ctx->Visual.depthBits );
440 exit( -1 );
441 }
442
443 /* Only have hw stencil when depth buffer is 24 bits deep */
444 rmesa->radeon.state.stencil.hwBuffer = ( ctx->Visual.stencilBits > 0 &&
445 ctx->Visual.depthBits == 24 );
446
447 rmesa->radeon.Fallback = 0;
448
449 if ( ctx->Visual.doubleBufferMode && rmesa->radeon.sarea->pfCurrentPage == 0 ) {
450 drawOffset = rmesa->radeon.radeonScreen->backOffset;
451 drawPitch = rmesa->radeon.radeonScreen->backPitch;
452 } else {
453 drawOffset = rmesa->radeon.radeonScreen->frontOffset;
454 drawPitch = rmesa->radeon.radeonScreen->frontPitch;
455 }
456 #if 000
457 if ( ctx->Visual.doubleBufferMode && rmesa->sarea->pfCurrentPage == 0 ) {
458 rmesa->radeon.state.color.drawOffset = rmesa->radeon.radeonScreen->backOffset;
459 rmesa->radeon.state.color.drawPitch = rmesa->radeon.radeonScreen->backPitch;
460 } else {
461 rmesa->radeon.state.color.drawOffset = rmesa->radeon.radeonScreen->frontOffset;
462 rmesa->radeon.state.color.drawPitch = rmesa->radeon.radeonScreen->frontPitch;
463 }
464
465 rmesa->state.pixel.readOffset = rmesa->radeon.state.color.drawOffset;
466 rmesa->state.pixel.readPitch = rmesa->radeon.state.color.drawPitch;
467 #endif
468
469 rmesa->hw.max_state_size = 0;
470
471 #define ALLOC_STATE( ATOM, CHK, SZ, NM, IDX ) \
472 do { \
473 rmesa->hw.ATOM.cmd_size = SZ; \
474 rmesa->hw.ATOM.cmd = (GLuint *)CALLOC(SZ * sizeof(int)); \
475 rmesa->hw.ATOM.lastcmd = (GLuint *)CALLOC(SZ * sizeof(int)); \
476 rmesa->hw.ATOM.name = NM; \
477 rmesa->hw.ATOM.idx = IDX; \
478 rmesa->hw.ATOM.check = check_##CHK; \
479 rmesa->hw.ATOM.dirty = GL_FALSE; \
480 rmesa->hw.max_state_size += SZ * sizeof(int); \
481 } while (0)
482
483
484 /* Allocate state buffers:
485 */
486 if (rmesa->radeon.radeonScreen->drmSupportsBlendColor)
487 ALLOC_STATE( ctx, always, CTX_STATE_SIZE_NEWDRM, "CTX/context", 0 );
488 else
489 ALLOC_STATE( ctx, always, CTX_STATE_SIZE_OLDDRM, "CTX/context", 0 );
490
491 rmesa->hw.ctx.emit = ctx_emit;
492 ALLOC_STATE( set, always, SET_STATE_SIZE, "SET/setup", 0 );
493 ALLOC_STATE( lin, always, LIN_STATE_SIZE, "LIN/line", 0 );
494 ALLOC_STATE( msk, always, MSK_STATE_SIZE, "MSK/mask", 0 );
495 ALLOC_STATE( vpt, always, VPT_STATE_SIZE, "VPT/viewport", 0 );
496 ALLOC_STATE( vtx, always, VTX_STATE_SIZE, "VTX/vertex", 0 );
497 ALLOC_STATE( vap, always, VAP_STATE_SIZE, "VAP/vap", 0 );
498 ALLOC_STATE( vte, always, VTE_STATE_SIZE, "VTE/vte", 0 );
499 ALLOC_STATE( msc, always, MSC_STATE_SIZE, "MSC/misc", 0 );
500 ALLOC_STATE( cst, always, CST_STATE_SIZE, "CST/constant", 0 );
501 ALLOC_STATE( zbs, always, ZBS_STATE_SIZE, "ZBS/zbias", 0 );
502 ALLOC_STATE( tf, tf, TF_STATE_SIZE, "TF/tfactor", 0 );
503 if (rmesa->radeon.radeonScreen->drmSupportsFragShader) {
504 if (rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_R200) {
505 /* make sure texture units 0/1 are emitted pair-wise for r200 t0 hang workaround */
506 ALLOC_STATE( tex[0], tex_pair, TEX_STATE_SIZE_NEWDRM, "TEX/tex-0", 0 );
507 ALLOC_STATE( tex[1], tex_pair, TEX_STATE_SIZE_NEWDRM, "TEX/tex-1", 1 );
508 ALLOC_STATE( tam, tex_any, TAM_STATE_SIZE, "TAM/tam", 0 );
509 }
510 else {
511 ALLOC_STATE( tex[0], tex, TEX_STATE_SIZE_NEWDRM, "TEX/tex-0", 0 );
512 ALLOC_STATE( tex[1], tex, TEX_STATE_SIZE_NEWDRM, "TEX/tex-1", 1 );
513 ALLOC_STATE( tam, never, TAM_STATE_SIZE, "TAM/tam", 0 );
514 }
515 ALLOC_STATE( tex[2], tex, TEX_STATE_SIZE_NEWDRM, "TEX/tex-2", 2 );
516 ALLOC_STATE( tex[3], tex, TEX_STATE_SIZE_NEWDRM, "TEX/tex-3", 3 );
517 ALLOC_STATE( tex[4], tex, TEX_STATE_SIZE_NEWDRM, "TEX/tex-4", 4 );
518 ALLOC_STATE( tex[5], tex, TEX_STATE_SIZE_NEWDRM, "TEX/tex-5", 5 );
519 ALLOC_STATE( atf, afs, ATF_STATE_SIZE, "ATF/tfactor", 0 );
520 ALLOC_STATE( afs[0], afs_pass1, AFS_STATE_SIZE, "AFS/afsinst-0", 0 );
521 ALLOC_STATE( afs[1], afs, AFS_STATE_SIZE, "AFS/afsinst-1", 1 );
522 }
523 else {
524 if (rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_R200) {
525 ALLOC_STATE( tex[0], tex_pair, TEX_STATE_SIZE_OLDDRM, "TEX/tex-0", 0 );
526 ALLOC_STATE( tex[1], tex_pair, TEX_STATE_SIZE_OLDDRM, "TEX/tex-1", 1 );
527 ALLOC_STATE( tam, tex_any, TAM_STATE_SIZE, "TAM/tam", 0 );
528 }
529 else {
530 ALLOC_STATE( tex[0], tex, TEX_STATE_SIZE_OLDDRM, "TEX/tex-0", 0 );
531 ALLOC_STATE( tex[1], tex, TEX_STATE_SIZE_OLDDRM, "TEX/tex-1", 1 );
532 ALLOC_STATE( tam, never, TAM_STATE_SIZE, "TAM/tam", 0 );
533 }
534 ALLOC_STATE( tex[2], tex, TEX_STATE_SIZE_OLDDRM, "TEX/tex-2", 2 );
535 ALLOC_STATE( tex[3], tex, TEX_STATE_SIZE_OLDDRM, "TEX/tex-3", 3 );
536 ALLOC_STATE( tex[4], tex, TEX_STATE_SIZE_OLDDRM, "TEX/tex-4", 4 );
537 ALLOC_STATE( tex[5], tex, TEX_STATE_SIZE_OLDDRM, "TEX/tex-5", 5 );
538 ALLOC_STATE( atf, never, ATF_STATE_SIZE, "TF/tfactor", 0 );
539 ALLOC_STATE( afs[0], never, AFS_STATE_SIZE, "AFS/afsinst-0", 0 );
540 ALLOC_STATE( afs[1], never, AFS_STATE_SIZE, "AFS/afsinst-1", 1 );
541 }
542
543 for (i = 0; i < 5; i++)
544 rmesa->hw.tex[i].emit = tex_emit;
545 if (rmesa->radeon.radeonScreen->drmSupportsCubeMapsR200) {
546 ALLOC_STATE( cube[0], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-0", 0 );
547 ALLOC_STATE( cube[1], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-1", 1 );
548 ALLOC_STATE( cube[2], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-2", 2 );
549 ALLOC_STATE( cube[3], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-3", 3 );
550 ALLOC_STATE( cube[4], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-4", 4 );
551 ALLOC_STATE( cube[5], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-5", 5 );
552 for (i = 0; i < 5; i++)
553 rmesa->hw.cube[i].emit = cube_emit;
554 }
555 else {
556 ALLOC_STATE( cube[0], never, CUBE_STATE_SIZE, "CUBE/tex-0", 0 );
557 ALLOC_STATE( cube[1], never, CUBE_STATE_SIZE, "CUBE/tex-1", 1 );
558 ALLOC_STATE( cube[2], never, CUBE_STATE_SIZE, "CUBE/tex-2", 2 );
559 ALLOC_STATE( cube[3], never, CUBE_STATE_SIZE, "CUBE/tex-3", 3 );
560 ALLOC_STATE( cube[4], never, CUBE_STATE_SIZE, "CUBE/tex-4", 4 );
561 ALLOC_STATE( cube[5], never, CUBE_STATE_SIZE, "CUBE/tex-5", 5 );
562 }
563
564 if (rmesa->radeon.radeonScreen->drmSupportsVertexProgram) {
565 ALLOC_STATE( pvs, tcl_vp, PVS_STATE_SIZE, "PVS/pvscntl", 0 );
566 ALLOC_STATE( vpi[0], tcl_vp, VPI_STATE_SIZE, "VP/vertexprog-0", 0 );
567 ALLOC_STATE( vpi[1], tcl_vp_size, VPI_STATE_SIZE, "VP/vertexprog-1", 1 );
568 ALLOC_STATE( vpp[0], tcl_vp, VPP_STATE_SIZE, "VPP/vertexparam-0", 0 );
569 ALLOC_STATE( vpp[1], tcl_vpp_size, VPP_STATE_SIZE, "VPP/vertexparam-1", 1 );
570 }
571 else {
572 ALLOC_STATE( pvs, never, PVS_STATE_SIZE, "PVS/pvscntl", 0 );
573 ALLOC_STATE( vpi[0], never, VPI_STATE_SIZE, "VP/vertexprog-0", 0 );
574 ALLOC_STATE( vpi[1], never, VPI_STATE_SIZE, "VP/vertexprog-1", 1 );
575 ALLOC_STATE( vpp[0], never, VPP_STATE_SIZE, "VPP/vertexparam-0", 0 );
576 ALLOC_STATE( vpp[1], never, VPP_STATE_SIZE, "VPP/vertexparam-1", 1 );
577 }
578 /* FIXME: this atom has two commands, we need only one (ucp_vert_blend) for vp */
579 ALLOC_STATE( tcl, tcl_or_vp, TCL_STATE_SIZE, "TCL/tcl", 0 );
580 ALLOC_STATE( msl, tcl, MSL_STATE_SIZE, "MSL/matrix-select", 0 );
581 ALLOC_STATE( tcg, tcl, TCG_STATE_SIZE, "TCG/texcoordgen", 0 );
582 ALLOC_STATE( mtl[0], tcl_lighting, MTL_STATE_SIZE, "MTL0/material0", 0 );
583 ALLOC_STATE( mtl[1], tcl_lighting, MTL_STATE_SIZE, "MTL1/material1", 1 );
584 ALLOC_STATE( grd, tcl_or_vp, GRD_STATE_SIZE, "GRD/guard-band", 0 );
585 ALLOC_STATE( fog, tcl_fog, FOG_STATE_SIZE, "FOG/fog", 0 );
586 ALLOC_STATE( glt, tcl_lighting, GLT_STATE_SIZE, "GLT/light-global", 0 );
587 ALLOC_STATE( eye, tcl_lighting, EYE_STATE_SIZE, "EYE/eye-vector", 0 );
588 ALLOC_STATE( mat[R200_MTX_MV], tcl, MAT_STATE_SIZE, "MAT/modelview", 0 );
589 ALLOC_STATE( mat[R200_MTX_IMV], tcl, MAT_STATE_SIZE, "MAT/it-modelview", 0 );
590 ALLOC_STATE( mat[R200_MTX_MVP], tcl, MAT_STATE_SIZE, "MAT/modelproject", 0 );
591 ALLOC_STATE( mat[R200_MTX_TEX0], tcl_tex, MAT_STATE_SIZE, "MAT/texmat0", 0 );
592 ALLOC_STATE( mat[R200_MTX_TEX1], tcl_tex, MAT_STATE_SIZE, "MAT/texmat1", 1 );
593 ALLOC_STATE( mat[R200_MTX_TEX2], tcl_tex, MAT_STATE_SIZE, "MAT/texmat2", 2 );
594 ALLOC_STATE( mat[R200_MTX_TEX3], tcl_tex, MAT_STATE_SIZE, "MAT/texmat3", 3 );
595 ALLOC_STATE( mat[R200_MTX_TEX4], tcl_tex, MAT_STATE_SIZE, "MAT/texmat4", 4 );
596 ALLOC_STATE( mat[R200_MTX_TEX5], tcl_tex, MAT_STATE_SIZE, "MAT/texmat5", 5 );
597 ALLOC_STATE( ucp[0], tcl_ucp, UCP_STATE_SIZE, "UCP/userclip-0", 0 );
598 ALLOC_STATE( ucp[1], tcl_ucp, UCP_STATE_SIZE, "UCP/userclip-1", 1 );
599 ALLOC_STATE( ucp[2], tcl_ucp, UCP_STATE_SIZE, "UCP/userclip-2", 2 );
600 ALLOC_STATE( ucp[3], tcl_ucp, UCP_STATE_SIZE, "UCP/userclip-3", 3 );
601 ALLOC_STATE( ucp[4], tcl_ucp, UCP_STATE_SIZE, "UCP/userclip-4", 4 );
602 ALLOC_STATE( ucp[5], tcl_ucp, UCP_STATE_SIZE, "UCP/userclip-5", 5 );
603 ALLOC_STATE( lit[0], tcl_light, LIT_STATE_SIZE, "LIT/light-0", 0 );
604 ALLOC_STATE( lit[1], tcl_light, LIT_STATE_SIZE, "LIT/light-1", 1 );
605 ALLOC_STATE( lit[2], tcl_light, LIT_STATE_SIZE, "LIT/light-2", 2 );
606 ALLOC_STATE( lit[3], tcl_light, LIT_STATE_SIZE, "LIT/light-3", 3 );
607 ALLOC_STATE( lit[4], tcl_light, LIT_STATE_SIZE, "LIT/light-4", 4 );
608 ALLOC_STATE( lit[5], tcl_light, LIT_STATE_SIZE, "LIT/light-5", 5 );
609 ALLOC_STATE( lit[6], tcl_light, LIT_STATE_SIZE, "LIT/light-6", 6 );
610 ALLOC_STATE( lit[7], tcl_light, LIT_STATE_SIZE, "LIT/light-7", 7 );
611 ALLOC_STATE( pix[0], pix_zero, PIX_STATE_SIZE, "PIX/pixstage-0", 0 );
612 ALLOC_STATE( pix[1], texenv, PIX_STATE_SIZE, "PIX/pixstage-1", 1 );
613 ALLOC_STATE( pix[2], texenv, PIX_STATE_SIZE, "PIX/pixstage-2", 2 );
614 ALLOC_STATE( pix[3], texenv, PIX_STATE_SIZE, "PIX/pixstage-3", 3 );
615 ALLOC_STATE( pix[4], texenv, PIX_STATE_SIZE, "PIX/pixstage-4", 4 );
616 ALLOC_STATE( pix[5], texenv, PIX_STATE_SIZE, "PIX/pixstage-5", 5 );
617 if (rmesa->radeon.radeonScreen->drmSupportsTriPerf) {
618 ALLOC_STATE( prf, always, PRF_STATE_SIZE, "PRF/performance-tri", 0 );
619 }
620 else {
621 ALLOC_STATE( prf, never, PRF_STATE_SIZE, "PRF/performance-tri", 0 );
622 }
623 if (rmesa->radeon.radeonScreen->drmSupportsPointSprites) {
624 ALLOC_STATE( spr, always, SPR_STATE_SIZE, "SPR/pointsprite", 0 );
625 ALLOC_STATE( ptp, tcl, PTP_STATE_SIZE, "PTP/pointparams", 0 );
626 }
627 else {
628 ALLOC_STATE (spr, never, SPR_STATE_SIZE, "SPR/pointsprite", 0 );
629 ALLOC_STATE (ptp, never, PTP_STATE_SIZE, "PTP/pointparams", 0 );
630 }
631
632 r200SetUpAtomList( rmesa );
633
634 /* Fill in the packet headers:
635 */
636 rmesa->hw.ctx.cmd[CTX_CMD_0] = cmdpkt(RADEON_EMIT_PP_MISC);
637 rmesa->hw.ctx.cmd[CTX_CMD_1] = cmdpkt(RADEON_EMIT_PP_CNTL);
638 rmesa->hw.ctx.cmd[CTX_CMD_2] = cmdpkt(RADEON_EMIT_RB3D_COLORPITCH);
639 if (rmesa->radeon.radeonScreen->drmSupportsBlendColor)
640 rmesa->hw.ctx.cmd[CTX_CMD_3] = cmdpkt(R200_EMIT_RB3D_BLENDCOLOR);
641 rmesa->hw.lin.cmd[LIN_CMD_0] = cmdpkt(RADEON_EMIT_RE_LINE_PATTERN);
642 rmesa->hw.lin.cmd[LIN_CMD_1] = cmdpkt(RADEON_EMIT_SE_LINE_WIDTH);
643 rmesa->hw.msk.cmd[MSK_CMD_0] = cmdpkt(RADEON_EMIT_RB3D_STENCILREFMASK);
644 rmesa->hw.vpt.cmd[VPT_CMD_0] = cmdpkt(RADEON_EMIT_SE_VPORT_XSCALE);
645 rmesa->hw.set.cmd[SET_CMD_0] = cmdpkt(RADEON_EMIT_SE_CNTL);
646 rmesa->hw.msc.cmd[MSC_CMD_0] = cmdpkt(RADEON_EMIT_RE_MISC);
647 rmesa->hw.cst.cmd[CST_CMD_0] = cmdpkt(R200_EMIT_PP_CNTL_X);
648 rmesa->hw.cst.cmd[CST_CMD_1] = cmdpkt(R200_EMIT_RB3D_DEPTHXY_OFFSET);
649 rmesa->hw.cst.cmd[CST_CMD_2] = cmdpkt(R200_EMIT_RE_AUX_SCISSOR_CNTL);
650 rmesa->hw.cst.cmd[CST_CMD_3] = cmdpkt(R200_EMIT_RE_SCISSOR_TL_0);
651 rmesa->hw.cst.cmd[CST_CMD_4] = cmdpkt(R200_EMIT_SE_VAP_CNTL_STATUS);
652 rmesa->hw.cst.cmd[CST_CMD_5] = cmdpkt(R200_EMIT_RE_POINTSIZE);
653 rmesa->hw.cst.cmd[CST_CMD_6] = cmdpkt(R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0);
654 rmesa->hw.tam.cmd[TAM_CMD_0] = cmdpkt(R200_EMIT_PP_TAM_DEBUG3);
655 rmesa->hw.tf.cmd[TF_CMD_0] = cmdpkt(R200_EMIT_TFACTOR_0);
656 if (rmesa->radeon.radeonScreen->drmSupportsFragShader) {
657 rmesa->hw.atf.cmd[ATF_CMD_0] = cmdpkt(R200_EMIT_ATF_TFACTOR);
658 rmesa->hw.tex[0].cmd[TEX_CMD_0] = cmdpkt(R200_EMIT_PP_TXCTLALL_0);
659 rmesa->hw.tex[0].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(R200_EMIT_PP_TXOFFSET_0);
660 rmesa->hw.tex[1].cmd[TEX_CMD_0] = cmdpkt(R200_EMIT_PP_TXCTLALL_1);
661 rmesa->hw.tex[1].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(R200_EMIT_PP_TXOFFSET_1);
662 rmesa->hw.tex[2].cmd[TEX_CMD_0] = cmdpkt(R200_EMIT_PP_TXCTLALL_2);
663 rmesa->hw.tex[2].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(R200_EMIT_PP_TXOFFSET_2);
664 rmesa->hw.tex[3].cmd[TEX_CMD_0] = cmdpkt(R200_EMIT_PP_TXCTLALL_3);
665 rmesa->hw.tex[3].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(R200_EMIT_PP_TXOFFSET_3);
666 rmesa->hw.tex[4].cmd[TEX_CMD_0] = cmdpkt(R200_EMIT_PP_TXCTLALL_4);
667 rmesa->hw.tex[4].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(R200_EMIT_PP_TXOFFSET_4);
668 rmesa->hw.tex[5].cmd[TEX_CMD_0] = cmdpkt(R200_EMIT_PP_TXCTLALL_5);
669 rmesa->hw.tex[5].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(R200_EMIT_PP_TXOFFSET_5);
670 } else {
671 rmesa->hw.tex[0].cmd[TEX_CMD_0] = cmdpkt(R200_EMIT_PP_TXFILTER_0);
672 rmesa->hw.tex[0].cmd[TEX_CMD_1_OLDDRM] = cmdpkt(R200_EMIT_PP_TXOFFSET_0);
673 rmesa->hw.tex[1].cmd[TEX_CMD_0] = cmdpkt(R200_EMIT_PP_TXFILTER_1);
674 rmesa->hw.tex[1].cmd[TEX_CMD_1_OLDDRM] = cmdpkt(R200_EMIT_PP_TXOFFSET_1);
675 rmesa->hw.tex[2].cmd[TEX_CMD_0] = cmdpkt(R200_EMIT_PP_TXFILTER_2);
676 rmesa->hw.tex[2].cmd[TEX_CMD_1_OLDDRM] = cmdpkt(R200_EMIT_PP_TXOFFSET_2);
677 rmesa->hw.tex[3].cmd[TEX_CMD_0] = cmdpkt(R200_EMIT_PP_TXFILTER_3);
678 rmesa->hw.tex[3].cmd[TEX_CMD_1_OLDDRM] = cmdpkt(R200_EMIT_PP_TXOFFSET_3);
679 rmesa->hw.tex[4].cmd[TEX_CMD_0] = cmdpkt(R200_EMIT_PP_TXFILTER_4);
680 rmesa->hw.tex[4].cmd[TEX_CMD_1_OLDDRM] = cmdpkt(R200_EMIT_PP_TXOFFSET_4);
681 rmesa->hw.tex[5].cmd[TEX_CMD_0] = cmdpkt(R200_EMIT_PP_TXFILTER_5);
682 rmesa->hw.tex[5].cmd[TEX_CMD_1_OLDDRM] = cmdpkt(R200_EMIT_PP_TXOFFSET_5);
683 }
684 rmesa->hw.afs[0].cmd[AFS_CMD_0] = cmdpkt(R200_EMIT_PP_AFS_0);
685 rmesa->hw.afs[1].cmd[AFS_CMD_0] = cmdpkt(R200_EMIT_PP_AFS_1);
686 rmesa->hw.pvs.cmd[PVS_CMD_0] = cmdpkt(R200_EMIT_VAP_PVS_CNTL);
687 rmesa->hw.cube[0].cmd[CUBE_CMD_0] = cmdpkt(R200_EMIT_PP_CUBIC_FACES_0);
688 rmesa->hw.cube[0].cmd[CUBE_CMD_1] = cmdpkt(R200_EMIT_PP_CUBIC_OFFSETS_0);
689 rmesa->hw.cube[1].cmd[CUBE_CMD_0] = cmdpkt(R200_EMIT_PP_CUBIC_FACES_1);
690 rmesa->hw.cube[1].cmd[CUBE_CMD_1] = cmdpkt(R200_EMIT_PP_CUBIC_OFFSETS_1);
691 rmesa->hw.cube[2].cmd[CUBE_CMD_0] = cmdpkt(R200_EMIT_PP_CUBIC_FACES_2);
692 rmesa->hw.cube[2].cmd[CUBE_CMD_1] = cmdpkt(R200_EMIT_PP_CUBIC_OFFSETS_2);
693 rmesa->hw.cube[3].cmd[CUBE_CMD_0] = cmdpkt(R200_EMIT_PP_CUBIC_FACES_3);
694 rmesa->hw.cube[3].cmd[CUBE_CMD_1] = cmdpkt(R200_EMIT_PP_CUBIC_OFFSETS_3);
695 rmesa->hw.cube[4].cmd[CUBE_CMD_0] = cmdpkt(R200_EMIT_PP_CUBIC_FACES_4);
696 rmesa->hw.cube[4].cmd[CUBE_CMD_1] = cmdpkt(R200_EMIT_PP_CUBIC_OFFSETS_4);
697 rmesa->hw.cube[5].cmd[CUBE_CMD_0] = cmdpkt(R200_EMIT_PP_CUBIC_FACES_5);
698 rmesa->hw.cube[5].cmd[CUBE_CMD_1] = cmdpkt(R200_EMIT_PP_CUBIC_OFFSETS_5);
699 rmesa->hw.pix[0].cmd[PIX_CMD_0] = cmdpkt(R200_EMIT_PP_TXCBLEND_0);
700 rmesa->hw.pix[1].cmd[PIX_CMD_0] = cmdpkt(R200_EMIT_PP_TXCBLEND_1);
701 rmesa->hw.pix[2].cmd[PIX_CMD_0] = cmdpkt(R200_EMIT_PP_TXCBLEND_2);
702 rmesa->hw.pix[3].cmd[PIX_CMD_0] = cmdpkt(R200_EMIT_PP_TXCBLEND_3);
703 rmesa->hw.pix[4].cmd[PIX_CMD_0] = cmdpkt(R200_EMIT_PP_TXCBLEND_4);
704 rmesa->hw.pix[5].cmd[PIX_CMD_0] = cmdpkt(R200_EMIT_PP_TXCBLEND_5);
705 rmesa->hw.zbs.cmd[ZBS_CMD_0] = cmdpkt(RADEON_EMIT_SE_ZBIAS_FACTOR);
706 rmesa->hw.tcl.cmd[TCL_CMD_0] = cmdpkt(R200_EMIT_TCL_LIGHT_MODEL_CTL_0);
707 rmesa->hw.tcl.cmd[TCL_CMD_1] = cmdpkt(R200_EMIT_TCL_UCP_VERT_BLEND_CTL);
708 rmesa->hw.tcg.cmd[TCG_CMD_0] = cmdpkt(R200_EMIT_TEX_PROC_CTL_2);
709 rmesa->hw.msl.cmd[MSL_CMD_0] = cmdpkt(R200_EMIT_MATRIX_SELECT_0);
710 rmesa->hw.vap.cmd[VAP_CMD_0] = cmdpkt(R200_EMIT_VAP_CTL);
711 rmesa->hw.vtx.cmd[VTX_CMD_0] = cmdpkt(R200_EMIT_VTX_FMT_0);
712 rmesa->hw.vtx.cmd[VTX_CMD_1] = cmdpkt(R200_EMIT_OUTPUT_VTX_COMP_SEL);
713 rmesa->hw.vtx.cmd[VTX_CMD_2] = cmdpkt(R200_EMIT_SE_VTX_STATE_CNTL);
714 rmesa->hw.vte.cmd[VTE_CMD_0] = cmdpkt(R200_EMIT_VTE_CNTL);
715 rmesa->hw.prf.cmd[PRF_CMD_0] = cmdpkt(R200_EMIT_PP_TRI_PERF_CNTL);
716 rmesa->hw.spr.cmd[SPR_CMD_0] = cmdpkt(R200_EMIT_TCL_POINT_SPRITE_CNTL);
717 rmesa->hw.mtl[0].cmd[MTL_CMD_0] =
718 cmdvec( R200_VS_MAT_0_EMISS, 1, 16 );
719 rmesa->hw.mtl[0].cmd[MTL_CMD_1] =
720 cmdscl2( R200_SS_MAT_0_SHININESS, 1, 1 );
721 rmesa->hw.mtl[1].cmd[MTL_CMD_0] =
722 cmdvec( R200_VS_MAT_1_EMISS, 1, 16 );
723 rmesa->hw.mtl[1].cmd[MTL_CMD_1] =
724 cmdscl2( R200_SS_MAT_1_SHININESS, 1, 1 );
725
726 rmesa->hw.vpi[0].cmd[VPI_CMD_0] =
727 cmdveclinear( R200_PVS_PROG0, 64 );
728 rmesa->hw.vpi[1].cmd[VPI_CMD_0] =
729 cmdveclinear( R200_PVS_PROG1, 64 );
730 rmesa->hw.vpp[0].cmd[VPP_CMD_0] =
731 cmdveclinear( R200_PVS_PARAM0, 96 );
732 rmesa->hw.vpp[1].cmd[VPP_CMD_0] =
733 cmdveclinear( R200_PVS_PARAM1, 96 );
734
735 rmesa->hw.grd.cmd[GRD_CMD_0] =
736 cmdscl( R200_SS_VERT_GUARD_CLIP_ADJ_ADDR, 1, 4 );
737 rmesa->hw.fog.cmd[FOG_CMD_0] =
738 cmdvec( R200_VS_FOG_PARAM_ADDR, 1, 4 );
739 rmesa->hw.glt.cmd[GLT_CMD_0] =
740 cmdvec( R200_VS_GLOBAL_AMBIENT_ADDR, 1, 4 );
741 rmesa->hw.eye.cmd[EYE_CMD_0] =
742 cmdvec( R200_VS_EYE_VECTOR_ADDR, 1, 4 );
743
744 rmesa->hw.mat[R200_MTX_MV].cmd[MAT_CMD_0] =
745 cmdvec( R200_VS_MATRIX_0_MV, 1, 16);
746 rmesa->hw.mat[R200_MTX_IMV].cmd[MAT_CMD_0] =
747 cmdvec( R200_VS_MATRIX_1_INV_MV, 1, 16);
748 rmesa->hw.mat[R200_MTX_MVP].cmd[MAT_CMD_0] =
749 cmdvec( R200_VS_MATRIX_2_MVP, 1, 16);
750 rmesa->hw.mat[R200_MTX_TEX0].cmd[MAT_CMD_0] =
751 cmdvec( R200_VS_MATRIX_3_TEX0, 1, 16);
752 rmesa->hw.mat[R200_MTX_TEX1].cmd[MAT_CMD_0] =
753 cmdvec( R200_VS_MATRIX_4_TEX1, 1, 16);
754 rmesa->hw.mat[R200_MTX_TEX2].cmd[MAT_CMD_0] =
755 cmdvec( R200_VS_MATRIX_5_TEX2, 1, 16);
756 rmesa->hw.mat[R200_MTX_TEX3].cmd[MAT_CMD_0] =
757 cmdvec( R200_VS_MATRIX_6_TEX3, 1, 16);
758 rmesa->hw.mat[R200_MTX_TEX4].cmd[MAT_CMD_0] =
759 cmdvec( R200_VS_MATRIX_7_TEX4, 1, 16);
760 rmesa->hw.mat[R200_MTX_TEX5].cmd[MAT_CMD_0] =
761 cmdvec( R200_VS_MATRIX_8_TEX5, 1, 16);
762
763 for (i = 0 ; i < 8; i++) {
764 rmesa->hw.lit[i].cmd[LIT_CMD_0] =
765 cmdvec( R200_VS_LIGHT_AMBIENT_ADDR + i, 8, 24 );
766 rmesa->hw.lit[i].cmd[LIT_CMD_1] =
767 cmdscl( R200_SS_LIGHT_DCD_ADDR + i, 8, 7 );
768 }
769
770 for (i = 0 ; i < 6; i++) {
771 rmesa->hw.ucp[i].cmd[UCP_CMD_0] =
772 cmdvec( R200_VS_UCP_ADDR + i, 1, 4 );
773 }
774
775 rmesa->hw.ptp.cmd[PTP_CMD_0] =
776 cmdvec( R200_VS_PNT_SPRITE_VPORT_SCALE, 1, 4 );
777 rmesa->hw.ptp.cmd[PTP_CMD_1] =
778 cmdvec( R200_VS_PNT_SPRITE_ATT_CONST, 1, 12 );
779
780 /* Initial Harware state:
781 */
782 rmesa->hw.ctx.cmd[CTX_PP_MISC] = (R200_ALPHA_TEST_PASS
783 /* | R200_RIGHT_HAND_CUBE_OGL*/);
784
785 rmesa->hw.ctx.cmd[CTX_PP_FOG_COLOR] = (R200_FOG_VERTEX |
786 R200_FOG_USE_SPEC_ALPHA);
787
788 rmesa->hw.ctx.cmd[CTX_RE_SOLID_COLOR] = 0x00000000;
789
790 rmesa->hw.ctx.cmd[CTX_RB3D_BLENDCNTL] = (R200_COMB_FCN_ADD_CLAMP |
791 (R200_BLEND_GL_ONE << R200_SRC_BLEND_SHIFT) |
792 (R200_BLEND_GL_ZERO << R200_DST_BLEND_SHIFT));
793
794 if (rmesa->radeon.radeonScreen->drmSupportsBlendColor) {
795 rmesa->hw.ctx.cmd[CTX_RB3D_BLENDCOLOR] = 0x00000000;
796 rmesa->hw.ctx.cmd[CTX_RB3D_ABLENDCNTL] = (R200_COMB_FCN_ADD_CLAMP |
797 (R200_BLEND_GL_ONE << R200_SRC_BLEND_SHIFT) |
798 (R200_BLEND_GL_ZERO << R200_DST_BLEND_SHIFT));
799 rmesa->hw.ctx.cmd[CTX_RB3D_CBLENDCNTL] = (R200_COMB_FCN_ADD_CLAMP |
800 (R200_BLEND_GL_ONE << R200_SRC_BLEND_SHIFT) |
801 (R200_BLEND_GL_ZERO << R200_DST_BLEND_SHIFT));
802 }
803
804 rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHOFFSET] =
805 rmesa->radeon.radeonScreen->depthOffset + rmesa->radeon.radeonScreen->fbLocation;
806
807 rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHPITCH] =
808 ((rmesa->radeon.radeonScreen->depthPitch &
809 R200_DEPTHPITCH_MASK) |
810 R200_DEPTH_ENDIAN_NO_SWAP);
811
812 if (rmesa->using_hyperz)
813 rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHPITCH] |= R200_DEPTH_HYPERZ;
814
815 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] = (depth_fmt |
816 R200_Z_TEST_LESS |
817 R200_STENCIL_TEST_ALWAYS |
818 R200_STENCIL_FAIL_KEEP |
819 R200_STENCIL_ZPASS_KEEP |
820 R200_STENCIL_ZFAIL_KEEP |
821 R200_Z_WRITE_ENABLE);
822
823 if (rmesa->using_hyperz) {
824 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= R200_Z_COMPRESSION_ENABLE |
825 R200_Z_DECOMPRESSION_ENABLE;
826 /* if (rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_R200)
827 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_HIERARCHY_ENABLE;*/
828 }
829
830 rmesa->hw.ctx.cmd[CTX_PP_CNTL] = (R200_ANTI_ALIAS_NONE
831 | R200_TEX_BLEND_0_ENABLE);
832
833 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] = color_fmt;
834 switch ( driQueryOptioni( &rmesa->radeon.optionCache, "dither_mode" ) ) {
835 case DRI_CONF_DITHER_XERRORDIFFRESET:
836 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= R200_DITHER_INIT;
837 break;
838 case DRI_CONF_DITHER_ORDERED:
839 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= R200_SCALE_DITHER_ENABLE;
840 break;
841 }
842 if ( driQueryOptioni( &rmesa->radeon.optionCache, "round_mode" ) ==
843 DRI_CONF_ROUND_ROUND )
844 rmesa->radeon.state.color.roundEnable = R200_ROUND_ENABLE;
845 else
846 rmesa->radeon.state.color.roundEnable = 0;
847 if ( driQueryOptioni (&rmesa->radeon.optionCache, "color_reduction" ) ==
848 DRI_CONF_COLOR_REDUCTION_DITHER )
849 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= R200_DITHER_ENABLE;
850 else
851 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= rmesa->radeon.state.color.roundEnable;
852
853 #if 000
854 rmesa->hw.ctx.cmd[CTX_RB3D_COLOROFFSET] = ((rmesa->radeon.state.color.drawOffset +
855 rmesa->radeon.radeonScreen->fbLocation)
856 & R200_COLOROFFSET_MASK);
857
858 rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] = ((rmesa->radeon.state.color.drawPitch &
859 R200_COLORPITCH_MASK) |
860 R200_COLOR_ENDIAN_NO_SWAP);
861 #else
862 rmesa->hw.ctx.cmd[CTX_RB3D_COLOROFFSET] = ((drawOffset +
863 rmesa->radeon.radeonScreen->fbLocation)
864 & R200_COLOROFFSET_MASK);
865
866 rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] = ((drawPitch &
867 R200_COLORPITCH_MASK) |
868 R200_COLOR_ENDIAN_NO_SWAP);
869 #endif
870 /* (fixed size) sarea is initialized to zero afaics so can omit version check. Phew! */
871 if (rmesa->radeon.sarea->tiling_enabled) {
872 rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] |= R200_COLOR_TILE_ENABLE;
873 }
874
875 rmesa->hw.prf.cmd[PRF_PP_TRI_PERF] = R200_TRI_CUTOFF_MASK - R200_TRI_CUTOFF_MASK *
876 driQueryOptionf (&rmesa->radeon.optionCache,"texture_blend_quality");
877 rmesa->hw.prf.cmd[PRF_PP_PERF_CNTL] = 0;
878
879 rmesa->hw.set.cmd[SET_SE_CNTL] = (R200_FFACE_CULL_CCW |
880 R200_BFACE_SOLID |
881 R200_FFACE_SOLID |
882 R200_FLAT_SHADE_VTX_LAST |
883 R200_DIFFUSE_SHADE_GOURAUD |
884 R200_ALPHA_SHADE_GOURAUD |
885 R200_SPECULAR_SHADE_GOURAUD |
886 R200_FOG_SHADE_GOURAUD |
887 R200_DISC_FOG_SHADE_GOURAUD |
888 R200_VTX_PIX_CENTER_OGL |
889 R200_ROUND_MODE_TRUNC |
890 R200_ROUND_PREC_8TH_PIX);
891
892 rmesa->hw.set.cmd[SET_RE_CNTL] = (R200_PERSPECTIVE_ENABLE |
893 R200_SCISSOR_ENABLE);
894
895 rmesa->hw.lin.cmd[LIN_RE_LINE_PATTERN] = ((1 << 16) | 0xffff);
896
897 rmesa->hw.lin.cmd[LIN_RE_LINE_STATE] =
898 ((0 << R200_LINE_CURRENT_PTR_SHIFT) |
899 (1 << R200_LINE_CURRENT_COUNT_SHIFT));
900
901 rmesa->hw.lin.cmd[LIN_SE_LINE_WIDTH] = (1 << 4);
902
903 rmesa->hw.msk.cmd[MSK_RB3D_STENCILREFMASK] =
904 ((0x00 << R200_STENCIL_REF_SHIFT) |
905 (0xff << R200_STENCIL_MASK_SHIFT) |
906 (0xff << R200_STENCIL_WRITEMASK_SHIFT));
907
908 rmesa->hw.msk.cmd[MSK_RB3D_ROPCNTL] = R200_ROP_COPY;
909 rmesa->hw.msk.cmd[MSK_RB3D_PLANEMASK] = 0xffffffff;
910
911 rmesa->hw.tam.cmd[TAM_DEBUG3] = 0;
912
913 rmesa->hw.msc.cmd[MSC_RE_MISC] =
914 ((0 << R200_STIPPLE_X_OFFSET_SHIFT) |
915 (0 << R200_STIPPLE_Y_OFFSET_SHIFT) |
916 R200_STIPPLE_BIG_BIT_ORDER);
917
918
919 rmesa->hw.cst.cmd[CST_PP_CNTL_X] = 0;
920 rmesa->hw.cst.cmd[CST_RB3D_DEPTHXY_OFFSET] = 0;
921 rmesa->hw.cst.cmd[CST_RE_AUX_SCISSOR_CNTL] = 0x0;
922 rmesa->hw.cst.cmd[CST_RE_SCISSOR_TL_0] = 0;
923 rmesa->hw.cst.cmd[CST_RE_SCISSOR_BR_0] = 0;
924 rmesa->hw.cst.cmd[CST_SE_VAP_CNTL_STATUS] =
925 #ifdef MESA_BIG_ENDIAN
926 R200_VC_32BIT_SWAP;
927 #else
928 R200_VC_NO_SWAP;
929 #endif
930
931 if (!(rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL)) {
932 /* Bypass TCL */
933 rmesa->hw.cst.cmd[CST_SE_VAP_CNTL_STATUS] |= (1<<8);
934 }
935
936 rmesa->hw.cst.cmd[CST_RE_POINTSIZE] =
937 (((GLuint)(ctx->Const.MaxPointSize * 16.0)) << R200_MAXPOINTSIZE_SHIFT) | 0x10;
938 rmesa->hw.cst.cmd[CST_SE_TCL_INPUT_VTX_0] =
939 (0x0 << R200_VERTEX_POSITION_ADDR__SHIFT);
940 rmesa->hw.cst.cmd[CST_SE_TCL_INPUT_VTX_1] =
941 (0x02 << R200_VTX_COLOR_0_ADDR__SHIFT) |
942 (0x03 << R200_VTX_COLOR_1_ADDR__SHIFT);
943 rmesa->hw.cst.cmd[CST_SE_TCL_INPUT_VTX_2] =
944 (0x06 << R200_VTX_TEX_0_ADDR__SHIFT) |
945 (0x07 << R200_VTX_TEX_1_ADDR__SHIFT) |
946 (0x08 << R200_VTX_TEX_2_ADDR__SHIFT) |
947 (0x09 << R200_VTX_TEX_3_ADDR__SHIFT);
948 rmesa->hw.cst.cmd[CST_SE_TCL_INPUT_VTX_3] =
949 (0x0A << R200_VTX_TEX_4_ADDR__SHIFT) |
950 (0x0B << R200_VTX_TEX_5_ADDR__SHIFT);
951
952
953 rmesa->hw.vpt.cmd[VPT_SE_VPORT_XSCALE] = 0x00000000;
954 rmesa->hw.vpt.cmd[VPT_SE_VPORT_XOFFSET] = 0x00000000;
955 rmesa->hw.vpt.cmd[VPT_SE_VPORT_YSCALE] = 0x00000000;
956 rmesa->hw.vpt.cmd[VPT_SE_VPORT_YOFFSET] = 0x00000000;
957 rmesa->hw.vpt.cmd[VPT_SE_VPORT_ZSCALE] = 0x00000000;
958 rmesa->hw.vpt.cmd[VPT_SE_VPORT_ZOFFSET] = 0x00000000;
959
960 for ( i = 0 ; i < ctx->Const.MaxTextureUnits ; i++ ) {
961 rmesa->hw.tex[i].cmd[TEX_PP_TXFILTER] = R200_BORDER_MODE_OGL;
962 rmesa->hw.tex[i].cmd[TEX_PP_TXFORMAT] =
963 ((i << R200_TXFORMAT_ST_ROUTE_SHIFT) | /* <-- note i */
964 (2 << R200_TXFORMAT_WIDTH_SHIFT) |
965 (2 << R200_TXFORMAT_HEIGHT_SHIFT));
966 rmesa->hw.tex[i].cmd[TEX_PP_BORDER_COLOR] = 0;
967 rmesa->hw.tex[i].cmd[TEX_PP_TXFORMAT_X] =
968 (/* R200_TEXCOORD_PROJ | */
969 0x100000); /* Small default bias */
970 if (rmesa->radeon.radeonScreen->drmSupportsFragShader) {
971 rmesa->hw.tex[i].cmd[TEX_PP_TXOFFSET_NEWDRM] =
972 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
973 rmesa->hw.tex[i].cmd[TEX_PP_CUBIC_FACES] = 0;
974 rmesa->hw.tex[i].cmd[TEX_PP_TXMULTI_CTL] = 0;
975 }
976 else {
977 rmesa->hw.tex[i].cmd[TEX_PP_TXOFFSET_OLDDRM] =
978 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
979 }
980
981 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_FACES] = 0;
982 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F1] =
983 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
984 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F2] =
985 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
986 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F3] =
987 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
988 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F4] =
989 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
990 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F5] =
991 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
992
993 rmesa->hw.pix[i].cmd[PIX_PP_TXCBLEND] =
994 (R200_TXC_ARG_A_ZERO |
995 R200_TXC_ARG_B_ZERO |
996 R200_TXC_ARG_C_DIFFUSE_COLOR |
997 R200_TXC_OP_MADD);
998
999 rmesa->hw.pix[i].cmd[PIX_PP_TXCBLEND2] =
1000 ((i << R200_TXC_TFACTOR_SEL_SHIFT) |
1001 R200_TXC_SCALE_1X |
1002 R200_TXC_CLAMP_0_1 |
1003 R200_TXC_OUTPUT_REG_R0);
1004
1005 rmesa->hw.pix[i].cmd[PIX_PP_TXABLEND] =
1006 (R200_TXA_ARG_A_ZERO |
1007 R200_TXA_ARG_B_ZERO |
1008 R200_TXA_ARG_C_DIFFUSE_ALPHA |
1009 R200_TXA_OP_MADD);
1010
1011 rmesa->hw.pix[i].cmd[PIX_PP_TXABLEND2] =
1012 ((i << R200_TXA_TFACTOR_SEL_SHIFT) |
1013 R200_TXA_SCALE_1X |
1014 R200_TXA_CLAMP_0_1 |
1015 R200_TXA_OUTPUT_REG_R0);
1016 }
1017
1018 rmesa->hw.tf.cmd[TF_TFACTOR_0] = 0;
1019 rmesa->hw.tf.cmd[TF_TFACTOR_1] = 0;
1020 rmesa->hw.tf.cmd[TF_TFACTOR_2] = 0;
1021 rmesa->hw.tf.cmd[TF_TFACTOR_3] = 0;
1022 rmesa->hw.tf.cmd[TF_TFACTOR_4] = 0;
1023 rmesa->hw.tf.cmd[TF_TFACTOR_5] = 0;
1024
1025 rmesa->hw.vap.cmd[VAP_SE_VAP_CNTL] =
1026 (R200_VAP_TCL_ENABLE |
1027 (0x9 << R200_VAP_VF_MAX_VTX_NUM__SHIFT));
1028
1029 rmesa->hw.vte.cmd[VTE_SE_VTE_CNTL] =
1030 (R200_VPORT_X_SCALE_ENA |
1031 R200_VPORT_Y_SCALE_ENA |
1032 R200_VPORT_Z_SCALE_ENA |
1033 R200_VPORT_X_OFFSET_ENA |
1034 R200_VPORT_Y_OFFSET_ENA |
1035 R200_VPORT_Z_OFFSET_ENA |
1036 /* FIXME: Turn on for tex rect only */
1037 R200_VTX_ST_DENORMALIZED |
1038 R200_VTX_W0_FMT);
1039
1040
1041 rmesa->hw.vtx.cmd[VTX_VTXFMT_0] = 0;
1042 rmesa->hw.vtx.cmd[VTX_VTXFMT_1] = 0;
1043 rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_VTXFMT_0] =
1044 ((R200_VTX_Z0 | R200_VTX_W0 |
1045 (R200_VTX_FP_RGBA << R200_VTX_COLOR_0_SHIFT)));
1046 rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_VTXFMT_1] = 0;
1047 rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_COMPSEL] = (R200_OUTPUT_XYZW);
1048 rmesa->hw.vtx.cmd[VTX_STATE_CNTL] = R200_VSC_UPDATE_USER_COLOR_0_ENABLE;
1049
1050
1051 /* Matrix selection */
1052 rmesa->hw.msl.cmd[MSL_MATRIX_SELECT_0] =
1053 (R200_MTX_MV << R200_MODELVIEW_0_SHIFT);
1054
1055 rmesa->hw.msl.cmd[MSL_MATRIX_SELECT_1] =
1056 (R200_MTX_IMV << R200_IT_MODELVIEW_0_SHIFT);
1057
1058 rmesa->hw.msl.cmd[MSL_MATRIX_SELECT_2] =
1059 (R200_MTX_MVP << R200_MODELPROJECT_0_SHIFT);
1060
1061 rmesa->hw.msl.cmd[MSL_MATRIX_SELECT_3] =
1062 ((R200_MTX_TEX0 << R200_TEXMAT_0_SHIFT) |
1063 (R200_MTX_TEX1 << R200_TEXMAT_1_SHIFT) |
1064 (R200_MTX_TEX2 << R200_TEXMAT_2_SHIFT) |
1065 (R200_MTX_TEX3 << R200_TEXMAT_3_SHIFT));
1066
1067 rmesa->hw.msl.cmd[MSL_MATRIX_SELECT_4] =
1068 ((R200_MTX_TEX4 << R200_TEXMAT_4_SHIFT) |
1069 (R200_MTX_TEX5 << R200_TEXMAT_5_SHIFT));
1070
1071
1072 /* General TCL state */
1073 rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL_0] =
1074 (R200_SPECULAR_LIGHTS |
1075 R200_DIFFUSE_SPECULAR_COMBINE |
1076 R200_LOCAL_LIGHT_VEC_GL |
1077 R200_LM0_SOURCE_MATERIAL_0 << R200_FRONT_SHININESS_SOURCE_SHIFT |
1078 R200_LM0_SOURCE_MATERIAL_1 << R200_BACK_SHININESS_SOURCE_SHIFT);
1079
1080 rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL_1] =
1081 ((R200_LM1_SOURCE_MATERIAL_0 << R200_FRONT_EMISSIVE_SOURCE_SHIFT) |
1082 (R200_LM1_SOURCE_MATERIAL_0 << R200_FRONT_AMBIENT_SOURCE_SHIFT) |
1083 (R200_LM1_SOURCE_MATERIAL_0 << R200_FRONT_DIFFUSE_SOURCE_SHIFT) |
1084 (R200_LM1_SOURCE_MATERIAL_0 << R200_FRONT_SPECULAR_SOURCE_SHIFT) |
1085 (R200_LM1_SOURCE_MATERIAL_1 << R200_BACK_EMISSIVE_SOURCE_SHIFT) |
1086 (R200_LM1_SOURCE_MATERIAL_1 << R200_BACK_AMBIENT_SOURCE_SHIFT) |
1087 (R200_LM1_SOURCE_MATERIAL_1 << R200_BACK_DIFFUSE_SOURCE_SHIFT) |
1088 (R200_LM1_SOURCE_MATERIAL_1 << R200_BACK_SPECULAR_SOURCE_SHIFT));
1089
1090 rmesa->hw.tcl.cmd[TCL_PER_LIGHT_CTL_0] = 0; /* filled in via callbacks */
1091 rmesa->hw.tcl.cmd[TCL_PER_LIGHT_CTL_1] = 0;
1092 rmesa->hw.tcl.cmd[TCL_PER_LIGHT_CTL_2] = 0;
1093 rmesa->hw.tcl.cmd[TCL_PER_LIGHT_CTL_3] = 0;
1094
1095 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] =
1096 (R200_UCP_IN_CLIP_SPACE |
1097 R200_CULL_FRONT_IS_CCW);
1098
1099 /* Texgen/Texmat state */
1100 rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_2] = 0x00ffffff;
1101 rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_3] =
1102 ((0 << R200_TEXGEN_0_INPUT_TEX_SHIFT) |
1103 (1 << R200_TEXGEN_1_INPUT_TEX_SHIFT) |
1104 (2 << R200_TEXGEN_2_INPUT_TEX_SHIFT) |
1105 (3 << R200_TEXGEN_3_INPUT_TEX_SHIFT) |
1106 (4 << R200_TEXGEN_4_INPUT_TEX_SHIFT) |
1107 (5 << R200_TEXGEN_5_INPUT_TEX_SHIFT));
1108 rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_0] = 0;
1109 rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_1] =
1110 ((0 << R200_TEXGEN_0_INPUT_SHIFT) |
1111 (1 << R200_TEXGEN_1_INPUT_SHIFT) |
1112 (2 << R200_TEXGEN_2_INPUT_SHIFT) |
1113 (3 << R200_TEXGEN_3_INPUT_SHIFT) |
1114 (4 << R200_TEXGEN_4_INPUT_SHIFT) |
1115 (5 << R200_TEXGEN_5_INPUT_SHIFT));
1116 rmesa->hw.tcg.cmd[TCG_TEX_CYL_WRAP_CTL] = 0;
1117
1118
1119 for (i = 0 ; i < 8; i++) {
1120 struct gl_light *l = &ctx->Light.Light[i];
1121 GLenum p = GL_LIGHT0 + i;
1122 *(float *)&(rmesa->hw.lit[i].cmd[LIT_RANGE_CUTOFF]) = FLT_MAX;
1123
1124 ctx->Driver.Lightfv( ctx, p, GL_AMBIENT, l->Ambient );
1125 ctx->Driver.Lightfv( ctx, p, GL_DIFFUSE, l->Diffuse );
1126 ctx->Driver.Lightfv( ctx, p, GL_SPECULAR, l->Specular );
1127 ctx->Driver.Lightfv( ctx, p, GL_POSITION, NULL );
1128 ctx->Driver.Lightfv( ctx, p, GL_SPOT_DIRECTION, NULL );
1129 ctx->Driver.Lightfv( ctx, p, GL_SPOT_EXPONENT, &l->SpotExponent );
1130 ctx->Driver.Lightfv( ctx, p, GL_SPOT_CUTOFF, &l->SpotCutoff );
1131 ctx->Driver.Lightfv( ctx, p, GL_CONSTANT_ATTENUATION,
1132 &l->ConstantAttenuation );
1133 ctx->Driver.Lightfv( ctx, p, GL_LINEAR_ATTENUATION,
1134 &l->LinearAttenuation );
1135 ctx->Driver.Lightfv( ctx, p, GL_QUADRATIC_ATTENUATION,
1136 &l->QuadraticAttenuation );
1137 *(float *)&(rmesa->hw.lit[i].cmd[LIT_ATTEN_XXX]) = 0.0;
1138 }
1139
1140 ctx->Driver.LightModelfv( ctx, GL_LIGHT_MODEL_AMBIENT,
1141 ctx->Light.Model.Ambient );
1142
1143 TNL_CONTEXT(ctx)->Driver.NotifyMaterialChange( ctx );
1144
1145 for (i = 0 ; i < 6; i++) {
1146 ctx->Driver.ClipPlane( ctx, GL_CLIP_PLANE0 + i, NULL );
1147 }
1148
1149 ctx->Driver.Fogfv( ctx, GL_FOG_MODE, NULL );
1150 ctx->Driver.Fogfv( ctx, GL_FOG_DENSITY, &ctx->Fog.Density );
1151 ctx->Driver.Fogfv( ctx, GL_FOG_START, &ctx->Fog.Start );
1152 ctx->Driver.Fogfv( ctx, GL_FOG_END, &ctx->Fog.End );
1153 ctx->Driver.Fogfv( ctx, GL_FOG_COLOR, ctx->Fog.Color );
1154 ctx->Driver.Fogfv( ctx, GL_FOG_COORDINATE_SOURCE_EXT, NULL );
1155
1156 rmesa->hw.grd.cmd[GRD_VERT_GUARD_CLIP_ADJ] = IEEE_ONE;
1157 rmesa->hw.grd.cmd[GRD_VERT_GUARD_DISCARD_ADJ] = IEEE_ONE;
1158 rmesa->hw.grd.cmd[GRD_HORZ_GUARD_CLIP_ADJ] = IEEE_ONE;
1159 rmesa->hw.grd.cmd[GRD_HORZ_GUARD_DISCARD_ADJ] = IEEE_ONE;
1160
1161 rmesa->hw.eye.cmd[EYE_X] = 0;
1162 rmesa->hw.eye.cmd[EYE_Y] = 0;
1163 rmesa->hw.eye.cmd[EYE_Z] = IEEE_ONE;
1164 rmesa->hw.eye.cmd[EYE_RESCALE_FACTOR] = IEEE_ONE;
1165
1166 rmesa->hw.spr.cmd[SPR_POINT_SPRITE_CNTL] =
1167 R200_PS_SE_SEL_STATE | R200_PS_MULT_CONST;
1168
1169 /* ptp_eye is presumably used to calculate the attenuation wrt a different
1170 location? In any case, since point attenuation triggers _needeyecoords,
1171 it is constant. Probably ignored as long as R200_PS_USE_MODEL_EYE_VEC
1172 isn't set */
1173 rmesa->hw.ptp.cmd[PTP_EYE_X] = 0;
1174 rmesa->hw.ptp.cmd[PTP_EYE_Y] = 0;
1175 rmesa->hw.ptp.cmd[PTP_EYE_Z] = IEEE_ONE | 0x80000000; /* -1.0 */
1176 rmesa->hw.ptp.cmd[PTP_EYE_3] = 0;
1177 /* no idea what the ptp_vport_scale values are good for, except the
1178 PTSIZE one - hopefully doesn't matter */
1179 rmesa->hw.ptp.cmd[PTP_VPORT_SCALE_0] = IEEE_ONE;
1180 rmesa->hw.ptp.cmd[PTP_VPORT_SCALE_1] = IEEE_ONE;
1181 rmesa->hw.ptp.cmd[PTP_VPORT_SCALE_PTSIZE] = IEEE_ONE;
1182 rmesa->hw.ptp.cmd[PTP_VPORT_SCALE_3] = IEEE_ONE;
1183 rmesa->hw.ptp.cmd[PTP_ATT_CONST_QUAD] = 0;
1184 rmesa->hw.ptp.cmd[PTP_ATT_CONST_LIN] = 0;
1185 rmesa->hw.ptp.cmd[PTP_ATT_CONST_CON] = IEEE_ONE;
1186 rmesa->hw.ptp.cmd[PTP_ATT_CONST_3] = 0;
1187 rmesa->hw.ptp.cmd[PTP_CLAMP_MIN] = IEEE_ONE;
1188 rmesa->hw.ptp.cmd[PTP_CLAMP_MAX] = 0x44ffe000; /* 2047 */
1189 rmesa->hw.ptp.cmd[PTP_CLAMP_2] = 0;
1190 rmesa->hw.ptp.cmd[PTP_CLAMP_3] = 0;
1191
1192 r200LightingSpaceChange( ctx );
1193
1194 rmesa->hw.all_dirty = GL_TRUE;
1195
1196 rcommonInitCmdBuf(&rmesa->radeon, rmesa->hw.max_state_size);
1197 }