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r200: fix cubic emission.
[mesa.git] / src / mesa / drivers / dri / r200 / r200_state_init.c
1 /*
2 Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
3
4 The Weather Channel (TM) funded Tungsten Graphics to develop the
5 initial release of the Radeon 8500 driver under the XFree86 license.
6 This notice must be preserved.
7
8 Permission is hereby granted, free of charge, to any person obtaining
9 a copy of this software and associated documentation files (the
10 "Software"), to deal in the Software without restriction, including
11 without limitation the rights to use, copy, modify, merge, publish,
12 distribute, sublicense, and/or sell copies of the Software, and to
13 permit persons to whom the Software is furnished to do so, subject to
14 the following conditions:
15
16 The above copyright notice and this permission notice (including the
17 next paragraph) shall be included in all copies or substantial
18 portions of the Software.
19
20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 */
28
29 /*
30 * Authors:
31 * Keith Whitwell <keith@tungstengraphics.com>
32 */
33
34 #include "main/glheader.h"
35 #include "main/imports.h"
36 #include "main/enums.h"
37 #include "main/colormac.h"
38 #include "main/api_arrayelt.h"
39
40 #include "swrast/swrast.h"
41 #include "vbo/vbo.h"
42 #include "tnl/tnl.h"
43 #include "tnl/t_pipeline.h"
44 #include "swrast_setup/swrast_setup.h"
45
46 #include "radeon_common.h"
47 #include "radeon_mipmap_tree.h"
48 #include "r200_context.h"
49 #include "r200_ioctl.h"
50 #include "r200_state.h"
51 #include "r200_tcl.h"
52 #include "r200_tex.h"
53 #include "r200_swtcl.h"
54
55 #include "xmlpool.h"
56
57 /* New (1.3) state mechanism. 3 commands (packet, scalar, vector) in
58 * 1.3 cmdbuffers allow all previous state to be updated as well as
59 * the tcl scalar and vector areas.
60 */
61 static struct {
62 int start;
63 int len;
64 const char *name;
65 } packet[RADEON_MAX_STATE_PACKETS] = {
66 {RADEON_PP_MISC, 7, "RADEON_PP_MISC"},
67 {RADEON_PP_CNTL, 3, "RADEON_PP_CNTL"},
68 {RADEON_RB3D_COLORPITCH, 1, "RADEON_RB3D_COLORPITCH"},
69 {RADEON_RE_LINE_PATTERN, 2, "RADEON_RE_LINE_PATTERN"},
70 {RADEON_SE_LINE_WIDTH, 1, "RADEON_SE_LINE_WIDTH"},
71 {RADEON_PP_LUM_MATRIX, 1, "RADEON_PP_LUM_MATRIX"},
72 {RADEON_PP_ROT_MATRIX_0, 2, "RADEON_PP_ROT_MATRIX_0"},
73 {RADEON_RB3D_STENCILREFMASK, 3, "RADEON_RB3D_STENCILREFMASK"},
74 {RADEON_SE_VPORT_XSCALE, 6, "RADEON_SE_VPORT_XSCALE"},
75 {RADEON_SE_CNTL, 2, "RADEON_SE_CNTL"},
76 {RADEON_SE_CNTL_STATUS, 1, "RADEON_SE_CNTL_STATUS"},
77 {RADEON_RE_MISC, 1, "RADEON_RE_MISC"},
78 {RADEON_PP_TXFILTER_0, 6, "RADEON_PP_TXFILTER_0"},
79 {RADEON_PP_BORDER_COLOR_0, 1, "RADEON_PP_BORDER_COLOR_0"},
80 {RADEON_PP_TXFILTER_1, 6, "RADEON_PP_TXFILTER_1"},
81 {RADEON_PP_BORDER_COLOR_1, 1, "RADEON_PP_BORDER_COLOR_1"},
82 {RADEON_PP_TXFILTER_2, 6, "RADEON_PP_TXFILTER_2"},
83 {RADEON_PP_BORDER_COLOR_2, 1, "RADEON_PP_BORDER_COLOR_2"},
84 {RADEON_SE_ZBIAS_FACTOR, 2, "RADEON_SE_ZBIAS_FACTOR"},
85 {RADEON_SE_TCL_OUTPUT_VTX_FMT, 11, "RADEON_SE_TCL_OUTPUT_VTX_FMT"},
86 {RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED, 17,
87 "RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED"},
88 {R200_PP_TXCBLEND_0, 4, "R200_PP_TXCBLEND_0"},
89 {R200_PP_TXCBLEND_1, 4, "R200_PP_TXCBLEND_1"},
90 {R200_PP_TXCBLEND_2, 4, "R200_PP_TXCBLEND_2"},
91 {R200_PP_TXCBLEND_3, 4, "R200_PP_TXCBLEND_3"},
92 {R200_PP_TXCBLEND_4, 4, "R200_PP_TXCBLEND_4"},
93 {R200_PP_TXCBLEND_5, 4, "R200_PP_TXCBLEND_5"},
94 {R200_PP_TXCBLEND_6, 4, "R200_PP_TXCBLEND_6"},
95 {R200_PP_TXCBLEND_7, 4, "R200_PP_TXCBLEND_7"},
96 {R200_SE_TCL_LIGHT_MODEL_CTL_0, 6, "R200_SE_TCL_LIGHT_MODEL_CTL_0"},
97 {R200_PP_TFACTOR_0, 6, "R200_PP_TFACTOR_0"},
98 {R200_SE_VTX_FMT_0, 4, "R200_SE_VTX_FMT_0"},
99 {R200_SE_VAP_CNTL, 1, "R200_SE_VAP_CNTL"},
100 {R200_SE_TCL_MATRIX_SEL_0, 5, "R200_SE_TCL_MATRIX_SEL_0"},
101 {R200_SE_TCL_TEX_PROC_CTL_2, 5, "R200_SE_TCL_TEX_PROC_CTL_2"},
102 {R200_SE_TCL_UCP_VERT_BLEND_CTL, 1, "R200_SE_TCL_UCP_VERT_BLEND_CTL"},
103 {R200_PP_TXFILTER_0, 6, "R200_PP_TXFILTER_0"},
104 {R200_PP_TXFILTER_1, 6, "R200_PP_TXFILTER_1"},
105 {R200_PP_TXFILTER_2, 6, "R200_PP_TXFILTER_2"},
106 {R200_PP_TXFILTER_3, 6, "R200_PP_TXFILTER_3"},
107 {R200_PP_TXFILTER_4, 6, "R200_PP_TXFILTER_4"},
108 {R200_PP_TXFILTER_5, 6, "R200_PP_TXFILTER_5"},
109 {R200_PP_TXOFFSET_0, 1, "R200_PP_TXOFFSET_0"},
110 {R200_PP_TXOFFSET_1, 1, "R200_PP_TXOFFSET_1"},
111 {R200_PP_TXOFFSET_2, 1, "R200_PP_TXOFFSET_2"},
112 {R200_PP_TXOFFSET_3, 1, "R200_PP_TXOFFSET_3"},
113 {R200_PP_TXOFFSET_4, 1, "R200_PP_TXOFFSET_4"},
114 {R200_PP_TXOFFSET_5, 1, "R200_PP_TXOFFSET_5"},
115 {R200_SE_VTE_CNTL, 1, "R200_SE_VTE_CNTL"},
116 {R200_SE_TCL_OUTPUT_VTX_COMP_SEL, 1,
117 "R200_SE_TCL_OUTPUT_VTX_COMP_SEL"},
118 {R200_PP_TAM_DEBUG3, 1, "R200_PP_TAM_DEBUG3"},
119 {R200_PP_CNTL_X, 1, "R200_PP_CNTL_X"},
120 {R200_RB3D_DEPTHXY_OFFSET, 1, "R200_RB3D_DEPTHXY_OFFSET"},
121 {R200_RE_AUX_SCISSOR_CNTL, 1, "R200_RE_AUX_SCISSOR_CNTL"},
122 {R200_RE_SCISSOR_TL_0, 2, "R200_RE_SCISSOR_TL_0"},
123 {R200_RE_SCISSOR_TL_1, 2, "R200_RE_SCISSOR_TL_1"},
124 {R200_RE_SCISSOR_TL_2, 2, "R200_RE_SCISSOR_TL_2"},
125 {R200_SE_VAP_CNTL_STATUS, 1, "R200_SE_VAP_CNTL_STATUS"},
126 {R200_SE_VTX_STATE_CNTL, 1, "R200_SE_VTX_STATE_CNTL"},
127 {R200_RE_POINTSIZE, 1, "R200_RE_POINTSIZE"},
128 {R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0, 4,
129 "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0"},
130 {R200_PP_CUBIC_FACES_0, 1, "R200_PP_CUBIC_FACES_0"}, /* 61 */
131 {R200_PP_CUBIC_OFFSET_F1_0, 5, "R200_PP_CUBIC_OFFSET_F1_0"}, /* 62 */
132 {R200_PP_CUBIC_FACES_1, 1, "R200_PP_CUBIC_FACES_1"},
133 {R200_PP_CUBIC_OFFSET_F1_1, 5, "R200_PP_CUBIC_OFFSET_F1_1"},
134 {R200_PP_CUBIC_FACES_2, 1, "R200_PP_CUBIC_FACES_2"},
135 {R200_PP_CUBIC_OFFSET_F1_2, 5, "R200_PP_CUBIC_OFFSET_F1_2"},
136 {R200_PP_CUBIC_FACES_3, 1, "R200_PP_CUBIC_FACES_3"},
137 {R200_PP_CUBIC_OFFSET_F1_3, 5, "R200_PP_CUBIC_OFFSET_F1_3"},
138 {R200_PP_CUBIC_FACES_4, 1, "R200_PP_CUBIC_FACES_4"},
139 {R200_PP_CUBIC_OFFSET_F1_4, 5, "R200_PP_CUBIC_OFFSET_F1_4"},
140 {R200_PP_CUBIC_FACES_5, 1, "R200_PP_CUBIC_FACES_5"},
141 {R200_PP_CUBIC_OFFSET_F1_5, 5, "R200_PP_CUBIC_OFFSET_F1_5"},
142 {RADEON_PP_TEX_SIZE_0, 2, "RADEON_PP_TEX_SIZE_0"},
143 {RADEON_PP_TEX_SIZE_1, 2, "RADEON_PP_TEX_SIZE_1"},
144 {RADEON_PP_TEX_SIZE_2, 2, "RADEON_PP_TEX_SIZE_2"},
145 {R200_RB3D_BLENDCOLOR, 3, "R200_RB3D_BLENDCOLOR"},
146 {R200_SE_TCL_POINT_SPRITE_CNTL, 1, "R200_SE_TCL_POINT_SPRITE_CNTL"},
147 {RADEON_PP_CUBIC_FACES_0, 1, "RADEON_PP_CUBIC_FACES_0"},
148 {RADEON_PP_CUBIC_OFFSET_T0_0, 5, "RADEON_PP_CUBIC_OFFSET_T0_0"},
149 {RADEON_PP_CUBIC_FACES_1, 1, "RADEON_PP_CUBIC_FACES_1"},
150 {RADEON_PP_CUBIC_OFFSET_T1_0, 5, "RADEON_PP_CUBIC_OFFSET_T1_0"},
151 {RADEON_PP_CUBIC_FACES_2, 1, "RADEON_PP_CUBIC_FACES_2"},
152 {RADEON_PP_CUBIC_OFFSET_T2_0, 5, "RADEON_PP_CUBIC_OFFSET_T2_0"},
153 {R200_PP_TRI_PERF, 2, "R200_PP_TRI_PERF"},
154 {R200_PP_TXCBLEND_8, 32, "R200_PP_AFS_0"}, /* 85 */
155 {R200_PP_TXCBLEND_0, 32, "R200_PP_AFS_1"},
156 {R200_PP_TFACTOR_0, 8, "R200_ATF_TFACTOR"},
157 {R200_PP_TXFILTER_0, 8, "R200_PP_TXCTLALL_0"},
158 {R200_PP_TXFILTER_1, 8, "R200_PP_TXCTLALL_1"},
159 {R200_PP_TXFILTER_2, 8, "R200_PP_TXCTLALL_2"},
160 {R200_PP_TXFILTER_3, 8, "R200_PP_TXCTLALL_3"},
161 {R200_PP_TXFILTER_4, 8, "R200_PP_TXCTLALL_4"},
162 {R200_PP_TXFILTER_5, 8, "R200_PP_TXCTLALL_5"},
163 {R200_VAP_PVS_CNTL_1, 2, "R200_VAP_PVS_CNTL"},
164 };
165
166 /* =============================================================
167 * State initialization
168 */
169 static int cmdpkt( r200ContextPtr rmesa, int id )
170 {
171 drm_radeon_cmd_header_t h;
172
173 if (rmesa->radeon.radeonScreen->kernel_mm) {
174 return CP_PACKET0(packet[id].start, packet[id].len - 1);
175 } else {
176 h.i = 0;
177 h.packet.cmd_type = RADEON_CMD_PACKET;
178 h.packet.packet_id = id;
179 }
180 return h.i;
181 }
182
183 static int cmdvec( int offset, int stride, int count )
184 {
185 drm_radeon_cmd_header_t h;
186 h.i = 0;
187 h.vectors.cmd_type = RADEON_CMD_VECTORS;
188 h.vectors.offset = offset;
189 h.vectors.stride = stride;
190 h.vectors.count = count;
191 return h.i;
192 }
193
194 /* warning: the count here is divided by 4 compared to other cmds
195 (so it doesn't exceed the char size)! */
196 static int cmdveclinear( int offset, int count )
197 {
198 drm_radeon_cmd_header_t h;
199 h.i = 0;
200 h.veclinear.cmd_type = RADEON_CMD_VECLINEAR;
201 h.veclinear.addr_lo = offset & 0xff;
202 h.veclinear.addr_hi = (offset & 0xff00) >> 8;
203 h.veclinear.count = count;
204 return h.i;
205 }
206
207 static int cmdscl( int offset, int stride, int count )
208 {
209 drm_radeon_cmd_header_t h;
210 h.i = 0;
211 h.scalars.cmd_type = RADEON_CMD_SCALARS;
212 h.scalars.offset = offset;
213 h.scalars.stride = stride;
214 h.scalars.count = count;
215 return h.i;
216 }
217
218 static int cmdscl2( int offset, int stride, int count )
219 {
220 drm_radeon_cmd_header_t h;
221 h.i = 0;
222 h.scalars.cmd_type = RADEON_CMD_SCALARS2;
223 h.scalars.offset = offset - 0x100;
224 h.scalars.stride = stride;
225 h.scalars.count = count;
226 return h.i;
227 }
228
229 #define CHECK( NM, FLAG ) \
230 static int check_##NM( GLcontext *ctx, struct radeon_state_atom *atom) \
231 { \
232 r200ContextPtr rmesa = R200_CONTEXT(ctx); \
233 (void) rmesa; \
234 return (FLAG) ? atom->cmd_size : 0; \
235 }
236
237 #define TCL_CHECK( NM, FLAG ) \
238 static int check_##NM( GLcontext *ctx, struct radeon_state_atom *atom) \
239 { \
240 r200ContextPtr rmesa = R200_CONTEXT(ctx); \
241 return (!rmesa->radeon.TclFallback && !ctx->VertexProgram._Enabled && (FLAG)) ? atom->cmd_size : 0; \
242 }
243
244 #define TCL_OR_VP_CHECK( NM, FLAG ) \
245 static int check_##NM( GLcontext *ctx, struct radeon_state_atom *atom ) \
246 { \
247 r200ContextPtr rmesa = R200_CONTEXT(ctx); \
248 return (!rmesa->radeon.TclFallback && (FLAG)) ? atom->cmd_size : 0; \
249 }
250
251 #define VP_CHECK( NM, FLAG ) \
252 static int check_##NM( GLcontext *ctx, struct radeon_state_atom *atom ) \
253 { \
254 r200ContextPtr rmesa = R200_CONTEXT(ctx); \
255 (void) atom; \
256 return (!rmesa->radeon.TclFallback && ctx->VertexProgram._Enabled && (FLAG)) ? atom->cmd_size : 0; \
257 }
258
259 CHECK( always, GL_TRUE )
260 CHECK( never, GL_FALSE )
261 CHECK( tex_any, ctx->Texture._EnabledUnits )
262 CHECK( tf, (ctx->Texture._EnabledUnits && !ctx->ATIFragmentShader._Enabled) );
263 CHECK( tex_pair, (rmesa->state.texture.unit[atom->idx].unitneeded | rmesa->state.texture.unit[atom->idx & ~1].unitneeded) )
264 CHECK( tex, rmesa->state.texture.unit[atom->idx].unitneeded )
265 CHECK( pix_zero, !ctx->ATIFragmentShader._Enabled )
266 CHECK( texenv, (rmesa->state.envneeded & (1 << (atom->idx)) && !ctx->ATIFragmentShader._Enabled) )
267 CHECK( afs_pass1, (ctx->ATIFragmentShader._Enabled && (ctx->ATIFragmentShader.Current->NumPasses > 1)) )
268 CHECK( afs, ctx->ATIFragmentShader._Enabled )
269 CHECK( tex_cube, rmesa->state.texture.unit[atom->idx].unitneeded & TEXTURE_CUBE_BIT )
270 TCL_CHECK( tcl_fog, ctx->Fog.Enabled )
271 TCL_CHECK( tcl, GL_TRUE )
272 TCL_CHECK( tcl_tex, rmesa->state.texture.unit[atom->idx].unitneeded )
273 TCL_CHECK( tcl_lighting, ctx->Light.Enabled )
274 TCL_CHECK( tcl_light, ctx->Light.Enabled && ctx->Light.Light[atom->idx].Enabled )
275 TCL_OR_VP_CHECK( tcl_ucp, (ctx->Transform.ClipPlanesEnabled & (1 << (atom->idx))) )
276 TCL_OR_VP_CHECK( tcl_or_vp, GL_TRUE )
277 VP_CHECK( tcl_vp, GL_TRUE )
278 VP_CHECK( tcl_vp_size, ctx->VertexProgram.Current->Base.NumNativeInstructions > 64 )
279 VP_CHECK( tcl_vpp_size, ctx->VertexProgram.Current->Base.NumNativeParameters > 96 )
280
281 #define OUT_VEC(hdr, data) do { \
282 drm_radeon_cmd_header_t h; \
283 h.i = hdr; \
284 OUT_BATCH(CP_PACKET0(RADEON_SE_TCL_STATE_FLUSH, 0)); \
285 OUT_BATCH(0); \
286 OUT_BATCH(CP_PACKET0(R200_SE_TCL_VECTOR_INDX_REG, 0)); \
287 OUT_BATCH(h.vectors.offset | (h.vectors.stride << RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT)); \
288 OUT_BATCH(CP_PACKET0_ONE(R200_SE_TCL_VECTOR_DATA_REG, h.vectors.count - 1)); \
289 OUT_BATCH_TABLE((data), h.vectors.count); \
290 } while(0)
291
292 #define OUT_VECLINEAR(hdr, data) do { \
293 drm_radeon_cmd_header_t h; \
294 uint32_t _start, _sz; \
295 h.i = hdr; \
296 _start = h.veclinear.addr_lo | (h.veclinear.addr_hi << 8); \
297 _sz = h.veclinear.count * 4; \
298 OUT_BATCH(CP_PACKET0(RADEON_SE_TCL_STATE_FLUSH, 0)); \
299 OUT_BATCH(0); \
300 OUT_BATCH(CP_PACKET0(R200_SE_TCL_VECTOR_INDX_REG, 0)); \
301 OUT_BATCH(_start | (1 << RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT)); \
302 OUT_BATCH(CP_PACKET0_ONE(R200_SE_TCL_VECTOR_DATA_REG, _sz - 1)); \
303 OUT_BATCH_TABLE((data), _sz); \
304 } while(0)
305
306 #define OUT_SCL(hdr, data) do { \
307 drm_radeon_cmd_header_t h; \
308 h.i = hdr; \
309 OUT_BATCH(CP_PACKET0(R200_SE_TCL_SCALAR_INDX_REG, 0)); \
310 OUT_BATCH((h.scalars.offset) | (h.scalars.stride << RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT)); \
311 OUT_BATCH(CP_PACKET0_ONE(R200_SE_TCL_SCALAR_DATA_REG, h.scalars.count - 1)); \
312 OUT_BATCH_TABLE((data), h.scalars.count); \
313 } while(0)
314
315 #define OUT_SCL2(hdr, data) do { \
316 drm_radeon_cmd_header_t h; \
317 h.i = hdr; \
318 OUT_BATCH(CP_PACKET0(R200_SE_TCL_SCALAR_INDX_REG, 0)); \
319 OUT_BATCH((h.scalars.offset + 0x100) | (h.scalars.stride << RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT)); \
320 OUT_BATCH(CP_PACKET0_ONE(R200_SE_TCL_SCALAR_DATA_REG, h.scalars.count - 1)); \
321 OUT_BATCH_TABLE((data), h.scalars.count); \
322 } while(0)
323
324 static void mtl_emit(GLcontext *ctx, struct radeon_state_atom *atom)
325 {
326 r200ContextPtr r200 = R200_CONTEXT(ctx);
327 BATCH_LOCALS(&r200->radeon);
328 uint32_t dwords = atom->cmd_size;
329
330 dwords += 6;
331 BEGIN_BATCH_NO_AUTOSTATE(dwords);
332 OUT_VEC(atom->cmd[MTL_CMD_0], (atom->cmd+1));
333 OUT_SCL2(atom->cmd[MTL_CMD_1], (atom->cmd + 18));
334 END_BATCH();
335 }
336
337 static void lit_emit(GLcontext *ctx, struct radeon_state_atom *atom)
338 {
339 r200ContextPtr r200 = R200_CONTEXT(ctx);
340 BATCH_LOCALS(&r200->radeon);
341 uint32_t dwords = atom->cmd_size;
342
343 dwords += 8;
344 BEGIN_BATCH_NO_AUTOSTATE(dwords);
345 OUT_VEC(atom->cmd[LIT_CMD_0], atom->cmd+1);
346 OUT_VEC(atom->cmd[LIT_CMD_1], atom->cmd+LIT_CMD_1+1);
347 END_BATCH();
348 }
349
350 static void ptp_emit(GLcontext *ctx, struct radeon_state_atom *atom)
351 {
352 r200ContextPtr r200 = R200_CONTEXT(ctx);
353 BATCH_LOCALS(&r200->radeon);
354 uint32_t dwords = atom->cmd_size;
355
356 dwords += 8;
357 BEGIN_BATCH_NO_AUTOSTATE(dwords);
358 OUT_VEC(atom->cmd[PTP_CMD_0], atom->cmd+1);
359 OUT_VEC(atom->cmd[PTP_CMD_1], atom->cmd+PTP_CMD_1+1);
360 END_BATCH();
361 }
362
363 static void veclinear_emit(GLcontext *ctx, struct radeon_state_atom *atom)
364 {
365 r200ContextPtr r200 = R200_CONTEXT(ctx);
366 BATCH_LOCALS(&r200->radeon);
367 uint32_t dwords = atom->cmd_size;
368
369 dwords += 4;
370 BEGIN_BATCH_NO_AUTOSTATE(dwords);
371 OUT_VECLINEAR(atom->cmd[0], atom->cmd+1);
372 END_BATCH();
373 }
374
375 static void scl_emit(GLcontext *ctx, struct radeon_state_atom *atom)
376 {
377 r200ContextPtr r200 = R200_CONTEXT(ctx);
378 BATCH_LOCALS(&r200->radeon);
379 uint32_t dwords = atom->cmd_size;
380
381 dwords += 2;
382 BEGIN_BATCH_NO_AUTOSTATE(dwords);
383 OUT_SCL(atom->cmd[0], atom->cmd+1);
384 END_BATCH();
385 }
386
387
388 static void vec_emit(GLcontext *ctx, struct radeon_state_atom *atom)
389 {
390 r200ContextPtr r200 = R200_CONTEXT(ctx);
391 BATCH_LOCALS(&r200->radeon);
392 uint32_t dwords = atom->cmd_size;
393
394 dwords += 4;
395 BEGIN_BATCH_NO_AUTOSTATE(dwords);
396 OUT_VEC(atom->cmd[0], atom->cmd+1);
397 END_BATCH();
398 }
399
400 static void ctx_emit(GLcontext *ctx, struct radeon_state_atom *atom)
401 {
402 r200ContextPtr r200 = R200_CONTEXT(ctx);
403 BATCH_LOCALS(&r200->radeon);
404 struct radeon_renderbuffer *rrb;
405 uint32_t cbpitch;
406 uint32_t zbpitch, depth_fmt;
407 uint32_t dwords = atom->cmd_size;
408
409 /* output the first 7 bytes of context */
410 BEGIN_BATCH_NO_AUTOSTATE(dwords+2+2);
411 OUT_BATCH_TABLE(atom->cmd, 5);
412
413 rrb = radeon_get_depthbuffer(&r200->radeon);
414 if (!rrb) {
415 OUT_BATCH(0);
416 OUT_BATCH(0);
417 } else {
418 zbpitch = (rrb->pitch / rrb->cpp);
419 if (r200->using_hyperz)
420 zbpitch |= RADEON_DEPTH_HYPERZ;
421 OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
422 OUT_BATCH(zbpitch);
423 if (rrb->cpp == 4)
424 depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
425 else
426 depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
427 atom->cmd[CTX_RB3D_ZSTENCILCNTL] &= ~RADEON_DEPTH_FORMAT_MASK;
428 atom->cmd[CTX_RB3D_ZSTENCILCNTL] |= depth_fmt;
429 }
430
431 OUT_BATCH(atom->cmd[CTX_RB3D_ZSTENCILCNTL]);
432 OUT_BATCH(atom->cmd[CTX_CMD_1]);
433 OUT_BATCH(atom->cmd[CTX_PP_CNTL]);
434
435 rrb = radeon_get_colorbuffer(&r200->radeon);
436 if (!rrb || !rrb->bo) {
437 OUT_BATCH(atom->cmd[CTX_RB3D_CNTL]);
438 OUT_BATCH(atom->cmd[CTX_RB3D_COLOROFFSET]);
439 } else {
440 atom->cmd[CTX_RB3D_CNTL] &= ~(0xf << 10);
441 if (rrb->cpp == 4)
442 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB8888;
443 else
444 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_RGB565;
445
446 OUT_BATCH(atom->cmd[CTX_RB3D_CNTL]);
447 OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
448 }
449
450 OUT_BATCH(atom->cmd[CTX_CMD_2]);
451
452 if (!rrb || !rrb->bo) {
453 OUT_BATCH(atom->cmd[CTX_RB3D_COLORPITCH]);
454 } else {
455 cbpitch = (rrb->pitch / rrb->cpp);
456 if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE)
457 cbpitch |= R200_COLOR_TILE_ENABLE;
458 OUT_BATCH(cbpitch);
459 }
460
461 if (atom->cmd_size == CTX_STATE_SIZE_NEWDRM)
462 OUT_BATCH_TABLE((atom->cmd + 14), 4);
463
464 END_BATCH();
465 }
466
467 static void ctx_emit_cs(GLcontext *ctx, struct radeon_state_atom *atom)
468 {
469 r200ContextPtr r200 = R200_CONTEXT(ctx);
470 BATCH_LOCALS(&r200->radeon);
471 struct radeon_renderbuffer *rrb, *drb;
472 uint32_t cbpitch = 0;
473 uint32_t zbpitch = 0;
474 uint32_t dwords = atom->cmd_size;
475 uint32_t depth_fmt;
476
477 rrb = radeon_get_colorbuffer(&r200->radeon);
478 if (!rrb || !rrb->bo) {
479 return;
480 }
481
482 atom->cmd[CTX_RB3D_CNTL] &= ~(0xf << 10);
483 if (rrb->cpp == 4)
484 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB8888;
485 else
486 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_RGB565;
487
488 cbpitch = (rrb->pitch / rrb->cpp);
489 if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE)
490 cbpitch |= R200_COLOR_TILE_ENABLE;
491
492 drb = radeon_get_depthbuffer(&r200->radeon);
493 if (drb) {
494 zbpitch = (drb->pitch / drb->cpp);
495 if (drb->cpp == 4)
496 depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
497 else
498 depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
499 atom->cmd[CTX_RB3D_ZSTENCILCNTL] &= ~RADEON_DEPTH_FORMAT_MASK;
500 atom->cmd[CTX_RB3D_ZSTENCILCNTL] |= depth_fmt;
501 }
502
503 dwords = 10;
504 if (drb)
505 dwords += 6;
506 if (rrb)
507 dwords += 6;
508 if (atom->cmd_size == CTX_STATE_SIZE_NEWDRM)
509 dwords += 4;
510
511 /* output the first 7 bytes of context */
512 BEGIN_BATCH_NO_AUTOSTATE(dwords);
513
514 /* In the CS case we need to split this up */
515 OUT_BATCH(CP_PACKET0(packet[0].start, 3));
516 OUT_BATCH_TABLE((atom->cmd + 1), 4);
517
518 if (drb) {
519 OUT_BATCH(CP_PACKET0(RADEON_RB3D_DEPTHOFFSET, 0));
520 OUT_BATCH_RELOC(0, drb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
521
522 OUT_BATCH(CP_PACKET0(RADEON_RB3D_DEPTHPITCH, 0));
523 OUT_BATCH(zbpitch);
524 }
525
526 OUT_BATCH(CP_PACKET0(RADEON_RB3D_ZSTENCILCNTL, 0));
527 OUT_BATCH(atom->cmd[CTX_RB3D_ZSTENCILCNTL]);
528 OUT_BATCH(CP_PACKET0(RADEON_PP_CNTL, 1));
529 OUT_BATCH(atom->cmd[CTX_PP_CNTL]);
530 OUT_BATCH(atom->cmd[CTX_RB3D_CNTL]);
531
532
533 if (rrb) {
534 OUT_BATCH(CP_PACKET0(RADEON_RB3D_COLOROFFSET, 0));
535 OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
536
537 OUT_BATCH(CP_PACKET0(RADEON_RB3D_COLORPITCH, 0));
538 OUT_BATCH(cbpitch);
539 }
540
541 if (atom->cmd_size == CTX_STATE_SIZE_NEWDRM) {
542 OUT_BATCH_TABLE((atom->cmd + 14), 4);
543 }
544
545 END_BATCH();
546 }
547
548 static void tex_emit(GLcontext *ctx, struct radeon_state_atom *atom)
549 {
550 r200ContextPtr r200 = R200_CONTEXT(ctx);
551 BATCH_LOCALS(&r200->radeon);
552 uint32_t dwords = atom->cmd_size;
553 int i = atom->idx;
554 radeonTexObj *t = r200->state.texture.unit[i].texobj;
555 radeon_mipmap_level *lvl;
556
557 if (t && t->mt && !t->image_override)
558 dwords += 2;
559 BEGIN_BATCH_NO_AUTOSTATE(dwords);
560 /* is this ok even with drm older than 1.18? */
561 OUT_BATCH_TABLE(atom->cmd, 10);
562
563 if (t && t->mt && !t->image_override) {
564 OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, 0,
565 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
566 } else if (!t) {
567 /* workaround for old CS mechanism */
568 OUT_BATCH(r200->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP]);
569 } else {
570 OUT_BATCH(t->override_offset);
571 }
572
573 END_BATCH();
574 }
575
576 static void tex_emit_cs(GLcontext *ctx, struct radeon_state_atom *atom)
577 {
578 r200ContextPtr r200 = R200_CONTEXT(ctx);
579 BATCH_LOCALS(&r200->radeon);
580 uint32_t dwords = atom->cmd_size;
581 int i = atom->idx;
582 radeonTexObj *t = r200->state.texture.unit[i].texobj;
583 radeon_mipmap_level *lvl;
584 int hastexture = 1;
585
586 if (!t)
587 hastexture = 0;
588 else {
589 if (!t->mt && !t->bo)
590 hastexture = 0;
591 }
592
593 if (hastexture)
594 dwords += 2;
595 else
596 dwords -= 2;
597 BEGIN_BATCH_NO_AUTOSTATE(dwords);
598
599 OUT_BATCH(CP_PACKET0(R200_PP_TXFILTER_0 + (24 * i), 7));
600 OUT_BATCH_TABLE((atom->cmd + 1), 8);
601
602 if (hastexture) {
603 OUT_BATCH(CP_PACKET0(R200_PP_TXOFFSET_0 + (24 * i), 0));
604 if (t->mt && !t->image_override) {
605 OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, 0,
606 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
607 } else {
608 if (t->bo)
609 OUT_BATCH_RELOC(t->tile_bits, t->bo, 0,
610 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
611 }
612 }
613 END_BATCH();
614 }
615
616
617 static void cube_emit(GLcontext *ctx, struct radeon_state_atom *atom)
618 {
619 r200ContextPtr r200 = R200_CONTEXT(ctx);
620 BATCH_LOCALS(&r200->radeon);
621 uint32_t dwords = 2;
622 int i = atom->idx, j;
623 radeonTexObj *t = r200->state.texture.unit[i].texobj;
624 radeon_mipmap_level *lvl;
625
626 BEGIN_BATCH_NO_AUTOSTATE(dwords + (4 * 5));
627 OUT_BATCH_TABLE(atom->cmd, 2);
628
629 if (t && !t->image_override) {
630 lvl = &t->mt->levels[0];
631 for (j = 1; j <= 5; j++) {
632 OUT_BATCH(CP_PACKET0(R200_PP_CUBIC_OFFSET_F1_0 + (24*i) + (4 * (j-1)), 0));
633 OUT_BATCH_RELOC(lvl->faces[j].offset, t->mt->bo, lvl->faces[j].offset,
634 RADEON_GEM_DOMAIN_VRAM, 0, 0);
635 }
636 }
637 END_BATCH();
638 }
639
640 /* Initialize the context's hardware state.
641 */
642 void r200InitState( r200ContextPtr rmesa )
643 {
644 GLcontext *ctx = rmesa->radeon.glCtx;
645 GLuint i;
646
647 rmesa->radeon.state.color.clear = 0x00000000;
648
649 switch ( ctx->Visual.depthBits ) {
650 case 16:
651 rmesa->radeon.state.depth.clear = 0x0000ffff;
652 rmesa->radeon.state.stencil.clear = 0x00000000;
653 break;
654 case 24:
655 default:
656 rmesa->radeon.state.depth.clear = 0x00ffffff;
657 rmesa->radeon.state.stencil.clear = 0xffff0000;
658 break;
659 }
660
661 rmesa->radeon.Fallback = 0;
662
663 rmesa->radeon.hw.max_state_size = 0;
664
665 #define ALLOC_STATE( ATOM, CHK, SZ, NM, IDX ) \
666 do { \
667 rmesa->hw.ATOM.cmd_size = SZ; \
668 rmesa->hw.ATOM.cmd = (GLuint *)CALLOC(SZ * sizeof(int)); \
669 rmesa->hw.ATOM.lastcmd = (GLuint *)CALLOC(SZ * sizeof(int)); \
670 rmesa->hw.ATOM.name = NM; \
671 rmesa->hw.ATOM.idx = IDX; \
672 rmesa->hw.ATOM.check = check_##CHK; \
673 rmesa->hw.ATOM.dirty = GL_FALSE; \
674 rmesa->radeon.hw.max_state_size += SZ * sizeof(int); \
675 } while (0)
676
677
678 /* Allocate state buffers:
679 */
680 if (rmesa->radeon.radeonScreen->drmSupportsBlendColor)
681 ALLOC_STATE( ctx, always, CTX_STATE_SIZE_NEWDRM, "CTX/context", 0 );
682 else
683 ALLOC_STATE( ctx, always, CTX_STATE_SIZE_OLDDRM, "CTX/context", 0 );
684
685 if (rmesa->radeon.radeonScreen->kernel_mm)
686 rmesa->hw.ctx.emit = ctx_emit_cs;
687 else
688 rmesa->hw.ctx.emit = ctx_emit;
689 ALLOC_STATE( set, always, SET_STATE_SIZE, "SET/setup", 0 );
690 ALLOC_STATE( lin, always, LIN_STATE_SIZE, "LIN/line", 0 );
691 ALLOC_STATE( msk, always, MSK_STATE_SIZE, "MSK/mask", 0 );
692 ALLOC_STATE( vpt, always, VPT_STATE_SIZE, "VPT/viewport", 0 );
693 ALLOC_STATE( vtx, always, VTX_STATE_SIZE, "VTX/vertex", 0 );
694 ALLOC_STATE( vap, always, VAP_STATE_SIZE, "VAP/vap", 0 );
695 ALLOC_STATE( vte, always, VTE_STATE_SIZE, "VTE/vte", 0 );
696 ALLOC_STATE( msc, always, MSC_STATE_SIZE, "MSC/misc", 0 );
697 ALLOC_STATE( cst, always, CST_STATE_SIZE, "CST/constant", 0 );
698 ALLOC_STATE( zbs, always, ZBS_STATE_SIZE, "ZBS/zbias", 0 );
699 ALLOC_STATE( tf, tf, TF_STATE_SIZE, "TF/tfactor", 0 );
700 if (rmesa->radeon.radeonScreen->drmSupportsFragShader) {
701 if (rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_R200) {
702 /* make sure texture units 0/1 are emitted pair-wise for r200 t0 hang workaround */
703 ALLOC_STATE( tex[0], tex_pair, TEX_STATE_SIZE_NEWDRM, "TEX/tex-0", 0 );
704 ALLOC_STATE( tex[1], tex_pair, TEX_STATE_SIZE_NEWDRM, "TEX/tex-1", 1 );
705 ALLOC_STATE( tam, tex_any, TAM_STATE_SIZE, "TAM/tam", 0 );
706 }
707 else {
708 ALLOC_STATE( tex[0], tex, TEX_STATE_SIZE_NEWDRM, "TEX/tex-0", 0 );
709 ALLOC_STATE( tex[1], tex, TEX_STATE_SIZE_NEWDRM, "TEX/tex-1", 1 );
710 ALLOC_STATE( tam, never, TAM_STATE_SIZE, "TAM/tam", 0 );
711 }
712 ALLOC_STATE( tex[2], tex, TEX_STATE_SIZE_NEWDRM, "TEX/tex-2", 2 );
713 ALLOC_STATE( tex[3], tex, TEX_STATE_SIZE_NEWDRM, "TEX/tex-3", 3 );
714 ALLOC_STATE( tex[4], tex, TEX_STATE_SIZE_NEWDRM, "TEX/tex-4", 4 );
715 ALLOC_STATE( tex[5], tex, TEX_STATE_SIZE_NEWDRM, "TEX/tex-5", 5 );
716 ALLOC_STATE( atf, afs, ATF_STATE_SIZE, "ATF/tfactor", 0 );
717 ALLOC_STATE( afs[0], afs_pass1, AFS_STATE_SIZE, "AFS/afsinst-0", 0 );
718 ALLOC_STATE( afs[1], afs, AFS_STATE_SIZE, "AFS/afsinst-1", 1 );
719 }
720 else {
721 if (rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_R200) {
722 ALLOC_STATE( tex[0], tex_pair, TEX_STATE_SIZE_OLDDRM, "TEX/tex-0", 0 );
723 ALLOC_STATE( tex[1], tex_pair, TEX_STATE_SIZE_OLDDRM, "TEX/tex-1", 1 );
724 ALLOC_STATE( tam, tex_any, TAM_STATE_SIZE, "TAM/tam", 0 );
725 }
726 else {
727 ALLOC_STATE( tex[0], tex, TEX_STATE_SIZE_OLDDRM, "TEX/tex-0", 0 );
728 ALLOC_STATE( tex[1], tex, TEX_STATE_SIZE_OLDDRM, "TEX/tex-1", 1 );
729 ALLOC_STATE( tam, never, TAM_STATE_SIZE, "TAM/tam", 0 );
730 }
731 ALLOC_STATE( tex[2], tex, TEX_STATE_SIZE_OLDDRM, "TEX/tex-2", 2 );
732 ALLOC_STATE( tex[3], tex, TEX_STATE_SIZE_OLDDRM, "TEX/tex-3", 3 );
733 ALLOC_STATE( tex[4], tex, TEX_STATE_SIZE_OLDDRM, "TEX/tex-4", 4 );
734 ALLOC_STATE( tex[5], tex, TEX_STATE_SIZE_OLDDRM, "TEX/tex-5", 5 );
735 ALLOC_STATE( atf, never, ATF_STATE_SIZE, "TF/tfactor", 0 );
736 ALLOC_STATE( afs[0], never, AFS_STATE_SIZE, "AFS/afsinst-0", 0 );
737 ALLOC_STATE( afs[1], never, AFS_STATE_SIZE, "AFS/afsinst-1", 1 );
738 }
739
740 for (i = 0; i < 5; i++)
741 if (rmesa->radeon.radeonScreen->kernel_mm)
742 rmesa->hw.tex[i].emit = tex_emit_cs;
743 else
744 rmesa->hw.tex[i].emit = tex_emit;
745 if (rmesa->radeon.radeonScreen->drmSupportsCubeMapsR200) {
746 ALLOC_STATE( cube[0], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-0", 0 );
747 ALLOC_STATE( cube[1], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-1", 1 );
748 ALLOC_STATE( cube[2], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-2", 2 );
749 ALLOC_STATE( cube[3], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-3", 3 );
750 ALLOC_STATE( cube[4], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-4", 4 );
751 ALLOC_STATE( cube[5], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-5", 5 );
752 for (i = 0; i < 5; i++)
753 rmesa->hw.cube[i].emit = cube_emit;
754 }
755 else {
756 ALLOC_STATE( cube[0], never, CUBE_STATE_SIZE, "CUBE/tex-0", 0 );
757 ALLOC_STATE( cube[1], never, CUBE_STATE_SIZE, "CUBE/tex-1", 1 );
758 ALLOC_STATE( cube[2], never, CUBE_STATE_SIZE, "CUBE/tex-2", 2 );
759 ALLOC_STATE( cube[3], never, CUBE_STATE_SIZE, "CUBE/tex-3", 3 );
760 ALLOC_STATE( cube[4], never, CUBE_STATE_SIZE, "CUBE/tex-4", 4 );
761 ALLOC_STATE( cube[5], never, CUBE_STATE_SIZE, "CUBE/tex-5", 5 );
762 }
763
764 if (rmesa->radeon.radeonScreen->drmSupportsVertexProgram) {
765 ALLOC_STATE( pvs, tcl_vp, PVS_STATE_SIZE, "PVS/pvscntl", 0 );
766 ALLOC_STATE( vpi[0], tcl_vp, VPI_STATE_SIZE, "VP/vertexprog-0", 0 );
767 ALLOC_STATE( vpi[1], tcl_vp_size, VPI_STATE_SIZE, "VP/vertexprog-1", 1 );
768 ALLOC_STATE( vpp[0], tcl_vp, VPP_STATE_SIZE, "VPP/vertexparam-0", 0 );
769 ALLOC_STATE( vpp[1], tcl_vpp_size, VPP_STATE_SIZE, "VPP/vertexparam-1", 1 );
770 }
771 else {
772 ALLOC_STATE( pvs, never, PVS_STATE_SIZE, "PVS/pvscntl", 0 );
773 ALLOC_STATE( vpi[0], never, VPI_STATE_SIZE, "VP/vertexprog-0", 0 );
774 ALLOC_STATE( vpi[1], never, VPI_STATE_SIZE, "VP/vertexprog-1", 1 );
775 ALLOC_STATE( vpp[0], never, VPP_STATE_SIZE, "VPP/vertexparam-0", 0 );
776 ALLOC_STATE( vpp[1], never, VPP_STATE_SIZE, "VPP/vertexparam-1", 1 );
777 }
778 /* FIXME: this atom has two commands, we need only one (ucp_vert_blend) for vp */
779 ALLOC_STATE( tcl, tcl_or_vp, TCL_STATE_SIZE, "TCL/tcl", 0 );
780 ALLOC_STATE( msl, tcl, MSL_STATE_SIZE, "MSL/matrix-select", 0 );
781 ALLOC_STATE( tcg, tcl, TCG_STATE_SIZE, "TCG/texcoordgen", 0 );
782 ALLOC_STATE( mtl[0], tcl_lighting, MTL_STATE_SIZE, "MTL0/material0", 0 );
783 ALLOC_STATE( mtl[1], tcl_lighting, MTL_STATE_SIZE, "MTL1/material1", 1 );
784 ALLOC_STATE( grd, tcl_or_vp, GRD_STATE_SIZE, "GRD/guard-band", 0 );
785 ALLOC_STATE( fog, tcl_fog, FOG_STATE_SIZE, "FOG/fog", 0 );
786 ALLOC_STATE( glt, tcl_lighting, GLT_STATE_SIZE, "GLT/light-global", 0 );
787 ALLOC_STATE( eye, tcl_lighting, EYE_STATE_SIZE, "EYE/eye-vector", 0 );
788 ALLOC_STATE( mat[R200_MTX_MV], tcl, MAT_STATE_SIZE, "MAT/modelview", 0 );
789 ALLOC_STATE( mat[R200_MTX_IMV], tcl, MAT_STATE_SIZE, "MAT/it-modelview", 0 );
790 ALLOC_STATE( mat[R200_MTX_MVP], tcl, MAT_STATE_SIZE, "MAT/modelproject", 0 );
791 ALLOC_STATE( mat[R200_MTX_TEX0], tcl_tex, MAT_STATE_SIZE, "MAT/texmat0", 0 );
792 ALLOC_STATE( mat[R200_MTX_TEX1], tcl_tex, MAT_STATE_SIZE, "MAT/texmat1", 1 );
793 ALLOC_STATE( mat[R200_MTX_TEX2], tcl_tex, MAT_STATE_SIZE, "MAT/texmat2", 2 );
794 ALLOC_STATE( mat[R200_MTX_TEX3], tcl_tex, MAT_STATE_SIZE, "MAT/texmat3", 3 );
795 ALLOC_STATE( mat[R200_MTX_TEX4], tcl_tex, MAT_STATE_SIZE, "MAT/texmat4", 4 );
796 ALLOC_STATE( mat[R200_MTX_TEX5], tcl_tex, MAT_STATE_SIZE, "MAT/texmat5", 5 );
797 ALLOC_STATE( ucp[0], tcl_ucp, UCP_STATE_SIZE, "UCP/userclip-0", 0 );
798 ALLOC_STATE( ucp[1], tcl_ucp, UCP_STATE_SIZE, "UCP/userclip-1", 1 );
799 ALLOC_STATE( ucp[2], tcl_ucp, UCP_STATE_SIZE, "UCP/userclip-2", 2 );
800 ALLOC_STATE( ucp[3], tcl_ucp, UCP_STATE_SIZE, "UCP/userclip-3", 3 );
801 ALLOC_STATE( ucp[4], tcl_ucp, UCP_STATE_SIZE, "UCP/userclip-4", 4 );
802 ALLOC_STATE( ucp[5], tcl_ucp, UCP_STATE_SIZE, "UCP/userclip-5", 5 );
803 ALLOC_STATE( lit[0], tcl_light, LIT_STATE_SIZE, "LIT/light-0", 0 );
804 ALLOC_STATE( lit[1], tcl_light, LIT_STATE_SIZE, "LIT/light-1", 1 );
805 ALLOC_STATE( lit[2], tcl_light, LIT_STATE_SIZE, "LIT/light-2", 2 );
806 ALLOC_STATE( lit[3], tcl_light, LIT_STATE_SIZE, "LIT/light-3", 3 );
807 ALLOC_STATE( lit[4], tcl_light, LIT_STATE_SIZE, "LIT/light-4", 4 );
808 ALLOC_STATE( lit[5], tcl_light, LIT_STATE_SIZE, "LIT/light-5", 5 );
809 ALLOC_STATE( lit[6], tcl_light, LIT_STATE_SIZE, "LIT/light-6", 6 );
810 ALLOC_STATE( lit[7], tcl_light, LIT_STATE_SIZE, "LIT/light-7", 7 );
811 ALLOC_STATE( pix[0], pix_zero, PIX_STATE_SIZE, "PIX/pixstage-0", 0 );
812 ALLOC_STATE( pix[1], texenv, PIX_STATE_SIZE, "PIX/pixstage-1", 1 );
813 ALLOC_STATE( pix[2], texenv, PIX_STATE_SIZE, "PIX/pixstage-2", 2 );
814 ALLOC_STATE( pix[3], texenv, PIX_STATE_SIZE, "PIX/pixstage-3", 3 );
815 ALLOC_STATE( pix[4], texenv, PIX_STATE_SIZE, "PIX/pixstage-4", 4 );
816 ALLOC_STATE( pix[5], texenv, PIX_STATE_SIZE, "PIX/pixstage-5", 5 );
817 if (rmesa->radeon.radeonScreen->drmSupportsTriPerf) {
818 ALLOC_STATE( prf, always, PRF_STATE_SIZE, "PRF/performance-tri", 0 );
819 }
820 else {
821 ALLOC_STATE( prf, never, PRF_STATE_SIZE, "PRF/performance-tri", 0 );
822 }
823 if (rmesa->radeon.radeonScreen->drmSupportsPointSprites) {
824 ALLOC_STATE( spr, always, SPR_STATE_SIZE, "SPR/pointsprite", 0 );
825 ALLOC_STATE( ptp, tcl, PTP_STATE_SIZE, "PTP/pointparams", 0 );
826 }
827 else {
828 ALLOC_STATE (spr, never, SPR_STATE_SIZE, "SPR/pointsprite", 0 );
829 ALLOC_STATE (ptp, never, PTP_STATE_SIZE, "PTP/pointparams", 0 );
830 }
831
832 r200SetUpAtomList( rmesa );
833
834 /* Fill in the packet headers:
835 */
836 rmesa->hw.ctx.cmd[CTX_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_MISC);
837 rmesa->hw.ctx.cmd[CTX_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_PP_CNTL);
838 rmesa->hw.ctx.cmd[CTX_CMD_2] = cmdpkt(rmesa, RADEON_EMIT_RB3D_COLORPITCH);
839 if (rmesa->radeon.radeonScreen->drmSupportsBlendColor)
840 rmesa->hw.ctx.cmd[CTX_CMD_3] = cmdpkt(rmesa, R200_EMIT_RB3D_BLENDCOLOR);
841 rmesa->hw.lin.cmd[LIN_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_RE_LINE_PATTERN);
842 rmesa->hw.lin.cmd[LIN_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_SE_LINE_WIDTH);
843 rmesa->hw.msk.cmd[MSK_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_RB3D_STENCILREFMASK);
844 rmesa->hw.vpt.cmd[VPT_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_SE_VPORT_XSCALE);
845 rmesa->hw.set.cmd[SET_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_SE_CNTL);
846 rmesa->hw.msc.cmd[MSC_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_RE_MISC);
847 rmesa->hw.cst.cmd[CST_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_CNTL_X);
848 rmesa->hw.cst.cmd[CST_CMD_1] = cmdpkt(rmesa, R200_EMIT_RB3D_DEPTHXY_OFFSET);
849 rmesa->hw.cst.cmd[CST_CMD_2] = cmdpkt(rmesa, R200_EMIT_RE_AUX_SCISSOR_CNTL);
850 rmesa->hw.cst.cmd[CST_CMD_3] = cmdpkt(rmesa, R200_EMIT_RE_SCISSOR_TL_0);
851 rmesa->hw.cst.cmd[CST_CMD_4] = cmdpkt(rmesa, R200_EMIT_SE_VAP_CNTL_STATUS);
852 rmesa->hw.cst.cmd[CST_CMD_5] = cmdpkt(rmesa, R200_EMIT_RE_POINTSIZE);
853 rmesa->hw.cst.cmd[CST_CMD_6] = cmdpkt(rmesa, R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0);
854 rmesa->hw.tam.cmd[TAM_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TAM_DEBUG3);
855 rmesa->hw.tf.cmd[TF_CMD_0] = cmdpkt(rmesa, R200_EMIT_TFACTOR_0);
856 if (rmesa->radeon.radeonScreen->drmSupportsFragShader) {
857 rmesa->hw.atf.cmd[ATF_CMD_0] = cmdpkt(rmesa, R200_EMIT_ATF_TFACTOR);
858 rmesa->hw.tex[0].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCTLALL_0);
859 rmesa->hw.tex[0].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_0);
860 rmesa->hw.tex[1].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCTLALL_1);
861 rmesa->hw.tex[1].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_1);
862 rmesa->hw.tex[2].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCTLALL_2);
863 rmesa->hw.tex[2].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_2);
864 rmesa->hw.tex[3].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCTLALL_3);
865 rmesa->hw.tex[3].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_3);
866 rmesa->hw.tex[4].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCTLALL_4);
867 rmesa->hw.tex[4].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_4);
868 rmesa->hw.tex[5].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCTLALL_5);
869 rmesa->hw.tex[5].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_5);
870 } else {
871 rmesa->hw.tex[0].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXFILTER_0);
872 rmesa->hw.tex[0].cmd[TEX_CMD_1_OLDDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_0);
873 rmesa->hw.tex[1].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXFILTER_1);
874 rmesa->hw.tex[1].cmd[TEX_CMD_1_OLDDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_1);
875 rmesa->hw.tex[2].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXFILTER_2);
876 rmesa->hw.tex[2].cmd[TEX_CMD_1_OLDDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_2);
877 rmesa->hw.tex[3].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXFILTER_3);
878 rmesa->hw.tex[3].cmd[TEX_CMD_1_OLDDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_3);
879 rmesa->hw.tex[4].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXFILTER_4);
880 rmesa->hw.tex[4].cmd[TEX_CMD_1_OLDDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_4);
881 rmesa->hw.tex[5].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXFILTER_5);
882 rmesa->hw.tex[5].cmd[TEX_CMD_1_OLDDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_5);
883 }
884 rmesa->hw.afs[0].cmd[AFS_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_AFS_0);
885 rmesa->hw.afs[1].cmd[AFS_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_AFS_1);
886 rmesa->hw.pvs.cmd[PVS_CMD_0] = cmdpkt(rmesa, R200_EMIT_VAP_PVS_CNTL);
887 rmesa->hw.cube[0].cmd[CUBE_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_FACES_0);
888 rmesa->hw.cube[0].cmd[CUBE_CMD_1] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_OFFSETS_0);
889 rmesa->hw.cube[1].cmd[CUBE_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_FACES_1);
890 rmesa->hw.cube[1].cmd[CUBE_CMD_1] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_OFFSETS_1);
891 rmesa->hw.cube[2].cmd[CUBE_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_FACES_2);
892 rmesa->hw.cube[2].cmd[CUBE_CMD_1] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_OFFSETS_2);
893 rmesa->hw.cube[3].cmd[CUBE_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_FACES_3);
894 rmesa->hw.cube[3].cmd[CUBE_CMD_1] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_OFFSETS_3);
895 rmesa->hw.cube[4].cmd[CUBE_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_FACES_4);
896 rmesa->hw.cube[4].cmd[CUBE_CMD_1] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_OFFSETS_4);
897 rmesa->hw.cube[5].cmd[CUBE_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_FACES_5);
898 rmesa->hw.cube[5].cmd[CUBE_CMD_1] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_OFFSETS_5);
899 rmesa->hw.pix[0].cmd[PIX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCBLEND_0);
900 rmesa->hw.pix[1].cmd[PIX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCBLEND_1);
901 rmesa->hw.pix[2].cmd[PIX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCBLEND_2);
902 rmesa->hw.pix[3].cmd[PIX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCBLEND_3);
903 rmesa->hw.pix[4].cmd[PIX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCBLEND_4);
904 rmesa->hw.pix[5].cmd[PIX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCBLEND_5);
905 rmesa->hw.zbs.cmd[ZBS_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_SE_ZBIAS_FACTOR);
906 rmesa->hw.tcl.cmd[TCL_CMD_0] = cmdpkt(rmesa, R200_EMIT_TCL_LIGHT_MODEL_CTL_0);
907 rmesa->hw.tcl.cmd[TCL_CMD_1] = cmdpkt(rmesa, R200_EMIT_TCL_UCP_VERT_BLEND_CTL);
908 rmesa->hw.tcg.cmd[TCG_CMD_0] = cmdpkt(rmesa, R200_EMIT_TEX_PROC_CTL_2);
909 rmesa->hw.msl.cmd[MSL_CMD_0] = cmdpkt(rmesa, R200_EMIT_MATRIX_SELECT_0);
910 rmesa->hw.vap.cmd[VAP_CMD_0] = cmdpkt(rmesa, R200_EMIT_VAP_CTL);
911 rmesa->hw.vtx.cmd[VTX_CMD_0] = cmdpkt(rmesa, R200_EMIT_VTX_FMT_0);
912 rmesa->hw.vtx.cmd[VTX_CMD_1] = cmdpkt(rmesa, R200_EMIT_OUTPUT_VTX_COMP_SEL);
913 rmesa->hw.vtx.cmd[VTX_CMD_2] = cmdpkt(rmesa, R200_EMIT_SE_VTX_STATE_CNTL);
914 rmesa->hw.vte.cmd[VTE_CMD_0] = cmdpkt(rmesa, R200_EMIT_VTE_CNTL);
915 rmesa->hw.prf.cmd[PRF_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TRI_PERF_CNTL);
916 rmesa->hw.spr.cmd[SPR_CMD_0] = cmdpkt(rmesa, R200_EMIT_TCL_POINT_SPRITE_CNTL);
917 if (rmesa->radeon.radeonScreen->kernel_mm) {
918 rmesa->hw.mtl[0].emit = mtl_emit;
919 rmesa->hw.mtl[1].emit = mtl_emit;
920
921 rmesa->hw.vpi[0].emit = veclinear_emit;
922 rmesa->hw.vpi[1].emit = veclinear_emit;
923 rmesa->hw.vpp[0].emit = veclinear_emit;
924 rmesa->hw.vpp[1].emit = veclinear_emit;
925
926 rmesa->hw.grd.emit = scl_emit;
927 rmesa->hw.fog.emit = vec_emit;
928 rmesa->hw.glt.emit = vec_emit;
929 rmesa->hw.eye.emit = vec_emit;
930
931 for (i = R200_MTX_MV; i <= R200_MTX_TEX5; i++)
932 rmesa->hw.mat[i].emit = vec_emit;
933
934 for (i = 0; i < 8; i++)
935 rmesa->hw.lit[i].emit = lit_emit;
936
937 for (i = 0; i < 6; i++)
938 rmesa->hw.ucp[i].emit = vec_emit;
939
940 rmesa->hw.ptp.emit = ptp_emit;
941 }
942
943
944
945 rmesa->hw.mtl[0].cmd[MTL_CMD_0] =
946 cmdvec( R200_VS_MAT_0_EMISS, 1, 16 );
947 rmesa->hw.mtl[0].cmd[MTL_CMD_1] =
948 cmdscl2( R200_SS_MAT_0_SHININESS, 1, 1 );
949 rmesa->hw.mtl[1].cmd[MTL_CMD_0] =
950 cmdvec( R200_VS_MAT_1_EMISS, 1, 16 );
951 rmesa->hw.mtl[1].cmd[MTL_CMD_1] =
952 cmdscl2( R200_SS_MAT_1_SHININESS, 1, 1 );
953
954 rmesa->hw.vpi[0].cmd[VPI_CMD_0] =
955 cmdveclinear( R200_PVS_PROG0, 64 );
956 rmesa->hw.vpi[1].cmd[VPI_CMD_0] =
957 cmdveclinear( R200_PVS_PROG1, 64 );
958 rmesa->hw.vpp[0].cmd[VPP_CMD_0] =
959 cmdveclinear( R200_PVS_PARAM0, 96 );
960 rmesa->hw.vpp[1].cmd[VPP_CMD_0] =
961 cmdveclinear( R200_PVS_PARAM1, 96 );
962
963 rmesa->hw.grd.cmd[GRD_CMD_0] =
964 cmdscl( R200_SS_VERT_GUARD_CLIP_ADJ_ADDR, 1, 4 );
965 rmesa->hw.fog.cmd[FOG_CMD_0] =
966 cmdvec( R200_VS_FOG_PARAM_ADDR, 1, 4 );
967 rmesa->hw.glt.cmd[GLT_CMD_0] =
968 cmdvec( R200_VS_GLOBAL_AMBIENT_ADDR, 1, 4 );
969 rmesa->hw.eye.cmd[EYE_CMD_0] =
970 cmdvec( R200_VS_EYE_VECTOR_ADDR, 1, 4 );
971
972 rmesa->hw.mat[R200_MTX_MV].cmd[MAT_CMD_0] =
973 cmdvec( R200_VS_MATRIX_0_MV, 1, 16);
974 rmesa->hw.mat[R200_MTX_IMV].cmd[MAT_CMD_0] =
975 cmdvec( R200_VS_MATRIX_1_INV_MV, 1, 16);
976 rmesa->hw.mat[R200_MTX_MVP].cmd[MAT_CMD_0] =
977 cmdvec( R200_VS_MATRIX_2_MVP, 1, 16);
978 rmesa->hw.mat[R200_MTX_TEX0].cmd[MAT_CMD_0] =
979 cmdvec( R200_VS_MATRIX_3_TEX0, 1, 16);
980 rmesa->hw.mat[R200_MTX_TEX1].cmd[MAT_CMD_0] =
981 cmdvec( R200_VS_MATRIX_4_TEX1, 1, 16);
982 rmesa->hw.mat[R200_MTX_TEX2].cmd[MAT_CMD_0] =
983 cmdvec( R200_VS_MATRIX_5_TEX2, 1, 16);
984 rmesa->hw.mat[R200_MTX_TEX3].cmd[MAT_CMD_0] =
985 cmdvec( R200_VS_MATRIX_6_TEX3, 1, 16);
986 rmesa->hw.mat[R200_MTX_TEX4].cmd[MAT_CMD_0] =
987 cmdvec( R200_VS_MATRIX_7_TEX4, 1, 16);
988 rmesa->hw.mat[R200_MTX_TEX5].cmd[MAT_CMD_0] =
989 cmdvec( R200_VS_MATRIX_8_TEX5, 1, 16);
990
991 for (i = 0 ; i < 8; i++) {
992 rmesa->hw.lit[i].cmd[LIT_CMD_0] =
993 cmdvec( R200_VS_LIGHT_AMBIENT_ADDR + i, 8, 24 );
994 rmesa->hw.lit[i].cmd[LIT_CMD_1] =
995 cmdscl( R200_SS_LIGHT_DCD_ADDR + i, 8, 7 );
996 }
997
998 for (i = 0 ; i < 6; i++) {
999 rmesa->hw.ucp[i].cmd[UCP_CMD_0] =
1000 cmdvec( R200_VS_UCP_ADDR + i, 1, 4 );
1001 }
1002
1003 rmesa->hw.ptp.cmd[PTP_CMD_0] =
1004 cmdvec( R200_VS_PNT_SPRITE_VPORT_SCALE, 1, 4 );
1005 rmesa->hw.ptp.cmd[PTP_CMD_1] =
1006 cmdvec( R200_VS_PNT_SPRITE_ATT_CONST, 1, 12 );
1007
1008 /* Initial Harware state:
1009 */
1010 rmesa->hw.ctx.cmd[CTX_PP_MISC] = (R200_ALPHA_TEST_PASS
1011 /* | R200_RIGHT_HAND_CUBE_OGL*/);
1012
1013 rmesa->hw.ctx.cmd[CTX_PP_FOG_COLOR] = (R200_FOG_VERTEX |
1014 R200_FOG_USE_SPEC_ALPHA);
1015
1016 rmesa->hw.ctx.cmd[CTX_RE_SOLID_COLOR] = 0x00000000;
1017
1018 rmesa->hw.ctx.cmd[CTX_RB3D_BLENDCNTL] = (R200_COMB_FCN_ADD_CLAMP |
1019 (R200_BLEND_GL_ONE << R200_SRC_BLEND_SHIFT) |
1020 (R200_BLEND_GL_ZERO << R200_DST_BLEND_SHIFT));
1021
1022 if (rmesa->radeon.radeonScreen->drmSupportsBlendColor) {
1023 rmesa->hw.ctx.cmd[CTX_RB3D_BLENDCOLOR] = 0x00000000;
1024 rmesa->hw.ctx.cmd[CTX_RB3D_ABLENDCNTL] = (R200_COMB_FCN_ADD_CLAMP |
1025 (R200_BLEND_GL_ONE << R200_SRC_BLEND_SHIFT) |
1026 (R200_BLEND_GL_ZERO << R200_DST_BLEND_SHIFT));
1027 rmesa->hw.ctx.cmd[CTX_RB3D_CBLENDCNTL] = (R200_COMB_FCN_ADD_CLAMP |
1028 (R200_BLEND_GL_ONE << R200_SRC_BLEND_SHIFT) |
1029 (R200_BLEND_GL_ZERO << R200_DST_BLEND_SHIFT));
1030 }
1031
1032 rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHOFFSET] =
1033 rmesa->radeon.radeonScreen->depthOffset + rmesa->radeon.radeonScreen->fbLocation;
1034
1035 rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHPITCH] =
1036 ((rmesa->radeon.radeonScreen->depthPitch &
1037 R200_DEPTHPITCH_MASK) |
1038 R200_DEPTH_ENDIAN_NO_SWAP);
1039
1040 if (rmesa->using_hyperz)
1041 rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHPITCH] |= R200_DEPTH_HYPERZ;
1042
1043 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] = (R200_Z_TEST_LESS |
1044 R200_STENCIL_TEST_ALWAYS |
1045 R200_STENCIL_FAIL_KEEP |
1046 R200_STENCIL_ZPASS_KEEP |
1047 R200_STENCIL_ZFAIL_KEEP |
1048 R200_Z_WRITE_ENABLE);
1049
1050 if (rmesa->using_hyperz) {
1051 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= R200_Z_COMPRESSION_ENABLE |
1052 R200_Z_DECOMPRESSION_ENABLE;
1053 /* if (rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_R200)
1054 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_HIERARCHY_ENABLE;*/
1055 }
1056
1057 rmesa->hw.ctx.cmd[CTX_PP_CNTL] = (R200_ANTI_ALIAS_NONE
1058 | R200_TEX_BLEND_0_ENABLE);
1059
1060 switch ( driQueryOptioni( &rmesa->radeon.optionCache, "dither_mode" ) ) {
1061 case DRI_CONF_DITHER_XERRORDIFFRESET:
1062 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= R200_DITHER_INIT;
1063 break;
1064 case DRI_CONF_DITHER_ORDERED:
1065 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= R200_SCALE_DITHER_ENABLE;
1066 break;
1067 }
1068 if ( driQueryOptioni( &rmesa->radeon.optionCache, "round_mode" ) ==
1069 DRI_CONF_ROUND_ROUND )
1070 rmesa->radeon.state.color.roundEnable = R200_ROUND_ENABLE;
1071 else
1072 rmesa->radeon.state.color.roundEnable = 0;
1073 if ( driQueryOptioni (&rmesa->radeon.optionCache, "color_reduction" ) ==
1074 DRI_CONF_COLOR_REDUCTION_DITHER )
1075 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= R200_DITHER_ENABLE;
1076 else
1077 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= rmesa->radeon.state.color.roundEnable;
1078
1079 rmesa->hw.prf.cmd[PRF_PP_TRI_PERF] = R200_TRI_CUTOFF_MASK - R200_TRI_CUTOFF_MASK *
1080 driQueryOptionf (&rmesa->radeon.optionCache,"texture_blend_quality");
1081 rmesa->hw.prf.cmd[PRF_PP_PERF_CNTL] = 0;
1082
1083 rmesa->hw.set.cmd[SET_SE_CNTL] = (R200_FFACE_CULL_CCW |
1084 R200_BFACE_SOLID |
1085 R200_FFACE_SOLID |
1086 R200_FLAT_SHADE_VTX_LAST |
1087 R200_DIFFUSE_SHADE_GOURAUD |
1088 R200_ALPHA_SHADE_GOURAUD |
1089 R200_SPECULAR_SHADE_GOURAUD |
1090 R200_FOG_SHADE_GOURAUD |
1091 R200_DISC_FOG_SHADE_GOURAUD |
1092 R200_VTX_PIX_CENTER_OGL |
1093 R200_ROUND_MODE_TRUNC |
1094 R200_ROUND_PREC_8TH_PIX);
1095
1096 rmesa->hw.set.cmd[SET_RE_CNTL] = (R200_PERSPECTIVE_ENABLE |
1097 R200_SCISSOR_ENABLE);
1098
1099 rmesa->hw.lin.cmd[LIN_RE_LINE_PATTERN] = ((1 << 16) | 0xffff);
1100
1101 rmesa->hw.lin.cmd[LIN_RE_LINE_STATE] =
1102 ((0 << R200_LINE_CURRENT_PTR_SHIFT) |
1103 (1 << R200_LINE_CURRENT_COUNT_SHIFT));
1104
1105 rmesa->hw.lin.cmd[LIN_SE_LINE_WIDTH] = (1 << 4);
1106
1107 rmesa->hw.msk.cmd[MSK_RB3D_STENCILREFMASK] =
1108 ((0x00 << R200_STENCIL_REF_SHIFT) |
1109 (0xff << R200_STENCIL_MASK_SHIFT) |
1110 (0xff << R200_STENCIL_WRITEMASK_SHIFT));
1111
1112 rmesa->hw.msk.cmd[MSK_RB3D_ROPCNTL] = R200_ROP_COPY;
1113 rmesa->hw.msk.cmd[MSK_RB3D_PLANEMASK] = 0xffffffff;
1114
1115 rmesa->hw.tam.cmd[TAM_DEBUG3] = 0;
1116
1117 rmesa->hw.msc.cmd[MSC_RE_MISC] =
1118 ((0 << R200_STIPPLE_X_OFFSET_SHIFT) |
1119 (0 << R200_STIPPLE_Y_OFFSET_SHIFT) |
1120 R200_STIPPLE_BIG_BIT_ORDER);
1121
1122
1123 rmesa->hw.cst.cmd[CST_PP_CNTL_X] = 0;
1124 rmesa->hw.cst.cmd[CST_RB3D_DEPTHXY_OFFSET] = 0;
1125 rmesa->hw.cst.cmd[CST_RE_AUX_SCISSOR_CNTL] = 0x0;
1126 rmesa->hw.cst.cmd[CST_RE_SCISSOR_TL_0] = 0;
1127 rmesa->hw.cst.cmd[CST_RE_SCISSOR_BR_0] = 0;
1128 rmesa->hw.cst.cmd[CST_SE_VAP_CNTL_STATUS] =
1129 #ifdef MESA_BIG_ENDIAN
1130 R200_VC_32BIT_SWAP;
1131 #else
1132 R200_VC_NO_SWAP;
1133 #endif
1134
1135 if (!(rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL)) {
1136 /* Bypass TCL */
1137 rmesa->hw.cst.cmd[CST_SE_VAP_CNTL_STATUS] |= (1<<8);
1138 }
1139
1140 rmesa->hw.cst.cmd[CST_RE_POINTSIZE] =
1141 (((GLuint)(ctx->Const.MaxPointSize * 16.0)) << R200_MAXPOINTSIZE_SHIFT) | 0x10;
1142 rmesa->hw.cst.cmd[CST_SE_TCL_INPUT_VTX_0] =
1143 (0x0 << R200_VERTEX_POSITION_ADDR__SHIFT);
1144 rmesa->hw.cst.cmd[CST_SE_TCL_INPUT_VTX_1] =
1145 (0x02 << R200_VTX_COLOR_0_ADDR__SHIFT) |
1146 (0x03 << R200_VTX_COLOR_1_ADDR__SHIFT);
1147 rmesa->hw.cst.cmd[CST_SE_TCL_INPUT_VTX_2] =
1148 (0x06 << R200_VTX_TEX_0_ADDR__SHIFT) |
1149 (0x07 << R200_VTX_TEX_1_ADDR__SHIFT) |
1150 (0x08 << R200_VTX_TEX_2_ADDR__SHIFT) |
1151 (0x09 << R200_VTX_TEX_3_ADDR__SHIFT);
1152 rmesa->hw.cst.cmd[CST_SE_TCL_INPUT_VTX_3] =
1153 (0x0A << R200_VTX_TEX_4_ADDR__SHIFT) |
1154 (0x0B << R200_VTX_TEX_5_ADDR__SHIFT);
1155
1156
1157 rmesa->hw.vpt.cmd[VPT_SE_VPORT_XSCALE] = 0x00000000;
1158 rmesa->hw.vpt.cmd[VPT_SE_VPORT_XOFFSET] = 0x00000000;
1159 rmesa->hw.vpt.cmd[VPT_SE_VPORT_YSCALE] = 0x00000000;
1160 rmesa->hw.vpt.cmd[VPT_SE_VPORT_YOFFSET] = 0x00000000;
1161 rmesa->hw.vpt.cmd[VPT_SE_VPORT_ZSCALE] = 0x00000000;
1162 rmesa->hw.vpt.cmd[VPT_SE_VPORT_ZOFFSET] = 0x00000000;
1163
1164 for ( i = 0 ; i < ctx->Const.MaxTextureUnits ; i++ ) {
1165 rmesa->hw.tex[i].cmd[TEX_PP_TXFILTER] = R200_BORDER_MODE_OGL;
1166 rmesa->hw.tex[i].cmd[TEX_PP_TXFORMAT] =
1167 ((i << R200_TXFORMAT_ST_ROUTE_SHIFT) | /* <-- note i */
1168 (2 << R200_TXFORMAT_WIDTH_SHIFT) |
1169 (2 << R200_TXFORMAT_HEIGHT_SHIFT));
1170 rmesa->hw.tex[i].cmd[TEX_PP_BORDER_COLOR] = 0;
1171 rmesa->hw.tex[i].cmd[TEX_PP_TXFORMAT_X] =
1172 (/* R200_TEXCOORD_PROJ | */
1173 0x100000); /* Small default bias */
1174 if (rmesa->radeon.radeonScreen->drmSupportsFragShader) {
1175 rmesa->hw.tex[i].cmd[TEX_PP_TXOFFSET_NEWDRM] =
1176 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
1177 rmesa->hw.tex[i].cmd[TEX_PP_CUBIC_FACES] = 0;
1178 rmesa->hw.tex[i].cmd[TEX_PP_TXMULTI_CTL] = 0;
1179 }
1180 else {
1181 rmesa->hw.tex[i].cmd[TEX_PP_TXOFFSET_OLDDRM] =
1182 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
1183 }
1184
1185 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_FACES] = 0;
1186 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F1] =
1187 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
1188 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F2] =
1189 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
1190 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F3] =
1191 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
1192 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F4] =
1193 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
1194 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F5] =
1195 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
1196
1197 rmesa->hw.pix[i].cmd[PIX_PP_TXCBLEND] =
1198 (R200_TXC_ARG_A_ZERO |
1199 R200_TXC_ARG_B_ZERO |
1200 R200_TXC_ARG_C_DIFFUSE_COLOR |
1201 R200_TXC_OP_MADD);
1202
1203 rmesa->hw.pix[i].cmd[PIX_PP_TXCBLEND2] =
1204 ((i << R200_TXC_TFACTOR_SEL_SHIFT) |
1205 R200_TXC_SCALE_1X |
1206 R200_TXC_CLAMP_0_1 |
1207 R200_TXC_OUTPUT_REG_R0);
1208
1209 rmesa->hw.pix[i].cmd[PIX_PP_TXABLEND] =
1210 (R200_TXA_ARG_A_ZERO |
1211 R200_TXA_ARG_B_ZERO |
1212 R200_TXA_ARG_C_DIFFUSE_ALPHA |
1213 R200_TXA_OP_MADD);
1214
1215 rmesa->hw.pix[i].cmd[PIX_PP_TXABLEND2] =
1216 ((i << R200_TXA_TFACTOR_SEL_SHIFT) |
1217 R200_TXA_SCALE_1X |
1218 R200_TXA_CLAMP_0_1 |
1219 R200_TXA_OUTPUT_REG_R0);
1220 }
1221
1222 rmesa->hw.tf.cmd[TF_TFACTOR_0] = 0;
1223 rmesa->hw.tf.cmd[TF_TFACTOR_1] = 0;
1224 rmesa->hw.tf.cmd[TF_TFACTOR_2] = 0;
1225 rmesa->hw.tf.cmd[TF_TFACTOR_3] = 0;
1226 rmesa->hw.tf.cmd[TF_TFACTOR_4] = 0;
1227 rmesa->hw.tf.cmd[TF_TFACTOR_5] = 0;
1228
1229 rmesa->hw.vap.cmd[VAP_SE_VAP_CNTL] =
1230 (R200_VAP_TCL_ENABLE |
1231 (0x9 << R200_VAP_VF_MAX_VTX_NUM__SHIFT));
1232
1233 rmesa->hw.vte.cmd[VTE_SE_VTE_CNTL] =
1234 (R200_VPORT_X_SCALE_ENA |
1235 R200_VPORT_Y_SCALE_ENA |
1236 R200_VPORT_Z_SCALE_ENA |
1237 R200_VPORT_X_OFFSET_ENA |
1238 R200_VPORT_Y_OFFSET_ENA |
1239 R200_VPORT_Z_OFFSET_ENA |
1240 /* FIXME: Turn on for tex rect only */
1241 R200_VTX_ST_DENORMALIZED |
1242 R200_VTX_W0_FMT);
1243
1244
1245 rmesa->hw.vtx.cmd[VTX_VTXFMT_0] = 0;
1246 rmesa->hw.vtx.cmd[VTX_VTXFMT_1] = 0;
1247 rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_VTXFMT_0] =
1248 ((R200_VTX_Z0 | R200_VTX_W0 |
1249 (R200_VTX_FP_RGBA << R200_VTX_COLOR_0_SHIFT)));
1250 rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_VTXFMT_1] = 0;
1251 rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_COMPSEL] = (R200_OUTPUT_XYZW);
1252 rmesa->hw.vtx.cmd[VTX_STATE_CNTL] = R200_VSC_UPDATE_USER_COLOR_0_ENABLE;
1253
1254
1255 /* Matrix selection */
1256 rmesa->hw.msl.cmd[MSL_MATRIX_SELECT_0] =
1257 (R200_MTX_MV << R200_MODELVIEW_0_SHIFT);
1258
1259 rmesa->hw.msl.cmd[MSL_MATRIX_SELECT_1] =
1260 (R200_MTX_IMV << R200_IT_MODELVIEW_0_SHIFT);
1261
1262 rmesa->hw.msl.cmd[MSL_MATRIX_SELECT_2] =
1263 (R200_MTX_MVP << R200_MODELPROJECT_0_SHIFT);
1264
1265 rmesa->hw.msl.cmd[MSL_MATRIX_SELECT_3] =
1266 ((R200_MTX_TEX0 << R200_TEXMAT_0_SHIFT) |
1267 (R200_MTX_TEX1 << R200_TEXMAT_1_SHIFT) |
1268 (R200_MTX_TEX2 << R200_TEXMAT_2_SHIFT) |
1269 (R200_MTX_TEX3 << R200_TEXMAT_3_SHIFT));
1270
1271 rmesa->hw.msl.cmd[MSL_MATRIX_SELECT_4] =
1272 ((R200_MTX_TEX4 << R200_TEXMAT_4_SHIFT) |
1273 (R200_MTX_TEX5 << R200_TEXMAT_5_SHIFT));
1274
1275
1276 /* General TCL state */
1277 rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL_0] =
1278 (R200_SPECULAR_LIGHTS |
1279 R200_DIFFUSE_SPECULAR_COMBINE |
1280 R200_LOCAL_LIGHT_VEC_GL |
1281 R200_LM0_SOURCE_MATERIAL_0 << R200_FRONT_SHININESS_SOURCE_SHIFT |
1282 R200_LM0_SOURCE_MATERIAL_1 << R200_BACK_SHININESS_SOURCE_SHIFT);
1283
1284 rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL_1] =
1285 ((R200_LM1_SOURCE_MATERIAL_0 << R200_FRONT_EMISSIVE_SOURCE_SHIFT) |
1286 (R200_LM1_SOURCE_MATERIAL_0 << R200_FRONT_AMBIENT_SOURCE_SHIFT) |
1287 (R200_LM1_SOURCE_MATERIAL_0 << R200_FRONT_DIFFUSE_SOURCE_SHIFT) |
1288 (R200_LM1_SOURCE_MATERIAL_0 << R200_FRONT_SPECULAR_SOURCE_SHIFT) |
1289 (R200_LM1_SOURCE_MATERIAL_1 << R200_BACK_EMISSIVE_SOURCE_SHIFT) |
1290 (R200_LM1_SOURCE_MATERIAL_1 << R200_BACK_AMBIENT_SOURCE_SHIFT) |
1291 (R200_LM1_SOURCE_MATERIAL_1 << R200_BACK_DIFFUSE_SOURCE_SHIFT) |
1292 (R200_LM1_SOURCE_MATERIAL_1 << R200_BACK_SPECULAR_SOURCE_SHIFT));
1293
1294 rmesa->hw.tcl.cmd[TCL_PER_LIGHT_CTL_0] = 0; /* filled in via callbacks */
1295 rmesa->hw.tcl.cmd[TCL_PER_LIGHT_CTL_1] = 0;
1296 rmesa->hw.tcl.cmd[TCL_PER_LIGHT_CTL_2] = 0;
1297 rmesa->hw.tcl.cmd[TCL_PER_LIGHT_CTL_3] = 0;
1298
1299 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] =
1300 (R200_UCP_IN_CLIP_SPACE |
1301 R200_CULL_FRONT_IS_CCW);
1302
1303 /* Texgen/Texmat state */
1304 rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_2] = 0x00ffffff;
1305 rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_3] =
1306 ((0 << R200_TEXGEN_0_INPUT_TEX_SHIFT) |
1307 (1 << R200_TEXGEN_1_INPUT_TEX_SHIFT) |
1308 (2 << R200_TEXGEN_2_INPUT_TEX_SHIFT) |
1309 (3 << R200_TEXGEN_3_INPUT_TEX_SHIFT) |
1310 (4 << R200_TEXGEN_4_INPUT_TEX_SHIFT) |
1311 (5 << R200_TEXGEN_5_INPUT_TEX_SHIFT));
1312 rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_0] = 0;
1313 rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_1] =
1314 ((0 << R200_TEXGEN_0_INPUT_SHIFT) |
1315 (1 << R200_TEXGEN_1_INPUT_SHIFT) |
1316 (2 << R200_TEXGEN_2_INPUT_SHIFT) |
1317 (3 << R200_TEXGEN_3_INPUT_SHIFT) |
1318 (4 << R200_TEXGEN_4_INPUT_SHIFT) |
1319 (5 << R200_TEXGEN_5_INPUT_SHIFT));
1320 rmesa->hw.tcg.cmd[TCG_TEX_CYL_WRAP_CTL] = 0;
1321
1322
1323 for (i = 0 ; i < 8; i++) {
1324 struct gl_light *l = &ctx->Light.Light[i];
1325 GLenum p = GL_LIGHT0 + i;
1326 *(float *)&(rmesa->hw.lit[i].cmd[LIT_RANGE_CUTOFF]) = FLT_MAX;
1327
1328 ctx->Driver.Lightfv( ctx, p, GL_AMBIENT, l->Ambient );
1329 ctx->Driver.Lightfv( ctx, p, GL_DIFFUSE, l->Diffuse );
1330 ctx->Driver.Lightfv( ctx, p, GL_SPECULAR, l->Specular );
1331 ctx->Driver.Lightfv( ctx, p, GL_POSITION, NULL );
1332 ctx->Driver.Lightfv( ctx, p, GL_SPOT_DIRECTION, NULL );
1333 ctx->Driver.Lightfv( ctx, p, GL_SPOT_EXPONENT, &l->SpotExponent );
1334 ctx->Driver.Lightfv( ctx, p, GL_SPOT_CUTOFF, &l->SpotCutoff );
1335 ctx->Driver.Lightfv( ctx, p, GL_CONSTANT_ATTENUATION,
1336 &l->ConstantAttenuation );
1337 ctx->Driver.Lightfv( ctx, p, GL_LINEAR_ATTENUATION,
1338 &l->LinearAttenuation );
1339 ctx->Driver.Lightfv( ctx, p, GL_QUADRATIC_ATTENUATION,
1340 &l->QuadraticAttenuation );
1341 *(float *)&(rmesa->hw.lit[i].cmd[LIT_ATTEN_XXX]) = 0.0;
1342 }
1343
1344 ctx->Driver.LightModelfv( ctx, GL_LIGHT_MODEL_AMBIENT,
1345 ctx->Light.Model.Ambient );
1346
1347 TNL_CONTEXT(ctx)->Driver.NotifyMaterialChange( ctx );
1348
1349 for (i = 0 ; i < 6; i++) {
1350 ctx->Driver.ClipPlane( ctx, GL_CLIP_PLANE0 + i, NULL );
1351 }
1352
1353 ctx->Driver.Fogfv( ctx, GL_FOG_MODE, NULL );
1354 ctx->Driver.Fogfv( ctx, GL_FOG_DENSITY, &ctx->Fog.Density );
1355 ctx->Driver.Fogfv( ctx, GL_FOG_START, &ctx->Fog.Start );
1356 ctx->Driver.Fogfv( ctx, GL_FOG_END, &ctx->Fog.End );
1357 ctx->Driver.Fogfv( ctx, GL_FOG_COLOR, ctx->Fog.Color );
1358 ctx->Driver.Fogfv( ctx, GL_FOG_COORDINATE_SOURCE_EXT, NULL );
1359
1360 rmesa->hw.grd.cmd[GRD_VERT_GUARD_CLIP_ADJ] = IEEE_ONE;
1361 rmesa->hw.grd.cmd[GRD_VERT_GUARD_DISCARD_ADJ] = IEEE_ONE;
1362 rmesa->hw.grd.cmd[GRD_HORZ_GUARD_CLIP_ADJ] = IEEE_ONE;
1363 rmesa->hw.grd.cmd[GRD_HORZ_GUARD_DISCARD_ADJ] = IEEE_ONE;
1364
1365 rmesa->hw.eye.cmd[EYE_X] = 0;
1366 rmesa->hw.eye.cmd[EYE_Y] = 0;
1367 rmesa->hw.eye.cmd[EYE_Z] = IEEE_ONE;
1368 rmesa->hw.eye.cmd[EYE_RESCALE_FACTOR] = IEEE_ONE;
1369
1370 rmesa->hw.spr.cmd[SPR_POINT_SPRITE_CNTL] =
1371 R200_PS_SE_SEL_STATE | R200_PS_MULT_CONST;
1372
1373 /* ptp_eye is presumably used to calculate the attenuation wrt a different
1374 location? In any case, since point attenuation triggers _needeyecoords,
1375 it is constant. Probably ignored as long as R200_PS_USE_MODEL_EYE_VEC
1376 isn't set */
1377 rmesa->hw.ptp.cmd[PTP_EYE_X] = 0;
1378 rmesa->hw.ptp.cmd[PTP_EYE_Y] = 0;
1379 rmesa->hw.ptp.cmd[PTP_EYE_Z] = IEEE_ONE | 0x80000000; /* -1.0 */
1380 rmesa->hw.ptp.cmd[PTP_EYE_3] = 0;
1381 /* no idea what the ptp_vport_scale values are good for, except the
1382 PTSIZE one - hopefully doesn't matter */
1383 rmesa->hw.ptp.cmd[PTP_VPORT_SCALE_0] = IEEE_ONE;
1384 rmesa->hw.ptp.cmd[PTP_VPORT_SCALE_1] = IEEE_ONE;
1385 rmesa->hw.ptp.cmd[PTP_VPORT_SCALE_PTSIZE] = IEEE_ONE;
1386 rmesa->hw.ptp.cmd[PTP_VPORT_SCALE_3] = IEEE_ONE;
1387 rmesa->hw.ptp.cmd[PTP_ATT_CONST_QUAD] = 0;
1388 rmesa->hw.ptp.cmd[PTP_ATT_CONST_LIN] = 0;
1389 rmesa->hw.ptp.cmd[PTP_ATT_CONST_CON] = IEEE_ONE;
1390 rmesa->hw.ptp.cmd[PTP_ATT_CONST_3] = 0;
1391 rmesa->hw.ptp.cmd[PTP_CLAMP_MIN] = IEEE_ONE;
1392 rmesa->hw.ptp.cmd[PTP_CLAMP_MAX] = 0x44ffe000; /* 2047 */
1393 rmesa->hw.ptp.cmd[PTP_CLAMP_2] = 0;
1394 rmesa->hw.ptp.cmd[PTP_CLAMP_3] = 0;
1395
1396 r200LightingSpaceChange( ctx );
1397
1398 rmesa->radeon.hw.all_dirty = GL_TRUE;
1399
1400 rcommonInitCmdBuf(&rmesa->radeon);
1401 }