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Merge branch 'radeon-fbo-hacking' into radeon-rewrite
[mesa.git] / src / mesa / drivers / dri / r200 / r200_state_init.c
1 /*
2 Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
3
4 The Weather Channel (TM) funded Tungsten Graphics to develop the
5 initial release of the Radeon 8500 driver under the XFree86 license.
6 This notice must be preserved.
7
8 Permission is hereby granted, free of charge, to any person obtaining
9 a copy of this software and associated documentation files (the
10 "Software"), to deal in the Software without restriction, including
11 without limitation the rights to use, copy, modify, merge, publish,
12 distribute, sublicense, and/or sell copies of the Software, and to
13 permit persons to whom the Software is furnished to do so, subject to
14 the following conditions:
15
16 The above copyright notice and this permission notice (including the
17 next paragraph) shall be included in all copies or substantial
18 portions of the Software.
19
20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 */
28
29 /*
30 * Authors:
31 * Keith Whitwell <keith@tungstengraphics.com>
32 */
33
34 #include "main/glheader.h"
35 #include "main/imports.h"
36 #include "main/enums.h"
37 #include "main/colormac.h"
38 #include "main/api_arrayelt.h"
39
40 #include "swrast/swrast.h"
41 #include "vbo/vbo.h"
42 #include "tnl/tnl.h"
43 #include "tnl/t_pipeline.h"
44 #include "swrast_setup/swrast_setup.h"
45
46 #include "radeon_common.h"
47 #include "radeon_mipmap_tree.h"
48 #include "r200_context.h"
49 #include "r200_ioctl.h"
50 #include "r200_state.h"
51 #include "r200_tcl.h"
52 #include "r200_tex.h"
53 #include "r200_swtcl.h"
54
55 #include "xmlpool.h"
56
57 /* New (1.3) state mechanism. 3 commands (packet, scalar, vector) in
58 * 1.3 cmdbuffers allow all previous state to be updated as well as
59 * the tcl scalar and vector areas.
60 */
61 static struct {
62 int start;
63 int len;
64 const char *name;
65 } packet[RADEON_MAX_STATE_PACKETS] = {
66 {RADEON_PP_MISC, 7, "RADEON_PP_MISC"},
67 {RADEON_PP_CNTL, 3, "RADEON_PP_CNTL"},
68 {RADEON_RB3D_COLORPITCH, 1, "RADEON_RB3D_COLORPITCH"},
69 {RADEON_RE_LINE_PATTERN, 2, "RADEON_RE_LINE_PATTERN"},
70 {RADEON_SE_LINE_WIDTH, 1, "RADEON_SE_LINE_WIDTH"},
71 {RADEON_PP_LUM_MATRIX, 1, "RADEON_PP_LUM_MATRIX"},
72 {RADEON_PP_ROT_MATRIX_0, 2, "RADEON_PP_ROT_MATRIX_0"},
73 {RADEON_RB3D_STENCILREFMASK, 3, "RADEON_RB3D_STENCILREFMASK"},
74 {RADEON_SE_VPORT_XSCALE, 6, "RADEON_SE_VPORT_XSCALE"},
75 {RADEON_SE_CNTL, 2, "RADEON_SE_CNTL"},
76 {RADEON_SE_CNTL_STATUS, 1, "RADEON_SE_CNTL_STATUS"},
77 {RADEON_RE_MISC, 1, "RADEON_RE_MISC"},
78 {RADEON_PP_TXFILTER_0, 6, "RADEON_PP_TXFILTER_0"},
79 {RADEON_PP_BORDER_COLOR_0, 1, "RADEON_PP_BORDER_COLOR_0"},
80 {RADEON_PP_TXFILTER_1, 6, "RADEON_PP_TXFILTER_1"},
81 {RADEON_PP_BORDER_COLOR_1, 1, "RADEON_PP_BORDER_COLOR_1"},
82 {RADEON_PP_TXFILTER_2, 6, "RADEON_PP_TXFILTER_2"},
83 {RADEON_PP_BORDER_COLOR_2, 1, "RADEON_PP_BORDER_COLOR_2"},
84 {RADEON_SE_ZBIAS_FACTOR, 2, "RADEON_SE_ZBIAS_FACTOR"},
85 {RADEON_SE_TCL_OUTPUT_VTX_FMT, 11, "RADEON_SE_TCL_OUTPUT_VTX_FMT"},
86 {RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED, 17,
87 "RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED"},
88 {R200_PP_TXCBLEND_0, 4, "R200_PP_TXCBLEND_0"},
89 {R200_PP_TXCBLEND_1, 4, "R200_PP_TXCBLEND_1"},
90 {R200_PP_TXCBLEND_2, 4, "R200_PP_TXCBLEND_2"},
91 {R200_PP_TXCBLEND_3, 4, "R200_PP_TXCBLEND_3"},
92 {R200_PP_TXCBLEND_4, 4, "R200_PP_TXCBLEND_4"},
93 {R200_PP_TXCBLEND_5, 4, "R200_PP_TXCBLEND_5"},
94 {R200_PP_TXCBLEND_6, 4, "R200_PP_TXCBLEND_6"},
95 {R200_PP_TXCBLEND_7, 4, "R200_PP_TXCBLEND_7"},
96 {R200_SE_TCL_LIGHT_MODEL_CTL_0, 6, "R200_SE_TCL_LIGHT_MODEL_CTL_0"},
97 {R200_PP_TFACTOR_0, 6, "R200_PP_TFACTOR_0"},
98 {R200_SE_VTX_FMT_0, 4, "R200_SE_VTX_FMT_0"},
99 {R200_SE_VAP_CNTL, 1, "R200_SE_VAP_CNTL"},
100 {R200_SE_TCL_MATRIX_SEL_0, 5, "R200_SE_TCL_MATRIX_SEL_0"},
101 {R200_SE_TCL_TEX_PROC_CTL_2, 5, "R200_SE_TCL_TEX_PROC_CTL_2"},
102 {R200_SE_TCL_UCP_VERT_BLEND_CTL, 1, "R200_SE_TCL_UCP_VERT_BLEND_CTL"},
103 {R200_PP_TXFILTER_0, 6, "R200_PP_TXFILTER_0"},
104 {R200_PP_TXFILTER_1, 6, "R200_PP_TXFILTER_1"},
105 {R200_PP_TXFILTER_2, 6, "R200_PP_TXFILTER_2"},
106 {R200_PP_TXFILTER_3, 6, "R200_PP_TXFILTER_3"},
107 {R200_PP_TXFILTER_4, 6, "R200_PP_TXFILTER_4"},
108 {R200_PP_TXFILTER_5, 6, "R200_PP_TXFILTER_5"},
109 {R200_PP_TXOFFSET_0, 1, "R200_PP_TXOFFSET_0"},
110 {R200_PP_TXOFFSET_1, 1, "R200_PP_TXOFFSET_1"},
111 {R200_PP_TXOFFSET_2, 1, "R200_PP_TXOFFSET_2"},
112 {R200_PP_TXOFFSET_3, 1, "R200_PP_TXOFFSET_3"},
113 {R200_PP_TXOFFSET_4, 1, "R200_PP_TXOFFSET_4"},
114 {R200_PP_TXOFFSET_5, 1, "R200_PP_TXOFFSET_5"},
115 {R200_SE_VTE_CNTL, 1, "R200_SE_VTE_CNTL"},
116 {R200_SE_TCL_OUTPUT_VTX_COMP_SEL, 1,
117 "R200_SE_TCL_OUTPUT_VTX_COMP_SEL"},
118 {R200_PP_TAM_DEBUG3, 1, "R200_PP_TAM_DEBUG3"},
119 {R200_PP_CNTL_X, 1, "R200_PP_CNTL_X"},
120 {R200_RB3D_DEPTHXY_OFFSET, 1, "R200_RB3D_DEPTHXY_OFFSET"},
121 {R200_RE_AUX_SCISSOR_CNTL, 1, "R200_RE_AUX_SCISSOR_CNTL"},
122 {R200_RE_SCISSOR_TL_0, 2, "R200_RE_SCISSOR_TL_0"},
123 {R200_RE_SCISSOR_TL_1, 2, "R200_RE_SCISSOR_TL_1"},
124 {R200_RE_SCISSOR_TL_2, 2, "R200_RE_SCISSOR_TL_2"},
125 {R200_SE_VAP_CNTL_STATUS, 1, "R200_SE_VAP_CNTL_STATUS"},
126 {R200_SE_VTX_STATE_CNTL, 1, "R200_SE_VTX_STATE_CNTL"},
127 {R200_RE_POINTSIZE, 1, "R200_RE_POINTSIZE"},
128 {R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0, 4,
129 "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0"},
130 {R200_PP_CUBIC_FACES_0, 1, "R200_PP_CUBIC_FACES_0"}, /* 61 */
131 {R200_PP_CUBIC_OFFSET_F1_0, 5, "R200_PP_CUBIC_OFFSET_F1_0"}, /* 62 */
132 {R200_PP_CUBIC_FACES_1, 1, "R200_PP_CUBIC_FACES_1"},
133 {R200_PP_CUBIC_OFFSET_F1_1, 5, "R200_PP_CUBIC_OFFSET_F1_1"},
134 {R200_PP_CUBIC_FACES_2, 1, "R200_PP_CUBIC_FACES_2"},
135 {R200_PP_CUBIC_OFFSET_F1_2, 5, "R200_PP_CUBIC_OFFSET_F1_2"},
136 {R200_PP_CUBIC_FACES_3, 1, "R200_PP_CUBIC_FACES_3"},
137 {R200_PP_CUBIC_OFFSET_F1_3, 5, "R200_PP_CUBIC_OFFSET_F1_3"},
138 {R200_PP_CUBIC_FACES_4, 1, "R200_PP_CUBIC_FACES_4"},
139 {R200_PP_CUBIC_OFFSET_F1_4, 5, "R200_PP_CUBIC_OFFSET_F1_4"},
140 {R200_PP_CUBIC_FACES_5, 1, "R200_PP_CUBIC_FACES_5"},
141 {R200_PP_CUBIC_OFFSET_F1_5, 5, "R200_PP_CUBIC_OFFSET_F1_5"},
142 {RADEON_PP_TEX_SIZE_0, 2, "RADEON_PP_TEX_SIZE_0"},
143 {RADEON_PP_TEX_SIZE_1, 2, "RADEON_PP_TEX_SIZE_1"},
144 {RADEON_PP_TEX_SIZE_2, 2, "RADEON_PP_TEX_SIZE_2"},
145 {R200_RB3D_BLENDCOLOR, 3, "R200_RB3D_BLENDCOLOR"},
146 {R200_SE_TCL_POINT_SPRITE_CNTL, 1, "R200_SE_TCL_POINT_SPRITE_CNTL"},
147 {RADEON_PP_CUBIC_FACES_0, 1, "RADEON_PP_CUBIC_FACES_0"},
148 {RADEON_PP_CUBIC_OFFSET_T0_0, 5, "RADEON_PP_CUBIC_OFFSET_T0_0"},
149 {RADEON_PP_CUBIC_FACES_1, 1, "RADEON_PP_CUBIC_FACES_1"},
150 {RADEON_PP_CUBIC_OFFSET_T1_0, 5, "RADEON_PP_CUBIC_OFFSET_T1_0"},
151 {RADEON_PP_CUBIC_FACES_2, 1, "RADEON_PP_CUBIC_FACES_2"},
152 {RADEON_PP_CUBIC_OFFSET_T2_0, 5, "RADEON_PP_CUBIC_OFFSET_T2_0"},
153 {R200_PP_TRI_PERF, 2, "R200_PP_TRI_PERF"},
154 {R200_PP_TXCBLEND_8, 32, "R200_PP_AFS_0"}, /* 85 */
155 {R200_PP_TXCBLEND_0, 32, "R200_PP_AFS_1"},
156 {R200_PP_TFACTOR_0, 8, "R200_ATF_TFACTOR"},
157 {R200_PP_TXFILTER_0, 8, "R200_PP_TXCTLALL_0"},
158 {R200_PP_TXFILTER_1, 8, "R200_PP_TXCTLALL_1"},
159 {R200_PP_TXFILTER_2, 8, "R200_PP_TXCTLALL_2"},
160 {R200_PP_TXFILTER_3, 8, "R200_PP_TXCTLALL_3"},
161 {R200_PP_TXFILTER_4, 8, "R200_PP_TXCTLALL_4"},
162 {R200_PP_TXFILTER_5, 8, "R200_PP_TXCTLALL_5"},
163 {R200_VAP_PVS_CNTL_1, 2, "R200_VAP_PVS_CNTL"},
164 };
165
166 /* =============================================================
167 * State initialization
168 */
169
170 void r200PrintDirty( r200ContextPtr rmesa, const char *msg )
171 {
172 struct radeon_state_atom *l;
173
174 fprintf(stderr, msg);
175 fprintf(stderr, ": ");
176
177 foreach(l, &rmesa->radeon.hw.atomlist) {
178 if (l->dirty || rmesa->radeon.hw.all_dirty)
179 fprintf(stderr, "%s, ", l->name);
180 }
181
182 fprintf(stderr, "\n");
183 }
184
185 static int cmdpkt( r200ContextPtr rmesa, int id )
186 {
187 drm_radeon_cmd_header_t h;
188
189 if (rmesa->radeon.radeonScreen->kernel_mm) {
190 return CP_PACKET0(packet[id].start, packet[id].len - 1);
191 } else {
192 h.i = 0;
193 h.packet.cmd_type = RADEON_CMD_PACKET;
194 h.packet.packet_id = id;
195 }
196 return h.i;
197 }
198
199 static int cmdvec( int offset, int stride, int count )
200 {
201 drm_radeon_cmd_header_t h;
202 h.i = 0;
203 h.vectors.cmd_type = RADEON_CMD_VECTORS;
204 h.vectors.offset = offset;
205 h.vectors.stride = stride;
206 h.vectors.count = count;
207 return h.i;
208 }
209
210 /* warning: the count here is divided by 4 compared to other cmds
211 (so it doesn't exceed the char size)! */
212 static int cmdveclinear( int offset, int count )
213 {
214 drm_radeon_cmd_header_t h;
215 h.i = 0;
216 h.veclinear.cmd_type = RADEON_CMD_VECLINEAR;
217 h.veclinear.addr_lo = offset & 0xff;
218 h.veclinear.addr_hi = (offset & 0xff00) >> 8;
219 h.veclinear.count = count;
220 return h.i;
221 }
222
223 static int cmdscl( int offset, int stride, int count )
224 {
225 drm_radeon_cmd_header_t h;
226 h.i = 0;
227 h.scalars.cmd_type = RADEON_CMD_SCALARS;
228 h.scalars.offset = offset;
229 h.scalars.stride = stride;
230 h.scalars.count = count;
231 return h.i;
232 }
233
234 static int cmdscl2( int offset, int stride, int count )
235 {
236 drm_radeon_cmd_header_t h;
237 h.i = 0;
238 h.scalars.cmd_type = RADEON_CMD_SCALARS2;
239 h.scalars.offset = offset - 0x100;
240 h.scalars.stride = stride;
241 h.scalars.count = count;
242 return h.i;
243 }
244
245 #define CHECK( NM, FLAG ) \
246 static int check_##NM( GLcontext *ctx, struct radeon_state_atom *atom) \
247 { \
248 r200ContextPtr rmesa = R200_CONTEXT(ctx); \
249 (void) rmesa; \
250 return (FLAG) ? atom->cmd_size : 0; \
251 }
252
253 #define TCL_CHECK( NM, FLAG ) \
254 static int check_##NM( GLcontext *ctx, struct radeon_state_atom *atom) \
255 { \
256 r200ContextPtr rmesa = R200_CONTEXT(ctx); \
257 return (!rmesa->radeon.TclFallback && !ctx->VertexProgram._Enabled && (FLAG)) ? atom->cmd_size : 0; \
258 }
259
260 #define TCL_OR_VP_CHECK( NM, FLAG ) \
261 static int check_##NM( GLcontext *ctx, struct radeon_state_atom *atom ) \
262 { \
263 r200ContextPtr rmesa = R200_CONTEXT(ctx); \
264 return (!rmesa->radeon.TclFallback && (FLAG)) ? atom->cmd_size : 0; \
265 }
266
267 #define VP_CHECK( NM, FLAG ) \
268 static int check_##NM( GLcontext *ctx, struct radeon_state_atom *atom ) \
269 { \
270 r200ContextPtr rmesa = R200_CONTEXT(ctx); \
271 (void) atom; \
272 return (!rmesa->radeon.TclFallback && ctx->VertexProgram._Enabled && (FLAG)) ? atom->cmd_size : 0; \
273 }
274
275 CHECK( always, GL_TRUE )
276 CHECK( never, GL_FALSE )
277 CHECK( tex_any, ctx->Texture._EnabledUnits )
278 CHECK( tf, (ctx->Texture._EnabledUnits && !ctx->ATIFragmentShader._Enabled) );
279 CHECK( tex_pair, (rmesa->state.texture.unit[atom->idx].unitneeded | rmesa->state.texture.unit[atom->idx & ~1].unitneeded) )
280 CHECK( tex, rmesa->state.texture.unit[atom->idx].unitneeded )
281 CHECK( pix_zero, !ctx->ATIFragmentShader._Enabled )
282 CHECK( texenv, (rmesa->state.envneeded & (1 << (atom->idx)) && !ctx->ATIFragmentShader._Enabled) )
283 CHECK( afs_pass1, (ctx->ATIFragmentShader._Enabled && (ctx->ATIFragmentShader.Current->NumPasses > 1)) )
284 CHECK( afs, ctx->ATIFragmentShader._Enabled )
285 CHECK( tex_cube, rmesa->state.texture.unit[atom->idx].unitneeded & TEXTURE_CUBE_BIT )
286 TCL_CHECK( tcl_fog, ctx->Fog.Enabled )
287 TCL_CHECK( tcl, GL_TRUE )
288 TCL_CHECK( tcl_tex, rmesa->state.texture.unit[atom->idx].unitneeded )
289 TCL_CHECK( tcl_lighting, ctx->Light.Enabled )
290 TCL_CHECK( tcl_light, ctx->Light.Enabled && ctx->Light.Light[atom->idx].Enabled )
291 TCL_OR_VP_CHECK( tcl_ucp, (ctx->Transform.ClipPlanesEnabled & (1 << (atom->idx))) )
292 TCL_OR_VP_CHECK( tcl_or_vp, GL_TRUE )
293 VP_CHECK( tcl_vp, GL_TRUE )
294 VP_CHECK( tcl_vp_size, ctx->VertexProgram.Current->Base.NumNativeInstructions > 64 )
295 VP_CHECK( tcl_vpp_size, ctx->VertexProgram.Current->Base.NumNativeParameters > 96 )
296
297 #define OUT_VEC(hdr, data) do { \
298 drm_radeon_cmd_header_t h; \
299 h.i = hdr; \
300 OUT_BATCH(CP_PACKET0(RADEON_SE_TCL_STATE_FLUSH, 0)); \
301 OUT_BATCH(0); \
302 OUT_BATCH(CP_PACKET0(R200_SE_TCL_VECTOR_INDX_REG, 0)); \
303 OUT_BATCH(h.vectors.offset | (h.vectors.stride << RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT)); \
304 OUT_BATCH(CP_PACKET0_ONE(R200_SE_TCL_VECTOR_DATA_REG, h.vectors.count - 1)); \
305 OUT_BATCH_TABLE((data), h.vectors.count); \
306 } while(0)
307
308 #define OUT_VECLINEAR(hdr, data) do { \
309 drm_radeon_cmd_header_t h; \
310 uint32_t _start = h.veclinear.addr_lo | (h.veclinear.addr_hi << 8); \
311 uint32_t _sz = h.veclinear.count * 4; \
312 h.i = hdr; \
313 OUT_BATCH(CP_PACKET0(RADEON_SE_TCL_STATE_FLUSH, 0)); \
314 OUT_BATCH(0); \
315 OUT_BATCH(CP_PACKET0(R200_SE_TCL_VECTOR_INDX_REG, 0)); \
316 OUT_BATCH(_start | (1 << RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT)); \
317 OUT_BATCH(CP_PACKET0_ONE(R200_SE_TCL_VECTOR_DATA_REG, _sz - 1)); \
318 OUT_BATCH_TABLE((data), _sz); \
319 } while(0)
320
321 #define OUT_SCL(hdr, data) do { \
322 drm_radeon_cmd_header_t h; \
323 h.i = hdr; \
324 OUT_BATCH(CP_PACKET0(R200_SE_TCL_SCALAR_INDX_REG, 0)); \
325 OUT_BATCH((h.scalars.offset) | (h.scalars.stride << RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT)); \
326 OUT_BATCH(CP_PACKET0_ONE(R200_SE_TCL_SCALAR_DATA_REG, h.scalars.count - 1)); \
327 OUT_BATCH_TABLE((data), h.scalars.count); \
328 } while(0)
329
330 #define OUT_SCL2(hdr, data) do { \
331 drm_radeon_cmd_header_t h; \
332 h.i = hdr; \
333 OUT_BATCH(CP_PACKET0(R200_SE_TCL_SCALAR_INDX_REG, 0)); \
334 OUT_BATCH((h.scalars.offset + 0x100) | (h.scalars.stride << RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT)); \
335 OUT_BATCH(CP_PACKET0_ONE(R200_SE_TCL_SCALAR_DATA_REG, h.scalars.count - 1)); \
336 OUT_BATCH_TABLE((data), h.scalars.count); \
337 } while(0)
338
339 static void mtl_emit(GLcontext *ctx, struct radeon_state_atom *atom)
340 {
341 r200ContextPtr r200 = R200_CONTEXT(ctx);
342 BATCH_LOCALS(&r200->radeon);
343 uint32_t dwords = atom->cmd_size;
344
345 dwords += 6;
346 BEGIN_BATCH_NO_AUTOSTATE(dwords);
347 OUT_VEC(atom->cmd[MTL_CMD_0], (atom->cmd+1));
348 OUT_SCL2(atom->cmd[MTL_CMD_1], (atom->cmd + 18));
349 END_BATCH();
350 }
351
352 static void lit_emit(GLcontext *ctx, struct radeon_state_atom *atom)
353 {
354 r200ContextPtr r200 = R200_CONTEXT(ctx);
355 BATCH_LOCALS(&r200->radeon);
356 uint32_t dwords = atom->cmd_size;
357
358 dwords += 8;
359 BEGIN_BATCH_NO_AUTOSTATE(dwords);
360 OUT_VEC(atom->cmd[LIT_CMD_0], atom->cmd+1);
361 OUT_VEC(atom->cmd[LIT_CMD_1], atom->cmd+LIT_CMD_1+1);
362 END_BATCH();
363 }
364
365 static void ptp_emit(GLcontext *ctx, struct radeon_state_atom *atom)
366 {
367 r200ContextPtr r200 = R200_CONTEXT(ctx);
368 BATCH_LOCALS(&r200->radeon);
369 uint32_t dwords = atom->cmd_size;
370
371 dwords += 8;
372 BEGIN_BATCH_NO_AUTOSTATE(dwords);
373 OUT_VEC(atom->cmd[PTP_CMD_0], atom->cmd+1);
374 OUT_VEC(atom->cmd[PTP_CMD_1], atom->cmd+PTP_CMD_1+1);
375 END_BATCH();
376 }
377
378 static void veclinear_emit(GLcontext *ctx, struct radeon_state_atom *atom)
379 {
380 r200ContextPtr r200 = R200_CONTEXT(ctx);
381 BATCH_LOCALS(&r200->radeon);
382 uint32_t dwords = atom->cmd_size;
383
384 dwords += 4;
385 BEGIN_BATCH_NO_AUTOSTATE(dwords);
386 OUT_VECLINEAR(atom->cmd[0], atom->cmd+1);
387 END_BATCH();
388 }
389
390 static void scl_emit(GLcontext *ctx, struct radeon_state_atom *atom)
391 {
392 r200ContextPtr r200 = R200_CONTEXT(ctx);
393 BATCH_LOCALS(&r200->radeon);
394 uint32_t dwords = atom->cmd_size;
395
396 dwords += 2;
397 BEGIN_BATCH_NO_AUTOSTATE(dwords);
398 OUT_SCL(atom->cmd[0], atom->cmd+1);
399 END_BATCH();
400 }
401
402
403 static void vec_emit(GLcontext *ctx, struct radeon_state_atom *atom)
404 {
405 r200ContextPtr r200 = R200_CONTEXT(ctx);
406 BATCH_LOCALS(&r200->radeon);
407 uint32_t dwords = atom->cmd_size;
408
409 dwords += 4;
410 BEGIN_BATCH_NO_AUTOSTATE(dwords);
411 OUT_VEC(atom->cmd[0], atom->cmd+1);
412 END_BATCH();
413 }
414
415 static void ctx_emit(GLcontext *ctx, struct radeon_state_atom *atom)
416 {
417 r200ContextPtr r200 = R200_CONTEXT(ctx);
418 BATCH_LOCALS(&r200->radeon);
419 struct radeon_renderbuffer *rrb;
420 uint32_t cbpitch;
421 uint32_t zbpitch, depth_fmt;
422 uint32_t dwords = atom->cmd_size;
423
424 /* output the first 7 bytes of context */
425 BEGIN_BATCH_NO_AUTOSTATE(dwords+2+2);
426 OUT_BATCH_TABLE(atom->cmd, 5);
427
428 rrb = radeon_get_depthbuffer(&r200->radeon);
429 if (!rrb) {
430 OUT_BATCH(0);
431 OUT_BATCH(0);
432 } else {
433 zbpitch = (rrb->pitch / rrb->cpp);
434 if (r200->using_hyperz)
435 zbpitch |= RADEON_DEPTH_HYPERZ;
436 OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
437 OUT_BATCH(zbpitch);
438 if (rrb->cpp == 4)
439 depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
440 else
441 depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
442 atom->cmd[CTX_RB3D_ZSTENCILCNTL] &= ~RADEON_DEPTH_FORMAT_MASK;
443 atom->cmd[CTX_RB3D_ZSTENCILCNTL] |= depth_fmt;
444 }
445
446 OUT_BATCH(atom->cmd[CTX_RB3D_ZSTENCILCNTL]);
447 OUT_BATCH(atom->cmd[CTX_CMD_1]);
448 OUT_BATCH(atom->cmd[CTX_PP_CNTL]);
449
450 rrb = radeon_get_colorbuffer(&r200->radeon);
451 if (!rrb || !rrb->bo) {
452 OUT_BATCH(atom->cmd[CTX_RB3D_CNTL]);
453 OUT_BATCH(atom->cmd[CTX_RB3D_COLOROFFSET]);
454 } else {
455 atom->cmd[CTX_RB3D_CNTL] &= ~(0xf << 10);
456 if (rrb->cpp == 4)
457 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB8888;
458 else
459 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_RGB565;
460
461 OUT_BATCH(atom->cmd[CTX_RB3D_CNTL]);
462 OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
463 }
464
465 OUT_BATCH(atom->cmd[CTX_CMD_2]);
466
467 if (!rrb || !rrb->bo) {
468 OUT_BATCH(atom->cmd[CTX_RB3D_COLORPITCH]);
469 } else {
470 cbpitch = (rrb->pitch / rrb->cpp);
471 if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE)
472 cbpitch |= R200_COLOR_TILE_ENABLE;
473 OUT_BATCH(cbpitch);
474 }
475
476 if (atom->cmd_size == CTX_STATE_SIZE_NEWDRM)
477 OUT_BATCH_TABLE((atom->cmd + 14), 4);
478
479 END_BATCH();
480 }
481
482 static void ctx_emit_cs(GLcontext *ctx, struct radeon_state_atom *atom)
483 {
484 r200ContextPtr r200 = R200_CONTEXT(ctx);
485 BATCH_LOCALS(&r200->radeon);
486 struct radeon_renderbuffer *rrb, *drb;
487 uint32_t cbpitch = 0;
488 uint32_t zbpitch = 0;
489 uint32_t dwords = atom->cmd_size;
490 uint32_t depth_fmt;
491
492 rrb = radeon_get_colorbuffer(&r200->radeon);
493 if (!rrb || !rrb->bo) {
494 return;
495 }
496
497 atom->cmd[CTX_RB3D_CNTL] &= ~(0xf << 10);
498 if (rrb->cpp == 4)
499 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB8888;
500 else
501 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_RGB565;
502
503 cbpitch = (rrb->pitch / rrb->cpp);
504 if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE)
505 cbpitch |= R200_COLOR_TILE_ENABLE;
506
507 drb = radeon_get_depthbuffer(&r200->radeon);
508 if (drb) {
509 zbpitch = (drb->pitch / drb->cpp);
510 if (drb->cpp == 4)
511 depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
512 else
513 depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
514 atom->cmd[CTX_RB3D_ZSTENCILCNTL] &= ~RADEON_DEPTH_FORMAT_MASK;
515 atom->cmd[CTX_RB3D_ZSTENCILCNTL] |= depth_fmt;
516 }
517
518 dwords = 10;
519 if (drb)
520 dwords += 6;
521 if (rrb)
522 dwords += 6;
523
524 /* output the first 7 bytes of context */
525 BEGIN_BATCH_NO_AUTOSTATE(dwords);
526
527 /* In the CS case we need to split this up */
528 OUT_BATCH(CP_PACKET0(packet[0].start, 3));
529 OUT_BATCH_TABLE((atom->cmd + 1), 4);
530
531 if (drb) {
532 OUT_BATCH(CP_PACKET0(RADEON_RB3D_DEPTHOFFSET, 0));
533 OUT_BATCH_RELOC(0, drb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
534
535 OUT_BATCH(CP_PACKET0(RADEON_RB3D_DEPTHPITCH, 0));
536 OUT_BATCH(zbpitch);
537 }
538
539 OUT_BATCH(CP_PACKET0(RADEON_RB3D_ZSTENCILCNTL, 0));
540 OUT_BATCH(atom->cmd[CTX_RB3D_ZSTENCILCNTL]);
541 OUT_BATCH(CP_PACKET0(RADEON_PP_CNTL, 1));
542 OUT_BATCH(atom->cmd[CTX_PP_CNTL]);
543 OUT_BATCH(atom->cmd[CTX_RB3D_CNTL]);
544
545
546 if (rrb) {
547 OUT_BATCH(CP_PACKET0(RADEON_RB3D_COLOROFFSET, 0));
548 OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
549
550 OUT_BATCH(CP_PACKET0(RADEON_RB3D_COLORPITCH, 0));
551 OUT_BATCH(cbpitch);
552 }
553
554 if (atom->cmd_size == CTX_STATE_SIZE_NEWDRM) {
555 OUT_BATCH_TABLE((atom->cmd + 14), 4);
556 }
557
558 END_BATCH();
559 }
560
561 static void tex_emit(GLcontext *ctx, struct radeon_state_atom *atom)
562 {
563 r200ContextPtr r200 = R200_CONTEXT(ctx);
564 BATCH_LOCALS(&r200->radeon);
565 uint32_t dwords = atom->cmd_size;
566 int i = atom->idx;
567 radeonTexObj *t = r200->state.texture.unit[i].texobj;
568 radeon_mipmap_level *lvl;
569
570 if (t && t->mt && !t->image_override)
571 dwords += 2;
572 BEGIN_BATCH_NO_AUTOSTATE(dwords);
573 OUT_BATCH_TABLE(atom->cmd, 10);
574
575 if (t && t->mt && !t->image_override) {
576 if ((ctx->Texture.Unit[i]._ReallyEnabled & TEXTURE_CUBE_BIT)) {
577 lvl = &t->mt->levels[0];
578 OUT_BATCH_RELOC(lvl->faces[5].offset, t->mt->bo, lvl->faces[5].offset,
579 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
580 } else {
581 OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, 0,
582 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
583 }
584 } else if (!t) {
585 /* workaround for old CS mechanism */
586 OUT_BATCH(r200->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP]);
587 } else {
588 OUT_BATCH(t->override_offset);
589 }
590
591 END_BATCH();
592 }
593
594 static void tex_emit_cs(GLcontext *ctx, struct radeon_state_atom *atom)
595 {
596 r200ContextPtr r200 = R200_CONTEXT(ctx);
597 BATCH_LOCALS(&r200->radeon);
598 uint32_t dwords = atom->cmd_size;
599 int i = atom->idx;
600 radeonTexObj *t = r200->state.texture.unit[i].texobj;
601 radeon_mipmap_level *lvl;
602 int hastexture = 1;
603
604 if (!t)
605 hastexture = 0;
606 else {
607 if (!t->mt && !t->bo)
608 hastexture = 0;
609 }
610
611 dwords += 2;
612 if (hastexture)
613 dwords += 2;
614 else
615 dwords -= 2;
616 BEGIN_BATCH_NO_AUTOSTATE(dwords);
617
618 OUT_BATCH(CP_PACKET0(R200_PP_TXFILTER_0 + (24 * i), 7));
619 OUT_BATCH_TABLE((atom->cmd + 1), 8);
620
621 if (hastexture) {
622 OUT_BATCH(CP_PACKET0(R200_PP_TXOFFSET_0 + (24 * i), 0));
623 if (t->mt && !t->image_override) {
624 if ((ctx->Texture.Unit[i]._ReallyEnabled & TEXTURE_CUBE_BIT)) {
625 lvl = &t->mt->levels[0];
626 OUT_BATCH_RELOC(lvl->faces[5].offset, t->mt->bo, lvl->faces[5].offset,
627 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
628 } else {
629 OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, 0,
630 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
631 }
632 } else {
633 if (t->bo)
634 OUT_BATCH_RELOC(t->tile_bits, t->bo, 0,
635 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
636 }
637 }
638 END_BATCH();
639 }
640
641
642 static void cube_emit(GLcontext *ctx, struct radeon_state_atom *atom)
643 {
644 r200ContextPtr r200 = R200_CONTEXT(ctx);
645 BATCH_LOCALS(&r200->radeon);
646 uint32_t dwords = atom->cmd_size;
647 int i = atom->idx;
648 radeonTexObj *t = r200->state.texture.unit[i].texobj;
649 GLuint size;
650
651 BEGIN_BATCH_NO_AUTOSTATE(dwords + (2 * 5));
652 OUT_BATCH_TABLE(atom->cmd, 3);
653
654 if (t && !t->image_override) {
655 size = t->mt->totalsize / 6;
656 OUT_BATCH_RELOC(0, t->mt->bo, size, RADEON_GEM_DOMAIN_VRAM, 0, 0);
657 OUT_BATCH_RELOC(0, t->mt->bo, size * 2, RADEON_GEM_DOMAIN_VRAM, 0, 0);
658 OUT_BATCH_RELOC(0, t->mt->bo, size * 3, RADEON_GEM_DOMAIN_VRAM, 0, 0);
659 OUT_BATCH_RELOC(0, t->mt->bo, size * 4, RADEON_GEM_DOMAIN_VRAM, 0, 0);
660 OUT_BATCH_RELOC(0, t->mt->bo, size * 5, RADEON_GEM_DOMAIN_VRAM, 0, 0);
661 }
662 END_BATCH();
663 }
664
665 /* Initialize the context's hardware state.
666 */
667 void r200InitState( r200ContextPtr rmesa )
668 {
669 GLcontext *ctx = rmesa->radeon.glCtx;
670 GLuint i;
671
672 rmesa->radeon.state.color.clear = 0x00000000;
673
674 switch ( ctx->Visual.depthBits ) {
675 case 16:
676 rmesa->radeon.state.depth.clear = 0x0000ffff;
677 rmesa->radeon.state.stencil.clear = 0x00000000;
678 break;
679 case 24:
680 default:
681 rmesa->radeon.state.depth.clear = 0x00ffffff;
682 rmesa->radeon.state.stencil.clear = 0xffff0000;
683 break;
684 }
685
686 rmesa->radeon.Fallback = 0;
687
688 rmesa->radeon.hw.max_state_size = 0;
689
690 #define ALLOC_STATE( ATOM, CHK, SZ, NM, IDX ) \
691 do { \
692 rmesa->hw.ATOM.cmd_size = SZ; \
693 rmesa->hw.ATOM.cmd = (GLuint *)CALLOC(SZ * sizeof(int)); \
694 rmesa->hw.ATOM.lastcmd = (GLuint *)CALLOC(SZ * sizeof(int)); \
695 rmesa->hw.ATOM.name = NM; \
696 rmesa->hw.ATOM.idx = IDX; \
697 rmesa->hw.ATOM.check = check_##CHK; \
698 rmesa->hw.ATOM.dirty = GL_FALSE; \
699 rmesa->radeon.hw.max_state_size += SZ * sizeof(int); \
700 } while (0)
701
702
703 /* Allocate state buffers:
704 */
705 if (rmesa->radeon.radeonScreen->drmSupportsBlendColor)
706 ALLOC_STATE( ctx, always, CTX_STATE_SIZE_NEWDRM, "CTX/context", 0 );
707 else
708 ALLOC_STATE( ctx, always, CTX_STATE_SIZE_OLDDRM, "CTX/context", 0 );
709
710 if (rmesa->radeon.radeonScreen->kernel_mm)
711 rmesa->hw.ctx.emit = ctx_emit_cs;
712 else
713 rmesa->hw.ctx.emit = ctx_emit;
714 ALLOC_STATE( set, always, SET_STATE_SIZE, "SET/setup", 0 );
715 ALLOC_STATE( lin, always, LIN_STATE_SIZE, "LIN/line", 0 );
716 ALLOC_STATE( msk, always, MSK_STATE_SIZE, "MSK/mask", 0 );
717 ALLOC_STATE( vpt, always, VPT_STATE_SIZE, "VPT/viewport", 0 );
718 ALLOC_STATE( vtx, always, VTX_STATE_SIZE, "VTX/vertex", 0 );
719 ALLOC_STATE( vap, always, VAP_STATE_SIZE, "VAP/vap", 0 );
720 ALLOC_STATE( vte, always, VTE_STATE_SIZE, "VTE/vte", 0 );
721 ALLOC_STATE( msc, always, MSC_STATE_SIZE, "MSC/misc", 0 );
722 ALLOC_STATE( cst, always, CST_STATE_SIZE, "CST/constant", 0 );
723 ALLOC_STATE( zbs, always, ZBS_STATE_SIZE, "ZBS/zbias", 0 );
724 ALLOC_STATE( tf, tf, TF_STATE_SIZE, "TF/tfactor", 0 );
725 if (rmesa->radeon.radeonScreen->drmSupportsFragShader) {
726 if (rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_R200) {
727 /* make sure texture units 0/1 are emitted pair-wise for r200 t0 hang workaround */
728 ALLOC_STATE( tex[0], tex_pair, TEX_STATE_SIZE_NEWDRM, "TEX/tex-0", 0 );
729 ALLOC_STATE( tex[1], tex_pair, TEX_STATE_SIZE_NEWDRM, "TEX/tex-1", 1 );
730 ALLOC_STATE( tam, tex_any, TAM_STATE_SIZE, "TAM/tam", 0 );
731 }
732 else {
733 ALLOC_STATE( tex[0], tex, TEX_STATE_SIZE_NEWDRM, "TEX/tex-0", 0 );
734 ALLOC_STATE( tex[1], tex, TEX_STATE_SIZE_NEWDRM, "TEX/tex-1", 1 );
735 ALLOC_STATE( tam, never, TAM_STATE_SIZE, "TAM/tam", 0 );
736 }
737 ALLOC_STATE( tex[2], tex, TEX_STATE_SIZE_NEWDRM, "TEX/tex-2", 2 );
738 ALLOC_STATE( tex[3], tex, TEX_STATE_SIZE_NEWDRM, "TEX/tex-3", 3 );
739 ALLOC_STATE( tex[4], tex, TEX_STATE_SIZE_NEWDRM, "TEX/tex-4", 4 );
740 ALLOC_STATE( tex[5], tex, TEX_STATE_SIZE_NEWDRM, "TEX/tex-5", 5 );
741 ALLOC_STATE( atf, afs, ATF_STATE_SIZE, "ATF/tfactor", 0 );
742 ALLOC_STATE( afs[0], afs_pass1, AFS_STATE_SIZE, "AFS/afsinst-0", 0 );
743 ALLOC_STATE( afs[1], afs, AFS_STATE_SIZE, "AFS/afsinst-1", 1 );
744 }
745 else {
746 if (rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_R200) {
747 ALLOC_STATE( tex[0], tex_pair, TEX_STATE_SIZE_OLDDRM, "TEX/tex-0", 0 );
748 ALLOC_STATE( tex[1], tex_pair, TEX_STATE_SIZE_OLDDRM, "TEX/tex-1", 1 );
749 ALLOC_STATE( tam, tex_any, TAM_STATE_SIZE, "TAM/tam", 0 );
750 }
751 else {
752 ALLOC_STATE( tex[0], tex, TEX_STATE_SIZE_OLDDRM, "TEX/tex-0", 0 );
753 ALLOC_STATE( tex[1], tex, TEX_STATE_SIZE_OLDDRM, "TEX/tex-1", 1 );
754 ALLOC_STATE( tam, never, TAM_STATE_SIZE, "TAM/tam", 0 );
755 }
756 ALLOC_STATE( tex[2], tex, TEX_STATE_SIZE_OLDDRM, "TEX/tex-2", 2 );
757 ALLOC_STATE( tex[3], tex, TEX_STATE_SIZE_OLDDRM, "TEX/tex-3", 3 );
758 ALLOC_STATE( tex[4], tex, TEX_STATE_SIZE_OLDDRM, "TEX/tex-4", 4 );
759 ALLOC_STATE( tex[5], tex, TEX_STATE_SIZE_OLDDRM, "TEX/tex-5", 5 );
760 ALLOC_STATE( atf, never, ATF_STATE_SIZE, "TF/tfactor", 0 );
761 ALLOC_STATE( afs[0], never, AFS_STATE_SIZE, "AFS/afsinst-0", 0 );
762 ALLOC_STATE( afs[1], never, AFS_STATE_SIZE, "AFS/afsinst-1", 1 );
763 }
764
765 for (i = 0; i < 5; i++)
766 if (rmesa->radeon.radeonScreen->kernel_mm)
767 rmesa->hw.tex[i].emit = tex_emit_cs;
768 else
769 rmesa->hw.tex[i].emit = tex_emit;
770 if (rmesa->radeon.radeonScreen->drmSupportsCubeMapsR200) {
771 ALLOC_STATE( cube[0], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-0", 0 );
772 ALLOC_STATE( cube[1], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-1", 1 );
773 ALLOC_STATE( cube[2], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-2", 2 );
774 ALLOC_STATE( cube[3], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-3", 3 );
775 ALLOC_STATE( cube[4], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-4", 4 );
776 ALLOC_STATE( cube[5], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-5", 5 );
777 for (i = 0; i < 5; i++)
778 rmesa->hw.cube[i].emit = cube_emit;
779 }
780 else {
781 ALLOC_STATE( cube[0], never, CUBE_STATE_SIZE, "CUBE/tex-0", 0 );
782 ALLOC_STATE( cube[1], never, CUBE_STATE_SIZE, "CUBE/tex-1", 1 );
783 ALLOC_STATE( cube[2], never, CUBE_STATE_SIZE, "CUBE/tex-2", 2 );
784 ALLOC_STATE( cube[3], never, CUBE_STATE_SIZE, "CUBE/tex-3", 3 );
785 ALLOC_STATE( cube[4], never, CUBE_STATE_SIZE, "CUBE/tex-4", 4 );
786 ALLOC_STATE( cube[5], never, CUBE_STATE_SIZE, "CUBE/tex-5", 5 );
787 }
788
789 if (rmesa->radeon.radeonScreen->drmSupportsVertexProgram) {
790 ALLOC_STATE( pvs, tcl_vp, PVS_STATE_SIZE, "PVS/pvscntl", 0 );
791 ALLOC_STATE( vpi[0], tcl_vp, VPI_STATE_SIZE, "VP/vertexprog-0", 0 );
792 ALLOC_STATE( vpi[1], tcl_vp_size, VPI_STATE_SIZE, "VP/vertexprog-1", 1 );
793 ALLOC_STATE( vpp[0], tcl_vp, VPP_STATE_SIZE, "VPP/vertexparam-0", 0 );
794 ALLOC_STATE( vpp[1], tcl_vpp_size, VPP_STATE_SIZE, "VPP/vertexparam-1", 1 );
795 }
796 else {
797 ALLOC_STATE( pvs, never, PVS_STATE_SIZE, "PVS/pvscntl", 0 );
798 ALLOC_STATE( vpi[0], never, VPI_STATE_SIZE, "VP/vertexprog-0", 0 );
799 ALLOC_STATE( vpi[1], never, VPI_STATE_SIZE, "VP/vertexprog-1", 1 );
800 ALLOC_STATE( vpp[0], never, VPP_STATE_SIZE, "VPP/vertexparam-0", 0 );
801 ALLOC_STATE( vpp[1], never, VPP_STATE_SIZE, "VPP/vertexparam-1", 1 );
802 }
803 /* FIXME: this atom has two commands, we need only one (ucp_vert_blend) for vp */
804 ALLOC_STATE( tcl, tcl_or_vp, TCL_STATE_SIZE, "TCL/tcl", 0 );
805 ALLOC_STATE( msl, tcl, MSL_STATE_SIZE, "MSL/matrix-select", 0 );
806 ALLOC_STATE( tcg, tcl, TCG_STATE_SIZE, "TCG/texcoordgen", 0 );
807 ALLOC_STATE( mtl[0], tcl_lighting, MTL_STATE_SIZE, "MTL0/material0", 0 );
808 ALLOC_STATE( mtl[1], tcl_lighting, MTL_STATE_SIZE, "MTL1/material1", 1 );
809 ALLOC_STATE( grd, tcl_or_vp, GRD_STATE_SIZE, "GRD/guard-band", 0 );
810 ALLOC_STATE( fog, tcl_fog, FOG_STATE_SIZE, "FOG/fog", 0 );
811 ALLOC_STATE( glt, tcl_lighting, GLT_STATE_SIZE, "GLT/light-global", 0 );
812 ALLOC_STATE( eye, tcl_lighting, EYE_STATE_SIZE, "EYE/eye-vector", 0 );
813 ALLOC_STATE( mat[R200_MTX_MV], tcl, MAT_STATE_SIZE, "MAT/modelview", 0 );
814 ALLOC_STATE( mat[R200_MTX_IMV], tcl, MAT_STATE_SIZE, "MAT/it-modelview", 0 );
815 ALLOC_STATE( mat[R200_MTX_MVP], tcl, MAT_STATE_SIZE, "MAT/modelproject", 0 );
816 ALLOC_STATE( mat[R200_MTX_TEX0], tcl_tex, MAT_STATE_SIZE, "MAT/texmat0", 0 );
817 ALLOC_STATE( mat[R200_MTX_TEX1], tcl_tex, MAT_STATE_SIZE, "MAT/texmat1", 1 );
818 ALLOC_STATE( mat[R200_MTX_TEX2], tcl_tex, MAT_STATE_SIZE, "MAT/texmat2", 2 );
819 ALLOC_STATE( mat[R200_MTX_TEX3], tcl_tex, MAT_STATE_SIZE, "MAT/texmat3", 3 );
820 ALLOC_STATE( mat[R200_MTX_TEX4], tcl_tex, MAT_STATE_SIZE, "MAT/texmat4", 4 );
821 ALLOC_STATE( mat[R200_MTX_TEX5], tcl_tex, MAT_STATE_SIZE, "MAT/texmat5", 5 );
822 ALLOC_STATE( ucp[0], tcl_ucp, UCP_STATE_SIZE, "UCP/userclip-0", 0 );
823 ALLOC_STATE( ucp[1], tcl_ucp, UCP_STATE_SIZE, "UCP/userclip-1", 1 );
824 ALLOC_STATE( ucp[2], tcl_ucp, UCP_STATE_SIZE, "UCP/userclip-2", 2 );
825 ALLOC_STATE( ucp[3], tcl_ucp, UCP_STATE_SIZE, "UCP/userclip-3", 3 );
826 ALLOC_STATE( ucp[4], tcl_ucp, UCP_STATE_SIZE, "UCP/userclip-4", 4 );
827 ALLOC_STATE( ucp[5], tcl_ucp, UCP_STATE_SIZE, "UCP/userclip-5", 5 );
828 ALLOC_STATE( lit[0], tcl_light, LIT_STATE_SIZE, "LIT/light-0", 0 );
829 ALLOC_STATE( lit[1], tcl_light, LIT_STATE_SIZE, "LIT/light-1", 1 );
830 ALLOC_STATE( lit[2], tcl_light, LIT_STATE_SIZE, "LIT/light-2", 2 );
831 ALLOC_STATE( lit[3], tcl_light, LIT_STATE_SIZE, "LIT/light-3", 3 );
832 ALLOC_STATE( lit[4], tcl_light, LIT_STATE_SIZE, "LIT/light-4", 4 );
833 ALLOC_STATE( lit[5], tcl_light, LIT_STATE_SIZE, "LIT/light-5", 5 );
834 ALLOC_STATE( lit[6], tcl_light, LIT_STATE_SIZE, "LIT/light-6", 6 );
835 ALLOC_STATE( lit[7], tcl_light, LIT_STATE_SIZE, "LIT/light-7", 7 );
836 ALLOC_STATE( pix[0], pix_zero, PIX_STATE_SIZE, "PIX/pixstage-0", 0 );
837 ALLOC_STATE( pix[1], texenv, PIX_STATE_SIZE, "PIX/pixstage-1", 1 );
838 ALLOC_STATE( pix[2], texenv, PIX_STATE_SIZE, "PIX/pixstage-2", 2 );
839 ALLOC_STATE( pix[3], texenv, PIX_STATE_SIZE, "PIX/pixstage-3", 3 );
840 ALLOC_STATE( pix[4], texenv, PIX_STATE_SIZE, "PIX/pixstage-4", 4 );
841 ALLOC_STATE( pix[5], texenv, PIX_STATE_SIZE, "PIX/pixstage-5", 5 );
842 if (rmesa->radeon.radeonScreen->drmSupportsTriPerf) {
843 ALLOC_STATE( prf, always, PRF_STATE_SIZE, "PRF/performance-tri", 0 );
844 }
845 else {
846 ALLOC_STATE( prf, never, PRF_STATE_SIZE, "PRF/performance-tri", 0 );
847 }
848 if (rmesa->radeon.radeonScreen->drmSupportsPointSprites) {
849 ALLOC_STATE( spr, always, SPR_STATE_SIZE, "SPR/pointsprite", 0 );
850 ALLOC_STATE( ptp, tcl, PTP_STATE_SIZE, "PTP/pointparams", 0 );
851 }
852 else {
853 ALLOC_STATE (spr, never, SPR_STATE_SIZE, "SPR/pointsprite", 0 );
854 ALLOC_STATE (ptp, never, PTP_STATE_SIZE, "PTP/pointparams", 0 );
855 }
856
857 r200SetUpAtomList( rmesa );
858
859 /* Fill in the packet headers:
860 */
861 rmesa->hw.ctx.cmd[CTX_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_MISC);
862 rmesa->hw.ctx.cmd[CTX_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_PP_CNTL);
863 rmesa->hw.ctx.cmd[CTX_CMD_2] = cmdpkt(rmesa, RADEON_EMIT_RB3D_COLORPITCH);
864 if (rmesa->radeon.radeonScreen->drmSupportsBlendColor)
865 rmesa->hw.ctx.cmd[CTX_CMD_3] = cmdpkt(rmesa, R200_EMIT_RB3D_BLENDCOLOR);
866 rmesa->hw.lin.cmd[LIN_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_RE_LINE_PATTERN);
867 rmesa->hw.lin.cmd[LIN_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_SE_LINE_WIDTH);
868 rmesa->hw.msk.cmd[MSK_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_RB3D_STENCILREFMASK);
869 rmesa->hw.vpt.cmd[VPT_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_SE_VPORT_XSCALE);
870 rmesa->hw.set.cmd[SET_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_SE_CNTL);
871 rmesa->hw.msc.cmd[MSC_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_RE_MISC);
872 rmesa->hw.cst.cmd[CST_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_CNTL_X);
873 rmesa->hw.cst.cmd[CST_CMD_1] = cmdpkt(rmesa, R200_EMIT_RB3D_DEPTHXY_OFFSET);
874 rmesa->hw.cst.cmd[CST_CMD_2] = cmdpkt(rmesa, R200_EMIT_RE_AUX_SCISSOR_CNTL);
875 rmesa->hw.cst.cmd[CST_CMD_3] = cmdpkt(rmesa, R200_EMIT_RE_SCISSOR_TL_0);
876 rmesa->hw.cst.cmd[CST_CMD_4] = cmdpkt(rmesa, R200_EMIT_SE_VAP_CNTL_STATUS);
877 rmesa->hw.cst.cmd[CST_CMD_5] = cmdpkt(rmesa, R200_EMIT_RE_POINTSIZE);
878 rmesa->hw.cst.cmd[CST_CMD_6] = cmdpkt(rmesa, R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0);
879 rmesa->hw.tam.cmd[TAM_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TAM_DEBUG3);
880 rmesa->hw.tf.cmd[TF_CMD_0] = cmdpkt(rmesa, R200_EMIT_TFACTOR_0);
881 if (rmesa->radeon.radeonScreen->drmSupportsFragShader) {
882 rmesa->hw.atf.cmd[ATF_CMD_0] = cmdpkt(rmesa, R200_EMIT_ATF_TFACTOR);
883 rmesa->hw.tex[0].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCTLALL_0);
884 rmesa->hw.tex[0].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_0);
885 rmesa->hw.tex[1].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCTLALL_1);
886 rmesa->hw.tex[1].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_1);
887 rmesa->hw.tex[2].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCTLALL_2);
888 rmesa->hw.tex[2].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_2);
889 rmesa->hw.tex[3].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCTLALL_3);
890 rmesa->hw.tex[3].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_3);
891 rmesa->hw.tex[4].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCTLALL_4);
892 rmesa->hw.tex[4].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_4);
893 rmesa->hw.tex[5].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCTLALL_5);
894 rmesa->hw.tex[5].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_5);
895 } else {
896 rmesa->hw.tex[0].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXFILTER_0);
897 rmesa->hw.tex[0].cmd[TEX_CMD_1_OLDDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_0);
898 rmesa->hw.tex[1].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXFILTER_1);
899 rmesa->hw.tex[1].cmd[TEX_CMD_1_OLDDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_1);
900 rmesa->hw.tex[2].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXFILTER_2);
901 rmesa->hw.tex[2].cmd[TEX_CMD_1_OLDDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_2);
902 rmesa->hw.tex[3].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXFILTER_3);
903 rmesa->hw.tex[3].cmd[TEX_CMD_1_OLDDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_3);
904 rmesa->hw.tex[4].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXFILTER_4);
905 rmesa->hw.tex[4].cmd[TEX_CMD_1_OLDDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_4);
906 rmesa->hw.tex[5].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXFILTER_5);
907 rmesa->hw.tex[5].cmd[TEX_CMD_1_OLDDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_5);
908 }
909 rmesa->hw.afs[0].cmd[AFS_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_AFS_0);
910 rmesa->hw.afs[1].cmd[AFS_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_AFS_1);
911 rmesa->hw.pvs.cmd[PVS_CMD_0] = cmdpkt(rmesa, R200_EMIT_VAP_PVS_CNTL);
912 rmesa->hw.cube[0].cmd[CUBE_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_FACES_0);
913 rmesa->hw.cube[0].cmd[CUBE_CMD_1] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_OFFSETS_0);
914 rmesa->hw.cube[1].cmd[CUBE_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_FACES_1);
915 rmesa->hw.cube[1].cmd[CUBE_CMD_1] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_OFFSETS_1);
916 rmesa->hw.cube[2].cmd[CUBE_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_FACES_2);
917 rmesa->hw.cube[2].cmd[CUBE_CMD_1] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_OFFSETS_2);
918 rmesa->hw.cube[3].cmd[CUBE_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_FACES_3);
919 rmesa->hw.cube[3].cmd[CUBE_CMD_1] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_OFFSETS_3);
920 rmesa->hw.cube[4].cmd[CUBE_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_FACES_4);
921 rmesa->hw.cube[4].cmd[CUBE_CMD_1] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_OFFSETS_4);
922 rmesa->hw.cube[5].cmd[CUBE_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_FACES_5);
923 rmesa->hw.cube[5].cmd[CUBE_CMD_1] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_OFFSETS_5);
924 rmesa->hw.pix[0].cmd[PIX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCBLEND_0);
925 rmesa->hw.pix[1].cmd[PIX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCBLEND_1);
926 rmesa->hw.pix[2].cmd[PIX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCBLEND_2);
927 rmesa->hw.pix[3].cmd[PIX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCBLEND_3);
928 rmesa->hw.pix[4].cmd[PIX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCBLEND_4);
929 rmesa->hw.pix[5].cmd[PIX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCBLEND_5);
930 rmesa->hw.zbs.cmd[ZBS_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_SE_ZBIAS_FACTOR);
931 rmesa->hw.tcl.cmd[TCL_CMD_0] = cmdpkt(rmesa, R200_EMIT_TCL_LIGHT_MODEL_CTL_0);
932 rmesa->hw.tcl.cmd[TCL_CMD_1] = cmdpkt(rmesa, R200_EMIT_TCL_UCP_VERT_BLEND_CTL);
933 rmesa->hw.tcg.cmd[TCG_CMD_0] = cmdpkt(rmesa, R200_EMIT_TEX_PROC_CTL_2);
934 rmesa->hw.msl.cmd[MSL_CMD_0] = cmdpkt(rmesa, R200_EMIT_MATRIX_SELECT_0);
935 rmesa->hw.vap.cmd[VAP_CMD_0] = cmdpkt(rmesa, R200_EMIT_VAP_CTL);
936 rmesa->hw.vtx.cmd[VTX_CMD_0] = cmdpkt(rmesa, R200_EMIT_VTX_FMT_0);
937 rmesa->hw.vtx.cmd[VTX_CMD_1] = cmdpkt(rmesa, R200_EMIT_OUTPUT_VTX_COMP_SEL);
938 rmesa->hw.vtx.cmd[VTX_CMD_2] = cmdpkt(rmesa, R200_EMIT_SE_VTX_STATE_CNTL);
939 rmesa->hw.vte.cmd[VTE_CMD_0] = cmdpkt(rmesa, R200_EMIT_VTE_CNTL);
940 rmesa->hw.prf.cmd[PRF_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TRI_PERF_CNTL);
941 rmesa->hw.spr.cmd[SPR_CMD_0] = cmdpkt(rmesa, R200_EMIT_TCL_POINT_SPRITE_CNTL);
942 if (rmesa->radeon.radeonScreen->kernel_mm) {
943 rmesa->hw.mtl[0].emit = mtl_emit;
944 rmesa->hw.mtl[1].emit = mtl_emit;
945
946 rmesa->hw.vpi[0].emit = veclinear_emit;
947 rmesa->hw.vpi[1].emit = veclinear_emit;
948 rmesa->hw.vpp[0].emit = veclinear_emit;
949 rmesa->hw.vpp[1].emit = veclinear_emit;
950
951 rmesa->hw.grd.emit = scl_emit;
952 rmesa->hw.fog.emit = vec_emit;
953 rmesa->hw.glt.emit = vec_emit;
954 rmesa->hw.eye.emit = vec_emit;
955
956 for (i = R200_MTX_MV; i <= R200_MTX_TEX5; i++)
957 rmesa->hw.mat[i].emit = vec_emit;
958
959 for (i = 0; i < 8; i++)
960 rmesa->hw.lit[i].emit = lit_emit;
961
962 for (i = 0; i < 6; i++)
963 rmesa->hw.ucp[i].emit = vec_emit;
964
965 rmesa->hw.ptp.emit = ptp_emit;
966 }
967
968
969
970 rmesa->hw.mtl[0].cmd[MTL_CMD_0] =
971 cmdvec( R200_VS_MAT_0_EMISS, 1, 16 );
972 rmesa->hw.mtl[0].cmd[MTL_CMD_1] =
973 cmdscl2( R200_SS_MAT_0_SHININESS, 1, 1 );
974 rmesa->hw.mtl[1].cmd[MTL_CMD_0] =
975 cmdvec( R200_VS_MAT_1_EMISS, 1, 16 );
976 rmesa->hw.mtl[1].cmd[MTL_CMD_1] =
977 cmdscl2( R200_SS_MAT_1_SHININESS, 1, 1 );
978
979 rmesa->hw.vpi[0].cmd[VPI_CMD_0] =
980 cmdveclinear( R200_PVS_PROG0, 64 );
981 rmesa->hw.vpi[1].cmd[VPI_CMD_0] =
982 cmdveclinear( R200_PVS_PROG1, 64 );
983 rmesa->hw.vpp[0].cmd[VPP_CMD_0] =
984 cmdveclinear( R200_PVS_PARAM0, 96 );
985 rmesa->hw.vpp[1].cmd[VPP_CMD_0] =
986 cmdveclinear( R200_PVS_PARAM1, 96 );
987
988 rmesa->hw.grd.cmd[GRD_CMD_0] =
989 cmdscl( R200_SS_VERT_GUARD_CLIP_ADJ_ADDR, 1, 4 );
990 rmesa->hw.fog.cmd[FOG_CMD_0] =
991 cmdvec( R200_VS_FOG_PARAM_ADDR, 1, 4 );
992 rmesa->hw.glt.cmd[GLT_CMD_0] =
993 cmdvec( R200_VS_GLOBAL_AMBIENT_ADDR, 1, 4 );
994 rmesa->hw.eye.cmd[EYE_CMD_0] =
995 cmdvec( R200_VS_EYE_VECTOR_ADDR, 1, 4 );
996
997 rmesa->hw.mat[R200_MTX_MV].cmd[MAT_CMD_0] =
998 cmdvec( R200_VS_MATRIX_0_MV, 1, 16);
999 rmesa->hw.mat[R200_MTX_IMV].cmd[MAT_CMD_0] =
1000 cmdvec( R200_VS_MATRIX_1_INV_MV, 1, 16);
1001 rmesa->hw.mat[R200_MTX_MVP].cmd[MAT_CMD_0] =
1002 cmdvec( R200_VS_MATRIX_2_MVP, 1, 16);
1003 rmesa->hw.mat[R200_MTX_TEX0].cmd[MAT_CMD_0] =
1004 cmdvec( R200_VS_MATRIX_3_TEX0, 1, 16);
1005 rmesa->hw.mat[R200_MTX_TEX1].cmd[MAT_CMD_0] =
1006 cmdvec( R200_VS_MATRIX_4_TEX1, 1, 16);
1007 rmesa->hw.mat[R200_MTX_TEX2].cmd[MAT_CMD_0] =
1008 cmdvec( R200_VS_MATRIX_5_TEX2, 1, 16);
1009 rmesa->hw.mat[R200_MTX_TEX3].cmd[MAT_CMD_0] =
1010 cmdvec( R200_VS_MATRIX_6_TEX3, 1, 16);
1011 rmesa->hw.mat[R200_MTX_TEX4].cmd[MAT_CMD_0] =
1012 cmdvec( R200_VS_MATRIX_7_TEX4, 1, 16);
1013 rmesa->hw.mat[R200_MTX_TEX5].cmd[MAT_CMD_0] =
1014 cmdvec( R200_VS_MATRIX_8_TEX5, 1, 16);
1015
1016 for (i = 0 ; i < 8; i++) {
1017 rmesa->hw.lit[i].cmd[LIT_CMD_0] =
1018 cmdvec( R200_VS_LIGHT_AMBIENT_ADDR + i, 8, 24 );
1019 rmesa->hw.lit[i].cmd[LIT_CMD_1] =
1020 cmdscl( R200_SS_LIGHT_DCD_ADDR + i, 8, 7 );
1021 }
1022
1023 for (i = 0 ; i < 6; i++) {
1024 rmesa->hw.ucp[i].cmd[UCP_CMD_0] =
1025 cmdvec( R200_VS_UCP_ADDR + i, 1, 4 );
1026 }
1027
1028 rmesa->hw.ptp.cmd[PTP_CMD_0] =
1029 cmdvec( R200_VS_PNT_SPRITE_VPORT_SCALE, 1, 4 );
1030 rmesa->hw.ptp.cmd[PTP_CMD_1] =
1031 cmdvec( R200_VS_PNT_SPRITE_ATT_CONST, 1, 12 );
1032
1033 /* Initial Harware state:
1034 */
1035 rmesa->hw.ctx.cmd[CTX_PP_MISC] = (R200_ALPHA_TEST_PASS
1036 /* | R200_RIGHT_HAND_CUBE_OGL*/);
1037
1038 rmesa->hw.ctx.cmd[CTX_PP_FOG_COLOR] = (R200_FOG_VERTEX |
1039 R200_FOG_USE_SPEC_ALPHA);
1040
1041 rmesa->hw.ctx.cmd[CTX_RE_SOLID_COLOR] = 0x00000000;
1042
1043 rmesa->hw.ctx.cmd[CTX_RB3D_BLENDCNTL] = (R200_COMB_FCN_ADD_CLAMP |
1044 (R200_BLEND_GL_ONE << R200_SRC_BLEND_SHIFT) |
1045 (R200_BLEND_GL_ZERO << R200_DST_BLEND_SHIFT));
1046
1047 if (rmesa->radeon.radeonScreen->drmSupportsBlendColor) {
1048 rmesa->hw.ctx.cmd[CTX_RB3D_BLENDCOLOR] = 0x00000000;
1049 rmesa->hw.ctx.cmd[CTX_RB3D_ABLENDCNTL] = (R200_COMB_FCN_ADD_CLAMP |
1050 (R200_BLEND_GL_ONE << R200_SRC_BLEND_SHIFT) |
1051 (R200_BLEND_GL_ZERO << R200_DST_BLEND_SHIFT));
1052 rmesa->hw.ctx.cmd[CTX_RB3D_CBLENDCNTL] = (R200_COMB_FCN_ADD_CLAMP |
1053 (R200_BLEND_GL_ONE << R200_SRC_BLEND_SHIFT) |
1054 (R200_BLEND_GL_ZERO << R200_DST_BLEND_SHIFT));
1055 }
1056
1057 rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHOFFSET] =
1058 rmesa->radeon.radeonScreen->depthOffset + rmesa->radeon.radeonScreen->fbLocation;
1059
1060 rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHPITCH] =
1061 ((rmesa->radeon.radeonScreen->depthPitch &
1062 R200_DEPTHPITCH_MASK) |
1063 R200_DEPTH_ENDIAN_NO_SWAP);
1064
1065 if (rmesa->using_hyperz)
1066 rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHPITCH] |= R200_DEPTH_HYPERZ;
1067
1068 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] = (R200_Z_TEST_LESS |
1069 R200_STENCIL_TEST_ALWAYS |
1070 R200_STENCIL_FAIL_KEEP |
1071 R200_STENCIL_ZPASS_KEEP |
1072 R200_STENCIL_ZFAIL_KEEP |
1073 R200_Z_WRITE_ENABLE);
1074
1075 if (rmesa->using_hyperz) {
1076 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= R200_Z_COMPRESSION_ENABLE |
1077 R200_Z_DECOMPRESSION_ENABLE;
1078 /* if (rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_R200)
1079 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_HIERARCHY_ENABLE;*/
1080 }
1081
1082 rmesa->hw.ctx.cmd[CTX_PP_CNTL] = (R200_ANTI_ALIAS_NONE
1083 | R200_TEX_BLEND_0_ENABLE);
1084
1085 switch ( driQueryOptioni( &rmesa->radeon.optionCache, "dither_mode" ) ) {
1086 case DRI_CONF_DITHER_XERRORDIFFRESET:
1087 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= R200_DITHER_INIT;
1088 break;
1089 case DRI_CONF_DITHER_ORDERED:
1090 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= R200_SCALE_DITHER_ENABLE;
1091 break;
1092 }
1093 if ( driQueryOptioni( &rmesa->radeon.optionCache, "round_mode" ) ==
1094 DRI_CONF_ROUND_ROUND )
1095 rmesa->radeon.state.color.roundEnable = R200_ROUND_ENABLE;
1096 else
1097 rmesa->radeon.state.color.roundEnable = 0;
1098 if ( driQueryOptioni (&rmesa->radeon.optionCache, "color_reduction" ) ==
1099 DRI_CONF_COLOR_REDUCTION_DITHER )
1100 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= R200_DITHER_ENABLE;
1101 else
1102 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= rmesa->radeon.state.color.roundEnable;
1103
1104 rmesa->hw.prf.cmd[PRF_PP_TRI_PERF] = R200_TRI_CUTOFF_MASK - R200_TRI_CUTOFF_MASK *
1105 driQueryOptionf (&rmesa->radeon.optionCache,"texture_blend_quality");
1106 rmesa->hw.prf.cmd[PRF_PP_PERF_CNTL] = 0;
1107
1108 rmesa->hw.set.cmd[SET_SE_CNTL] = (R200_FFACE_CULL_CCW |
1109 R200_BFACE_SOLID |
1110 R200_FFACE_SOLID |
1111 R200_FLAT_SHADE_VTX_LAST |
1112 R200_DIFFUSE_SHADE_GOURAUD |
1113 R200_ALPHA_SHADE_GOURAUD |
1114 R200_SPECULAR_SHADE_GOURAUD |
1115 R200_FOG_SHADE_GOURAUD |
1116 R200_DISC_FOG_SHADE_GOURAUD |
1117 R200_VTX_PIX_CENTER_OGL |
1118 R200_ROUND_MODE_TRUNC |
1119 R200_ROUND_PREC_8TH_PIX);
1120
1121 rmesa->hw.set.cmd[SET_RE_CNTL] = (R200_PERSPECTIVE_ENABLE |
1122 R200_SCISSOR_ENABLE);
1123
1124 rmesa->hw.lin.cmd[LIN_RE_LINE_PATTERN] = ((1 << 16) | 0xffff);
1125
1126 rmesa->hw.lin.cmd[LIN_RE_LINE_STATE] =
1127 ((0 << R200_LINE_CURRENT_PTR_SHIFT) |
1128 (1 << R200_LINE_CURRENT_COUNT_SHIFT));
1129
1130 rmesa->hw.lin.cmd[LIN_SE_LINE_WIDTH] = (1 << 4);
1131
1132 rmesa->hw.msk.cmd[MSK_RB3D_STENCILREFMASK] =
1133 ((0x00 << R200_STENCIL_REF_SHIFT) |
1134 (0xff << R200_STENCIL_MASK_SHIFT) |
1135 (0xff << R200_STENCIL_WRITEMASK_SHIFT));
1136
1137 rmesa->hw.msk.cmd[MSK_RB3D_ROPCNTL] = R200_ROP_COPY;
1138 rmesa->hw.msk.cmd[MSK_RB3D_PLANEMASK] = 0xffffffff;
1139
1140 rmesa->hw.tam.cmd[TAM_DEBUG3] = 0;
1141
1142 rmesa->hw.msc.cmd[MSC_RE_MISC] =
1143 ((0 << R200_STIPPLE_X_OFFSET_SHIFT) |
1144 (0 << R200_STIPPLE_Y_OFFSET_SHIFT) |
1145 R200_STIPPLE_BIG_BIT_ORDER);
1146
1147
1148 rmesa->hw.cst.cmd[CST_PP_CNTL_X] = 0;
1149 rmesa->hw.cst.cmd[CST_RB3D_DEPTHXY_OFFSET] = 0;
1150 rmesa->hw.cst.cmd[CST_RE_AUX_SCISSOR_CNTL] = 0x0;
1151 rmesa->hw.cst.cmd[CST_RE_SCISSOR_TL_0] = 0;
1152 rmesa->hw.cst.cmd[CST_RE_SCISSOR_BR_0] = 0;
1153 rmesa->hw.cst.cmd[CST_SE_VAP_CNTL_STATUS] =
1154 #ifdef MESA_BIG_ENDIAN
1155 R200_VC_32BIT_SWAP;
1156 #else
1157 R200_VC_NO_SWAP;
1158 #endif
1159
1160 if (!(rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL)) {
1161 /* Bypass TCL */
1162 rmesa->hw.cst.cmd[CST_SE_VAP_CNTL_STATUS] |= (1<<8);
1163 }
1164
1165 rmesa->hw.cst.cmd[CST_RE_POINTSIZE] =
1166 (((GLuint)(ctx->Const.MaxPointSize * 16.0)) << R200_MAXPOINTSIZE_SHIFT) | 0x10;
1167 rmesa->hw.cst.cmd[CST_SE_TCL_INPUT_VTX_0] =
1168 (0x0 << R200_VERTEX_POSITION_ADDR__SHIFT);
1169 rmesa->hw.cst.cmd[CST_SE_TCL_INPUT_VTX_1] =
1170 (0x02 << R200_VTX_COLOR_0_ADDR__SHIFT) |
1171 (0x03 << R200_VTX_COLOR_1_ADDR__SHIFT);
1172 rmesa->hw.cst.cmd[CST_SE_TCL_INPUT_VTX_2] =
1173 (0x06 << R200_VTX_TEX_0_ADDR__SHIFT) |
1174 (0x07 << R200_VTX_TEX_1_ADDR__SHIFT) |
1175 (0x08 << R200_VTX_TEX_2_ADDR__SHIFT) |
1176 (0x09 << R200_VTX_TEX_3_ADDR__SHIFT);
1177 rmesa->hw.cst.cmd[CST_SE_TCL_INPUT_VTX_3] =
1178 (0x0A << R200_VTX_TEX_4_ADDR__SHIFT) |
1179 (0x0B << R200_VTX_TEX_5_ADDR__SHIFT);
1180
1181
1182 rmesa->hw.vpt.cmd[VPT_SE_VPORT_XSCALE] = 0x00000000;
1183 rmesa->hw.vpt.cmd[VPT_SE_VPORT_XOFFSET] = 0x00000000;
1184 rmesa->hw.vpt.cmd[VPT_SE_VPORT_YSCALE] = 0x00000000;
1185 rmesa->hw.vpt.cmd[VPT_SE_VPORT_YOFFSET] = 0x00000000;
1186 rmesa->hw.vpt.cmd[VPT_SE_VPORT_ZSCALE] = 0x00000000;
1187 rmesa->hw.vpt.cmd[VPT_SE_VPORT_ZOFFSET] = 0x00000000;
1188
1189 for ( i = 0 ; i < ctx->Const.MaxTextureUnits ; i++ ) {
1190 rmesa->hw.tex[i].cmd[TEX_PP_TXFILTER] = R200_BORDER_MODE_OGL;
1191 rmesa->hw.tex[i].cmd[TEX_PP_TXFORMAT] =
1192 ((i << R200_TXFORMAT_ST_ROUTE_SHIFT) | /* <-- note i */
1193 (2 << R200_TXFORMAT_WIDTH_SHIFT) |
1194 (2 << R200_TXFORMAT_HEIGHT_SHIFT));
1195 rmesa->hw.tex[i].cmd[TEX_PP_BORDER_COLOR] = 0;
1196 rmesa->hw.tex[i].cmd[TEX_PP_TXFORMAT_X] =
1197 (/* R200_TEXCOORD_PROJ | */
1198 0x100000); /* Small default bias */
1199 if (rmesa->radeon.radeonScreen->drmSupportsFragShader) {
1200 rmesa->hw.tex[i].cmd[TEX_PP_TXOFFSET_NEWDRM] =
1201 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
1202 rmesa->hw.tex[i].cmd[TEX_PP_CUBIC_FACES] = 0;
1203 rmesa->hw.tex[i].cmd[TEX_PP_TXMULTI_CTL] = 0;
1204 }
1205 else {
1206 rmesa->hw.tex[i].cmd[TEX_PP_TXOFFSET_OLDDRM] =
1207 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
1208 }
1209
1210 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_FACES] = 0;
1211 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F1] =
1212 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
1213 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F2] =
1214 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
1215 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F3] =
1216 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
1217 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F4] =
1218 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
1219 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F5] =
1220 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
1221
1222 rmesa->hw.pix[i].cmd[PIX_PP_TXCBLEND] =
1223 (R200_TXC_ARG_A_ZERO |
1224 R200_TXC_ARG_B_ZERO |
1225 R200_TXC_ARG_C_DIFFUSE_COLOR |
1226 R200_TXC_OP_MADD);
1227
1228 rmesa->hw.pix[i].cmd[PIX_PP_TXCBLEND2] =
1229 ((i << R200_TXC_TFACTOR_SEL_SHIFT) |
1230 R200_TXC_SCALE_1X |
1231 R200_TXC_CLAMP_0_1 |
1232 R200_TXC_OUTPUT_REG_R0);
1233
1234 rmesa->hw.pix[i].cmd[PIX_PP_TXABLEND] =
1235 (R200_TXA_ARG_A_ZERO |
1236 R200_TXA_ARG_B_ZERO |
1237 R200_TXA_ARG_C_DIFFUSE_ALPHA |
1238 R200_TXA_OP_MADD);
1239
1240 rmesa->hw.pix[i].cmd[PIX_PP_TXABLEND2] =
1241 ((i << R200_TXA_TFACTOR_SEL_SHIFT) |
1242 R200_TXA_SCALE_1X |
1243 R200_TXA_CLAMP_0_1 |
1244 R200_TXA_OUTPUT_REG_R0);
1245 }
1246
1247 rmesa->hw.tf.cmd[TF_TFACTOR_0] = 0;
1248 rmesa->hw.tf.cmd[TF_TFACTOR_1] = 0;
1249 rmesa->hw.tf.cmd[TF_TFACTOR_2] = 0;
1250 rmesa->hw.tf.cmd[TF_TFACTOR_3] = 0;
1251 rmesa->hw.tf.cmd[TF_TFACTOR_4] = 0;
1252 rmesa->hw.tf.cmd[TF_TFACTOR_5] = 0;
1253
1254 rmesa->hw.vap.cmd[VAP_SE_VAP_CNTL] =
1255 (R200_VAP_TCL_ENABLE |
1256 (0x9 << R200_VAP_VF_MAX_VTX_NUM__SHIFT));
1257
1258 rmesa->hw.vte.cmd[VTE_SE_VTE_CNTL] =
1259 (R200_VPORT_X_SCALE_ENA |
1260 R200_VPORT_Y_SCALE_ENA |
1261 R200_VPORT_Z_SCALE_ENA |
1262 R200_VPORT_X_OFFSET_ENA |
1263 R200_VPORT_Y_OFFSET_ENA |
1264 R200_VPORT_Z_OFFSET_ENA |
1265 /* FIXME: Turn on for tex rect only */
1266 R200_VTX_ST_DENORMALIZED |
1267 R200_VTX_W0_FMT);
1268
1269
1270 rmesa->hw.vtx.cmd[VTX_VTXFMT_0] = 0;
1271 rmesa->hw.vtx.cmd[VTX_VTXFMT_1] = 0;
1272 rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_VTXFMT_0] =
1273 ((R200_VTX_Z0 | R200_VTX_W0 |
1274 (R200_VTX_FP_RGBA << R200_VTX_COLOR_0_SHIFT)));
1275 rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_VTXFMT_1] = 0;
1276 rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_COMPSEL] = (R200_OUTPUT_XYZW);
1277 rmesa->hw.vtx.cmd[VTX_STATE_CNTL] = R200_VSC_UPDATE_USER_COLOR_0_ENABLE;
1278
1279
1280 /* Matrix selection */
1281 rmesa->hw.msl.cmd[MSL_MATRIX_SELECT_0] =
1282 (R200_MTX_MV << R200_MODELVIEW_0_SHIFT);
1283
1284 rmesa->hw.msl.cmd[MSL_MATRIX_SELECT_1] =
1285 (R200_MTX_IMV << R200_IT_MODELVIEW_0_SHIFT);
1286
1287 rmesa->hw.msl.cmd[MSL_MATRIX_SELECT_2] =
1288 (R200_MTX_MVP << R200_MODELPROJECT_0_SHIFT);
1289
1290 rmesa->hw.msl.cmd[MSL_MATRIX_SELECT_3] =
1291 ((R200_MTX_TEX0 << R200_TEXMAT_0_SHIFT) |
1292 (R200_MTX_TEX1 << R200_TEXMAT_1_SHIFT) |
1293 (R200_MTX_TEX2 << R200_TEXMAT_2_SHIFT) |
1294 (R200_MTX_TEX3 << R200_TEXMAT_3_SHIFT));
1295
1296 rmesa->hw.msl.cmd[MSL_MATRIX_SELECT_4] =
1297 ((R200_MTX_TEX4 << R200_TEXMAT_4_SHIFT) |
1298 (R200_MTX_TEX5 << R200_TEXMAT_5_SHIFT));
1299
1300
1301 /* General TCL state */
1302 rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL_0] =
1303 (R200_SPECULAR_LIGHTS |
1304 R200_DIFFUSE_SPECULAR_COMBINE |
1305 R200_LOCAL_LIGHT_VEC_GL |
1306 R200_LM0_SOURCE_MATERIAL_0 << R200_FRONT_SHININESS_SOURCE_SHIFT |
1307 R200_LM0_SOURCE_MATERIAL_1 << R200_BACK_SHININESS_SOURCE_SHIFT);
1308
1309 rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL_1] =
1310 ((R200_LM1_SOURCE_MATERIAL_0 << R200_FRONT_EMISSIVE_SOURCE_SHIFT) |
1311 (R200_LM1_SOURCE_MATERIAL_0 << R200_FRONT_AMBIENT_SOURCE_SHIFT) |
1312 (R200_LM1_SOURCE_MATERIAL_0 << R200_FRONT_DIFFUSE_SOURCE_SHIFT) |
1313 (R200_LM1_SOURCE_MATERIAL_0 << R200_FRONT_SPECULAR_SOURCE_SHIFT) |
1314 (R200_LM1_SOURCE_MATERIAL_1 << R200_BACK_EMISSIVE_SOURCE_SHIFT) |
1315 (R200_LM1_SOURCE_MATERIAL_1 << R200_BACK_AMBIENT_SOURCE_SHIFT) |
1316 (R200_LM1_SOURCE_MATERIAL_1 << R200_BACK_DIFFUSE_SOURCE_SHIFT) |
1317 (R200_LM1_SOURCE_MATERIAL_1 << R200_BACK_SPECULAR_SOURCE_SHIFT));
1318
1319 rmesa->hw.tcl.cmd[TCL_PER_LIGHT_CTL_0] = 0; /* filled in via callbacks */
1320 rmesa->hw.tcl.cmd[TCL_PER_LIGHT_CTL_1] = 0;
1321 rmesa->hw.tcl.cmd[TCL_PER_LIGHT_CTL_2] = 0;
1322 rmesa->hw.tcl.cmd[TCL_PER_LIGHT_CTL_3] = 0;
1323
1324 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] =
1325 (R200_UCP_IN_CLIP_SPACE |
1326 R200_CULL_FRONT_IS_CCW);
1327
1328 /* Texgen/Texmat state */
1329 rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_2] = 0x00ffffff;
1330 rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_3] =
1331 ((0 << R200_TEXGEN_0_INPUT_TEX_SHIFT) |
1332 (1 << R200_TEXGEN_1_INPUT_TEX_SHIFT) |
1333 (2 << R200_TEXGEN_2_INPUT_TEX_SHIFT) |
1334 (3 << R200_TEXGEN_3_INPUT_TEX_SHIFT) |
1335 (4 << R200_TEXGEN_4_INPUT_TEX_SHIFT) |
1336 (5 << R200_TEXGEN_5_INPUT_TEX_SHIFT));
1337 rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_0] = 0;
1338 rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_1] =
1339 ((0 << R200_TEXGEN_0_INPUT_SHIFT) |
1340 (1 << R200_TEXGEN_1_INPUT_SHIFT) |
1341 (2 << R200_TEXGEN_2_INPUT_SHIFT) |
1342 (3 << R200_TEXGEN_3_INPUT_SHIFT) |
1343 (4 << R200_TEXGEN_4_INPUT_SHIFT) |
1344 (5 << R200_TEXGEN_5_INPUT_SHIFT));
1345 rmesa->hw.tcg.cmd[TCG_TEX_CYL_WRAP_CTL] = 0;
1346
1347
1348 for (i = 0 ; i < 8; i++) {
1349 struct gl_light *l = &ctx->Light.Light[i];
1350 GLenum p = GL_LIGHT0 + i;
1351 *(float *)&(rmesa->hw.lit[i].cmd[LIT_RANGE_CUTOFF]) = FLT_MAX;
1352
1353 ctx->Driver.Lightfv( ctx, p, GL_AMBIENT, l->Ambient );
1354 ctx->Driver.Lightfv( ctx, p, GL_DIFFUSE, l->Diffuse );
1355 ctx->Driver.Lightfv( ctx, p, GL_SPECULAR, l->Specular );
1356 ctx->Driver.Lightfv( ctx, p, GL_POSITION, NULL );
1357 ctx->Driver.Lightfv( ctx, p, GL_SPOT_DIRECTION, NULL );
1358 ctx->Driver.Lightfv( ctx, p, GL_SPOT_EXPONENT, &l->SpotExponent );
1359 ctx->Driver.Lightfv( ctx, p, GL_SPOT_CUTOFF, &l->SpotCutoff );
1360 ctx->Driver.Lightfv( ctx, p, GL_CONSTANT_ATTENUATION,
1361 &l->ConstantAttenuation );
1362 ctx->Driver.Lightfv( ctx, p, GL_LINEAR_ATTENUATION,
1363 &l->LinearAttenuation );
1364 ctx->Driver.Lightfv( ctx, p, GL_QUADRATIC_ATTENUATION,
1365 &l->QuadraticAttenuation );
1366 *(float *)&(rmesa->hw.lit[i].cmd[LIT_ATTEN_XXX]) = 0.0;
1367 }
1368
1369 ctx->Driver.LightModelfv( ctx, GL_LIGHT_MODEL_AMBIENT,
1370 ctx->Light.Model.Ambient );
1371
1372 TNL_CONTEXT(ctx)->Driver.NotifyMaterialChange( ctx );
1373
1374 for (i = 0 ; i < 6; i++) {
1375 ctx->Driver.ClipPlane( ctx, GL_CLIP_PLANE0 + i, NULL );
1376 }
1377
1378 ctx->Driver.Fogfv( ctx, GL_FOG_MODE, NULL );
1379 ctx->Driver.Fogfv( ctx, GL_FOG_DENSITY, &ctx->Fog.Density );
1380 ctx->Driver.Fogfv( ctx, GL_FOG_START, &ctx->Fog.Start );
1381 ctx->Driver.Fogfv( ctx, GL_FOG_END, &ctx->Fog.End );
1382 ctx->Driver.Fogfv( ctx, GL_FOG_COLOR, ctx->Fog.Color );
1383 ctx->Driver.Fogfv( ctx, GL_FOG_COORDINATE_SOURCE_EXT, NULL );
1384
1385 rmesa->hw.grd.cmd[GRD_VERT_GUARD_CLIP_ADJ] = IEEE_ONE;
1386 rmesa->hw.grd.cmd[GRD_VERT_GUARD_DISCARD_ADJ] = IEEE_ONE;
1387 rmesa->hw.grd.cmd[GRD_HORZ_GUARD_CLIP_ADJ] = IEEE_ONE;
1388 rmesa->hw.grd.cmd[GRD_HORZ_GUARD_DISCARD_ADJ] = IEEE_ONE;
1389
1390 rmesa->hw.eye.cmd[EYE_X] = 0;
1391 rmesa->hw.eye.cmd[EYE_Y] = 0;
1392 rmesa->hw.eye.cmd[EYE_Z] = IEEE_ONE;
1393 rmesa->hw.eye.cmd[EYE_RESCALE_FACTOR] = IEEE_ONE;
1394
1395 rmesa->hw.spr.cmd[SPR_POINT_SPRITE_CNTL] =
1396 R200_PS_SE_SEL_STATE | R200_PS_MULT_CONST;
1397
1398 /* ptp_eye is presumably used to calculate the attenuation wrt a different
1399 location? In any case, since point attenuation triggers _needeyecoords,
1400 it is constant. Probably ignored as long as R200_PS_USE_MODEL_EYE_VEC
1401 isn't set */
1402 rmesa->hw.ptp.cmd[PTP_EYE_X] = 0;
1403 rmesa->hw.ptp.cmd[PTP_EYE_Y] = 0;
1404 rmesa->hw.ptp.cmd[PTP_EYE_Z] = IEEE_ONE | 0x80000000; /* -1.0 */
1405 rmesa->hw.ptp.cmd[PTP_EYE_3] = 0;
1406 /* no idea what the ptp_vport_scale values are good for, except the
1407 PTSIZE one - hopefully doesn't matter */
1408 rmesa->hw.ptp.cmd[PTP_VPORT_SCALE_0] = IEEE_ONE;
1409 rmesa->hw.ptp.cmd[PTP_VPORT_SCALE_1] = IEEE_ONE;
1410 rmesa->hw.ptp.cmd[PTP_VPORT_SCALE_PTSIZE] = IEEE_ONE;
1411 rmesa->hw.ptp.cmd[PTP_VPORT_SCALE_3] = IEEE_ONE;
1412 rmesa->hw.ptp.cmd[PTP_ATT_CONST_QUAD] = 0;
1413 rmesa->hw.ptp.cmd[PTP_ATT_CONST_LIN] = 0;
1414 rmesa->hw.ptp.cmd[PTP_ATT_CONST_CON] = IEEE_ONE;
1415 rmesa->hw.ptp.cmd[PTP_ATT_CONST_3] = 0;
1416 rmesa->hw.ptp.cmd[PTP_CLAMP_MIN] = IEEE_ONE;
1417 rmesa->hw.ptp.cmd[PTP_CLAMP_MAX] = 0x44ffe000; /* 2047 */
1418 rmesa->hw.ptp.cmd[PTP_CLAMP_2] = 0;
1419 rmesa->hw.ptp.cmd[PTP_CLAMP_3] = 0;
1420
1421 r200LightingSpaceChange( ctx );
1422
1423 rmesa->radeon.hw.all_dirty = GL_TRUE;
1424
1425 rcommonInitCmdBuf(&rmesa->radeon);
1426 }