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r200: port over cs emit changes from radeon
[mesa.git] / src / mesa / drivers / dri / r200 / r200_state_init.c
1 /*
2 Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
3
4 The Weather Channel (TM) funded Tungsten Graphics to develop the
5 initial release of the Radeon 8500 driver under the XFree86 license.
6 This notice must be preserved.
7
8 Permission is hereby granted, free of charge, to any person obtaining
9 a copy of this software and associated documentation files (the
10 "Software"), to deal in the Software without restriction, including
11 without limitation the rights to use, copy, modify, merge, publish,
12 distribute, sublicense, and/or sell copies of the Software, and to
13 permit persons to whom the Software is furnished to do so, subject to
14 the following conditions:
15
16 The above copyright notice and this permission notice (including the
17 next paragraph) shall be included in all copies or substantial
18 portions of the Software.
19
20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 */
28
29 /*
30 * Authors:
31 * Keith Whitwell <keith@tungstengraphics.com>
32 */
33
34 #include "main/glheader.h"
35 #include "main/imports.h"
36 #include "main/enums.h"
37 #include "main/colormac.h"
38 #include "main/api_arrayelt.h"
39
40 #include "swrast/swrast.h"
41 #include "vbo/vbo.h"
42 #include "tnl/tnl.h"
43 #include "tnl/t_pipeline.h"
44 #include "swrast_setup/swrast_setup.h"
45
46 #include "radeon_common.h"
47 #include "radeon_mipmap_tree.h"
48 #include "r200_context.h"
49 #include "r200_ioctl.h"
50 #include "r200_state.h"
51 #include "r200_tcl.h"
52 #include "r200_tex.h"
53 #include "r200_swtcl.h"
54
55 #include "xmlpool.h"
56
57 /* New (1.3) state mechanism. 3 commands (packet, scalar, vector) in
58 * 1.3 cmdbuffers allow all previous state to be updated as well as
59 * the tcl scalar and vector areas.
60 */
61 static struct {
62 int start;
63 int len;
64 const char *name;
65 } packet[RADEON_MAX_STATE_PACKETS] = {
66 {RADEON_PP_MISC, 7, "RADEON_PP_MISC"},
67 {RADEON_PP_CNTL, 3, "RADEON_PP_CNTL"},
68 {RADEON_RB3D_COLORPITCH, 1, "RADEON_RB3D_COLORPITCH"},
69 {RADEON_RE_LINE_PATTERN, 2, "RADEON_RE_LINE_PATTERN"},
70 {RADEON_SE_LINE_WIDTH, 1, "RADEON_SE_LINE_WIDTH"},
71 {RADEON_PP_LUM_MATRIX, 1, "RADEON_PP_LUM_MATRIX"},
72 {RADEON_PP_ROT_MATRIX_0, 2, "RADEON_PP_ROT_MATRIX_0"},
73 {RADEON_RB3D_STENCILREFMASK, 3, "RADEON_RB3D_STENCILREFMASK"},
74 {RADEON_SE_VPORT_XSCALE, 6, "RADEON_SE_VPORT_XSCALE"},
75 {RADEON_SE_CNTL, 2, "RADEON_SE_CNTL"},
76 {RADEON_SE_CNTL_STATUS, 1, "RADEON_SE_CNTL_STATUS"},
77 {RADEON_RE_MISC, 1, "RADEON_RE_MISC"},
78 {RADEON_PP_TXFILTER_0, 6, "RADEON_PP_TXFILTER_0"},
79 {RADEON_PP_BORDER_COLOR_0, 1, "RADEON_PP_BORDER_COLOR_0"},
80 {RADEON_PP_TXFILTER_1, 6, "RADEON_PP_TXFILTER_1"},
81 {RADEON_PP_BORDER_COLOR_1, 1, "RADEON_PP_BORDER_COLOR_1"},
82 {RADEON_PP_TXFILTER_2, 6, "RADEON_PP_TXFILTER_2"},
83 {RADEON_PP_BORDER_COLOR_2, 1, "RADEON_PP_BORDER_COLOR_2"},
84 {RADEON_SE_ZBIAS_FACTOR, 2, "RADEON_SE_ZBIAS_FACTOR"},
85 {RADEON_SE_TCL_OUTPUT_VTX_FMT, 11, "RADEON_SE_TCL_OUTPUT_VTX_FMT"},
86 {RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED, 17,
87 "RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED"},
88 {R200_PP_TXCBLEND_0, 4, "R200_PP_TXCBLEND_0"},
89 {R200_PP_TXCBLEND_1, 4, "R200_PP_TXCBLEND_1"},
90 {R200_PP_TXCBLEND_2, 4, "R200_PP_TXCBLEND_2"},
91 {R200_PP_TXCBLEND_3, 4, "R200_PP_TXCBLEND_3"},
92 {R200_PP_TXCBLEND_4, 4, "R200_PP_TXCBLEND_4"},
93 {R200_PP_TXCBLEND_5, 4, "R200_PP_TXCBLEND_5"},
94 {R200_PP_TXCBLEND_6, 4, "R200_PP_TXCBLEND_6"},
95 {R200_PP_TXCBLEND_7, 4, "R200_PP_TXCBLEND_7"},
96 {R200_SE_TCL_LIGHT_MODEL_CTL_0, 6, "R200_SE_TCL_LIGHT_MODEL_CTL_0"},
97 {R200_PP_TFACTOR_0, 6, "R200_PP_TFACTOR_0"},
98 {R200_SE_VTX_FMT_0, 4, "R200_SE_VTX_FMT_0"},
99 {R200_SE_VAP_CNTL, 1, "R200_SE_VAP_CNTL"},
100 {R200_SE_TCL_MATRIX_SEL_0, 5, "R200_SE_TCL_MATRIX_SEL_0"},
101 {R200_SE_TCL_TEX_PROC_CTL_2, 5, "R200_SE_TCL_TEX_PROC_CTL_2"},
102 {R200_SE_TCL_UCP_VERT_BLEND_CTL, 1, "R200_SE_TCL_UCP_VERT_BLEND_CTL"},
103 {R200_PP_TXFILTER_0, 6, "R200_PP_TXFILTER_0"},
104 {R200_PP_TXFILTER_1, 6, "R200_PP_TXFILTER_1"},
105 {R200_PP_TXFILTER_2, 6, "R200_PP_TXFILTER_2"},
106 {R200_PP_TXFILTER_3, 6, "R200_PP_TXFILTER_3"},
107 {R200_PP_TXFILTER_4, 6, "R200_PP_TXFILTER_4"},
108 {R200_PP_TXFILTER_5, 6, "R200_PP_TXFILTER_5"},
109 {R200_PP_TXOFFSET_0, 1, "R200_PP_TXOFFSET_0"},
110 {R200_PP_TXOFFSET_1, 1, "R200_PP_TXOFFSET_1"},
111 {R200_PP_TXOFFSET_2, 1, "R200_PP_TXOFFSET_2"},
112 {R200_PP_TXOFFSET_3, 1, "R200_PP_TXOFFSET_3"},
113 {R200_PP_TXOFFSET_4, 1, "R200_PP_TXOFFSET_4"},
114 {R200_PP_TXOFFSET_5, 1, "R200_PP_TXOFFSET_5"},
115 {R200_SE_VTE_CNTL, 1, "R200_SE_VTE_CNTL"},
116 {R200_SE_TCL_OUTPUT_VTX_COMP_SEL, 1,
117 "R200_SE_TCL_OUTPUT_VTX_COMP_SEL"},
118 {R200_PP_TAM_DEBUG3, 1, "R200_PP_TAM_DEBUG3"},
119 {R200_PP_CNTL_X, 1, "R200_PP_CNTL_X"},
120 {R200_RB3D_DEPTHXY_OFFSET, 1, "R200_RB3D_DEPTHXY_OFFSET"},
121 {R200_RE_AUX_SCISSOR_CNTL, 1, "R200_RE_AUX_SCISSOR_CNTL"},
122 {R200_RE_SCISSOR_TL_0, 2, "R200_RE_SCISSOR_TL_0"},
123 {R200_RE_SCISSOR_TL_1, 2, "R200_RE_SCISSOR_TL_1"},
124 {R200_RE_SCISSOR_TL_2, 2, "R200_RE_SCISSOR_TL_2"},
125 {R200_SE_VAP_CNTL_STATUS, 1, "R200_SE_VAP_CNTL_STATUS"},
126 {R200_SE_VTX_STATE_CNTL, 1, "R200_SE_VTX_STATE_CNTL"},
127 {R200_RE_POINTSIZE, 1, "R200_RE_POINTSIZE"},
128 {R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0, 4,
129 "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0"},
130 {R200_PP_CUBIC_FACES_0, 1, "R200_PP_CUBIC_FACES_0"}, /* 61 */
131 {R200_PP_CUBIC_OFFSET_F1_0, 5, "R200_PP_CUBIC_OFFSET_F1_0"}, /* 62 */
132 {R200_PP_CUBIC_FACES_1, 1, "R200_PP_CUBIC_FACES_1"},
133 {R200_PP_CUBIC_OFFSET_F1_1, 5, "R200_PP_CUBIC_OFFSET_F1_1"},
134 {R200_PP_CUBIC_FACES_2, 1, "R200_PP_CUBIC_FACES_2"},
135 {R200_PP_CUBIC_OFFSET_F1_2, 5, "R200_PP_CUBIC_OFFSET_F1_2"},
136 {R200_PP_CUBIC_FACES_3, 1, "R200_PP_CUBIC_FACES_3"},
137 {R200_PP_CUBIC_OFFSET_F1_3, 5, "R200_PP_CUBIC_OFFSET_F1_3"},
138 {R200_PP_CUBIC_FACES_4, 1, "R200_PP_CUBIC_FACES_4"},
139 {R200_PP_CUBIC_OFFSET_F1_4, 5, "R200_PP_CUBIC_OFFSET_F1_4"},
140 {R200_PP_CUBIC_FACES_5, 1, "R200_PP_CUBIC_FACES_5"},
141 {R200_PP_CUBIC_OFFSET_F1_5, 5, "R200_PP_CUBIC_OFFSET_F1_5"},
142 {RADEON_PP_TEX_SIZE_0, 2, "RADEON_PP_TEX_SIZE_0"},
143 {RADEON_PP_TEX_SIZE_1, 2, "RADEON_PP_TEX_SIZE_1"},
144 {RADEON_PP_TEX_SIZE_2, 2, "RADEON_PP_TEX_SIZE_2"},
145 {R200_RB3D_BLENDCOLOR, 3, "R200_RB3D_BLENDCOLOR"},
146 {R200_SE_TCL_POINT_SPRITE_CNTL, 1, "R200_SE_TCL_POINT_SPRITE_CNTL"},
147 {RADEON_PP_CUBIC_FACES_0, 1, "RADEON_PP_CUBIC_FACES_0"},
148 {RADEON_PP_CUBIC_OFFSET_T0_0, 5, "RADEON_PP_CUBIC_OFFSET_T0_0"},
149 {RADEON_PP_CUBIC_FACES_1, 1, "RADEON_PP_CUBIC_FACES_1"},
150 {RADEON_PP_CUBIC_OFFSET_T1_0, 5, "RADEON_PP_CUBIC_OFFSET_T1_0"},
151 {RADEON_PP_CUBIC_FACES_2, 1, "RADEON_PP_CUBIC_FACES_2"},
152 {RADEON_PP_CUBIC_OFFSET_T2_0, 5, "RADEON_PP_CUBIC_OFFSET_T2_0"},
153 {R200_PP_TRI_PERF, 2, "R200_PP_TRI_PERF"},
154 {R200_PP_TXCBLEND_8, 32, "R200_PP_AFS_0"}, /* 85 */
155 {R200_PP_TXCBLEND_0, 32, "R200_PP_AFS_1"},
156 {R200_PP_TFACTOR_0, 8, "R200_ATF_TFACTOR"},
157 {R200_PP_TXFILTER_0, 8, "R200_PP_TXCTLALL_0"},
158 {R200_PP_TXFILTER_1, 8, "R200_PP_TXCTLALL_1"},
159 {R200_PP_TXFILTER_2, 8, "R200_PP_TXCTLALL_2"},
160 {R200_PP_TXFILTER_3, 8, "R200_PP_TXCTLALL_3"},
161 {R200_PP_TXFILTER_4, 8, "R200_PP_TXCTLALL_4"},
162 {R200_PP_TXFILTER_5, 8, "R200_PP_TXCTLALL_5"},
163 {R200_VAP_PVS_CNTL_1, 2, "R200_VAP_PVS_CNTL"},
164 };
165
166 /* =============================================================
167 * State initialization
168 */
169
170 void r200PrintDirty( r200ContextPtr rmesa, const char *msg )
171 {
172 struct radeon_state_atom *l;
173
174 fprintf(stderr, msg);
175 fprintf(stderr, ": ");
176
177 foreach(l, &rmesa->radeon.hw.atomlist) {
178 if (l->dirty || rmesa->radeon.hw.all_dirty)
179 fprintf(stderr, "%s, ", l->name);
180 }
181
182 fprintf(stderr, "\n");
183 }
184
185 static int cmdpkt( r200ContextPtr rmesa, int id )
186 {
187 drm_radeon_cmd_header_t h;
188
189 if (rmesa->radeon.radeonScreen->kernel_mm) {
190 return CP_PACKET0(packet[id].start, packet[id].len - 1);
191 } else {
192 h.i = 0;
193 h.packet.cmd_type = RADEON_CMD_PACKET;
194 h.packet.packet_id = id;
195 }
196 return h.i;
197 }
198
199 static int cmdvec( int offset, int stride, int count )
200 {
201 drm_radeon_cmd_header_t h;
202 h.i = 0;
203 h.vectors.cmd_type = RADEON_CMD_VECTORS;
204 h.vectors.offset = offset;
205 h.vectors.stride = stride;
206 h.vectors.count = count;
207 return h.i;
208 }
209
210 /* warning: the count here is divided by 4 compared to other cmds
211 (so it doesn't exceed the char size)! */
212 static int cmdveclinear( int offset, int count )
213 {
214 drm_radeon_cmd_header_t h;
215 h.i = 0;
216 h.veclinear.cmd_type = RADEON_CMD_VECLINEAR;
217 h.veclinear.addr_lo = offset & 0xff;
218 h.veclinear.addr_hi = (offset & 0xff00) >> 8;
219 h.veclinear.count = count;
220 return h.i;
221 }
222
223 static int cmdscl( int offset, int stride, int count )
224 {
225 drm_radeon_cmd_header_t h;
226 h.i = 0;
227 h.scalars.cmd_type = RADEON_CMD_SCALARS;
228 h.scalars.offset = offset;
229 h.scalars.stride = stride;
230 h.scalars.count = count;
231 return h.i;
232 }
233
234 static int cmdscl2( int offset, int stride, int count )
235 {
236 drm_radeon_cmd_header_t h;
237 h.i = 0;
238 h.scalars.cmd_type = RADEON_CMD_SCALARS2;
239 h.scalars.offset = offset - 0x100;
240 h.scalars.stride = stride;
241 h.scalars.count = count;
242 return h.i;
243 }
244
245 #define CHECK( NM, FLAG ) \
246 static int check_##NM( GLcontext *ctx, struct radeon_state_atom *atom) \
247 { \
248 r200ContextPtr rmesa = R200_CONTEXT(ctx); \
249 (void) rmesa; \
250 return (FLAG) ? atom->cmd_size : 0; \
251 }
252
253 #define TCL_CHECK( NM, FLAG ) \
254 static int check_##NM( GLcontext *ctx, struct radeon_state_atom *atom) \
255 { \
256 r200ContextPtr rmesa = R200_CONTEXT(ctx); \
257 return (!rmesa->radeon.TclFallback && !ctx->VertexProgram._Enabled && (FLAG)) ? atom->cmd_size : 0; \
258 }
259
260 #define TCL_OR_VP_CHECK( NM, FLAG ) \
261 static int check_##NM( GLcontext *ctx, struct radeon_state_atom *atom ) \
262 { \
263 r200ContextPtr rmesa = R200_CONTEXT(ctx); \
264 return (!rmesa->radeon.TclFallback && (FLAG)) ? atom->cmd_size : 0; \
265 }
266
267 #define VP_CHECK( NM, FLAG ) \
268 static int check_##NM( GLcontext *ctx, struct radeon_state_atom *atom ) \
269 { \
270 r200ContextPtr rmesa = R200_CONTEXT(ctx); \
271 (void) atom; \
272 return (!rmesa->radeon.TclFallback && ctx->VertexProgram._Enabled && (FLAG)) ? atom->cmd_size : 0; \
273 }
274
275 CHECK( always, GL_TRUE )
276 CHECK( never, GL_FALSE )
277 CHECK( tex_any, ctx->Texture._EnabledUnits )
278 CHECK( tf, (ctx->Texture._EnabledUnits && !ctx->ATIFragmentShader._Enabled) );
279 CHECK( tex_pair, (rmesa->state.texture.unit[atom->idx].unitneeded | rmesa->state.texture.unit[atom->idx & ~1].unitneeded) )
280 CHECK( tex, rmesa->state.texture.unit[atom->idx].unitneeded )
281 CHECK( pix_zero, !ctx->ATIFragmentShader._Enabled )
282 CHECK( texenv, (rmesa->state.envneeded & (1 << (atom->idx)) && !ctx->ATIFragmentShader._Enabled) )
283 CHECK( afs_pass1, (ctx->ATIFragmentShader._Enabled && (ctx->ATIFragmentShader.Current->NumPasses > 1)) )
284 CHECK( afs, ctx->ATIFragmentShader._Enabled )
285 CHECK( tex_cube, rmesa->state.texture.unit[atom->idx].unitneeded & TEXTURE_CUBE_BIT )
286 TCL_CHECK( tcl_fog, ctx->Fog.Enabled )
287 TCL_CHECK( tcl, GL_TRUE )
288 TCL_CHECK( tcl_tex, rmesa->state.texture.unit[atom->idx].unitneeded )
289 TCL_CHECK( tcl_lighting, ctx->Light.Enabled )
290 TCL_CHECK( tcl_light, ctx->Light.Enabled && ctx->Light.Light[atom->idx].Enabled )
291 TCL_OR_VP_CHECK( tcl_ucp, (ctx->Transform.ClipPlanesEnabled & (1 << (atom->idx))) )
292 TCL_OR_VP_CHECK( tcl_or_vp, GL_TRUE )
293 VP_CHECK( tcl_vp, GL_TRUE )
294 VP_CHECK( tcl_vp_size, ctx->VertexProgram.Current->Base.NumNativeInstructions > 64 )
295 VP_CHECK( tcl_vpp_size, ctx->VertexProgram.Current->Base.NumNativeParameters > 96 )
296
297 #define OUT_VEC(hdr, data) do { \
298 drm_radeon_cmd_header_t h; \
299 h.i = hdr; \
300 OUT_BATCH(CP_PACKET0(RADEON_SE_TCL_STATE_FLUSH, 0)); \
301 OUT_BATCH(0); \
302 OUT_BATCH(CP_PACKET0(R200_SE_TCL_VECTOR_INDX_REG, 0)); \
303 OUT_BATCH(h.vectors.offset | (h.vectors.stride << RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT)); \
304 OUT_BATCH(CP_PACKET0_ONE(R200_SE_TCL_VECTOR_DATA_REG, h.vectors.count - 1)); \
305 OUT_BATCH_TABLE((data), h.vectors.count); \
306 } while(0)
307
308 #define OUT_VECLINEAR(hdr, data) do { \
309 drm_radeon_cmd_header_t h; \
310 uint32_t _start = h.veclinear.addr_lo | (h.veclinear.addr_hi << 8); \
311 uint32_t _sz = h.veclinear.count * 4; \
312 h.i = hdr; \
313 OUT_BATCH(CP_PACKET0(RADEON_SE_TCL_STATE_FLUSH, 0)); \
314 OUT_BATCH(0); \
315 OUT_BATCH(CP_PACKET0(R200_SE_TCL_VECTOR_INDX_REG, 0)); \
316 OUT_BATCH(_start | (1 << RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT)); \
317 OUT_BATCH(CP_PACKET0_ONE(R200_SE_TCL_VECTOR_DATA_REG, _sz - 1)); \
318 OUT_BATCH_TABLE((data), _sz); \
319 } while(0)
320
321 #define OUT_SCL(hdr, data) do { \
322 drm_radeon_cmd_header_t h; \
323 h.i = hdr; \
324 OUT_BATCH(CP_PACKET0(R200_SE_TCL_SCALAR_INDX_REG, 0)); \
325 OUT_BATCH((h.scalars.offset) | (h.scalars.stride << RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT)); \
326 OUT_BATCH(CP_PACKET0_ONE(R200_SE_TCL_SCALAR_DATA_REG, h.scalars.count - 1)); \
327 OUT_BATCH_TABLE((data), h.scalars.count); \
328 } while(0)
329
330 #define OUT_SCL2(hdr, data) do { \
331 drm_radeon_cmd_header_t h; \
332 h.i = hdr; \
333 OUT_BATCH(CP_PACKET0(R200_SE_TCL_SCALAR_INDX_REG, 0)); \
334 OUT_BATCH((h.scalars.offset + 0x100) | (h.scalars.stride << RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT)); \
335 OUT_BATCH(CP_PACKET0_ONE(R200_SE_TCL_SCALAR_DATA_REG, h.scalars.count - 1)); \
336 OUT_BATCH_TABLE((data), h.scalars.count); \
337 } while(0)
338
339 static void mtl_emit(GLcontext *ctx, struct radeon_state_atom *atom)
340 {
341 r200ContextPtr r200 = R200_CONTEXT(ctx);
342 BATCH_LOCALS(&r200->radeon);
343 uint32_t dwords = atom->cmd_size;
344
345 BEGIN_BATCH_NO_AUTOSTATE(dwords);
346 OUT_VEC(atom->cmd[MTL_CMD_0], (atom->cmd+1));
347 OUT_SCL2(atom->cmd[MTL_CMD_1], (atom->cmd + 18));
348 END_BATCH();
349 }
350
351 static void lit_emit(GLcontext *ctx, struct radeon_state_atom *atom)
352 {
353 r200ContextPtr r200 = R200_CONTEXT(ctx);
354 BATCH_LOCALS(&r200->radeon);
355 uint32_t dwords = atom->cmd_size;
356
357 BEGIN_BATCH_NO_AUTOSTATE(dwords);
358 OUT_VEC(atom->cmd[LIT_CMD_0], atom->cmd+1);
359 OUT_VEC(atom->cmd[LIT_CMD_1], atom->cmd+LIT_CMD_1+1);
360 END_BATCH();
361 }
362
363 static void ptp_emit(GLcontext *ctx, struct radeon_state_atom *atom)
364 {
365 r200ContextPtr r200 = R200_CONTEXT(ctx);
366 BATCH_LOCALS(&r200->radeon);
367 uint32_t dwords = atom->cmd_size;
368
369 BEGIN_BATCH_NO_AUTOSTATE(dwords);
370 OUT_VEC(atom->cmd[PTP_CMD_0], atom->cmd+1);
371 OUT_VEC(atom->cmd[PTP_CMD_1], atom->cmd+PTP_CMD_1+1);
372 END_BATCH();
373 }
374
375 static void veclinear_emit(GLcontext *ctx, struct radeon_state_atom *atom)
376 {
377 r200ContextPtr r200 = R200_CONTEXT(ctx);
378 BATCH_LOCALS(&r200->radeon);
379 uint32_t dwords = atom->cmd_size;
380
381 BEGIN_BATCH_NO_AUTOSTATE(dwords);
382 OUT_VECLINEAR(atom->cmd[0], atom->cmd+1);
383 END_BATCH();
384 }
385
386 static void scl_emit(GLcontext *ctx, struct radeon_state_atom *atom)
387 {
388 r200ContextPtr r200 = R200_CONTEXT(ctx);
389 BATCH_LOCALS(&r200->radeon);
390 uint32_t dwords = atom->cmd_size;
391
392 BEGIN_BATCH_NO_AUTOSTATE(dwords);
393 OUT_SCL(atom->cmd[0], atom->cmd+1);
394 END_BATCH();
395 }
396
397
398 static void vec_emit(GLcontext *ctx, struct radeon_state_atom *atom)
399 {
400 r200ContextPtr r200 = R200_CONTEXT(ctx);
401 BATCH_LOCALS(&r200->radeon);
402 uint32_t dwords = atom->cmd_size;
403
404 BEGIN_BATCH_NO_AUTOSTATE(dwords);
405 OUT_VEC(atom->cmd[0], atom->cmd+1);
406 END_BATCH();
407 }
408
409 static void ctx_emit(GLcontext *ctx, struct radeon_state_atom *atom)
410 {
411 r200ContextPtr r200 = R200_CONTEXT(ctx);
412 BATCH_LOCALS(&r200->radeon);
413 struct radeon_renderbuffer *rrb;
414 uint32_t cbpitch;
415 uint32_t zbpitch, depth_fmt;
416 uint32_t dwords = atom->cmd_size;
417
418 /* output the first 7 bytes of context */
419 BEGIN_BATCH_NO_AUTOSTATE(dwords+2+2);
420 OUT_BATCH_TABLE(atom->cmd, 5);
421
422 rrb = radeon_get_depthbuffer(&r200->radeon);
423 if (!rrb) {
424 OUT_BATCH(0);
425 OUT_BATCH(0);
426 } else {
427 zbpitch = (rrb->pitch / rrb->cpp);
428 if (r200->using_hyperz)
429 zbpitch |= RADEON_DEPTH_HYPERZ;
430 OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
431 OUT_BATCH(zbpitch);
432 if (rrb->cpp == 4)
433 depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
434 else
435 depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
436 atom->cmd[CTX_RB3D_ZSTENCILCNTL] &= ~RADEON_DEPTH_FORMAT_MASK;
437 atom->cmd[CTX_RB3D_ZSTENCILCNTL] |= depth_fmt;
438 }
439
440 OUT_BATCH(atom->cmd[CTX_RB3D_ZSTENCILCNTL]);
441 OUT_BATCH(atom->cmd[CTX_CMD_1]);
442 OUT_BATCH(atom->cmd[CTX_PP_CNTL]);
443
444 rrb = radeon_get_colorbuffer(&r200->radeon);
445 if (!rrb || !rrb->bo) {
446 OUT_BATCH(atom->cmd[CTX_RB3D_CNTL]);
447 OUT_BATCH(atom->cmd[CTX_RB3D_COLOROFFSET]);
448 } else {
449 atom->cmd[CTX_RB3D_CNTL] &= ~(0xf << 10);
450 if (rrb->cpp == 4)
451 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB8888;
452 else
453 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_RGB565;
454
455 OUT_BATCH(atom->cmd[CTX_RB3D_CNTL]);
456 OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
457 }
458
459 OUT_BATCH(atom->cmd[CTX_CMD_2]);
460
461 if (!rrb || !rrb->bo) {
462 OUT_BATCH(atom->cmd[CTX_RB3D_COLORPITCH]);
463 } else {
464 cbpitch = (rrb->pitch / rrb->cpp);
465 if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE)
466 cbpitch |= R200_COLOR_TILE_ENABLE;
467 OUT_BATCH(cbpitch);
468 }
469
470 if (atom->cmd_size == CTX_STATE_SIZE_NEWDRM)
471 OUT_BATCH_TABLE((atom->cmd + 14), 4);
472
473 END_BATCH();
474 }
475
476 static void ctx_emit_cs(GLcontext *ctx, struct radeon_state_atom *atom)
477 {
478 r200ContextPtr r200 = R200_CONTEXT(ctx);
479 BATCH_LOCALS(&r200->radeon);
480 struct radeon_renderbuffer *rrb, *drb;
481 uint32_t cbpitch = 0;
482 uint32_t zbpitch = 0;
483 uint32_t dwords = atom->cmd_size;
484 uint32_t depth_fmt;
485
486 rrb = radeon_get_colorbuffer(&r200->radeon);
487 if (!rrb || !rrb->bo) {
488 return;
489 }
490
491 atom->cmd[CTX_RB3D_CNTL] &= ~(0xf << 10);
492 if (rrb->cpp == 4)
493 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB8888;
494 else
495 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_RGB565;
496
497 cbpitch = (rrb->pitch / rrb->cpp);
498 if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE)
499 cbpitch |= R200_COLOR_TILE_ENABLE;
500
501 drb = radeon_get_depthbuffer(&r200->radeon);
502 if (drb) {
503 zbpitch = (drb->pitch / drb->cpp);
504 if (drb->cpp == 4)
505 depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
506 else
507 depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
508 atom->cmd[CTX_RB3D_ZSTENCILCNTL] &= ~RADEON_DEPTH_FORMAT_MASK;
509 atom->cmd[CTX_RB3D_ZSTENCILCNTL] |= depth_fmt;
510 }
511
512 if (drb)
513 dwords += 4;
514 if (rrb)
515 dwords += 4;
516
517 /* output the first 7 bytes of context */
518 BEGIN_BATCH_NO_AUTOSTATE(dwords);
519
520 /* In the CS case we need to split this up */
521 OUT_BATCH(CP_PACKET0(packet[0].start, 3));
522 OUT_BATCH_TABLE((atom->cmd + 1), 4);
523
524 if (drb) {
525 OUT_BATCH(CP_PACKET0(RADEON_RB3D_DEPTHOFFSET, 0));
526 OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
527
528 OUT_BATCH(CP_PACKET0(RADEON_RB3D_DEPTHPITCH, 0));
529 OUT_BATCH(zbpitch);
530 }
531
532 OUT_BATCH(CP_PACKET0(RADEON_RB3D_ZSTENCILCNTL, 0));
533 OUT_BATCH(atom->cmd[CTX_RB3D_ZSTENCILCNTL]);
534 OUT_BATCH(CP_PACKET0(RADEON_PP_CNTL, 1));
535 OUT_BATCH(atom->cmd[CTX_PP_CNTL]);
536 OUT_BATCH(atom->cmd[CTX_RB3D_CNTL]);
537
538
539 if (rrb) {
540 OUT_BATCH(CP_PACKET0(RADEON_RB3D_COLOROFFSET, 0));
541 OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
542 }
543
544 if (rrb) {
545 OUT_BATCH(CP_PACKET0(RADEON_RB3D_COLORPITCH, 0));
546 OUT_BATCH(cbpitch);
547 }
548
549 if (atom->cmd_size == CTX_STATE_SIZE_NEWDRM) {
550 OUT_BATCH_TABLE((atom->cmd + 14), 4);
551 }
552
553 END_BATCH();
554 }
555
556 static void tex_emit(GLcontext *ctx, struct radeon_state_atom *atom)
557 {
558 r200ContextPtr r200 = R200_CONTEXT(ctx);
559 BATCH_LOCALS(&r200->radeon);
560 uint32_t dwords = atom->cmd_size;
561 int i = atom->idx;
562 radeonTexObj *t = r200->state.texture.unit[i].texobj;
563
564 if (t && t->mt && !t->image_override)
565 dwords += 2;
566 BEGIN_BATCH_NO_AUTOSTATE(dwords);
567 OUT_BATCH_TABLE(atom->cmd, 10);
568 if (t && !t->image_override) {
569 OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, 0,
570 RADEON_GEM_DOMAIN_VRAM, 0, 0);
571 } else if (!t) {
572 /* workaround for old CS mechanism */
573 OUT_BATCH(r200->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP]);
574 } else if (t->image_override)
575 OUT_BATCH(t->override_offset);
576
577 END_BATCH();
578 }
579
580 static void cube_emit(GLcontext *ctx, struct radeon_state_atom *atom)
581 {
582 r200ContextPtr r200 = R200_CONTEXT(ctx);
583 BATCH_LOCALS(&r200->radeon);
584 uint32_t dwords = atom->cmd_size;
585 int i = atom->idx;
586 radeonTexObj *t = r200->state.texture.unit[i].texobj;
587 GLuint size;
588
589 BEGIN_BATCH_NO_AUTOSTATE(dwords + (2 * 5));
590 OUT_BATCH_TABLE(atom->cmd, 3);
591
592 if (t && !t->image_override) {
593 size = t->mt->totalsize / 6;
594 OUT_BATCH_RELOC(0, t->mt->bo, size, RADEON_GEM_DOMAIN_VRAM, 0, 0);
595 OUT_BATCH_RELOC(0, t->mt->bo, size * 2, RADEON_GEM_DOMAIN_VRAM, 0, 0);
596 OUT_BATCH_RELOC(0, t->mt->bo, size * 3, RADEON_GEM_DOMAIN_VRAM, 0, 0);
597 OUT_BATCH_RELOC(0, t->mt->bo, size * 4, RADEON_GEM_DOMAIN_VRAM, 0, 0);
598 OUT_BATCH_RELOC(0, t->mt->bo, size * 5, RADEON_GEM_DOMAIN_VRAM, 0, 0);
599 }
600 END_BATCH();
601 }
602
603 /* Initialize the context's hardware state.
604 */
605 void r200InitState( r200ContextPtr rmesa )
606 {
607 GLcontext *ctx = rmesa->radeon.glCtx;
608 GLuint i;
609
610 rmesa->radeon.state.color.clear = 0x00000000;
611
612 switch ( ctx->Visual.depthBits ) {
613 case 16:
614 rmesa->radeon.state.depth.clear = 0x0000ffff;
615 rmesa->radeon.state.depth.scale = 1.0 / (GLfloat)0xffff;
616 rmesa->radeon.state.stencil.clear = 0x00000000;
617 break;
618 case 24:
619 rmesa->radeon.state.depth.clear = 0x00ffffff;
620 rmesa->radeon.state.depth.scale = 1.0 / (GLfloat)0xffffff;
621 rmesa->radeon.state.stencil.clear = 0xffff0000;
622 break;
623 default:
624 fprintf( stderr, "Error: Unsupported depth %d... exiting\n",
625 ctx->Visual.depthBits );
626 exit( -1 );
627 }
628
629 /* Only have hw stencil when depth buffer is 24 bits deep */
630 rmesa->radeon.state.stencil.hwBuffer = ( ctx->Visual.stencilBits > 0 &&
631 ctx->Visual.depthBits == 24 );
632
633 rmesa->radeon.Fallback = 0;
634
635 rmesa->radeon.hw.max_state_size = 0;
636
637 #define ALLOC_STATE( ATOM, CHK, SZ, NM, IDX ) \
638 do { \
639 rmesa->hw.ATOM.cmd_size = SZ; \
640 rmesa->hw.ATOM.cmd = (GLuint *)CALLOC(SZ * sizeof(int)); \
641 rmesa->hw.ATOM.lastcmd = (GLuint *)CALLOC(SZ * sizeof(int)); \
642 rmesa->hw.ATOM.name = NM; \
643 rmesa->hw.ATOM.idx = IDX; \
644 rmesa->hw.ATOM.check = check_##CHK; \
645 rmesa->hw.ATOM.dirty = GL_FALSE; \
646 rmesa->radeon.hw.max_state_size += SZ * sizeof(int); \
647 } while (0)
648
649
650 /* Allocate state buffers:
651 */
652 if (rmesa->radeon.radeonScreen->drmSupportsBlendColor)
653 ALLOC_STATE( ctx, always, CTX_STATE_SIZE_NEWDRM, "CTX/context", 0 );
654 else
655 ALLOC_STATE( ctx, always, CTX_STATE_SIZE_OLDDRM, "CTX/context", 0 );
656
657 if (rmesa->radeon.radeonScreen->kernel_mm)
658 rmesa->hw.ctx.emit = ctx_emit_cs;
659 else
660 rmesa->hw.ctx.emit = ctx_emit;
661 ALLOC_STATE( set, always, SET_STATE_SIZE, "SET/setup", 0 );
662 ALLOC_STATE( lin, always, LIN_STATE_SIZE, "LIN/line", 0 );
663 ALLOC_STATE( msk, always, MSK_STATE_SIZE, "MSK/mask", 0 );
664 ALLOC_STATE( vpt, always, VPT_STATE_SIZE, "VPT/viewport", 0 );
665 ALLOC_STATE( vtx, always, VTX_STATE_SIZE, "VTX/vertex", 0 );
666 ALLOC_STATE( vap, always, VAP_STATE_SIZE, "VAP/vap", 0 );
667 ALLOC_STATE( vte, always, VTE_STATE_SIZE, "VTE/vte", 0 );
668 ALLOC_STATE( msc, always, MSC_STATE_SIZE, "MSC/misc", 0 );
669 ALLOC_STATE( cst, always, CST_STATE_SIZE, "CST/constant", 0 );
670 ALLOC_STATE( zbs, always, ZBS_STATE_SIZE, "ZBS/zbias", 0 );
671 ALLOC_STATE( tf, tf, TF_STATE_SIZE, "TF/tfactor", 0 );
672 if (rmesa->radeon.radeonScreen->drmSupportsFragShader) {
673 if (rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_R200) {
674 /* make sure texture units 0/1 are emitted pair-wise for r200 t0 hang workaround */
675 ALLOC_STATE( tex[0], tex_pair, TEX_STATE_SIZE_NEWDRM, "TEX/tex-0", 0 );
676 ALLOC_STATE( tex[1], tex_pair, TEX_STATE_SIZE_NEWDRM, "TEX/tex-1", 1 );
677 ALLOC_STATE( tam, tex_any, TAM_STATE_SIZE, "TAM/tam", 0 );
678 }
679 else {
680 ALLOC_STATE( tex[0], tex, TEX_STATE_SIZE_NEWDRM, "TEX/tex-0", 0 );
681 ALLOC_STATE( tex[1], tex, TEX_STATE_SIZE_NEWDRM, "TEX/tex-1", 1 );
682 ALLOC_STATE( tam, never, TAM_STATE_SIZE, "TAM/tam", 0 );
683 }
684 ALLOC_STATE( tex[2], tex, TEX_STATE_SIZE_NEWDRM, "TEX/tex-2", 2 );
685 ALLOC_STATE( tex[3], tex, TEX_STATE_SIZE_NEWDRM, "TEX/tex-3", 3 );
686 ALLOC_STATE( tex[4], tex, TEX_STATE_SIZE_NEWDRM, "TEX/tex-4", 4 );
687 ALLOC_STATE( tex[5], tex, TEX_STATE_SIZE_NEWDRM, "TEX/tex-5", 5 );
688 ALLOC_STATE( atf, afs, ATF_STATE_SIZE, "ATF/tfactor", 0 );
689 ALLOC_STATE( afs[0], afs_pass1, AFS_STATE_SIZE, "AFS/afsinst-0", 0 );
690 ALLOC_STATE( afs[1], afs, AFS_STATE_SIZE, "AFS/afsinst-1", 1 );
691 }
692 else {
693 if (rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_R200) {
694 ALLOC_STATE( tex[0], tex_pair, TEX_STATE_SIZE_OLDDRM, "TEX/tex-0", 0 );
695 ALLOC_STATE( tex[1], tex_pair, TEX_STATE_SIZE_OLDDRM, "TEX/tex-1", 1 );
696 ALLOC_STATE( tam, tex_any, TAM_STATE_SIZE, "TAM/tam", 0 );
697 }
698 else {
699 ALLOC_STATE( tex[0], tex, TEX_STATE_SIZE_OLDDRM, "TEX/tex-0", 0 );
700 ALLOC_STATE( tex[1], tex, TEX_STATE_SIZE_OLDDRM, "TEX/tex-1", 1 );
701 ALLOC_STATE( tam, never, TAM_STATE_SIZE, "TAM/tam", 0 );
702 }
703 ALLOC_STATE( tex[2], tex, TEX_STATE_SIZE_OLDDRM, "TEX/tex-2", 2 );
704 ALLOC_STATE( tex[3], tex, TEX_STATE_SIZE_OLDDRM, "TEX/tex-3", 3 );
705 ALLOC_STATE( tex[4], tex, TEX_STATE_SIZE_OLDDRM, "TEX/tex-4", 4 );
706 ALLOC_STATE( tex[5], tex, TEX_STATE_SIZE_OLDDRM, "TEX/tex-5", 5 );
707 ALLOC_STATE( atf, never, ATF_STATE_SIZE, "TF/tfactor", 0 );
708 ALLOC_STATE( afs[0], never, AFS_STATE_SIZE, "AFS/afsinst-0", 0 );
709 ALLOC_STATE( afs[1], never, AFS_STATE_SIZE, "AFS/afsinst-1", 1 );
710 }
711
712 for (i = 0; i < 5; i++)
713 rmesa->hw.tex[i].emit = tex_emit;
714 if (rmesa->radeon.radeonScreen->drmSupportsCubeMapsR200) {
715 ALLOC_STATE( cube[0], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-0", 0 );
716 ALLOC_STATE( cube[1], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-1", 1 );
717 ALLOC_STATE( cube[2], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-2", 2 );
718 ALLOC_STATE( cube[3], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-3", 3 );
719 ALLOC_STATE( cube[4], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-4", 4 );
720 ALLOC_STATE( cube[5], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-5", 5 );
721 for (i = 0; i < 5; i++)
722 rmesa->hw.cube[i].emit = cube_emit;
723 }
724 else {
725 ALLOC_STATE( cube[0], never, CUBE_STATE_SIZE, "CUBE/tex-0", 0 );
726 ALLOC_STATE( cube[1], never, CUBE_STATE_SIZE, "CUBE/tex-1", 1 );
727 ALLOC_STATE( cube[2], never, CUBE_STATE_SIZE, "CUBE/tex-2", 2 );
728 ALLOC_STATE( cube[3], never, CUBE_STATE_SIZE, "CUBE/tex-3", 3 );
729 ALLOC_STATE( cube[4], never, CUBE_STATE_SIZE, "CUBE/tex-4", 4 );
730 ALLOC_STATE( cube[5], never, CUBE_STATE_SIZE, "CUBE/tex-5", 5 );
731 }
732
733 if (rmesa->radeon.radeonScreen->drmSupportsVertexProgram) {
734 ALLOC_STATE( pvs, tcl_vp, PVS_STATE_SIZE, "PVS/pvscntl", 0 );
735 ALLOC_STATE( vpi[0], tcl_vp, VPI_STATE_SIZE, "VP/vertexprog-0", 0 );
736 ALLOC_STATE( vpi[1], tcl_vp_size, VPI_STATE_SIZE, "VP/vertexprog-1", 1 );
737 ALLOC_STATE( vpp[0], tcl_vp, VPP_STATE_SIZE, "VPP/vertexparam-0", 0 );
738 ALLOC_STATE( vpp[1], tcl_vpp_size, VPP_STATE_SIZE, "VPP/vertexparam-1", 1 );
739 }
740 else {
741 ALLOC_STATE( pvs, never, PVS_STATE_SIZE, "PVS/pvscntl", 0 );
742 ALLOC_STATE( vpi[0], never, VPI_STATE_SIZE, "VP/vertexprog-0", 0 );
743 ALLOC_STATE( vpi[1], never, VPI_STATE_SIZE, "VP/vertexprog-1", 1 );
744 ALLOC_STATE( vpp[0], never, VPP_STATE_SIZE, "VPP/vertexparam-0", 0 );
745 ALLOC_STATE( vpp[1], never, VPP_STATE_SIZE, "VPP/vertexparam-1", 1 );
746 }
747 /* FIXME: this atom has two commands, we need only one (ucp_vert_blend) for vp */
748 ALLOC_STATE( tcl, tcl_or_vp, TCL_STATE_SIZE, "TCL/tcl", 0 );
749 ALLOC_STATE( msl, tcl, MSL_STATE_SIZE, "MSL/matrix-select", 0 );
750 ALLOC_STATE( tcg, tcl, TCG_STATE_SIZE, "TCG/texcoordgen", 0 );
751 ALLOC_STATE( mtl[0], tcl_lighting, MTL_STATE_SIZE, "MTL0/material0", 0 );
752 ALLOC_STATE( mtl[1], tcl_lighting, MTL_STATE_SIZE, "MTL1/material1", 1 );
753 ALLOC_STATE( grd, tcl_or_vp, GRD_STATE_SIZE, "GRD/guard-band", 0 );
754 ALLOC_STATE( fog, tcl_fog, FOG_STATE_SIZE, "FOG/fog", 0 );
755 ALLOC_STATE( glt, tcl_lighting, GLT_STATE_SIZE, "GLT/light-global", 0 );
756 ALLOC_STATE( eye, tcl_lighting, EYE_STATE_SIZE, "EYE/eye-vector", 0 );
757 ALLOC_STATE( mat[R200_MTX_MV], tcl, MAT_STATE_SIZE, "MAT/modelview", 0 );
758 ALLOC_STATE( mat[R200_MTX_IMV], tcl, MAT_STATE_SIZE, "MAT/it-modelview", 0 );
759 ALLOC_STATE( mat[R200_MTX_MVP], tcl, MAT_STATE_SIZE, "MAT/modelproject", 0 );
760 ALLOC_STATE( mat[R200_MTX_TEX0], tcl_tex, MAT_STATE_SIZE, "MAT/texmat0", 0 );
761 ALLOC_STATE( mat[R200_MTX_TEX1], tcl_tex, MAT_STATE_SIZE, "MAT/texmat1", 1 );
762 ALLOC_STATE( mat[R200_MTX_TEX2], tcl_tex, MAT_STATE_SIZE, "MAT/texmat2", 2 );
763 ALLOC_STATE( mat[R200_MTX_TEX3], tcl_tex, MAT_STATE_SIZE, "MAT/texmat3", 3 );
764 ALLOC_STATE( mat[R200_MTX_TEX4], tcl_tex, MAT_STATE_SIZE, "MAT/texmat4", 4 );
765 ALLOC_STATE( mat[R200_MTX_TEX5], tcl_tex, MAT_STATE_SIZE, "MAT/texmat5", 5 );
766 ALLOC_STATE( ucp[0], tcl_ucp, UCP_STATE_SIZE, "UCP/userclip-0", 0 );
767 ALLOC_STATE( ucp[1], tcl_ucp, UCP_STATE_SIZE, "UCP/userclip-1", 1 );
768 ALLOC_STATE( ucp[2], tcl_ucp, UCP_STATE_SIZE, "UCP/userclip-2", 2 );
769 ALLOC_STATE( ucp[3], tcl_ucp, UCP_STATE_SIZE, "UCP/userclip-3", 3 );
770 ALLOC_STATE( ucp[4], tcl_ucp, UCP_STATE_SIZE, "UCP/userclip-4", 4 );
771 ALLOC_STATE( ucp[5], tcl_ucp, UCP_STATE_SIZE, "UCP/userclip-5", 5 );
772 ALLOC_STATE( lit[0], tcl_light, LIT_STATE_SIZE, "LIT/light-0", 0 );
773 ALLOC_STATE( lit[1], tcl_light, LIT_STATE_SIZE, "LIT/light-1", 1 );
774 ALLOC_STATE( lit[2], tcl_light, LIT_STATE_SIZE, "LIT/light-2", 2 );
775 ALLOC_STATE( lit[3], tcl_light, LIT_STATE_SIZE, "LIT/light-3", 3 );
776 ALLOC_STATE( lit[4], tcl_light, LIT_STATE_SIZE, "LIT/light-4", 4 );
777 ALLOC_STATE( lit[5], tcl_light, LIT_STATE_SIZE, "LIT/light-5", 5 );
778 ALLOC_STATE( lit[6], tcl_light, LIT_STATE_SIZE, "LIT/light-6", 6 );
779 ALLOC_STATE( lit[7], tcl_light, LIT_STATE_SIZE, "LIT/light-7", 7 );
780 ALLOC_STATE( pix[0], pix_zero, PIX_STATE_SIZE, "PIX/pixstage-0", 0 );
781 ALLOC_STATE( pix[1], texenv, PIX_STATE_SIZE, "PIX/pixstage-1", 1 );
782 ALLOC_STATE( pix[2], texenv, PIX_STATE_SIZE, "PIX/pixstage-2", 2 );
783 ALLOC_STATE( pix[3], texenv, PIX_STATE_SIZE, "PIX/pixstage-3", 3 );
784 ALLOC_STATE( pix[4], texenv, PIX_STATE_SIZE, "PIX/pixstage-4", 4 );
785 ALLOC_STATE( pix[5], texenv, PIX_STATE_SIZE, "PIX/pixstage-5", 5 );
786 if (rmesa->radeon.radeonScreen->drmSupportsTriPerf) {
787 ALLOC_STATE( prf, always, PRF_STATE_SIZE, "PRF/performance-tri", 0 );
788 }
789 else {
790 ALLOC_STATE( prf, never, PRF_STATE_SIZE, "PRF/performance-tri", 0 );
791 }
792 if (rmesa->radeon.radeonScreen->drmSupportsPointSprites) {
793 ALLOC_STATE( spr, always, SPR_STATE_SIZE, "SPR/pointsprite", 0 );
794 ALLOC_STATE( ptp, tcl, PTP_STATE_SIZE, "PTP/pointparams", 0 );
795 }
796 else {
797 ALLOC_STATE (spr, never, SPR_STATE_SIZE, "SPR/pointsprite", 0 );
798 ALLOC_STATE (ptp, never, PTP_STATE_SIZE, "PTP/pointparams", 0 );
799 }
800
801 r200SetUpAtomList( rmesa );
802
803 /* Fill in the packet headers:
804 */
805 rmesa->hw.ctx.cmd[CTX_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_MISC);
806 rmesa->hw.ctx.cmd[CTX_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_PP_CNTL);
807 rmesa->hw.ctx.cmd[CTX_CMD_2] = cmdpkt(rmesa, RADEON_EMIT_RB3D_COLORPITCH);
808 if (rmesa->radeon.radeonScreen->drmSupportsBlendColor)
809 rmesa->hw.ctx.cmd[CTX_CMD_3] = cmdpkt(rmesa, R200_EMIT_RB3D_BLENDCOLOR);
810 rmesa->hw.lin.cmd[LIN_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_RE_LINE_PATTERN);
811 rmesa->hw.lin.cmd[LIN_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_SE_LINE_WIDTH);
812 rmesa->hw.msk.cmd[MSK_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_RB3D_STENCILREFMASK);
813 rmesa->hw.vpt.cmd[VPT_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_SE_VPORT_XSCALE);
814 rmesa->hw.set.cmd[SET_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_SE_CNTL);
815 rmesa->hw.msc.cmd[MSC_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_RE_MISC);
816 rmesa->hw.cst.cmd[CST_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_CNTL_X);
817 rmesa->hw.cst.cmd[CST_CMD_1] = cmdpkt(rmesa, R200_EMIT_RB3D_DEPTHXY_OFFSET);
818 rmesa->hw.cst.cmd[CST_CMD_2] = cmdpkt(rmesa, R200_EMIT_RE_AUX_SCISSOR_CNTL);
819 rmesa->hw.cst.cmd[CST_CMD_3] = cmdpkt(rmesa, R200_EMIT_RE_SCISSOR_TL_0);
820 rmesa->hw.cst.cmd[CST_CMD_4] = cmdpkt(rmesa, R200_EMIT_SE_VAP_CNTL_STATUS);
821 rmesa->hw.cst.cmd[CST_CMD_5] = cmdpkt(rmesa, R200_EMIT_RE_POINTSIZE);
822 rmesa->hw.cst.cmd[CST_CMD_6] = cmdpkt(rmesa, R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0);
823 rmesa->hw.tam.cmd[TAM_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TAM_DEBUG3);
824 rmesa->hw.tf.cmd[TF_CMD_0] = cmdpkt(rmesa, R200_EMIT_TFACTOR_0);
825 if (rmesa->radeon.radeonScreen->drmSupportsFragShader) {
826 rmesa->hw.atf.cmd[ATF_CMD_0] = cmdpkt(rmesa, R200_EMIT_ATF_TFACTOR);
827 rmesa->hw.tex[0].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCTLALL_0);
828 rmesa->hw.tex[0].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_0);
829 rmesa->hw.tex[1].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCTLALL_1);
830 rmesa->hw.tex[1].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_1);
831 rmesa->hw.tex[2].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCTLALL_2);
832 rmesa->hw.tex[2].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_2);
833 rmesa->hw.tex[3].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCTLALL_3);
834 rmesa->hw.tex[3].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_3);
835 rmesa->hw.tex[4].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCTLALL_4);
836 rmesa->hw.tex[4].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_4);
837 rmesa->hw.tex[5].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCTLALL_5);
838 rmesa->hw.tex[5].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_5);
839 } else {
840 rmesa->hw.tex[0].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXFILTER_0);
841 rmesa->hw.tex[0].cmd[TEX_CMD_1_OLDDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_0);
842 rmesa->hw.tex[1].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXFILTER_1);
843 rmesa->hw.tex[1].cmd[TEX_CMD_1_OLDDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_1);
844 rmesa->hw.tex[2].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXFILTER_2);
845 rmesa->hw.tex[2].cmd[TEX_CMD_1_OLDDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_2);
846 rmesa->hw.tex[3].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXFILTER_3);
847 rmesa->hw.tex[3].cmd[TEX_CMD_1_OLDDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_3);
848 rmesa->hw.tex[4].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXFILTER_4);
849 rmesa->hw.tex[4].cmd[TEX_CMD_1_OLDDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_4);
850 rmesa->hw.tex[5].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXFILTER_5);
851 rmesa->hw.tex[5].cmd[TEX_CMD_1_OLDDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_5);
852 }
853 rmesa->hw.afs[0].cmd[AFS_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_AFS_0);
854 rmesa->hw.afs[1].cmd[AFS_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_AFS_1);
855 rmesa->hw.pvs.cmd[PVS_CMD_0] = cmdpkt(rmesa, R200_EMIT_VAP_PVS_CNTL);
856 rmesa->hw.cube[0].cmd[CUBE_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_FACES_0);
857 rmesa->hw.cube[0].cmd[CUBE_CMD_1] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_OFFSETS_0);
858 rmesa->hw.cube[1].cmd[CUBE_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_FACES_1);
859 rmesa->hw.cube[1].cmd[CUBE_CMD_1] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_OFFSETS_1);
860 rmesa->hw.cube[2].cmd[CUBE_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_FACES_2);
861 rmesa->hw.cube[2].cmd[CUBE_CMD_1] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_OFFSETS_2);
862 rmesa->hw.cube[3].cmd[CUBE_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_FACES_3);
863 rmesa->hw.cube[3].cmd[CUBE_CMD_1] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_OFFSETS_3);
864 rmesa->hw.cube[4].cmd[CUBE_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_FACES_4);
865 rmesa->hw.cube[4].cmd[CUBE_CMD_1] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_OFFSETS_4);
866 rmesa->hw.cube[5].cmd[CUBE_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_FACES_5);
867 rmesa->hw.cube[5].cmd[CUBE_CMD_1] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_OFFSETS_5);
868 rmesa->hw.pix[0].cmd[PIX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCBLEND_0);
869 rmesa->hw.pix[1].cmd[PIX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCBLEND_1);
870 rmesa->hw.pix[2].cmd[PIX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCBLEND_2);
871 rmesa->hw.pix[3].cmd[PIX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCBLEND_3);
872 rmesa->hw.pix[4].cmd[PIX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCBLEND_4);
873 rmesa->hw.pix[5].cmd[PIX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCBLEND_5);
874 rmesa->hw.zbs.cmd[ZBS_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_SE_ZBIAS_FACTOR);
875 rmesa->hw.tcl.cmd[TCL_CMD_0] = cmdpkt(rmesa, R200_EMIT_TCL_LIGHT_MODEL_CTL_0);
876 rmesa->hw.tcl.cmd[TCL_CMD_1] = cmdpkt(rmesa, R200_EMIT_TCL_UCP_VERT_BLEND_CTL);
877 rmesa->hw.tcg.cmd[TCG_CMD_0] = cmdpkt(rmesa, R200_EMIT_TEX_PROC_CTL_2);
878 rmesa->hw.msl.cmd[MSL_CMD_0] = cmdpkt(rmesa, R200_EMIT_MATRIX_SELECT_0);
879 rmesa->hw.vap.cmd[VAP_CMD_0] = cmdpkt(rmesa, R200_EMIT_VAP_CTL);
880 rmesa->hw.vtx.cmd[VTX_CMD_0] = cmdpkt(rmesa, R200_EMIT_VTX_FMT_0);
881 rmesa->hw.vtx.cmd[VTX_CMD_1] = cmdpkt(rmesa, R200_EMIT_OUTPUT_VTX_COMP_SEL);
882 rmesa->hw.vtx.cmd[VTX_CMD_2] = cmdpkt(rmesa, R200_EMIT_SE_VTX_STATE_CNTL);
883 rmesa->hw.vte.cmd[VTE_CMD_0] = cmdpkt(rmesa, R200_EMIT_VTE_CNTL);
884 rmesa->hw.prf.cmd[PRF_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TRI_PERF_CNTL);
885 rmesa->hw.spr.cmd[SPR_CMD_0] = cmdpkt(rmesa, R200_EMIT_TCL_POINT_SPRITE_CNTL);
886 if (rmesa->radeon.radeonScreen->kernel_mm) {
887 rmesa->hw.mtl[0].emit = mtl_emit;
888 rmesa->hw.mtl[1].emit = mtl_emit;
889
890 rmesa->hw.vpi[0].emit = veclinear_emit;
891 rmesa->hw.vpi[1].emit = veclinear_emit;
892 rmesa->hw.vpp[0].emit = veclinear_emit;
893 rmesa->hw.vpp[1].emit = veclinear_emit;
894
895 rmesa->hw.grd.emit = scl_emit;
896 rmesa->hw.fog.emit = vec_emit;
897 rmesa->hw.glt.emit = vec_emit;
898 rmesa->hw.eye.emit = vec_emit;
899
900 for (i = R200_MTX_MV; i <= R200_MTX_TEX5; i++)
901 rmesa->hw.mat[i].emit = vec_emit;
902
903 for (i = 0; i < 8; i++)
904 rmesa->hw.lit[i].emit = lit_emit;
905
906 for (i = 0; i < 6; i++)
907 rmesa->hw.ucp[i].emit = vec_emit;
908
909 rmesa->hw.ptp.emit = ptp_emit;
910 }
911
912
913
914 rmesa->hw.mtl[0].cmd[MTL_CMD_0] =
915 cmdvec( R200_VS_MAT_0_EMISS, 1, 16 );
916 rmesa->hw.mtl[0].cmd[MTL_CMD_1] =
917 cmdscl2( R200_SS_MAT_0_SHININESS, 1, 1 );
918 rmesa->hw.mtl[1].cmd[MTL_CMD_0] =
919 cmdvec( R200_VS_MAT_1_EMISS, 1, 16 );
920 rmesa->hw.mtl[1].cmd[MTL_CMD_1] =
921 cmdscl2( R200_SS_MAT_1_SHININESS, 1, 1 );
922
923 rmesa->hw.vpi[0].cmd[VPI_CMD_0] =
924 cmdveclinear( R200_PVS_PROG0, 64 );
925 rmesa->hw.vpi[1].cmd[VPI_CMD_0] =
926 cmdveclinear( R200_PVS_PROG1, 64 );
927 rmesa->hw.vpp[0].cmd[VPP_CMD_0] =
928 cmdveclinear( R200_PVS_PARAM0, 96 );
929 rmesa->hw.vpp[1].cmd[VPP_CMD_0] =
930 cmdveclinear( R200_PVS_PARAM1, 96 );
931
932 rmesa->hw.grd.cmd[GRD_CMD_0] =
933 cmdscl( R200_SS_VERT_GUARD_CLIP_ADJ_ADDR, 1, 4 );
934 rmesa->hw.fog.cmd[FOG_CMD_0] =
935 cmdvec( R200_VS_FOG_PARAM_ADDR, 1, 4 );
936 rmesa->hw.glt.cmd[GLT_CMD_0] =
937 cmdvec( R200_VS_GLOBAL_AMBIENT_ADDR, 1, 4 );
938 rmesa->hw.eye.cmd[EYE_CMD_0] =
939 cmdvec( R200_VS_EYE_VECTOR_ADDR, 1, 4 );
940
941 rmesa->hw.mat[R200_MTX_MV].cmd[MAT_CMD_0] =
942 cmdvec( R200_VS_MATRIX_0_MV, 1, 16);
943 rmesa->hw.mat[R200_MTX_IMV].cmd[MAT_CMD_0] =
944 cmdvec( R200_VS_MATRIX_1_INV_MV, 1, 16);
945 rmesa->hw.mat[R200_MTX_MVP].cmd[MAT_CMD_0] =
946 cmdvec( R200_VS_MATRIX_2_MVP, 1, 16);
947 rmesa->hw.mat[R200_MTX_TEX0].cmd[MAT_CMD_0] =
948 cmdvec( R200_VS_MATRIX_3_TEX0, 1, 16);
949 rmesa->hw.mat[R200_MTX_TEX1].cmd[MAT_CMD_0] =
950 cmdvec( R200_VS_MATRIX_4_TEX1, 1, 16);
951 rmesa->hw.mat[R200_MTX_TEX2].cmd[MAT_CMD_0] =
952 cmdvec( R200_VS_MATRIX_5_TEX2, 1, 16);
953 rmesa->hw.mat[R200_MTX_TEX3].cmd[MAT_CMD_0] =
954 cmdvec( R200_VS_MATRIX_6_TEX3, 1, 16);
955 rmesa->hw.mat[R200_MTX_TEX4].cmd[MAT_CMD_0] =
956 cmdvec( R200_VS_MATRIX_7_TEX4, 1, 16);
957 rmesa->hw.mat[R200_MTX_TEX5].cmd[MAT_CMD_0] =
958 cmdvec( R200_VS_MATRIX_8_TEX5, 1, 16);
959
960 for (i = 0 ; i < 8; i++) {
961 rmesa->hw.lit[i].cmd[LIT_CMD_0] =
962 cmdvec( R200_VS_LIGHT_AMBIENT_ADDR + i, 8, 24 );
963 rmesa->hw.lit[i].cmd[LIT_CMD_1] =
964 cmdscl( R200_SS_LIGHT_DCD_ADDR + i, 8, 7 );
965 }
966
967 for (i = 0 ; i < 6; i++) {
968 rmesa->hw.ucp[i].cmd[UCP_CMD_0] =
969 cmdvec( R200_VS_UCP_ADDR + i, 1, 4 );
970 }
971
972 rmesa->hw.ptp.cmd[PTP_CMD_0] =
973 cmdvec( R200_VS_PNT_SPRITE_VPORT_SCALE, 1, 4 );
974 rmesa->hw.ptp.cmd[PTP_CMD_1] =
975 cmdvec( R200_VS_PNT_SPRITE_ATT_CONST, 1, 12 );
976
977 /* Initial Harware state:
978 */
979 rmesa->hw.ctx.cmd[CTX_PP_MISC] = (R200_ALPHA_TEST_PASS
980 /* | R200_RIGHT_HAND_CUBE_OGL*/);
981
982 rmesa->hw.ctx.cmd[CTX_PP_FOG_COLOR] = (R200_FOG_VERTEX |
983 R200_FOG_USE_SPEC_ALPHA);
984
985 rmesa->hw.ctx.cmd[CTX_RE_SOLID_COLOR] = 0x00000000;
986
987 rmesa->hw.ctx.cmd[CTX_RB3D_BLENDCNTL] = (R200_COMB_FCN_ADD_CLAMP |
988 (R200_BLEND_GL_ONE << R200_SRC_BLEND_SHIFT) |
989 (R200_BLEND_GL_ZERO << R200_DST_BLEND_SHIFT));
990
991 if (rmesa->radeon.radeonScreen->drmSupportsBlendColor) {
992 rmesa->hw.ctx.cmd[CTX_RB3D_BLENDCOLOR] = 0x00000000;
993 rmesa->hw.ctx.cmd[CTX_RB3D_ABLENDCNTL] = (R200_COMB_FCN_ADD_CLAMP |
994 (R200_BLEND_GL_ONE << R200_SRC_BLEND_SHIFT) |
995 (R200_BLEND_GL_ZERO << R200_DST_BLEND_SHIFT));
996 rmesa->hw.ctx.cmd[CTX_RB3D_CBLENDCNTL] = (R200_COMB_FCN_ADD_CLAMP |
997 (R200_BLEND_GL_ONE << R200_SRC_BLEND_SHIFT) |
998 (R200_BLEND_GL_ZERO << R200_DST_BLEND_SHIFT));
999 }
1000
1001 rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHOFFSET] =
1002 rmesa->radeon.radeonScreen->depthOffset + rmesa->radeon.radeonScreen->fbLocation;
1003
1004 rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHPITCH] =
1005 ((rmesa->radeon.radeonScreen->depthPitch &
1006 R200_DEPTHPITCH_MASK) |
1007 R200_DEPTH_ENDIAN_NO_SWAP);
1008
1009 if (rmesa->using_hyperz)
1010 rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHPITCH] |= R200_DEPTH_HYPERZ;
1011
1012 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] = (R200_Z_TEST_LESS |
1013 R200_STENCIL_TEST_ALWAYS |
1014 R200_STENCIL_FAIL_KEEP |
1015 R200_STENCIL_ZPASS_KEEP |
1016 R200_STENCIL_ZFAIL_KEEP |
1017 R200_Z_WRITE_ENABLE);
1018
1019 if (rmesa->using_hyperz) {
1020 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= R200_Z_COMPRESSION_ENABLE |
1021 R200_Z_DECOMPRESSION_ENABLE;
1022 /* if (rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_R200)
1023 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_HIERARCHY_ENABLE;*/
1024 }
1025
1026 rmesa->hw.ctx.cmd[CTX_PP_CNTL] = (R200_ANTI_ALIAS_NONE
1027 | R200_TEX_BLEND_0_ENABLE);
1028
1029 switch ( driQueryOptioni( &rmesa->radeon.optionCache, "dither_mode" ) ) {
1030 case DRI_CONF_DITHER_XERRORDIFFRESET:
1031 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= R200_DITHER_INIT;
1032 break;
1033 case DRI_CONF_DITHER_ORDERED:
1034 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= R200_SCALE_DITHER_ENABLE;
1035 break;
1036 }
1037 if ( driQueryOptioni( &rmesa->radeon.optionCache, "round_mode" ) ==
1038 DRI_CONF_ROUND_ROUND )
1039 rmesa->radeon.state.color.roundEnable = R200_ROUND_ENABLE;
1040 else
1041 rmesa->radeon.state.color.roundEnable = 0;
1042 if ( driQueryOptioni (&rmesa->radeon.optionCache, "color_reduction" ) ==
1043 DRI_CONF_COLOR_REDUCTION_DITHER )
1044 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= R200_DITHER_ENABLE;
1045 else
1046 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= rmesa->radeon.state.color.roundEnable;
1047
1048 rmesa->hw.prf.cmd[PRF_PP_TRI_PERF] = R200_TRI_CUTOFF_MASK - R200_TRI_CUTOFF_MASK *
1049 driQueryOptionf (&rmesa->radeon.optionCache,"texture_blend_quality");
1050 rmesa->hw.prf.cmd[PRF_PP_PERF_CNTL] = 0;
1051
1052 rmesa->hw.set.cmd[SET_SE_CNTL] = (R200_FFACE_CULL_CCW |
1053 R200_BFACE_SOLID |
1054 R200_FFACE_SOLID |
1055 R200_FLAT_SHADE_VTX_LAST |
1056 R200_DIFFUSE_SHADE_GOURAUD |
1057 R200_ALPHA_SHADE_GOURAUD |
1058 R200_SPECULAR_SHADE_GOURAUD |
1059 R200_FOG_SHADE_GOURAUD |
1060 R200_DISC_FOG_SHADE_GOURAUD |
1061 R200_VTX_PIX_CENTER_OGL |
1062 R200_ROUND_MODE_TRUNC |
1063 R200_ROUND_PREC_8TH_PIX);
1064
1065 rmesa->hw.set.cmd[SET_RE_CNTL] = (R200_PERSPECTIVE_ENABLE |
1066 R200_SCISSOR_ENABLE);
1067
1068 rmesa->hw.lin.cmd[LIN_RE_LINE_PATTERN] = ((1 << 16) | 0xffff);
1069
1070 rmesa->hw.lin.cmd[LIN_RE_LINE_STATE] =
1071 ((0 << R200_LINE_CURRENT_PTR_SHIFT) |
1072 (1 << R200_LINE_CURRENT_COUNT_SHIFT));
1073
1074 rmesa->hw.lin.cmd[LIN_SE_LINE_WIDTH] = (1 << 4);
1075
1076 rmesa->hw.msk.cmd[MSK_RB3D_STENCILREFMASK] =
1077 ((0x00 << R200_STENCIL_REF_SHIFT) |
1078 (0xff << R200_STENCIL_MASK_SHIFT) |
1079 (0xff << R200_STENCIL_WRITEMASK_SHIFT));
1080
1081 rmesa->hw.msk.cmd[MSK_RB3D_ROPCNTL] = R200_ROP_COPY;
1082 rmesa->hw.msk.cmd[MSK_RB3D_PLANEMASK] = 0xffffffff;
1083
1084 rmesa->hw.tam.cmd[TAM_DEBUG3] = 0;
1085
1086 rmesa->hw.msc.cmd[MSC_RE_MISC] =
1087 ((0 << R200_STIPPLE_X_OFFSET_SHIFT) |
1088 (0 << R200_STIPPLE_Y_OFFSET_SHIFT) |
1089 R200_STIPPLE_BIG_BIT_ORDER);
1090
1091
1092 rmesa->hw.cst.cmd[CST_PP_CNTL_X] = 0;
1093 rmesa->hw.cst.cmd[CST_RB3D_DEPTHXY_OFFSET] = 0;
1094 rmesa->hw.cst.cmd[CST_RE_AUX_SCISSOR_CNTL] = 0x0;
1095 rmesa->hw.cst.cmd[CST_RE_SCISSOR_TL_0] = 0;
1096 rmesa->hw.cst.cmd[CST_RE_SCISSOR_BR_0] = 0;
1097 rmesa->hw.cst.cmd[CST_SE_VAP_CNTL_STATUS] =
1098 #ifdef MESA_BIG_ENDIAN
1099 R200_VC_32BIT_SWAP;
1100 #else
1101 R200_VC_NO_SWAP;
1102 #endif
1103
1104 if (!(rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL)) {
1105 /* Bypass TCL */
1106 rmesa->hw.cst.cmd[CST_SE_VAP_CNTL_STATUS] |= (1<<8);
1107 }
1108
1109 rmesa->hw.cst.cmd[CST_RE_POINTSIZE] =
1110 (((GLuint)(ctx->Const.MaxPointSize * 16.0)) << R200_MAXPOINTSIZE_SHIFT) | 0x10;
1111 rmesa->hw.cst.cmd[CST_SE_TCL_INPUT_VTX_0] =
1112 (0x0 << R200_VERTEX_POSITION_ADDR__SHIFT);
1113 rmesa->hw.cst.cmd[CST_SE_TCL_INPUT_VTX_1] =
1114 (0x02 << R200_VTX_COLOR_0_ADDR__SHIFT) |
1115 (0x03 << R200_VTX_COLOR_1_ADDR__SHIFT);
1116 rmesa->hw.cst.cmd[CST_SE_TCL_INPUT_VTX_2] =
1117 (0x06 << R200_VTX_TEX_0_ADDR__SHIFT) |
1118 (0x07 << R200_VTX_TEX_1_ADDR__SHIFT) |
1119 (0x08 << R200_VTX_TEX_2_ADDR__SHIFT) |
1120 (0x09 << R200_VTX_TEX_3_ADDR__SHIFT);
1121 rmesa->hw.cst.cmd[CST_SE_TCL_INPUT_VTX_3] =
1122 (0x0A << R200_VTX_TEX_4_ADDR__SHIFT) |
1123 (0x0B << R200_VTX_TEX_5_ADDR__SHIFT);
1124
1125
1126 rmesa->hw.vpt.cmd[VPT_SE_VPORT_XSCALE] = 0x00000000;
1127 rmesa->hw.vpt.cmd[VPT_SE_VPORT_XOFFSET] = 0x00000000;
1128 rmesa->hw.vpt.cmd[VPT_SE_VPORT_YSCALE] = 0x00000000;
1129 rmesa->hw.vpt.cmd[VPT_SE_VPORT_YOFFSET] = 0x00000000;
1130 rmesa->hw.vpt.cmd[VPT_SE_VPORT_ZSCALE] = 0x00000000;
1131 rmesa->hw.vpt.cmd[VPT_SE_VPORT_ZOFFSET] = 0x00000000;
1132
1133 for ( i = 0 ; i < ctx->Const.MaxTextureUnits ; i++ ) {
1134 rmesa->hw.tex[i].cmd[TEX_PP_TXFILTER] = R200_BORDER_MODE_OGL;
1135 rmesa->hw.tex[i].cmd[TEX_PP_TXFORMAT] =
1136 ((i << R200_TXFORMAT_ST_ROUTE_SHIFT) | /* <-- note i */
1137 (2 << R200_TXFORMAT_WIDTH_SHIFT) |
1138 (2 << R200_TXFORMAT_HEIGHT_SHIFT));
1139 rmesa->hw.tex[i].cmd[TEX_PP_BORDER_COLOR] = 0;
1140 rmesa->hw.tex[i].cmd[TEX_PP_TXFORMAT_X] =
1141 (/* R200_TEXCOORD_PROJ | */
1142 0x100000); /* Small default bias */
1143 if (rmesa->radeon.radeonScreen->drmSupportsFragShader) {
1144 rmesa->hw.tex[i].cmd[TEX_PP_TXOFFSET_NEWDRM] =
1145 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
1146 rmesa->hw.tex[i].cmd[TEX_PP_CUBIC_FACES] = 0;
1147 rmesa->hw.tex[i].cmd[TEX_PP_TXMULTI_CTL] = 0;
1148 }
1149 else {
1150 rmesa->hw.tex[i].cmd[TEX_PP_TXOFFSET_OLDDRM] =
1151 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
1152 }
1153
1154 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_FACES] = 0;
1155 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F1] =
1156 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
1157 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F2] =
1158 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
1159 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F3] =
1160 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
1161 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F4] =
1162 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
1163 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F5] =
1164 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
1165
1166 rmesa->hw.pix[i].cmd[PIX_PP_TXCBLEND] =
1167 (R200_TXC_ARG_A_ZERO |
1168 R200_TXC_ARG_B_ZERO |
1169 R200_TXC_ARG_C_DIFFUSE_COLOR |
1170 R200_TXC_OP_MADD);
1171
1172 rmesa->hw.pix[i].cmd[PIX_PP_TXCBLEND2] =
1173 ((i << R200_TXC_TFACTOR_SEL_SHIFT) |
1174 R200_TXC_SCALE_1X |
1175 R200_TXC_CLAMP_0_1 |
1176 R200_TXC_OUTPUT_REG_R0);
1177
1178 rmesa->hw.pix[i].cmd[PIX_PP_TXABLEND] =
1179 (R200_TXA_ARG_A_ZERO |
1180 R200_TXA_ARG_B_ZERO |
1181 R200_TXA_ARG_C_DIFFUSE_ALPHA |
1182 R200_TXA_OP_MADD);
1183
1184 rmesa->hw.pix[i].cmd[PIX_PP_TXABLEND2] =
1185 ((i << R200_TXA_TFACTOR_SEL_SHIFT) |
1186 R200_TXA_SCALE_1X |
1187 R200_TXA_CLAMP_0_1 |
1188 R200_TXA_OUTPUT_REG_R0);
1189 }
1190
1191 rmesa->hw.tf.cmd[TF_TFACTOR_0] = 0;
1192 rmesa->hw.tf.cmd[TF_TFACTOR_1] = 0;
1193 rmesa->hw.tf.cmd[TF_TFACTOR_2] = 0;
1194 rmesa->hw.tf.cmd[TF_TFACTOR_3] = 0;
1195 rmesa->hw.tf.cmd[TF_TFACTOR_4] = 0;
1196 rmesa->hw.tf.cmd[TF_TFACTOR_5] = 0;
1197
1198 rmesa->hw.vap.cmd[VAP_SE_VAP_CNTL] =
1199 (R200_VAP_TCL_ENABLE |
1200 (0x9 << R200_VAP_VF_MAX_VTX_NUM__SHIFT));
1201
1202 rmesa->hw.vte.cmd[VTE_SE_VTE_CNTL] =
1203 (R200_VPORT_X_SCALE_ENA |
1204 R200_VPORT_Y_SCALE_ENA |
1205 R200_VPORT_Z_SCALE_ENA |
1206 R200_VPORT_X_OFFSET_ENA |
1207 R200_VPORT_Y_OFFSET_ENA |
1208 R200_VPORT_Z_OFFSET_ENA |
1209 /* FIXME: Turn on for tex rect only */
1210 R200_VTX_ST_DENORMALIZED |
1211 R200_VTX_W0_FMT);
1212
1213
1214 rmesa->hw.vtx.cmd[VTX_VTXFMT_0] = 0;
1215 rmesa->hw.vtx.cmd[VTX_VTXFMT_1] = 0;
1216 rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_VTXFMT_0] =
1217 ((R200_VTX_Z0 | R200_VTX_W0 |
1218 (R200_VTX_FP_RGBA << R200_VTX_COLOR_0_SHIFT)));
1219 rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_VTXFMT_1] = 0;
1220 rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_COMPSEL] = (R200_OUTPUT_XYZW);
1221 rmesa->hw.vtx.cmd[VTX_STATE_CNTL] = R200_VSC_UPDATE_USER_COLOR_0_ENABLE;
1222
1223
1224 /* Matrix selection */
1225 rmesa->hw.msl.cmd[MSL_MATRIX_SELECT_0] =
1226 (R200_MTX_MV << R200_MODELVIEW_0_SHIFT);
1227
1228 rmesa->hw.msl.cmd[MSL_MATRIX_SELECT_1] =
1229 (R200_MTX_IMV << R200_IT_MODELVIEW_0_SHIFT);
1230
1231 rmesa->hw.msl.cmd[MSL_MATRIX_SELECT_2] =
1232 (R200_MTX_MVP << R200_MODELPROJECT_0_SHIFT);
1233
1234 rmesa->hw.msl.cmd[MSL_MATRIX_SELECT_3] =
1235 ((R200_MTX_TEX0 << R200_TEXMAT_0_SHIFT) |
1236 (R200_MTX_TEX1 << R200_TEXMAT_1_SHIFT) |
1237 (R200_MTX_TEX2 << R200_TEXMAT_2_SHIFT) |
1238 (R200_MTX_TEX3 << R200_TEXMAT_3_SHIFT));
1239
1240 rmesa->hw.msl.cmd[MSL_MATRIX_SELECT_4] =
1241 ((R200_MTX_TEX4 << R200_TEXMAT_4_SHIFT) |
1242 (R200_MTX_TEX5 << R200_TEXMAT_5_SHIFT));
1243
1244
1245 /* General TCL state */
1246 rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL_0] =
1247 (R200_SPECULAR_LIGHTS |
1248 R200_DIFFUSE_SPECULAR_COMBINE |
1249 R200_LOCAL_LIGHT_VEC_GL |
1250 R200_LM0_SOURCE_MATERIAL_0 << R200_FRONT_SHININESS_SOURCE_SHIFT |
1251 R200_LM0_SOURCE_MATERIAL_1 << R200_BACK_SHININESS_SOURCE_SHIFT);
1252
1253 rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL_1] =
1254 ((R200_LM1_SOURCE_MATERIAL_0 << R200_FRONT_EMISSIVE_SOURCE_SHIFT) |
1255 (R200_LM1_SOURCE_MATERIAL_0 << R200_FRONT_AMBIENT_SOURCE_SHIFT) |
1256 (R200_LM1_SOURCE_MATERIAL_0 << R200_FRONT_DIFFUSE_SOURCE_SHIFT) |
1257 (R200_LM1_SOURCE_MATERIAL_0 << R200_FRONT_SPECULAR_SOURCE_SHIFT) |
1258 (R200_LM1_SOURCE_MATERIAL_1 << R200_BACK_EMISSIVE_SOURCE_SHIFT) |
1259 (R200_LM1_SOURCE_MATERIAL_1 << R200_BACK_AMBIENT_SOURCE_SHIFT) |
1260 (R200_LM1_SOURCE_MATERIAL_1 << R200_BACK_DIFFUSE_SOURCE_SHIFT) |
1261 (R200_LM1_SOURCE_MATERIAL_1 << R200_BACK_SPECULAR_SOURCE_SHIFT));
1262
1263 rmesa->hw.tcl.cmd[TCL_PER_LIGHT_CTL_0] = 0; /* filled in via callbacks */
1264 rmesa->hw.tcl.cmd[TCL_PER_LIGHT_CTL_1] = 0;
1265 rmesa->hw.tcl.cmd[TCL_PER_LIGHT_CTL_2] = 0;
1266 rmesa->hw.tcl.cmd[TCL_PER_LIGHT_CTL_3] = 0;
1267
1268 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] =
1269 (R200_UCP_IN_CLIP_SPACE |
1270 R200_CULL_FRONT_IS_CCW);
1271
1272 /* Texgen/Texmat state */
1273 rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_2] = 0x00ffffff;
1274 rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_3] =
1275 ((0 << R200_TEXGEN_0_INPUT_TEX_SHIFT) |
1276 (1 << R200_TEXGEN_1_INPUT_TEX_SHIFT) |
1277 (2 << R200_TEXGEN_2_INPUT_TEX_SHIFT) |
1278 (3 << R200_TEXGEN_3_INPUT_TEX_SHIFT) |
1279 (4 << R200_TEXGEN_4_INPUT_TEX_SHIFT) |
1280 (5 << R200_TEXGEN_5_INPUT_TEX_SHIFT));
1281 rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_0] = 0;
1282 rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_1] =
1283 ((0 << R200_TEXGEN_0_INPUT_SHIFT) |
1284 (1 << R200_TEXGEN_1_INPUT_SHIFT) |
1285 (2 << R200_TEXGEN_2_INPUT_SHIFT) |
1286 (3 << R200_TEXGEN_3_INPUT_SHIFT) |
1287 (4 << R200_TEXGEN_4_INPUT_SHIFT) |
1288 (5 << R200_TEXGEN_5_INPUT_SHIFT));
1289 rmesa->hw.tcg.cmd[TCG_TEX_CYL_WRAP_CTL] = 0;
1290
1291
1292 for (i = 0 ; i < 8; i++) {
1293 struct gl_light *l = &ctx->Light.Light[i];
1294 GLenum p = GL_LIGHT0 + i;
1295 *(float *)&(rmesa->hw.lit[i].cmd[LIT_RANGE_CUTOFF]) = FLT_MAX;
1296
1297 ctx->Driver.Lightfv( ctx, p, GL_AMBIENT, l->Ambient );
1298 ctx->Driver.Lightfv( ctx, p, GL_DIFFUSE, l->Diffuse );
1299 ctx->Driver.Lightfv( ctx, p, GL_SPECULAR, l->Specular );
1300 ctx->Driver.Lightfv( ctx, p, GL_POSITION, NULL );
1301 ctx->Driver.Lightfv( ctx, p, GL_SPOT_DIRECTION, NULL );
1302 ctx->Driver.Lightfv( ctx, p, GL_SPOT_EXPONENT, &l->SpotExponent );
1303 ctx->Driver.Lightfv( ctx, p, GL_SPOT_CUTOFF, &l->SpotCutoff );
1304 ctx->Driver.Lightfv( ctx, p, GL_CONSTANT_ATTENUATION,
1305 &l->ConstantAttenuation );
1306 ctx->Driver.Lightfv( ctx, p, GL_LINEAR_ATTENUATION,
1307 &l->LinearAttenuation );
1308 ctx->Driver.Lightfv( ctx, p, GL_QUADRATIC_ATTENUATION,
1309 &l->QuadraticAttenuation );
1310 *(float *)&(rmesa->hw.lit[i].cmd[LIT_ATTEN_XXX]) = 0.0;
1311 }
1312
1313 ctx->Driver.LightModelfv( ctx, GL_LIGHT_MODEL_AMBIENT,
1314 ctx->Light.Model.Ambient );
1315
1316 TNL_CONTEXT(ctx)->Driver.NotifyMaterialChange( ctx );
1317
1318 for (i = 0 ; i < 6; i++) {
1319 ctx->Driver.ClipPlane( ctx, GL_CLIP_PLANE0 + i, NULL );
1320 }
1321
1322 ctx->Driver.Fogfv( ctx, GL_FOG_MODE, NULL );
1323 ctx->Driver.Fogfv( ctx, GL_FOG_DENSITY, &ctx->Fog.Density );
1324 ctx->Driver.Fogfv( ctx, GL_FOG_START, &ctx->Fog.Start );
1325 ctx->Driver.Fogfv( ctx, GL_FOG_END, &ctx->Fog.End );
1326 ctx->Driver.Fogfv( ctx, GL_FOG_COLOR, ctx->Fog.Color );
1327 ctx->Driver.Fogfv( ctx, GL_FOG_COORDINATE_SOURCE_EXT, NULL );
1328
1329 rmesa->hw.grd.cmd[GRD_VERT_GUARD_CLIP_ADJ] = IEEE_ONE;
1330 rmesa->hw.grd.cmd[GRD_VERT_GUARD_DISCARD_ADJ] = IEEE_ONE;
1331 rmesa->hw.grd.cmd[GRD_HORZ_GUARD_CLIP_ADJ] = IEEE_ONE;
1332 rmesa->hw.grd.cmd[GRD_HORZ_GUARD_DISCARD_ADJ] = IEEE_ONE;
1333
1334 rmesa->hw.eye.cmd[EYE_X] = 0;
1335 rmesa->hw.eye.cmd[EYE_Y] = 0;
1336 rmesa->hw.eye.cmd[EYE_Z] = IEEE_ONE;
1337 rmesa->hw.eye.cmd[EYE_RESCALE_FACTOR] = IEEE_ONE;
1338
1339 rmesa->hw.spr.cmd[SPR_POINT_SPRITE_CNTL] =
1340 R200_PS_SE_SEL_STATE | R200_PS_MULT_CONST;
1341
1342 /* ptp_eye is presumably used to calculate the attenuation wrt a different
1343 location? In any case, since point attenuation triggers _needeyecoords,
1344 it is constant. Probably ignored as long as R200_PS_USE_MODEL_EYE_VEC
1345 isn't set */
1346 rmesa->hw.ptp.cmd[PTP_EYE_X] = 0;
1347 rmesa->hw.ptp.cmd[PTP_EYE_Y] = 0;
1348 rmesa->hw.ptp.cmd[PTP_EYE_Z] = IEEE_ONE | 0x80000000; /* -1.0 */
1349 rmesa->hw.ptp.cmd[PTP_EYE_3] = 0;
1350 /* no idea what the ptp_vport_scale values are good for, except the
1351 PTSIZE one - hopefully doesn't matter */
1352 rmesa->hw.ptp.cmd[PTP_VPORT_SCALE_0] = IEEE_ONE;
1353 rmesa->hw.ptp.cmd[PTP_VPORT_SCALE_1] = IEEE_ONE;
1354 rmesa->hw.ptp.cmd[PTP_VPORT_SCALE_PTSIZE] = IEEE_ONE;
1355 rmesa->hw.ptp.cmd[PTP_VPORT_SCALE_3] = IEEE_ONE;
1356 rmesa->hw.ptp.cmd[PTP_ATT_CONST_QUAD] = 0;
1357 rmesa->hw.ptp.cmd[PTP_ATT_CONST_LIN] = 0;
1358 rmesa->hw.ptp.cmd[PTP_ATT_CONST_CON] = IEEE_ONE;
1359 rmesa->hw.ptp.cmd[PTP_ATT_CONST_3] = 0;
1360 rmesa->hw.ptp.cmd[PTP_CLAMP_MIN] = IEEE_ONE;
1361 rmesa->hw.ptp.cmd[PTP_CLAMP_MAX] = 0x44ffe000; /* 2047 */
1362 rmesa->hw.ptp.cmd[PTP_CLAMP_2] = 0;
1363 rmesa->hw.ptp.cmd[PTP_CLAMP_3] = 0;
1364
1365 r200LightingSpaceChange( ctx );
1366
1367 rmesa->radeon.hw.all_dirty = GL_TRUE;
1368
1369 rcommonInitCmdBuf(&rmesa->radeon);
1370 }