1 /* $XFree86: xc/lib/GL/mesa/src/drv/r200/r200_state_init.c,v 1.4 2003/02/22 06:21:11 dawes Exp $ */
3 Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
5 The Weather Channel (TM) funded Tungsten Graphics to develop the
6 initial release of the Radeon 8500 driver under the XFree86 license.
7 This notice must be preserved.
9 Permission is hereby granted, free of charge, to any person obtaining
10 a copy of this software and associated documentation files (the
11 "Software"), to deal in the Software without restriction, including
12 without limitation the rights to use, copy, modify, merge, publish,
13 distribute, sublicense, and/or sell copies of the Software, and to
14 permit persons to whom the Software is furnished to do so, subject to
15 the following conditions:
17 The above copyright notice and this permission notice (including the
18 next paragraph) shall be included in all copies or substantial
19 portions of the Software.
21 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
22 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
23 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
24 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
25 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
26 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
27 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
32 * Keith Whitwell <keith@tungstengraphics.com>
39 #include "api_arrayelt.h"
41 #include "swrast/swrast.h"
42 #include "array_cache/acache.h"
44 #include "tnl/t_pipeline.h"
45 #include "swrast_setup/swrast_setup.h"
47 #include "r200_context.h"
48 #include "r200_ioctl.h"
49 #include "r200_state.h"
52 #include "r200_swtcl.h"
53 #include "r200_vtxfmt.h"
57 /* =============================================================
58 * State initialization
61 void r200PrintDirty( r200ContextPtr rmesa
, const char *msg
)
63 struct r200_state_atom
*l
;
66 fprintf(stderr
, ": ");
68 foreach(l
, &rmesa
->hw
.atomlist
) {
69 if (l
->dirty
|| rmesa
->hw
.all_dirty
)
70 fprintf(stderr
, "%s, ", l
->name
);
73 fprintf(stderr
, "\n");
76 static int cmdpkt( int id
)
78 drm_radeon_cmd_header_t h
;
80 h
.packet
.cmd_type
= RADEON_CMD_PACKET
;
81 h
.packet
.packet_id
= id
;
85 static int cmdvec( int offset
, int stride
, int count
)
87 drm_radeon_cmd_header_t h
;
89 h
.vectors
.cmd_type
= RADEON_CMD_VECTORS
;
90 h
.vectors
.offset
= offset
;
91 h
.vectors
.stride
= stride
;
92 h
.vectors
.count
= count
;
96 static int cmdscl( int offset
, int stride
, int count
)
98 drm_radeon_cmd_header_t h
;
100 h
.scalars
.cmd_type
= RADEON_CMD_SCALARS
;
101 h
.scalars
.offset
= offset
;
102 h
.scalars
.stride
= stride
;
103 h
.scalars
.count
= count
;
107 static int cmdscl2( int offset
, int stride
, int count
)
109 drm_radeon_cmd_header_t h
;
111 h
.scalars
.cmd_type
= RADEON_CMD_SCALARS2
;
112 h
.scalars
.offset
= offset
- 0x100;
113 h
.scalars
.stride
= stride
;
114 h
.scalars
.count
= count
;
118 #define CHECK( NM, FLAG ) \
119 static GLboolean check_##NM( GLcontext *ctx, int idx ) \
121 r200ContextPtr rmesa = R200_CONTEXT(ctx); \
127 #define TCL_CHECK( NM, FLAG ) \
128 static GLboolean check_##NM( GLcontext *ctx, int idx ) \
130 r200ContextPtr rmesa = R200_CONTEXT(ctx); \
132 return !rmesa->TclFallback && (FLAG); \
137 CHECK( always
, GL_TRUE
)
138 CHECK( never
, GL_FALSE
)
139 CHECK( tex_any
, ctx
->Texture
._EnabledUnits
)
140 CHECK( tex_pair
, (rmesa
->state
.texture
.unit
[idx
].unitneeded
| rmesa
->state
.texture
.unit
[idx
& ~1].unitneeded
))
141 CHECK( tex
, rmesa
->state
.texture
.unit
[idx
].unitneeded
)
142 CHECK( texenv
, rmesa
->state
.envneeded
& (1 << idx
) )
143 CHECK( tex_cube
, rmesa
->state
.texture
.unit
[idx
].unitneeded
& TEXTURE_CUBE_BIT
)
144 CHECK( fog
, ctx
->Fog
.Enabled
)
145 TCL_CHECK( tcl
, GL_TRUE
)
146 TCL_CHECK( tcl_tex
, rmesa
->state
.texture
.unit
[idx
].unitneeded
)
147 TCL_CHECK( tcl_lighting
, ctx
->Light
.Enabled
)
148 TCL_CHECK( tcl_light
, ctx
->Light
.Enabled
&& ctx
->Light
.Light
[idx
].Enabled
)
149 TCL_CHECK( tcl_ucp
, (ctx
->Transform
.ClipPlanesEnabled
& (1 << idx
)) )
152 /* Initialize the context's hardware state.
154 void r200InitState( r200ContextPtr rmesa
)
156 GLcontext
*ctx
= rmesa
->glCtx
;
157 GLuint color_fmt
, depth_fmt
, i
;
158 GLint drawPitch
, drawOffset
;
160 switch ( rmesa
->r200Screen
->cpp
) {
162 color_fmt
= R200_COLOR_FORMAT_RGB565
;
165 color_fmt
= R200_COLOR_FORMAT_ARGB8888
;
168 fprintf( stderr
, "Error: Unsupported pixel depth... exiting\n" );
172 rmesa
->state
.color
.clear
= 0x00000000;
174 switch ( ctx
->Visual
.depthBits
) {
176 rmesa
->state
.depth
.clear
= 0x0000ffff;
177 rmesa
->state
.depth
.scale
= 1.0 / (GLfloat
)0xffff;
178 depth_fmt
= R200_DEPTH_FORMAT_16BIT_INT_Z
;
179 rmesa
->state
.stencil
.clear
= 0x00000000;
182 rmesa
->state
.depth
.clear
= 0x00ffffff;
183 rmesa
->state
.depth
.scale
= 1.0 / (GLfloat
)0xffffff;
184 depth_fmt
= R200_DEPTH_FORMAT_24BIT_INT_Z
;
185 rmesa
->state
.stencil
.clear
= 0xffff0000;
188 fprintf( stderr
, "Error: Unsupported depth %d... exiting\n",
189 ctx
->Visual
.depthBits
);
193 /* Only have hw stencil when depth buffer is 24 bits deep */
194 rmesa
->state
.stencil
.hwBuffer
= ( ctx
->Visual
.stencilBits
> 0 &&
195 ctx
->Visual
.depthBits
== 24 );
199 if ( ctx
->Visual
.doubleBufferMode
&& rmesa
->sarea
->pfCurrentPage
== 0 ) {
200 drawOffset
= rmesa
->r200Screen
->backOffset
;
201 drawPitch
= rmesa
->r200Screen
->backPitch
;
203 drawOffset
= rmesa
->r200Screen
->frontOffset
;
204 drawPitch
= rmesa
->r200Screen
->frontPitch
;
207 if ( ctx
->Visual
.doubleBufferMode
&& rmesa
->sarea
->pfCurrentPage
== 0 ) {
208 rmesa
->state
.color
.drawOffset
= rmesa
->r200Screen
->backOffset
;
209 rmesa
->state
.color
.drawPitch
= rmesa
->r200Screen
->backPitch
;
211 rmesa
->state
.color
.drawOffset
= rmesa
->r200Screen
->frontOffset
;
212 rmesa
->state
.color
.drawPitch
= rmesa
->r200Screen
->frontPitch
;
215 rmesa
->state
.pixel
.readOffset
= rmesa
->state
.color
.drawOffset
;
216 rmesa
->state
.pixel
.readPitch
= rmesa
->state
.color
.drawPitch
;
219 rmesa
->hw
.max_state_size
= 0;
221 #define ALLOC_STATE( ATOM, CHK, SZ, NM, IDX ) \
223 rmesa->hw.ATOM.cmd_size = SZ; \
224 rmesa->hw.ATOM.cmd = (int *)CALLOC(SZ * sizeof(int)); \
225 rmesa->hw.ATOM.lastcmd = (int *)CALLOC(SZ * sizeof(int)); \
226 rmesa->hw.ATOM.name = NM; \
227 rmesa->hw.ATOM.idx = IDX; \
228 rmesa->hw.ATOM.check = check_##CHK; \
229 rmesa->hw.ATOM.dirty = GL_FALSE; \
230 rmesa->hw.max_state_size += SZ * sizeof(int); \
234 /* Allocate state buffers:
236 if (rmesa
->r200Screen
->drmSupportsBlendColor
)
237 ALLOC_STATE( ctx
, always
, CTX_STATE_SIZE_NEWDRM
, "CTX/context", 0 );
239 ALLOC_STATE( ctx
, always
, CTX_STATE_SIZE_OLDDRM
, "CTX/context", 0 );
240 ALLOC_STATE( set
, always
, SET_STATE_SIZE
, "SET/setup", 0 );
241 ALLOC_STATE( lin
, always
, LIN_STATE_SIZE
, "LIN/line", 0 );
242 ALLOC_STATE( msk
, always
, MSK_STATE_SIZE
, "MSK/mask", 0 );
243 ALLOC_STATE( vpt
, always
, VPT_STATE_SIZE
, "VPT/viewport", 0 );
244 ALLOC_STATE( vtx
, always
, VTX_STATE_SIZE
, "VTX/vertex", 0 );
245 ALLOC_STATE( vap
, always
, VAP_STATE_SIZE
, "VAP/vap", 0 );
246 ALLOC_STATE( vte
, always
, VTE_STATE_SIZE
, "VTE/vte", 0 );
247 ALLOC_STATE( msc
, always
, MSC_STATE_SIZE
, "MSC/misc", 0 );
248 ALLOC_STATE( cst
, always
, CST_STATE_SIZE
, "CST/constant", 0 );
249 ALLOC_STATE( zbs
, always
, ZBS_STATE_SIZE
, "ZBS/zbias", 0 );
250 ALLOC_STATE( tf
, tex_any
, TF_STATE_SIZE
, "TF/tfactor", 0 );
251 if (rmesa
->r200Screen
->chipset
& R200_CHIPSET_REAL_R200
) {
252 /* make sure texture units 0/1 are emitted pair-wise for r200 t0 hang workaround */
253 ALLOC_STATE( tex
[0], tex_pair
, TEX_STATE_SIZE
, "TEX/tex-0", 0 );
254 ALLOC_STATE( tex
[1], tex_pair
, TEX_STATE_SIZE
, "TEX/tex-1", 1 );
255 ALLOC_STATE( tam
, tex_any
, TAM_STATE_SIZE
, "TAM/tam", 0 );
258 ALLOC_STATE( tex
[0], tex
, TEX_STATE_SIZE
, "TEX/tex-0", 0 );
259 ALLOC_STATE( tex
[1], tex
, TEX_STATE_SIZE
, "TEX/tex-1", 1 );
260 ALLOC_STATE( tam
, never
, TAM_STATE_SIZE
, "TAM/tam", 0 );
262 ALLOC_STATE( tex
[2], tex
, TEX_STATE_SIZE
, "TEX/tex-2", 2 );
263 ALLOC_STATE( tex
[3], tex
, TEX_STATE_SIZE
, "TEX/tex-3", 3 );
264 ALLOC_STATE( tex
[4], tex
, TEX_STATE_SIZE
, "TEX/tex-4", 4 );
265 ALLOC_STATE( tex
[5], tex
, TEX_STATE_SIZE
, "TEX/tex-5", 5 );
266 if (rmesa
->r200Screen
->drmSupportsCubeMaps
) {
267 ALLOC_STATE( cube
[0], tex_cube
, CUBE_STATE_SIZE
, "CUBE/tex-0", 0 );
268 ALLOC_STATE( cube
[1], tex_cube
, CUBE_STATE_SIZE
, "CUBE/tex-1", 1 );
269 ALLOC_STATE( cube
[2], tex_cube
, CUBE_STATE_SIZE
, "CUBE/tex-2", 2 );
270 ALLOC_STATE( cube
[3], tex_cube
, CUBE_STATE_SIZE
, "CUBE/tex-3", 3 );
271 ALLOC_STATE( cube
[4], tex_cube
, CUBE_STATE_SIZE
, "CUBE/tex-4", 4 );
272 ALLOC_STATE( cube
[5], tex_cube
, CUBE_STATE_SIZE
, "CUBE/tex-5", 5 );
275 ALLOC_STATE( cube
[0], never
, CUBE_STATE_SIZE
, "CUBE/tex-0", 0 );
276 ALLOC_STATE( cube
[1], never
, CUBE_STATE_SIZE
, "CUBE/tex-1", 1 );
277 ALLOC_STATE( cube
[2], never
, CUBE_STATE_SIZE
, "CUBE/tex-2", 2 );
278 ALLOC_STATE( cube
[3], never
, CUBE_STATE_SIZE
, "CUBE/tex-3", 3 );
279 ALLOC_STATE( cube
[4], never
, CUBE_STATE_SIZE
, "CUBE/tex-4", 4 );
280 ALLOC_STATE( cube
[5], never
, CUBE_STATE_SIZE
, "CUBE/tex-5", 5 );
283 ALLOC_STATE( tcl
, tcl
, TCL_STATE_SIZE
, "TCL/tcl", 0 );
284 ALLOC_STATE( msl
, tcl
, MSL_STATE_SIZE
, "MSL/matrix-select", 0 );
285 ALLOC_STATE( tcg
, tcl
, TCG_STATE_SIZE
, "TCG/texcoordgen", 0 );
286 ALLOC_STATE( mtl
[0], tcl_lighting
, MTL_STATE_SIZE
, "MTL0/material0", 0 );
287 ALLOC_STATE( mtl
[1], tcl_lighting
, MTL_STATE_SIZE
, "MTL1/material1", 1 );
288 ALLOC_STATE( grd
, tcl
, GRD_STATE_SIZE
, "GRD/guard-band", 0 );
289 ALLOC_STATE( fog
, fog
, FOG_STATE_SIZE
, "FOG/fog", 0 );
290 ALLOC_STATE( glt
, tcl_lighting
, GLT_STATE_SIZE
, "GLT/light-global", 0 );
291 ALLOC_STATE( eye
, tcl_lighting
, EYE_STATE_SIZE
, "EYE/eye-vector", 0 );
292 ALLOC_STATE( mat
[R200_MTX_MV
], tcl
, MAT_STATE_SIZE
, "MAT/modelview", 0 );
293 ALLOC_STATE( mat
[R200_MTX_IMV
], tcl
, MAT_STATE_SIZE
, "MAT/it-modelview", 0 );
294 ALLOC_STATE( mat
[R200_MTX_MVP
], tcl
, MAT_STATE_SIZE
, "MAT/modelproject", 0 );
295 ALLOC_STATE( mat
[R200_MTX_TEX0
], tcl_tex
, MAT_STATE_SIZE
, "MAT/texmat0", 0 );
296 ALLOC_STATE( mat
[R200_MTX_TEX1
], tcl_tex
, MAT_STATE_SIZE
, "MAT/texmat1", 1 );
297 ALLOC_STATE( mat
[R200_MTX_TEX2
], tcl_tex
, MAT_STATE_SIZE
, "MAT/texmat2", 2 );
298 ALLOC_STATE( mat
[R200_MTX_TEX3
], tcl_tex
, MAT_STATE_SIZE
, "MAT/texmat3", 3 );
299 ALLOC_STATE( mat
[R200_MTX_TEX4
], tcl_tex
, MAT_STATE_SIZE
, "MAT/texmat4", 4 );
300 ALLOC_STATE( mat
[R200_MTX_TEX5
], tcl_tex
, MAT_STATE_SIZE
, "MAT/texmat5", 5 );
301 ALLOC_STATE( ucp
[0], tcl_ucp
, UCP_STATE_SIZE
, "UCP/userclip-0", 0 );
302 ALLOC_STATE( ucp
[1], tcl_ucp
, UCP_STATE_SIZE
, "UCP/userclip-1", 1 );
303 ALLOC_STATE( ucp
[2], tcl_ucp
, UCP_STATE_SIZE
, "UCP/userclip-2", 2 );
304 ALLOC_STATE( ucp
[3], tcl_ucp
, UCP_STATE_SIZE
, "UCP/userclip-3", 3 );
305 ALLOC_STATE( ucp
[4], tcl_ucp
, UCP_STATE_SIZE
, "UCP/userclip-4", 4 );
306 ALLOC_STATE( ucp
[5], tcl_ucp
, UCP_STATE_SIZE
, "UCP/userclip-5", 5 );
307 ALLOC_STATE( lit
[0], tcl_light
, LIT_STATE_SIZE
, "LIT/light-0", 0 );
308 ALLOC_STATE( lit
[1], tcl_light
, LIT_STATE_SIZE
, "LIT/light-1", 1 );
309 ALLOC_STATE( lit
[2], tcl_light
, LIT_STATE_SIZE
, "LIT/light-2", 2 );
310 ALLOC_STATE( lit
[3], tcl_light
, LIT_STATE_SIZE
, "LIT/light-3", 3 );
311 ALLOC_STATE( lit
[4], tcl_light
, LIT_STATE_SIZE
, "LIT/light-4", 4 );
312 ALLOC_STATE( lit
[5], tcl_light
, LIT_STATE_SIZE
, "LIT/light-5", 5 );
313 ALLOC_STATE( lit
[6], tcl_light
, LIT_STATE_SIZE
, "LIT/light-6", 6 );
314 ALLOC_STATE( lit
[7], tcl_light
, LIT_STATE_SIZE
, "LIT/light-7", 7 );
315 ALLOC_STATE( pix
[0], always
, PIX_STATE_SIZE
, "PIX/pixstage-0", 0 );
316 ALLOC_STATE( pix
[1], texenv
, PIX_STATE_SIZE
, "PIX/pixstage-1", 1 );
317 ALLOC_STATE( pix
[2], texenv
, PIX_STATE_SIZE
, "PIX/pixstage-2", 2 );
318 ALLOC_STATE( pix
[3], texenv
, PIX_STATE_SIZE
, "PIX/pixstage-3", 3 );
319 ALLOC_STATE( pix
[4], texenv
, PIX_STATE_SIZE
, "PIX/pixstage-4", 4 );
320 ALLOC_STATE( pix
[5], texenv
, PIX_STATE_SIZE
, "PIX/pixstage-5", 5 );
321 if (rmesa
->r200Screen
->drmSupportsTriPerf
) {
322 ALLOC_STATE( prf
, always
, PRF_STATE_SIZE
, "PRF/performance-tri", 0 );
325 ALLOC_STATE( prf
, never
, PRF_STATE_SIZE
, "PRF/performance-tri", 0 );
328 r200SetUpAtomList( rmesa
);
330 /* Fill in the packet headers:
332 rmesa
->hw
.ctx
.cmd
[CTX_CMD_0
] = cmdpkt(RADEON_EMIT_PP_MISC
);
333 rmesa
->hw
.ctx
.cmd
[CTX_CMD_1
] = cmdpkt(RADEON_EMIT_PP_CNTL
);
334 rmesa
->hw
.ctx
.cmd
[CTX_CMD_2
] = cmdpkt(RADEON_EMIT_RB3D_COLORPITCH
);
335 if (rmesa
->r200Screen
->drmSupportsBlendColor
)
336 rmesa
->hw
.ctx
.cmd
[CTX_CMD_3
] = cmdpkt(R200_EMIT_RB3D_BLENDCOLOR
);
337 rmesa
->hw
.lin
.cmd
[LIN_CMD_0
] = cmdpkt(RADEON_EMIT_RE_LINE_PATTERN
);
338 rmesa
->hw
.lin
.cmd
[LIN_CMD_1
] = cmdpkt(RADEON_EMIT_SE_LINE_WIDTH
);
339 rmesa
->hw
.msk
.cmd
[MSK_CMD_0
] = cmdpkt(RADEON_EMIT_RB3D_STENCILREFMASK
);
340 rmesa
->hw
.vpt
.cmd
[VPT_CMD_0
] = cmdpkt(RADEON_EMIT_SE_VPORT_XSCALE
);
341 rmesa
->hw
.set
.cmd
[SET_CMD_0
] = cmdpkt(RADEON_EMIT_SE_CNTL
);
342 rmesa
->hw
.msc
.cmd
[MSC_CMD_0
] = cmdpkt(RADEON_EMIT_RE_MISC
);
343 rmesa
->hw
.cst
.cmd
[CST_CMD_0
] = cmdpkt(R200_EMIT_PP_CNTL_X
);
344 rmesa
->hw
.cst
.cmd
[CST_CMD_1
] = cmdpkt(R200_EMIT_RB3D_DEPTHXY_OFFSET
);
345 rmesa
->hw
.cst
.cmd
[CST_CMD_2
] = cmdpkt(R200_EMIT_RE_AUX_SCISSOR_CNTL
);
346 rmesa
->hw
.cst
.cmd
[CST_CMD_3
] = cmdpkt(R200_EMIT_RE_SCISSOR_TL_0
);
347 rmesa
->hw
.cst
.cmd
[CST_CMD_4
] = cmdpkt(R200_EMIT_SE_VAP_CNTL_STATUS
);
348 rmesa
->hw
.cst
.cmd
[CST_CMD_5
] = cmdpkt(R200_EMIT_RE_POINTSIZE
);
349 rmesa
->hw
.cst
.cmd
[CST_CMD_6
] = cmdpkt(R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0
);
350 rmesa
->hw
.tam
.cmd
[TAM_CMD_0
] = cmdpkt(R200_EMIT_PP_TAM_DEBUG3
);
351 rmesa
->hw
.tf
.cmd
[TF_CMD_0
] = cmdpkt(R200_EMIT_TFACTOR_0
);
352 rmesa
->hw
.tex
[0].cmd
[TEX_CMD_0
] = cmdpkt(R200_EMIT_PP_TXFILTER_0
);
353 rmesa
->hw
.tex
[0].cmd
[TEX_CMD_1
] = cmdpkt(R200_EMIT_PP_TXOFFSET_0
);
354 rmesa
->hw
.tex
[1].cmd
[TEX_CMD_0
] = cmdpkt(R200_EMIT_PP_TXFILTER_1
);
355 rmesa
->hw
.tex
[1].cmd
[TEX_CMD_1
] = cmdpkt(R200_EMIT_PP_TXOFFSET_1
);
356 rmesa
->hw
.tex
[2].cmd
[TEX_CMD_0
] = cmdpkt(R200_EMIT_PP_TXFILTER_2
);
357 rmesa
->hw
.tex
[2].cmd
[TEX_CMD_1
] = cmdpkt(R200_EMIT_PP_TXOFFSET_2
);
358 rmesa
->hw
.tex
[3].cmd
[TEX_CMD_0
] = cmdpkt(R200_EMIT_PP_TXFILTER_3
);
359 rmesa
->hw
.tex
[3].cmd
[TEX_CMD_1
] = cmdpkt(R200_EMIT_PP_TXOFFSET_3
);
360 rmesa
->hw
.tex
[4].cmd
[TEX_CMD_0
] = cmdpkt(R200_EMIT_PP_TXFILTER_4
);
361 rmesa
->hw
.tex
[4].cmd
[TEX_CMD_1
] = cmdpkt(R200_EMIT_PP_TXOFFSET_4
);
362 rmesa
->hw
.tex
[5].cmd
[TEX_CMD_0
] = cmdpkt(R200_EMIT_PP_TXFILTER_5
);
363 rmesa
->hw
.tex
[5].cmd
[TEX_CMD_1
] = cmdpkt(R200_EMIT_PP_TXOFFSET_5
);
364 rmesa
->hw
.cube
[0].cmd
[CUBE_CMD_0
] = cmdpkt(R200_EMIT_PP_CUBIC_FACES_0
);
365 rmesa
->hw
.cube
[0].cmd
[CUBE_CMD_1
] = cmdpkt(R200_EMIT_PP_CUBIC_OFFSETS_0
);
366 rmesa
->hw
.cube
[1].cmd
[CUBE_CMD_0
] = cmdpkt(R200_EMIT_PP_CUBIC_FACES_1
);
367 rmesa
->hw
.cube
[1].cmd
[CUBE_CMD_1
] = cmdpkt(R200_EMIT_PP_CUBIC_OFFSETS_1
);
368 rmesa
->hw
.cube
[2].cmd
[CUBE_CMD_0
] = cmdpkt(R200_EMIT_PP_CUBIC_FACES_2
);
369 rmesa
->hw
.cube
[2].cmd
[CUBE_CMD_1
] = cmdpkt(R200_EMIT_PP_CUBIC_OFFSETS_2
);
370 rmesa
->hw
.cube
[3].cmd
[CUBE_CMD_0
] = cmdpkt(R200_EMIT_PP_CUBIC_FACES_3
);
371 rmesa
->hw
.cube
[3].cmd
[CUBE_CMD_1
] = cmdpkt(R200_EMIT_PP_CUBIC_OFFSETS_3
);
372 rmesa
->hw
.cube
[4].cmd
[CUBE_CMD_0
] = cmdpkt(R200_EMIT_PP_CUBIC_FACES_4
);
373 rmesa
->hw
.cube
[4].cmd
[CUBE_CMD_1
] = cmdpkt(R200_EMIT_PP_CUBIC_OFFSETS_4
);
374 rmesa
->hw
.cube
[5].cmd
[CUBE_CMD_0
] = cmdpkt(R200_EMIT_PP_CUBIC_FACES_5
);
375 rmesa
->hw
.cube
[5].cmd
[CUBE_CMD_1
] = cmdpkt(R200_EMIT_PP_CUBIC_OFFSETS_5
);
376 rmesa
->hw
.pix
[0].cmd
[PIX_CMD_0
] = cmdpkt(R200_EMIT_PP_TXCBLEND_0
);
377 rmesa
->hw
.pix
[1].cmd
[PIX_CMD_0
] = cmdpkt(R200_EMIT_PP_TXCBLEND_1
);
378 rmesa
->hw
.pix
[2].cmd
[PIX_CMD_0
] = cmdpkt(R200_EMIT_PP_TXCBLEND_2
);
379 rmesa
->hw
.pix
[3].cmd
[PIX_CMD_0
] = cmdpkt(R200_EMIT_PP_TXCBLEND_3
);
380 rmesa
->hw
.pix
[4].cmd
[PIX_CMD_0
] = cmdpkt(R200_EMIT_PP_TXCBLEND_4
);
381 rmesa
->hw
.pix
[5].cmd
[PIX_CMD_0
] = cmdpkt(R200_EMIT_PP_TXCBLEND_5
);
382 rmesa
->hw
.zbs
.cmd
[ZBS_CMD_0
] = cmdpkt(RADEON_EMIT_SE_ZBIAS_FACTOR
);
383 rmesa
->hw
.tcl
.cmd
[TCL_CMD_0
] = cmdpkt(R200_EMIT_TCL_LIGHT_MODEL_CTL_0
);
384 rmesa
->hw
.tcl
.cmd
[TCL_CMD_1
] = cmdpkt(R200_EMIT_TCL_UCP_VERT_BLEND_CTL
);
385 rmesa
->hw
.tcg
.cmd
[TCG_CMD_0
] = cmdpkt(R200_EMIT_TEX_PROC_CTL_2
);
386 rmesa
->hw
.msl
.cmd
[MSL_CMD_0
] = cmdpkt(R200_EMIT_MATRIX_SELECT_0
);
387 rmesa
->hw
.vap
.cmd
[VAP_CMD_0
] = cmdpkt(R200_EMIT_VAP_CTL
);
388 rmesa
->hw
.vtx
.cmd
[VTX_CMD_0
] = cmdpkt(R200_EMIT_VTX_FMT_0
);
389 rmesa
->hw
.vtx
.cmd
[VTX_CMD_1
] = cmdpkt(R200_EMIT_OUTPUT_VTX_COMP_SEL
);
390 rmesa
->hw
.vtx
.cmd
[VTX_CMD_2
] = cmdpkt(R200_EMIT_SE_VTX_STATE_CNTL
);
391 rmesa
->hw
.vte
.cmd
[VTE_CMD_0
] = cmdpkt(R200_EMIT_VTE_CNTL
);
392 rmesa
->hw
.prf
.cmd
[PRF_CMD_0
] = cmdpkt(R200_EMIT_PP_TRI_PERF_CNTL
);
393 rmesa
->hw
.mtl
[0].cmd
[MTL_CMD_0
] =
394 cmdvec( R200_VS_MAT_0_EMISS
, 1, 16 );
395 rmesa
->hw
.mtl
[0].cmd
[MTL_CMD_1
] =
396 cmdscl2( R200_SS_MAT_0_SHININESS
, 1, 1 );
397 rmesa
->hw
.mtl
[1].cmd
[MTL_CMD_0
] =
398 cmdvec( R200_VS_MAT_1_EMISS
, 1, 16 );
399 rmesa
->hw
.mtl
[1].cmd
[MTL_CMD_1
] =
400 cmdscl2( R200_SS_MAT_1_SHININESS
, 1, 1 );
402 rmesa
->hw
.grd
.cmd
[GRD_CMD_0
] =
403 cmdscl( R200_SS_VERT_GUARD_CLIP_ADJ_ADDR
, 1, 4 );
404 rmesa
->hw
.fog
.cmd
[FOG_CMD_0
] =
405 cmdvec( R200_VS_FOG_PARAM_ADDR
, 1, 4 );
406 rmesa
->hw
.glt
.cmd
[GLT_CMD_0
] =
407 cmdvec( R200_VS_GLOBAL_AMBIENT_ADDR
, 1, 4 );
408 rmesa
->hw
.eye
.cmd
[EYE_CMD_0
] =
409 cmdvec( R200_VS_EYE_VECTOR_ADDR
, 1, 4 );
411 rmesa
->hw
.mat
[R200_MTX_MV
].cmd
[MAT_CMD_0
] =
412 cmdvec( R200_VS_MATRIX_0_MV
, 1, 16);
413 rmesa
->hw
.mat
[R200_MTX_IMV
].cmd
[MAT_CMD_0
] =
414 cmdvec( R200_VS_MATRIX_1_INV_MV
, 1, 16);
415 rmesa
->hw
.mat
[R200_MTX_MVP
].cmd
[MAT_CMD_0
] =
416 cmdvec( R200_VS_MATRIX_2_MVP
, 1, 16);
417 rmesa
->hw
.mat
[R200_MTX_TEX0
].cmd
[MAT_CMD_0
] =
418 cmdvec( R200_VS_MATRIX_3_TEX0
, 1, 16);
419 rmesa
->hw
.mat
[R200_MTX_TEX1
].cmd
[MAT_CMD_0
] =
420 cmdvec( R200_VS_MATRIX_4_TEX1
, 1, 16);
421 rmesa
->hw
.mat
[R200_MTX_TEX2
].cmd
[MAT_CMD_0
] =
422 cmdvec( R200_VS_MATRIX_5_TEX2
, 1, 16);
423 rmesa
->hw
.mat
[R200_MTX_TEX3
].cmd
[MAT_CMD_0
] =
424 cmdvec( R200_VS_MATRIX_6_TEX3
, 1, 16);
425 rmesa
->hw
.mat
[R200_MTX_TEX4
].cmd
[MAT_CMD_0
] =
426 cmdvec( R200_VS_MATRIX_7_TEX4
, 1, 16);
427 rmesa
->hw
.mat
[R200_MTX_TEX5
].cmd
[MAT_CMD_0
] =
428 cmdvec( R200_VS_MATRIX_8_TEX5
, 1, 16);
430 for (i
= 0 ; i
< 8; i
++) {
431 rmesa
->hw
.lit
[i
].cmd
[LIT_CMD_0
] =
432 cmdvec( R200_VS_LIGHT_AMBIENT_ADDR
+ i
, 8, 24 );
433 rmesa
->hw
.lit
[i
].cmd
[LIT_CMD_1
] =
434 cmdscl( R200_SS_LIGHT_DCD_ADDR
+ i
, 8, 7 );
437 for (i
= 0 ; i
< 6; i
++) {
438 rmesa
->hw
.ucp
[i
].cmd
[UCP_CMD_0
] =
439 cmdvec( R200_VS_UCP_ADDR
+ i
, 1, 4 );
442 /* Initial Harware state:
444 rmesa
->hw
.ctx
.cmd
[CTX_PP_MISC
] = (R200_ALPHA_TEST_PASS
445 /* | R200_RIGHT_HAND_CUBE_OGL*/);
447 rmesa
->hw
.ctx
.cmd
[CTX_PP_FOG_COLOR
] = (R200_FOG_VERTEX
|
448 R200_FOG_USE_SPEC_ALPHA
);
450 rmesa
->hw
.ctx
.cmd
[CTX_RE_SOLID_COLOR
] = 0x00000000;
452 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_BLENDCNTL
] = (R200_COMB_FCN_ADD_CLAMP
|
453 (R200_BLEND_GL_ONE
<< R200_SRC_BLEND_SHIFT
) |
454 (R200_BLEND_GL_ZERO
<< R200_DST_BLEND_SHIFT
));
456 if (rmesa
->r200Screen
->drmSupportsBlendColor
) {
457 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_BLENDCOLOR
] = 0x00000000;
458 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ABLENDCNTL
] = (R200_COMB_FCN_ADD_CLAMP
|
459 (R200_BLEND_GL_ONE
<< R200_SRC_BLEND_SHIFT
) |
460 (R200_BLEND_GL_ZERO
<< R200_DST_BLEND_SHIFT
));
461 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_CBLENDCNTL
] = (R200_COMB_FCN_ADD_CLAMP
|
462 (R200_BLEND_GL_ONE
<< R200_SRC_BLEND_SHIFT
) |
463 (R200_BLEND_GL_ZERO
<< R200_DST_BLEND_SHIFT
));
466 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_DEPTHOFFSET
] =
467 rmesa
->r200Screen
->depthOffset
+ rmesa
->r200Screen
->fbLocation
;
469 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_DEPTHPITCH
] =
470 ((rmesa
->r200Screen
->depthPitch
&
471 R200_DEPTHPITCH_MASK
) |
472 R200_DEPTH_ENDIAN_NO_SWAP
);
474 if (rmesa
->using_hyperz
)
475 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_DEPTHPITCH
] |= R200_DEPTH_HYPERZ
;
477 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] = (depth_fmt
|
479 R200_STENCIL_TEST_ALWAYS
|
480 R200_STENCIL_FAIL_KEEP
|
481 R200_STENCIL_ZPASS_KEEP
|
482 R200_STENCIL_ZFAIL_KEEP
|
483 R200_Z_WRITE_ENABLE
);
485 if (rmesa
->using_hyperz
) {
486 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= R200_Z_COMPRESSION_ENABLE
|
487 R200_Z_DECOMPRESSION_ENABLE
;
488 /* if (rmesa->r200Screen->chipset & R200_CHIPSET_REAL_R200)
489 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_HIERARCHY_ENABLE;*/
492 rmesa
->hw
.ctx
.cmd
[CTX_PP_CNTL
] = (R200_ANTI_ALIAS_NONE
493 | R200_TEX_BLEND_0_ENABLE
);
495 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_CNTL
] = color_fmt
;
496 switch ( driQueryOptioni( &rmesa
->optionCache
, "dither_mode" ) ) {
497 case DRI_CONF_DITHER_XERRORDIFFRESET
:
498 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_CNTL
] |= R200_DITHER_INIT
;
500 case DRI_CONF_DITHER_ORDERED
:
501 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_CNTL
] |= R200_SCALE_DITHER_ENABLE
;
504 if ( driQueryOptioni( &rmesa
->optionCache
, "round_mode" ) ==
505 DRI_CONF_ROUND_ROUND
)
506 rmesa
->state
.color
.roundEnable
= R200_ROUND_ENABLE
;
508 rmesa
->state
.color
.roundEnable
= 0;
509 if ( driQueryOptioni (&rmesa
->optionCache
, "color_reduction" ) ==
510 DRI_CONF_COLOR_REDUCTION_DITHER
)
511 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_CNTL
] |= R200_DITHER_ENABLE
;
513 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_CNTL
] |= rmesa
->state
.color
.roundEnable
;
516 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_COLOROFFSET
] = ((rmesa
->state
.color
.drawOffset
+
517 rmesa
->r200Screen
->fbLocation
)
518 & R200_COLOROFFSET_MASK
);
520 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_COLORPITCH
] = ((rmesa
->state
.color
.drawPitch
&
521 R200_COLORPITCH_MASK
) |
522 R200_COLOR_ENDIAN_NO_SWAP
);
524 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_COLOROFFSET
] = ((drawOffset
+
525 rmesa
->r200Screen
->fbLocation
)
526 & R200_COLOROFFSET_MASK
);
528 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_COLORPITCH
] = ((drawPitch
&
529 R200_COLORPITCH_MASK
) |
530 R200_COLOR_ENDIAN_NO_SWAP
);
532 /* (fixed size) sarea is initialized to zero afaics so can omit version check. Phew! */
533 if (rmesa
->sarea
->tiling_enabled
) {
534 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_COLORPITCH
] |= R200_COLOR_TILE_ENABLE
;
537 rmesa
->hw
.prf
.cmd
[PRF_PP_TRI_PERF
] = R200_TRI_CUTOFF_MASK
- R200_TRI_CUTOFF_MASK
*
538 driQueryOptionf (&rmesa
->optionCache
,"texture_blend_quality");
539 rmesa
->hw
.prf
.cmd
[PRF_PP_PERF_CNTL
] = 0;
541 rmesa
->hw
.set
.cmd
[SET_SE_CNTL
] = (R200_FFACE_CULL_CCW
|
544 R200_FLAT_SHADE_VTX_LAST
|
545 R200_DIFFUSE_SHADE_GOURAUD
|
546 R200_ALPHA_SHADE_GOURAUD
|
547 R200_SPECULAR_SHADE_GOURAUD
|
548 R200_FOG_SHADE_GOURAUD
|
549 R200_VTX_PIX_CENTER_OGL
|
550 R200_ROUND_MODE_TRUNC
|
551 R200_ROUND_PREC_8TH_PIX
);
553 rmesa
->hw
.set
.cmd
[SET_RE_CNTL
] = (R200_PERSPECTIVE_ENABLE
|
554 R200_SCISSOR_ENABLE
);
556 rmesa
->hw
.lin
.cmd
[LIN_RE_LINE_PATTERN
] = ((1 << 16) | 0xffff);
558 rmesa
->hw
.lin
.cmd
[LIN_RE_LINE_STATE
] =
559 ((0 << R200_LINE_CURRENT_PTR_SHIFT
) |
560 (1 << R200_LINE_CURRENT_COUNT_SHIFT
));
562 rmesa
->hw
.lin
.cmd
[LIN_SE_LINE_WIDTH
] = (1 << 4);
564 rmesa
->hw
.msk
.cmd
[MSK_RB3D_STENCILREFMASK
] =
565 ((0x00 << R200_STENCIL_REF_SHIFT
) |
566 (0xff << R200_STENCIL_MASK_SHIFT
) |
567 (0xff << R200_STENCIL_WRITEMASK_SHIFT
));
569 rmesa
->hw
.msk
.cmd
[MSK_RB3D_ROPCNTL
] = R200_ROP_COPY
;
570 rmesa
->hw
.msk
.cmd
[MSK_RB3D_PLANEMASK
] = 0xffffffff;
572 rmesa
->hw
.tam
.cmd
[TAM_DEBUG3
] = 0;
574 rmesa
->hw
.msc
.cmd
[MSC_RE_MISC
] =
575 ((0 << R200_STIPPLE_X_OFFSET_SHIFT
) |
576 (0 << R200_STIPPLE_Y_OFFSET_SHIFT
) |
577 R200_STIPPLE_BIG_BIT_ORDER
);
580 rmesa
->hw
.cst
.cmd
[CST_PP_CNTL_X
] = 0;
581 rmesa
->hw
.cst
.cmd
[CST_RB3D_DEPTHXY_OFFSET
] = 0;
582 rmesa
->hw
.cst
.cmd
[CST_RE_AUX_SCISSOR_CNTL
] = 0x0;
583 rmesa
->hw
.cst
.cmd
[CST_RE_SCISSOR_TL_0
] = 0;
584 rmesa
->hw
.cst
.cmd
[CST_RE_SCISSOR_BR_0
] = 0;
585 rmesa
->hw
.cst
.cmd
[CST_SE_VAP_CNTL_STATUS
] =
586 #ifdef MESA_BIG_ENDIAN
592 if (!(rmesa
->r200Screen
->chipset
& R200_CHIPSET_TCL
)) {
594 rmesa
->hw
.cst
.cmd
[CST_SE_VAP_CNTL_STATUS
] |= (1<<8);
597 rmesa
->hw
.cst
.cmd
[CST_RE_POINTSIZE
] = 0x100010;
598 rmesa
->hw
.cst
.cmd
[CST_SE_TCL_INPUT_VTX_0
] =
599 (0x0 << R200_VERTEX_POSITION_ADDR__SHIFT
);
600 rmesa
->hw
.cst
.cmd
[CST_SE_TCL_INPUT_VTX_1
] =
601 (0x02 << R200_VTX_COLOR_0_ADDR__SHIFT
) |
602 (0x03 << R200_VTX_COLOR_1_ADDR__SHIFT
);
603 rmesa
->hw
.cst
.cmd
[CST_SE_TCL_INPUT_VTX_2
] =
604 (0x06 << R200_VTX_TEX_0_ADDR__SHIFT
) |
605 (0x07 << R200_VTX_TEX_1_ADDR__SHIFT
) |
606 (0x08 << R200_VTX_TEX_2_ADDR__SHIFT
) |
607 (0x09 << R200_VTX_TEX_3_ADDR__SHIFT
);
608 rmesa
->hw
.cst
.cmd
[CST_SE_TCL_INPUT_VTX_3
] =
609 (0x0A << R200_VTX_TEX_4_ADDR__SHIFT
) |
610 (0x0B << R200_VTX_TEX_5_ADDR__SHIFT
);
613 rmesa
->hw
.vpt
.cmd
[VPT_SE_VPORT_XSCALE
] = 0x00000000;
614 rmesa
->hw
.vpt
.cmd
[VPT_SE_VPORT_XOFFSET
] = 0x00000000;
615 rmesa
->hw
.vpt
.cmd
[VPT_SE_VPORT_YSCALE
] = 0x00000000;
616 rmesa
->hw
.vpt
.cmd
[VPT_SE_VPORT_YOFFSET
] = 0x00000000;
617 rmesa
->hw
.vpt
.cmd
[VPT_SE_VPORT_ZSCALE
] = 0x00000000;
618 rmesa
->hw
.vpt
.cmd
[VPT_SE_VPORT_ZOFFSET
] = 0x00000000;
620 for ( i
= 0 ; i
< ctx
->Const
.MaxTextureUnits
; i
++ ) {
621 rmesa
->hw
.tex
[i
].cmd
[TEX_PP_TXFILTER
] = R200_BORDER_MODE_OGL
;
622 rmesa
->hw
.tex
[i
].cmd
[TEX_PP_TXFORMAT
] =
623 ((i
<< R200_TXFORMAT_ST_ROUTE_SHIFT
) | /* <-- note i */
624 (2 << R200_TXFORMAT_WIDTH_SHIFT
) |
625 (2 << R200_TXFORMAT_HEIGHT_SHIFT
));
626 rmesa
->hw
.tex
[i
].cmd
[TEX_PP_TXOFFSET
] =
627 rmesa
->r200Screen
->texOffset
[RADEON_LOCAL_TEX_HEAP
];
628 rmesa
->hw
.tex
[i
].cmd
[TEX_PP_BORDER_COLOR
] = 0;
629 rmesa
->hw
.tex
[i
].cmd
[TEX_PP_TXFORMAT_X
] =
630 (/* R200_TEXCOORD_PROJ | */
631 0x100000); /* Small default bias */
633 rmesa
->hw
.cube
[i
].cmd
[CUBE_PP_CUBIC_FACES
] = 0;
634 rmesa
->hw
.cube
[i
].cmd
[CUBE_PP_CUBIC_OFFSET_F1
] =
635 rmesa
->r200Screen
->texOffset
[RADEON_LOCAL_TEX_HEAP
];
636 rmesa
->hw
.cube
[i
].cmd
[CUBE_PP_CUBIC_OFFSET_F2
] =
637 rmesa
->r200Screen
->texOffset
[RADEON_LOCAL_TEX_HEAP
];
638 rmesa
->hw
.cube
[i
].cmd
[CUBE_PP_CUBIC_OFFSET_F3
] =
639 rmesa
->r200Screen
->texOffset
[RADEON_LOCAL_TEX_HEAP
];
640 rmesa
->hw
.cube
[i
].cmd
[CUBE_PP_CUBIC_OFFSET_F4
] =
641 rmesa
->r200Screen
->texOffset
[RADEON_LOCAL_TEX_HEAP
];
642 rmesa
->hw
.cube
[i
].cmd
[CUBE_PP_CUBIC_OFFSET_F5
] =
643 rmesa
->r200Screen
->texOffset
[RADEON_LOCAL_TEX_HEAP
];
645 rmesa
->hw
.pix
[i
].cmd
[PIX_PP_TXCBLEND
] =
646 (R200_TXC_ARG_A_ZERO
|
647 R200_TXC_ARG_B_ZERO
|
648 R200_TXC_ARG_C_DIFFUSE_COLOR
|
651 rmesa
->hw
.pix
[i
].cmd
[PIX_PP_TXCBLEND2
] =
652 ((i
<< R200_TXC_TFACTOR_SEL_SHIFT
) |
655 R200_TXC_OUTPUT_REG_R0
);
657 rmesa
->hw
.pix
[i
].cmd
[PIX_PP_TXABLEND
] =
658 (R200_TXA_ARG_A_ZERO
|
659 R200_TXA_ARG_B_ZERO
|
660 R200_TXA_ARG_C_DIFFUSE_ALPHA
|
663 rmesa
->hw
.pix
[i
].cmd
[PIX_PP_TXABLEND2
] =
664 ((i
<< R200_TXA_TFACTOR_SEL_SHIFT
) |
667 R200_TXA_OUTPUT_REG_R0
);
670 rmesa
->hw
.tf
.cmd
[TF_TFACTOR_0
] = 0;
671 rmesa
->hw
.tf
.cmd
[TF_TFACTOR_1
] = 0;
672 rmesa
->hw
.tf
.cmd
[TF_TFACTOR_2
] = 0;
673 rmesa
->hw
.tf
.cmd
[TF_TFACTOR_3
] = 0;
674 rmesa
->hw
.tf
.cmd
[TF_TFACTOR_4
] = 0;
675 rmesa
->hw
.tf
.cmd
[TF_TFACTOR_5
] = 0;
677 rmesa
->hw
.vap
.cmd
[VAP_SE_VAP_CNTL
] =
678 (R200_VAP_TCL_ENABLE
|
679 (0x9 << R200_VAP_VF_MAX_VTX_NUM__SHIFT
));
681 rmesa
->hw
.vte
.cmd
[VTE_SE_VTE_CNTL
] =
682 (R200_VPORT_X_SCALE_ENA
|
683 R200_VPORT_Y_SCALE_ENA
|
684 R200_VPORT_Z_SCALE_ENA
|
685 R200_VPORT_X_OFFSET_ENA
|
686 R200_VPORT_Y_OFFSET_ENA
|
687 R200_VPORT_Z_OFFSET_ENA
|
688 /* FIXME: Turn on for tex rect only */
689 R200_VTX_ST_DENORMALIZED
|
693 rmesa
->hw
.vtx
.cmd
[VTX_VTXFMT_0
] = 0;
694 rmesa
->hw
.vtx
.cmd
[VTX_VTXFMT_1
] = 0;
695 rmesa
->hw
.vtx
.cmd
[VTX_TCL_OUTPUT_VTXFMT_0
] =
696 ((R200_VTX_Z0
| R200_VTX_W0
|
697 (R200_VTX_FP_RGBA
<< R200_VTX_COLOR_0_SHIFT
)));
698 rmesa
->hw
.vtx
.cmd
[VTX_TCL_OUTPUT_VTXFMT_1
] = 0;
699 rmesa
->hw
.vtx
.cmd
[VTX_TCL_OUTPUT_COMPSEL
] = (R200_OUTPUT_XYZW
);
700 rmesa
->hw
.vtx
.cmd
[VTX_STATE_CNTL
] = R200_VSC_UPDATE_USER_COLOR_0_ENABLE
;
703 /* Matrix selection */
704 rmesa
->hw
.msl
.cmd
[MSL_MATRIX_SELECT_0
] =
705 (R200_MTX_MV
<< R200_MODELVIEW_0_SHIFT
);
707 rmesa
->hw
.msl
.cmd
[MSL_MATRIX_SELECT_1
] =
708 (R200_MTX_IMV
<< R200_IT_MODELVIEW_0_SHIFT
);
710 rmesa
->hw
.msl
.cmd
[MSL_MATRIX_SELECT_2
] =
711 (R200_MTX_MVP
<< R200_MODELPROJECT_0_SHIFT
);
713 rmesa
->hw
.msl
.cmd
[MSL_MATRIX_SELECT_3
] =
714 ((R200_MTX_TEX0
<< R200_TEXMAT_0_SHIFT
) |
715 (R200_MTX_TEX1
<< R200_TEXMAT_1_SHIFT
) |
716 (R200_MTX_TEX2
<< R200_TEXMAT_2_SHIFT
) |
717 (R200_MTX_TEX3
<< R200_TEXMAT_3_SHIFT
));
719 rmesa
->hw
.msl
.cmd
[MSL_MATRIX_SELECT_4
] =
720 ((R200_MTX_TEX4
<< R200_TEXMAT_4_SHIFT
) |
721 (R200_MTX_TEX5
<< R200_TEXMAT_5_SHIFT
));
724 /* General TCL state */
725 rmesa
->hw
.tcl
.cmd
[TCL_LIGHT_MODEL_CTL_0
] =
726 (R200_SPECULAR_LIGHTS
|
727 R200_DIFFUSE_SPECULAR_COMBINE
|
728 R200_LOCAL_LIGHT_VEC_GL
|
729 R200_LM0_SOURCE_MATERIAL_0
<< R200_FRONT_SHININESS_SOURCE_SHIFT
|
730 R200_LM0_SOURCE_MATERIAL_1
<< R200_BACK_SHININESS_SOURCE_SHIFT
);
732 rmesa
->hw
.tcl
.cmd
[TCL_LIGHT_MODEL_CTL_1
] =
733 ((R200_LM1_SOURCE_MATERIAL_0
<< R200_FRONT_EMISSIVE_SOURCE_SHIFT
) |
734 (R200_LM1_SOURCE_MATERIAL_0
<< R200_FRONT_AMBIENT_SOURCE_SHIFT
) |
735 (R200_LM1_SOURCE_MATERIAL_0
<< R200_FRONT_DIFFUSE_SOURCE_SHIFT
) |
736 (R200_LM1_SOURCE_MATERIAL_0
<< R200_FRONT_SPECULAR_SOURCE_SHIFT
) |
737 (R200_LM1_SOURCE_MATERIAL_1
<< R200_BACK_EMISSIVE_SOURCE_SHIFT
) |
738 (R200_LM1_SOURCE_MATERIAL_1
<< R200_BACK_AMBIENT_SOURCE_SHIFT
) |
739 (R200_LM1_SOURCE_MATERIAL_1
<< R200_BACK_DIFFUSE_SOURCE_SHIFT
) |
740 (R200_LM1_SOURCE_MATERIAL_1
<< R200_BACK_SPECULAR_SOURCE_SHIFT
));
742 rmesa
->hw
.tcl
.cmd
[TCL_PER_LIGHT_CTL_0
] = 0; /* filled in via callbacks */
743 rmesa
->hw
.tcl
.cmd
[TCL_PER_LIGHT_CTL_1
] = 0;
744 rmesa
->hw
.tcl
.cmd
[TCL_PER_LIGHT_CTL_2
] = 0;
745 rmesa
->hw
.tcl
.cmd
[TCL_PER_LIGHT_CTL_3
] = 0;
747 rmesa
->hw
.tcl
.cmd
[TCL_UCP_VERT_BLEND_CTL
] =
748 (R200_UCP_IN_CLIP_SPACE
|
749 R200_CULL_FRONT_IS_CCW
);
751 /* Texgen/Texmat state */
752 rmesa
->hw
.tcg
.cmd
[TCG_TEX_PROC_CTL_2
] = 0x00ffffff;
753 rmesa
->hw
.tcg
.cmd
[TCG_TEX_PROC_CTL_3
] =
754 ((0 << R200_TEXGEN_0_INPUT_TEX_SHIFT
) |
755 (1 << R200_TEXGEN_1_INPUT_TEX_SHIFT
) |
756 (2 << R200_TEXGEN_2_INPUT_TEX_SHIFT
) |
757 (3 << R200_TEXGEN_3_INPUT_TEX_SHIFT
) |
758 (4 << R200_TEXGEN_4_INPUT_TEX_SHIFT
) |
759 (5 << R200_TEXGEN_5_INPUT_TEX_SHIFT
));
760 rmesa
->hw
.tcg
.cmd
[TCG_TEX_PROC_CTL_0
] = 0;
761 rmesa
->hw
.tcg
.cmd
[TCG_TEX_PROC_CTL_1
] =
762 ((0 << R200_TEXGEN_0_INPUT_SHIFT
) |
763 (1 << R200_TEXGEN_1_INPUT_SHIFT
) |
764 (2 << R200_TEXGEN_2_INPUT_SHIFT
) |
765 (3 << R200_TEXGEN_3_INPUT_SHIFT
) |
766 (4 << R200_TEXGEN_4_INPUT_SHIFT
) |
767 (5 << R200_TEXGEN_5_INPUT_SHIFT
));
768 rmesa
->hw
.tcg
.cmd
[TCG_TEX_CYL_WRAP_CTL
] = 0;
771 for (i
= 0 ; i
< 8; i
++) {
772 struct gl_light
*l
= &ctx
->Light
.Light
[i
];
773 GLenum p
= GL_LIGHT0
+ i
;
774 *(float *)&(rmesa
->hw
.lit
[i
].cmd
[LIT_RANGE_CUTOFF
]) = FLT_MAX
;
776 ctx
->Driver
.Lightfv( ctx
, p
, GL_AMBIENT
, l
->Ambient
);
777 ctx
->Driver
.Lightfv( ctx
, p
, GL_DIFFUSE
, l
->Diffuse
);
778 ctx
->Driver
.Lightfv( ctx
, p
, GL_SPECULAR
, l
->Specular
);
779 ctx
->Driver
.Lightfv( ctx
, p
, GL_POSITION
, NULL
);
780 ctx
->Driver
.Lightfv( ctx
, p
, GL_SPOT_DIRECTION
, NULL
);
781 ctx
->Driver
.Lightfv( ctx
, p
, GL_SPOT_EXPONENT
, &l
->SpotExponent
);
782 ctx
->Driver
.Lightfv( ctx
, p
, GL_SPOT_CUTOFF
, &l
->SpotCutoff
);
783 ctx
->Driver
.Lightfv( ctx
, p
, GL_CONSTANT_ATTENUATION
,
784 &l
->ConstantAttenuation
);
785 ctx
->Driver
.Lightfv( ctx
, p
, GL_LINEAR_ATTENUATION
,
786 &l
->LinearAttenuation
);
787 ctx
->Driver
.Lightfv( ctx
, p
, GL_QUADRATIC_ATTENUATION
,
788 &l
->QuadraticAttenuation
);
789 *(float *)&(rmesa
->hw
.lit
[i
].cmd
[LIT_ATTEN_XXX
]) = 0.0;
792 ctx
->Driver
.LightModelfv( ctx
, GL_LIGHT_MODEL_AMBIENT
,
793 ctx
->Light
.Model
.Ambient
);
795 TNL_CONTEXT(ctx
)->Driver
.NotifyMaterialChange( ctx
);
797 for (i
= 0 ; i
< 6; i
++) {
798 ctx
->Driver
.ClipPlane( ctx
, GL_CLIP_PLANE0
+ i
, NULL
);
801 ctx
->Driver
.Fogfv( ctx
, GL_FOG_MODE
, NULL
);
802 ctx
->Driver
.Fogfv( ctx
, GL_FOG_DENSITY
, &ctx
->Fog
.Density
);
803 ctx
->Driver
.Fogfv( ctx
, GL_FOG_START
, &ctx
->Fog
.Start
);
804 ctx
->Driver
.Fogfv( ctx
, GL_FOG_END
, &ctx
->Fog
.End
);
805 ctx
->Driver
.Fogfv( ctx
, GL_FOG_COLOR
, ctx
->Fog
.Color
);
806 ctx
->Driver
.Fogfv( ctx
, GL_FOG_COORDINATE_SOURCE_EXT
, NULL
);
808 rmesa
->hw
.grd
.cmd
[GRD_VERT_GUARD_CLIP_ADJ
] = IEEE_ONE
;
809 rmesa
->hw
.grd
.cmd
[GRD_VERT_GUARD_DISCARD_ADJ
] = IEEE_ONE
;
810 rmesa
->hw
.grd
.cmd
[GRD_HORZ_GUARD_CLIP_ADJ
] = IEEE_ONE
;
811 rmesa
->hw
.grd
.cmd
[GRD_HORZ_GUARD_DISCARD_ADJ
] = IEEE_ONE
;
813 rmesa
->hw
.eye
.cmd
[EYE_X
] = 0;
814 rmesa
->hw
.eye
.cmd
[EYE_Y
] = 0;
815 rmesa
->hw
.eye
.cmd
[EYE_Z
] = IEEE_ONE
;
816 rmesa
->hw
.eye
.cmd
[EYE_RESCALE_FACTOR
] = IEEE_ONE
;
818 r200LightingSpaceChange( ctx
);
820 rmesa
->hw
.all_dirty
= GL_TRUE
;