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[mesa.git] / src / mesa / drivers / dri / r300 / compiler / r3xx_vertprog.c
1 /*
2 * Copyright 2009 Nicolai Hähnle <nhaehnle@gmail.com>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE. */
22
23 #include "radeon_compiler.h"
24
25 #include <stdio.h>
26
27 #include "../r300_reg.h"
28
29 #include "radeon_compiler_util.h"
30 #include "radeon_dataflow.h"
31 #include "radeon_program_alu.h"
32 #include "radeon_swizzle.h"
33 #include "radeon_emulate_branches.h"
34 #include "radeon_emulate_loops.h"
35 #include "radeon_remove_constants.h"
36
37 struct loop {
38 int BgnLoop;
39
40 };
41
42 /*
43 * Take an already-setup and valid source then swizzle it appropriately to
44 * obtain a constant ZERO or ONE source.
45 */
46 #define __CONST(x, y) \
47 (PVS_SRC_OPERAND(t_src_index(vp, &vpi->SrcReg[x]), \
48 t_swizzle(y), \
49 t_swizzle(y), \
50 t_swizzle(y), \
51 t_swizzle(y), \
52 t_src_class(vpi->SrcReg[x].File), \
53 RC_MASK_NONE) | (vpi->SrcReg[x].RelAddr << 4))
54
55
56 static unsigned long t_dst_mask(unsigned int mask)
57 {
58 /* RC_MASK_* is equivalent to VSF_FLAG_* */
59 return mask & RC_MASK_XYZW;
60 }
61
62 static unsigned long t_dst_class(rc_register_file file)
63 {
64 switch (file) {
65 default:
66 fprintf(stderr, "%s: Bad register file %i\n", __FUNCTION__, file);
67 /* fall-through */
68 case RC_FILE_TEMPORARY:
69 return PVS_DST_REG_TEMPORARY;
70 case RC_FILE_OUTPUT:
71 return PVS_DST_REG_OUT;
72 case RC_FILE_ADDRESS:
73 return PVS_DST_REG_A0;
74 }
75 }
76
77 static unsigned long t_dst_index(struct r300_vertex_program_code *vp,
78 struct rc_dst_register *dst)
79 {
80 if (dst->File == RC_FILE_OUTPUT)
81 return vp->outputs[dst->Index];
82
83 return dst->Index;
84 }
85
86 static unsigned long t_src_class(rc_register_file file)
87 {
88 switch (file) {
89 default:
90 fprintf(stderr, "%s: Bad register file %i\n", __FUNCTION__, file);
91 /* fall-through */
92 case RC_FILE_NONE:
93 case RC_FILE_TEMPORARY:
94 return PVS_SRC_REG_TEMPORARY;
95 case RC_FILE_INPUT:
96 return PVS_SRC_REG_INPUT;
97 case RC_FILE_CONSTANT:
98 return PVS_SRC_REG_CONSTANT;
99 }
100 }
101
102 static int t_src_conflict(struct rc_src_register a, struct rc_src_register b)
103 {
104 unsigned long aclass = t_src_class(a.File);
105 unsigned long bclass = t_src_class(b.File);
106
107 if (aclass != bclass)
108 return 0;
109 if (aclass == PVS_SRC_REG_TEMPORARY)
110 return 0;
111
112 if (a.RelAddr || b.RelAddr)
113 return 1;
114 if (a.Index != b.Index)
115 return 1;
116
117 return 0;
118 }
119
120 static inline unsigned long t_swizzle(unsigned int swizzle)
121 {
122 /* this is in fact a NOP as the Mesa RC_SWIZZLE_* are all identical to VSF_IN_COMPONENT_* */
123 return swizzle;
124 }
125
126 static unsigned long t_src_index(struct r300_vertex_program_code *vp,
127 struct rc_src_register *src)
128 {
129 if (src->File == RC_FILE_INPUT) {
130 assert(vp->inputs[src->Index] != -1);
131 return vp->inputs[src->Index];
132 } else {
133 if (src->Index < 0) {
134 fprintf(stderr,
135 "negative offsets for indirect addressing do not work.\n");
136 return 0;
137 }
138 return src->Index;
139 }
140 }
141
142 /* these two functions should probably be merged... */
143
144 static unsigned long t_src(struct r300_vertex_program_code *vp,
145 struct rc_src_register *src)
146 {
147 /* src->Negate uses the RC_MASK_ flags from program_instruction.h,
148 * which equal our VSF_FLAGS_ values, so it's safe to just pass it here.
149 */
150 return PVS_SRC_OPERAND(t_src_index(vp, src),
151 t_swizzle(GET_SWZ(src->Swizzle, 0)),
152 t_swizzle(GET_SWZ(src->Swizzle, 1)),
153 t_swizzle(GET_SWZ(src->Swizzle, 2)),
154 t_swizzle(GET_SWZ(src->Swizzle, 3)),
155 t_src_class(src->File),
156 src->Negate) |
157 (src->RelAddr << 4) | (src->Abs << 3);
158 }
159
160 static unsigned long t_src_scalar(struct r300_vertex_program_code *vp,
161 struct rc_src_register *src)
162 {
163 /* src->Negate uses the RC_MASK_ flags from program_instruction.h,
164 * which equal our VSF_FLAGS_ values, so it's safe to just pass it here.
165 */
166 return PVS_SRC_OPERAND(t_src_index(vp, src),
167 t_swizzle(GET_SWZ(src->Swizzle, 0)),
168 t_swizzle(GET_SWZ(src->Swizzle, 0)),
169 t_swizzle(GET_SWZ(src->Swizzle, 0)),
170 t_swizzle(GET_SWZ(src->Swizzle, 0)),
171 t_src_class(src->File),
172 src->Negate ? RC_MASK_XYZW : RC_MASK_NONE) |
173 (src->RelAddr << 4) | (src->Abs << 3);
174 }
175
176 static int valid_dst(struct r300_vertex_program_code *vp,
177 struct rc_dst_register *dst)
178 {
179 if (dst->File == RC_FILE_OUTPUT && vp->outputs[dst->Index] == -1) {
180 return 0;
181 } else if (dst->File == RC_FILE_ADDRESS) {
182 assert(dst->Index == 0);
183 }
184
185 return 1;
186 }
187
188 static void ei_vector1(struct r300_vertex_program_code *vp,
189 unsigned int hw_opcode,
190 struct rc_sub_instruction *vpi,
191 unsigned int * inst)
192 {
193 inst[0] = PVS_OP_DST_OPERAND(hw_opcode,
194 0,
195 0,
196 t_dst_index(vp, &vpi->DstReg),
197 t_dst_mask(vpi->DstReg.WriteMask),
198 t_dst_class(vpi->DstReg.File));
199 inst[1] = t_src(vp, &vpi->SrcReg[0]);
200 inst[2] = __CONST(0, RC_SWIZZLE_ZERO);
201 inst[3] = __CONST(0, RC_SWIZZLE_ZERO);
202 }
203
204 static void ei_vector2(struct r300_vertex_program_code *vp,
205 unsigned int hw_opcode,
206 struct rc_sub_instruction *vpi,
207 unsigned int * inst)
208 {
209 inst[0] = PVS_OP_DST_OPERAND(hw_opcode,
210 0,
211 0,
212 t_dst_index(vp, &vpi->DstReg),
213 t_dst_mask(vpi->DstReg.WriteMask),
214 t_dst_class(vpi->DstReg.File));
215 inst[1] = t_src(vp, &vpi->SrcReg[0]);
216 inst[2] = t_src(vp, &vpi->SrcReg[1]);
217 inst[3] = __CONST(1, RC_SWIZZLE_ZERO);
218 }
219
220 static void ei_math1(struct r300_vertex_program_code *vp,
221 unsigned int hw_opcode,
222 struct rc_sub_instruction *vpi,
223 unsigned int * inst)
224 {
225 inst[0] = PVS_OP_DST_OPERAND(hw_opcode,
226 1,
227 0,
228 t_dst_index(vp, &vpi->DstReg),
229 t_dst_mask(vpi->DstReg.WriteMask),
230 t_dst_class(vpi->DstReg.File));
231 inst[1] = t_src_scalar(vp, &vpi->SrcReg[0]);
232 inst[2] = __CONST(0, RC_SWIZZLE_ZERO);
233 inst[3] = __CONST(0, RC_SWIZZLE_ZERO);
234 }
235
236 static void ei_lit(struct r300_vertex_program_code *vp,
237 struct rc_sub_instruction *vpi,
238 unsigned int * inst)
239 {
240 //LIT TMP 1.Y Z TMP 1{} {X W Z Y} TMP 1{} {Y W Z X} TMP 1{} {Y X Z W}
241
242 inst[0] = PVS_OP_DST_OPERAND(ME_LIGHT_COEFF_DX,
243 1,
244 0,
245 t_dst_index(vp, &vpi->DstReg),
246 t_dst_mask(vpi->DstReg.WriteMask),
247 t_dst_class(vpi->DstReg.File));
248 /* NOTE: Users swizzling might not work. */
249 inst[1] = PVS_SRC_OPERAND(t_src_index(vp, &vpi->SrcReg[0]), t_swizzle(GET_SWZ(vpi->SrcReg[0].Swizzle, 0)), // X
250 t_swizzle(GET_SWZ(vpi->SrcReg[0].Swizzle, 3)), // W
251 PVS_SRC_SELECT_FORCE_0, // Z
252 t_swizzle(GET_SWZ(vpi->SrcReg[0].Swizzle, 1)), // Y
253 t_src_class(vpi->SrcReg[0].File),
254 vpi->SrcReg[0].Negate ? RC_MASK_XYZW : RC_MASK_NONE) |
255 (vpi->SrcReg[0].RelAddr << 4);
256 inst[2] = PVS_SRC_OPERAND(t_src_index(vp, &vpi->SrcReg[0]), t_swizzle(GET_SWZ(vpi->SrcReg[0].Swizzle, 1)), // Y
257 t_swizzle(GET_SWZ(vpi->SrcReg[0].Swizzle, 3)), // W
258 PVS_SRC_SELECT_FORCE_0, // Z
259 t_swizzle(GET_SWZ(vpi->SrcReg[0].Swizzle, 0)), // X
260 t_src_class(vpi->SrcReg[0].File),
261 vpi->SrcReg[0].Negate ? RC_MASK_XYZW : RC_MASK_NONE) |
262 (vpi->SrcReg[0].RelAddr << 4);
263 inst[3] = PVS_SRC_OPERAND(t_src_index(vp, &vpi->SrcReg[0]), t_swizzle(GET_SWZ(vpi->SrcReg[0].Swizzle, 1)), // Y
264 t_swizzle(GET_SWZ(vpi->SrcReg[0].Swizzle, 0)), // X
265 PVS_SRC_SELECT_FORCE_0, // Z
266 t_swizzle(GET_SWZ(vpi->SrcReg[0].Swizzle, 3)), // W
267 t_src_class(vpi->SrcReg[0].File),
268 vpi->SrcReg[0].Negate ? RC_MASK_XYZW : RC_MASK_NONE) |
269 (vpi->SrcReg[0].RelAddr << 4);
270 }
271
272 static void ei_mad(struct r300_vertex_program_code *vp,
273 struct rc_sub_instruction *vpi,
274 unsigned int * inst)
275 {
276 /* Remarks about hardware limitations of MAD
277 * (please preserve this comment, as this information is _NOT_
278 * in the documentation provided by AMD).
279 *
280 * As described in the documentation, MAD with three unique temporary
281 * source registers requires the use of the macro version.
282 *
283 * However (and this is not mentioned in the documentation), apparently
284 * the macro version is _NOT_ a full superset of the normal version.
285 * In particular, the macro version does not always work when relative
286 * addressing is used in the source operands.
287 *
288 * This limitation caused incorrect rendering in Sauerbraten's OpenGL
289 * assembly shader path when using medium quality animations
290 * (i.e. animations with matrix blending instead of quaternion blending).
291 *
292 * Unfortunately, I (nha) have been unable to extract a Piglit regression
293 * test for this issue - for some reason, it is possible to have vertex
294 * programs whose prefix is *exactly* the same as the prefix of the
295 * offending program in Sauerbraten up to the offending instruction
296 * without causing any trouble.
297 *
298 * Bottom line: Only use the macro version only when really necessary;
299 * according to AMD docs, this should improve performance by one clock
300 * as a nice side bonus.
301 */
302 if (vpi->SrcReg[0].File == RC_FILE_TEMPORARY &&
303 vpi->SrcReg[1].File == RC_FILE_TEMPORARY &&
304 vpi->SrcReg[2].File == RC_FILE_TEMPORARY &&
305 vpi->SrcReg[0].Index != vpi->SrcReg[1].Index &&
306 vpi->SrcReg[0].Index != vpi->SrcReg[2].Index &&
307 vpi->SrcReg[1].Index != vpi->SrcReg[2].Index) {
308 inst[0] = PVS_OP_DST_OPERAND(PVS_MACRO_OP_2CLK_MADD,
309 0,
310 1,
311 t_dst_index(vp, &vpi->DstReg),
312 t_dst_mask(vpi->DstReg.WriteMask),
313 t_dst_class(vpi->DstReg.File));
314 } else {
315 inst[0] = PVS_OP_DST_OPERAND(VE_MULTIPLY_ADD,
316 0,
317 0,
318 t_dst_index(vp, &vpi->DstReg),
319 t_dst_mask(vpi->DstReg.WriteMask),
320 t_dst_class(vpi->DstReg.File));
321 }
322 inst[1] = t_src(vp, &vpi->SrcReg[0]);
323 inst[2] = t_src(vp, &vpi->SrcReg[1]);
324 inst[3] = t_src(vp, &vpi->SrcReg[2]);
325 }
326
327 static void ei_pow(struct r300_vertex_program_code *vp,
328 struct rc_sub_instruction *vpi,
329 unsigned int * inst)
330 {
331 inst[0] = PVS_OP_DST_OPERAND(ME_POWER_FUNC_FF,
332 1,
333 0,
334 t_dst_index(vp, &vpi->DstReg),
335 t_dst_mask(vpi->DstReg.WriteMask),
336 t_dst_class(vpi->DstReg.File));
337 inst[1] = t_src_scalar(vp, &vpi->SrcReg[0]);
338 inst[2] = __CONST(0, RC_SWIZZLE_ZERO);
339 inst[3] = t_src_scalar(vp, &vpi->SrcReg[1]);
340 }
341
342 static void mark_write(void * userdata, struct rc_instruction * inst,
343 rc_register_file file, unsigned int index, unsigned int mask)
344 {
345 unsigned int * writemasks = userdata;
346
347 if (file != RC_FILE_TEMPORARY)
348 return;
349
350 if (index >= R300_VS_MAX_TEMPS)
351 return;
352
353 writemasks[index] |= mask;
354 }
355
356 static unsigned long t_pred_src(struct r300_vertex_program_compiler * compiler)
357 {
358 return PVS_SRC_OPERAND(compiler->PredicateIndex,
359 t_swizzle(RC_SWIZZLE_ZERO),
360 t_swizzle(RC_SWIZZLE_ZERO),
361 t_swizzle(RC_SWIZZLE_ZERO),
362 t_swizzle(RC_SWIZZLE_W),
363 t_src_class(RC_FILE_TEMPORARY),
364 0);
365 }
366
367 static unsigned long t_pred_dst(struct r300_vertex_program_compiler * compiler,
368 unsigned int hw_opcode, int is_math)
369 {
370 return PVS_OP_DST_OPERAND(hw_opcode,
371 is_math,
372 0,
373 compiler->PredicateIndex,
374 RC_MASK_W,
375 t_dst_class(RC_FILE_TEMPORARY));
376
377 }
378
379 static void ei_if(struct r300_vertex_program_compiler * compiler,
380 struct rc_instruction *rci,
381 unsigned int * inst,
382 unsigned int branch_depth)
383 {
384 unsigned int predicate_opcode;
385 int is_math = 0;
386
387 if (!compiler->Base.is_r500) {
388 rc_error(&compiler->Base,"Opcode IF not supported\n");
389 return;
390 }
391
392 /* Reserve a temporary to use as our predicate stack counter, if we
393 * don't already have one. */
394 if (!compiler->PredicateMask) {
395 unsigned int writemasks[RC_REGISTER_MAX_INDEX];
396 struct rc_instruction * inst;
397 unsigned int i;
398 memset(writemasks, 0, sizeof(writemasks));
399 for(inst = compiler->Base.Program.Instructions.Next;
400 inst != &compiler->Base.Program.Instructions;
401 inst = inst->Next) {
402 rc_for_all_writes_mask(inst, mark_write, writemasks);
403 }
404 for(i = 0; i < compiler->Base.max_temp_regs; i++) {
405 unsigned int mask = ~writemasks[i] & RC_MASK_XYZW;
406 /* Only the W component can be used fo the predicate
407 * stack counter. */
408 if (mask & RC_MASK_W) {
409 compiler->PredicateMask = RC_MASK_W;
410 compiler->PredicateIndex = i;
411 break;
412 }
413 }
414 if (i == compiler->Base.max_temp_regs) {
415 rc_error(&compiler->Base, "No free temporary to use for"
416 " predicate stack counter.\n");
417 return;
418 }
419 }
420 predicate_opcode =
421 branch_depth ? VE_PRED_SET_NEQ_PUSH : ME_PRED_SET_NEQ;
422
423 rci->U.I.SrcReg[0].Swizzle = RC_MAKE_SWIZZLE_SMEAR(GET_SWZ(rci->U.I.SrcReg[0].Swizzle,0));
424 if (branch_depth == 0) {
425 is_math = 1;
426 predicate_opcode = ME_PRED_SET_NEQ;
427 inst[1] = t_src(compiler->code, &rci->U.I.SrcReg[0]);
428 inst[2] = 0;
429 } else {
430 predicate_opcode = VE_PRED_SET_NEQ_PUSH;
431 inst[1] = t_pred_src(compiler);
432 inst[2] = t_src(compiler->code, &rci->U.I.SrcReg[0]);
433 }
434
435 inst[0] = t_pred_dst(compiler, predicate_opcode, is_math);
436 inst[3] = 0;
437
438 }
439
440 static void ei_else(struct r300_vertex_program_compiler * compiler,
441 unsigned int * inst)
442 {
443 if (!compiler->Base.is_r500) {
444 rc_error(&compiler->Base,"Opcode ELSE not supported\n");
445 return;
446 }
447 inst[0] = t_pred_dst(compiler, ME_PRED_SET_INV, 1);
448 inst[1] = t_pred_src(compiler);
449 inst[2] = 0;
450 inst[3] = 0;
451 }
452
453 static void ei_endif(struct r300_vertex_program_compiler *compiler,
454 unsigned int * inst)
455 {
456 if (!compiler->Base.is_r500) {
457 rc_error(&compiler->Base,"Opcode ENDIF not supported\n");
458 return;
459 }
460 inst[0] = t_pred_dst(compiler, ME_PRED_SET_POP, 1);
461 inst[1] = t_pred_src(compiler);
462 inst[2] = 0;
463 inst[3] = 0;
464 }
465
466 static void translate_vertex_program(struct radeon_compiler *c, void *user)
467 {
468 struct r300_vertex_program_compiler *compiler = (struct r300_vertex_program_compiler*)c;
469 struct rc_instruction *rci;
470
471 struct loop * loops = NULL;
472 int current_loop_depth = 0;
473 int loops_reserved = 0;
474
475 unsigned int branch_depth = 0;
476
477 compiler->code->pos_end = 0; /* Not supported yet */
478 compiler->code->length = 0;
479 compiler->code->num_temporaries = 0;
480
481 compiler->SetHwInputOutput(compiler);
482
483 for(rci = compiler->Base.Program.Instructions.Next; rci != &compiler->Base.Program.Instructions; rci = rci->Next) {
484 struct rc_sub_instruction *vpi = &rci->U.I;
485 unsigned int *inst = compiler->code->body.d + compiler->code->length;
486 const struct rc_opcode_info *info = rc_get_opcode_info(vpi->Opcode);
487
488 /* Skip instructions writing to non-existing destination */
489 if (!valid_dst(compiler->code, &vpi->DstReg))
490 continue;
491
492 if (info->HasDstReg) {
493 /* Neither is Saturate. */
494 if (vpi->SaturateMode != RC_SATURATE_NONE) {
495 rc_error(&compiler->Base, "Vertex program does not support the Saturate "
496 "modifier (yet).\n");
497 }
498 }
499
500 if (compiler->code->length >= c->max_alu_insts * 4) {
501 rc_error(&compiler->Base, "Vertex program has too many instructions\n");
502 return;
503 }
504
505 assert(compiler->Base.is_r500 ||
506 (vpi->Opcode != RC_OPCODE_SEQ &&
507 vpi->Opcode != RC_OPCODE_SNE));
508
509 switch (vpi->Opcode) {
510 case RC_OPCODE_ADD: ei_vector2(compiler->code, VE_ADD, vpi, inst); break;
511 case RC_OPCODE_ARL: ei_vector1(compiler->code, VE_FLT2FIX_DX, vpi, inst); break;
512 case RC_OPCODE_COS: ei_math1(compiler->code, ME_COS, vpi, inst); break;
513 case RC_OPCODE_DP4: ei_vector2(compiler->code, VE_DOT_PRODUCT, vpi, inst); break;
514 case RC_OPCODE_DST: ei_vector2(compiler->code, VE_DISTANCE_VECTOR, vpi, inst); break;
515 case RC_OPCODE_ELSE: ei_else(compiler, inst); break;
516 case RC_OPCODE_ENDIF: ei_endif(compiler, inst); branch_depth--; break;
517 case RC_OPCODE_EX2: ei_math1(compiler->code, ME_EXP_BASE2_FULL_DX, vpi, inst); break;
518 case RC_OPCODE_EXP: ei_math1(compiler->code, ME_EXP_BASE2_DX, vpi, inst); break;
519 case RC_OPCODE_FRC: ei_vector1(compiler->code, VE_FRACTION, vpi, inst); break;
520 case RC_OPCODE_IF: ei_if(compiler, rci, inst, branch_depth); branch_depth++; break;
521 case RC_OPCODE_LG2: ei_math1(compiler->code, ME_LOG_BASE2_FULL_DX, vpi, inst); break;
522 case RC_OPCODE_LIT: ei_lit(compiler->code, vpi, inst); break;
523 case RC_OPCODE_LOG: ei_math1(compiler->code, ME_LOG_BASE2_DX, vpi, inst); break;
524 case RC_OPCODE_MAD: ei_mad(compiler->code, vpi, inst); break;
525 case RC_OPCODE_MAX: ei_vector2(compiler->code, VE_MAXIMUM, vpi, inst); break;
526 case RC_OPCODE_MIN: ei_vector2(compiler->code, VE_MINIMUM, vpi, inst); break;
527 case RC_OPCODE_MOV: ei_vector1(compiler->code, VE_ADD, vpi, inst); break;
528 case RC_OPCODE_MUL: ei_vector2(compiler->code, VE_MULTIPLY, vpi, inst); break;
529 case RC_OPCODE_POW: ei_pow(compiler->code, vpi, inst); break;
530 case RC_OPCODE_RCP: ei_math1(compiler->code, ME_RECIP_DX, vpi, inst); break;
531 case RC_OPCODE_RSQ: ei_math1(compiler->code, ME_RECIP_SQRT_DX, vpi, inst); break;
532 case RC_OPCODE_SEQ: ei_vector2(compiler->code, VE_SET_EQUAL, vpi, inst); break;
533 case RC_OPCODE_SGE: ei_vector2(compiler->code, VE_SET_GREATER_THAN_EQUAL, vpi, inst); break;
534 case RC_OPCODE_SIN: ei_math1(compiler->code, ME_SIN, vpi, inst); break;
535 case RC_OPCODE_SLT: ei_vector2(compiler->code, VE_SET_LESS_THAN, vpi, inst); break;
536 case RC_OPCODE_SNE: ei_vector2(compiler->code, VE_SET_NOT_EQUAL, vpi, inst); break;
537 case RC_OPCODE_BGNLOOP:
538 {
539 struct loop * l;
540
541 if ((!compiler->Base.is_r500
542 && loops_reserved >= R300_VS_MAX_LOOP_DEPTH)
543 || loops_reserved >= R500_VS_MAX_FC_DEPTH) {
544 rc_error(&compiler->Base,
545 "Loops are nested too deep.");
546 return;
547 }
548 memory_pool_array_reserve(&compiler->Base.Pool,
549 struct loop, loops, current_loop_depth,
550 loops_reserved, 1);
551 l = &loops[current_loop_depth++];
552 memset(l , 0, sizeof(struct loop));
553 l->BgnLoop = (compiler->code->length / 4);
554 continue;
555 }
556 case RC_OPCODE_ENDLOOP:
557 {
558 struct loop * l;
559 unsigned int act_addr;
560 unsigned int last_addr;
561 unsigned int ret_addr;
562
563 assert(loops);
564 l = &loops[current_loop_depth - 1];
565 act_addr = l->BgnLoop - 1;
566 last_addr = (compiler->code->length / 4) - 1;
567 ret_addr = l->BgnLoop;
568
569 if (loops_reserved >= R300_VS_MAX_FC_OPS) {
570 rc_error(&compiler->Base,
571 "Too many flow control instructions.");
572 return;
573 }
574 if (compiler->Base.is_r500) {
575 compiler->code->fc_op_addrs.r500
576 [compiler->code->num_fc_ops].lw =
577 R500_PVS_FC_ACT_ADRS(act_addr)
578 | R500_PVS_FC_LOOP_CNT_JMP_INST(0xffff)
579 ;
580 compiler->code->fc_op_addrs.r500
581 [compiler->code->num_fc_ops].uw =
582 R500_PVS_FC_LAST_INST(last_addr)
583 | R500_PVS_FC_RTN_INST(ret_addr)
584 ;
585 } else {
586 compiler->code->fc_op_addrs.r300
587 [compiler->code->num_fc_ops] =
588 R300_PVS_FC_ACT_ADRS(act_addr)
589 | R300_PVS_FC_LOOP_CNT_JMP_INST(0xff)
590 | R300_PVS_FC_LAST_INST(last_addr)
591 | R300_PVS_FC_RTN_INST(ret_addr)
592 ;
593 }
594 compiler->code->fc_loop_index[compiler->code->num_fc_ops] =
595 R300_PVS_FC_LOOP_INIT_VAL(0x0)
596 | R300_PVS_FC_LOOP_STEP_VAL(0x1)
597 ;
598 compiler->code->fc_ops |= R300_VAP_PVS_FC_OPC_LOOP(
599 compiler->code->num_fc_ops);
600 compiler->code->num_fc_ops++;
601 current_loop_depth--;
602 continue;
603 }
604
605 default:
606 rc_error(&compiler->Base, "Unknown opcode %s\n", info->Name);
607 return;
608 }
609
610 /* Non-flow control instructions that are inside an if statement
611 * need to pay attention to the predicate bit. */
612 if (branch_depth
613 && vpi->Opcode != RC_OPCODE_IF
614 && vpi->Opcode != RC_OPCODE_ELSE
615 && vpi->Opcode != RC_OPCODE_ENDIF) {
616
617 inst[0] |= (PVS_DST_PRED_ENABLE_MASK
618 << PVS_DST_PRED_ENABLE_SHIFT);
619 inst[0] |= (PVS_DST_PRED_SENSE_MASK
620 << PVS_DST_PRED_SENSE_SHIFT);
621 }
622
623 /* Update the number of temporaries. */
624 if (info->HasDstReg && vpi->DstReg.File == RC_FILE_TEMPORARY &&
625 vpi->DstReg.Index >= compiler->code->num_temporaries)
626 compiler->code->num_temporaries = vpi->DstReg.Index + 1;
627
628 for (unsigned i = 0; i < info->NumSrcRegs; i++)
629 if (vpi->SrcReg[i].File == RC_FILE_TEMPORARY &&
630 vpi->SrcReg[i].Index >= compiler->code->num_temporaries)
631 compiler->code->num_temporaries = vpi->SrcReg[i].Index + 1;
632
633 if (compiler->PredicateMask)
634 if (compiler->PredicateIndex >= compiler->code->num_temporaries)
635 compiler->code->num_temporaries = compiler->PredicateIndex + 1;
636
637 if (compiler->code->num_temporaries > compiler->Base.max_temp_regs) {
638 rc_error(&compiler->Base, "Too many temporaries.\n");
639 return;
640 }
641
642 compiler->code->length += 4;
643
644 if (compiler->Base.Error)
645 return;
646 }
647 }
648
649 struct temporary_allocation {
650 unsigned int Allocated:1;
651 unsigned int HwTemp:15;
652 struct rc_instruction * LastRead;
653 };
654
655 static void allocate_temporary_registers(struct radeon_compiler *c, void *user)
656 {
657 struct r300_vertex_program_compiler *compiler = (struct r300_vertex_program_compiler*)c;
658 struct rc_instruction *inst;
659 struct rc_instruction *end_loop = NULL;
660 unsigned int num_orig_temps = 0;
661 char hwtemps[RC_REGISTER_MAX_INDEX];
662 struct temporary_allocation * ta;
663 unsigned int i, j;
664
665 memset(hwtemps, 0, sizeof(hwtemps));
666
667 rc_recompute_ips(c);
668
669 /* Pass 1: Count original temporaries. */
670 for(inst = compiler->Base.Program.Instructions.Next; inst != &compiler->Base.Program.Instructions; inst = inst->Next) {
671 const struct rc_opcode_info * opcode = rc_get_opcode_info(inst->U.I.Opcode);
672
673 for (i = 0; i < opcode->NumSrcRegs; ++i) {
674 if (inst->U.I.SrcReg[i].File == RC_FILE_TEMPORARY) {
675 if (inst->U.I.SrcReg[i].Index >= num_orig_temps)
676 num_orig_temps = inst->U.I.SrcReg[i].Index + 1;
677 }
678 }
679
680 if (opcode->HasDstReg) {
681 if (inst->U.I.DstReg.File == RC_FILE_TEMPORARY) {
682 if (inst->U.I.DstReg.Index >= num_orig_temps)
683 num_orig_temps = inst->U.I.DstReg.Index + 1;
684 }
685 }
686 }
687
688 ta = (struct temporary_allocation*)memory_pool_malloc(&compiler->Base.Pool,
689 sizeof(struct temporary_allocation) * num_orig_temps);
690 memset(ta, 0, sizeof(struct temporary_allocation) * num_orig_temps);
691
692 /* Pass 2: Determine original temporary lifetimes */
693 for(inst = compiler->Base.Program.Instructions.Next; inst != &compiler->Base.Program.Instructions; inst = inst->Next) {
694 const struct rc_opcode_info * opcode = rc_get_opcode_info(inst->U.I.Opcode);
695 /* Instructions inside of loops need to use the ENDLOOP
696 * instruction as their LastRead. */
697 if (!end_loop && inst->U.I.Opcode == RC_OPCODE_BGNLOOP) {
698 int endloops = 1;
699 struct rc_instruction * ptr;
700 for(ptr = inst->Next;
701 ptr != &compiler->Base.Program.Instructions;
702 ptr = ptr->Next){
703 if (ptr->U.I.Opcode == RC_OPCODE_BGNLOOP) {
704 endloops++;
705 } else if (ptr->U.I.Opcode == RC_OPCODE_ENDLOOP) {
706 endloops--;
707 if (endloops <= 0) {
708 end_loop = ptr;
709 break;
710 }
711 }
712 }
713 }
714
715 if (inst == end_loop) {
716 end_loop = NULL;
717 continue;
718 }
719
720 for (i = 0; i < opcode->NumSrcRegs; ++i) {
721 if (inst->U.I.SrcReg[i].File == RC_FILE_TEMPORARY) {
722 ta[inst->U.I.SrcReg[i].Index].LastRead = end_loop ? end_loop : inst;
723 }
724 }
725 }
726
727 /* Pass 3: Register allocation */
728 for(inst = compiler->Base.Program.Instructions.Next; inst != &compiler->Base.Program.Instructions; inst = inst->Next) {
729 const struct rc_opcode_info * opcode = rc_get_opcode_info(inst->U.I.Opcode);
730
731 for (i = 0; i < opcode->NumSrcRegs; ++i) {
732 if (inst->U.I.SrcReg[i].File == RC_FILE_TEMPORARY) {
733 unsigned int orig = inst->U.I.SrcReg[i].Index;
734 inst->U.I.SrcReg[i].Index = ta[orig].HwTemp;
735
736 if (ta[orig].Allocated && inst == ta[orig].LastRead)
737 hwtemps[ta[orig].HwTemp] = 0;
738 }
739 }
740
741 if (opcode->HasDstReg) {
742 if (inst->U.I.DstReg.File == RC_FILE_TEMPORARY) {
743 unsigned int orig = inst->U.I.DstReg.Index;
744
745 if (!ta[orig].Allocated) {
746 for(j = 0; j < c->max_temp_regs; ++j) {
747 if (!hwtemps[j])
748 break;
749 }
750 ta[orig].Allocated = 1;
751 ta[orig].HwTemp = j;
752 hwtemps[ta[orig].HwTemp] = 1;
753 }
754
755 inst->U.I.DstReg.Index = ta[orig].HwTemp;
756 }
757 }
758 }
759 }
760
761 /**
762 * R3xx-R4xx vertex engine does not support the Absolute source operand modifier
763 * and the Saturate opcode modifier. Only Absolute is currently transformed.
764 */
765 static int transform_nonnative_modifiers(
766 struct radeon_compiler *c,
767 struct rc_instruction *inst,
768 void* unused)
769 {
770 const struct rc_opcode_info *opcode = rc_get_opcode_info(inst->U.I.Opcode);
771 unsigned i;
772
773 /* Transform ABS(a) to MAX(a, -a). */
774 for (i = 0; i < opcode->NumSrcRegs; i++) {
775 if (inst->U.I.SrcReg[i].Abs) {
776 struct rc_instruction *new_inst;
777 unsigned temp;
778
779 inst->U.I.SrcReg[i].Abs = 0;
780
781 temp = rc_find_free_temporary(c);
782
783 new_inst = rc_insert_new_instruction(c, inst->Prev);
784 new_inst->U.I.Opcode = RC_OPCODE_MAX;
785 new_inst->U.I.DstReg.File = RC_FILE_TEMPORARY;
786 new_inst->U.I.DstReg.Index = temp;
787 new_inst->U.I.SrcReg[0] = inst->U.I.SrcReg[i];
788 new_inst->U.I.SrcReg[1] = inst->U.I.SrcReg[i];
789 new_inst->U.I.SrcReg[1].Negate ^= RC_MASK_XYZW;
790
791 memset(&inst->U.I.SrcReg[i], 0, sizeof(inst->U.I.SrcReg[i]));
792 inst->U.I.SrcReg[i].File = RC_FILE_TEMPORARY;
793 inst->U.I.SrcReg[i].Index = temp;
794 inst->U.I.SrcReg[i].Swizzle = RC_SWIZZLE_XYZW;
795 }
796 }
797 return 1;
798 }
799
800 /**
801 * Vertex engine cannot read two inputs or two constants at the same time.
802 * Introduce intermediate MOVs to temporary registers to account for this.
803 */
804 static int transform_source_conflicts(
805 struct radeon_compiler *c,
806 struct rc_instruction* inst,
807 void* unused)
808 {
809 const struct rc_opcode_info * opcode = rc_get_opcode_info(inst->U.I.Opcode);
810
811 if (opcode->NumSrcRegs == 3) {
812 if (t_src_conflict(inst->U.I.SrcReg[1], inst->U.I.SrcReg[2])
813 || t_src_conflict(inst->U.I.SrcReg[0], inst->U.I.SrcReg[2])) {
814 int tmpreg = rc_find_free_temporary(c);
815 struct rc_instruction * inst_mov = rc_insert_new_instruction(c, inst->Prev);
816 inst_mov->U.I.Opcode = RC_OPCODE_MOV;
817 inst_mov->U.I.DstReg.File = RC_FILE_TEMPORARY;
818 inst_mov->U.I.DstReg.Index = tmpreg;
819 inst_mov->U.I.SrcReg[0] = inst->U.I.SrcReg[2];
820
821 reset_srcreg(&inst->U.I.SrcReg[2]);
822 inst->U.I.SrcReg[2].File = RC_FILE_TEMPORARY;
823 inst->U.I.SrcReg[2].Index = tmpreg;
824 }
825 }
826
827 if (opcode->NumSrcRegs >= 2) {
828 if (t_src_conflict(inst->U.I.SrcReg[1], inst->U.I.SrcReg[0])) {
829 int tmpreg = rc_find_free_temporary(c);
830 struct rc_instruction * inst_mov = rc_insert_new_instruction(c, inst->Prev);
831 inst_mov->U.I.Opcode = RC_OPCODE_MOV;
832 inst_mov->U.I.DstReg.File = RC_FILE_TEMPORARY;
833 inst_mov->U.I.DstReg.Index = tmpreg;
834 inst_mov->U.I.SrcReg[0] = inst->U.I.SrcReg[1];
835
836 reset_srcreg(&inst->U.I.SrcReg[1]);
837 inst->U.I.SrcReg[1].File = RC_FILE_TEMPORARY;
838 inst->U.I.SrcReg[1].Index = tmpreg;
839 }
840 }
841
842 return 1;
843 }
844
845 static void rc_vs_add_artificial_outputs(struct radeon_compiler *c, void *user)
846 {
847 struct r300_vertex_program_compiler * compiler = (struct r300_vertex_program_compiler*)c;
848 int i;
849
850 for(i = 0; i < 32; ++i) {
851 if ((compiler->RequiredOutputs & (1 << i)) &&
852 !(compiler->Base.Program.OutputsWritten & (1 << i))) {
853 struct rc_instruction * inst = rc_insert_new_instruction(&compiler->Base, compiler->Base.Program.Instructions.Prev);
854 inst->U.I.Opcode = RC_OPCODE_MOV;
855
856 inst->U.I.DstReg.File = RC_FILE_OUTPUT;
857 inst->U.I.DstReg.Index = i;
858 inst->U.I.DstReg.WriteMask = RC_MASK_XYZW;
859
860 inst->U.I.SrcReg[0].File = RC_FILE_CONSTANT;
861 inst->U.I.SrcReg[0].Index = 0;
862 inst->U.I.SrcReg[0].Swizzle = RC_SWIZZLE_XYZW;
863
864 compiler->Base.Program.OutputsWritten |= 1 << i;
865 }
866 }
867 }
868
869 static void dataflow_outputs_mark_used(void * userdata, void * data,
870 void (*callback)(void *, unsigned int, unsigned int))
871 {
872 struct r300_vertex_program_compiler * c = userdata;
873 int i;
874
875 for(i = 0; i < 32; ++i) {
876 if (c->RequiredOutputs & (1 << i))
877 callback(data, i, RC_MASK_XYZW);
878 }
879 }
880
881 static int swizzle_is_native(rc_opcode opcode, struct rc_src_register reg)
882 {
883 (void) opcode;
884 (void) reg;
885
886 return 1;
887 }
888
889 static void transform_negative_addressing(struct r300_vertex_program_compiler *c,
890 struct rc_instruction *arl,
891 struct rc_instruction *end,
892 int min_offset)
893 {
894 struct rc_instruction *inst, *add;
895 unsigned const_swizzle;
896
897 /* Transform ARL */
898 add = rc_insert_new_instruction(&c->Base, arl->Prev);
899 add->U.I.Opcode = RC_OPCODE_ADD;
900 add->U.I.DstReg.File = RC_FILE_TEMPORARY;
901 add->U.I.DstReg.Index = rc_find_free_temporary(&c->Base);
902 add->U.I.DstReg.WriteMask = RC_MASK_X;
903 add->U.I.SrcReg[0] = arl->U.I.SrcReg[0];
904 add->U.I.SrcReg[1].File = RC_FILE_CONSTANT;
905 add->U.I.SrcReg[1].Index = rc_constants_add_immediate_scalar(&c->Base.Program.Constants,
906 min_offset, &const_swizzle);
907 add->U.I.SrcReg[1].Swizzle = const_swizzle;
908
909 arl->U.I.SrcReg[0].File = RC_FILE_TEMPORARY;
910 arl->U.I.SrcReg[0].Index = add->U.I.DstReg.Index;
911 arl->U.I.SrcReg[0].Swizzle = RC_SWIZZLE_XXXX;
912
913 /* Rewrite offsets up to and excluding inst. */
914 for (inst = arl->Next; inst != end; inst = inst->Next) {
915 const struct rc_opcode_info * opcode = rc_get_opcode_info(inst->U.I.Opcode);
916
917 for (unsigned i = 0; i < opcode->NumSrcRegs; i++)
918 if (inst->U.I.SrcReg[i].RelAddr)
919 inst->U.I.SrcReg[i].Index -= min_offset;
920 }
921 }
922
923 static void rc_emulate_negative_addressing(struct radeon_compiler *compiler, void *user)
924 {
925 struct r300_vertex_program_compiler * c = (struct r300_vertex_program_compiler*)compiler;
926 struct rc_instruction *inst, *lastARL = NULL;
927 int min_offset = 0;
928
929 for (inst = c->Base.Program.Instructions.Next; inst != &c->Base.Program.Instructions; inst = inst->Next) {
930 const struct rc_opcode_info * opcode = rc_get_opcode_info(inst->U.I.Opcode);
931
932 if (inst->U.I.Opcode == RC_OPCODE_ARL) {
933 if (lastARL != NULL && min_offset < 0)
934 transform_negative_addressing(c, lastARL, inst, min_offset);
935
936 lastARL = inst;
937 min_offset = 0;
938 continue;
939 }
940
941 for (unsigned i = 0; i < opcode->NumSrcRegs; i++) {
942 if (inst->U.I.SrcReg[i].RelAddr &&
943 inst->U.I.SrcReg[i].Index < 0) {
944 /* ARL must precede any indirect addressing. */
945 if (lastARL == NULL) {
946 rc_error(&c->Base, "Vertex shader: Found relative addressing without ARL.");
947 return;
948 }
949
950 if (inst->U.I.SrcReg[i].Index < min_offset)
951 min_offset = inst->U.I.SrcReg[i].Index;
952 }
953 }
954 }
955
956 if (lastARL != NULL && min_offset < 0)
957 transform_negative_addressing(c, lastARL, inst, min_offset);
958 }
959
960 static struct rc_swizzle_caps r300_vertprog_swizzle_caps = {
961 .IsNative = &swizzle_is_native,
962 .Split = 0 /* should never be called */
963 };
964
965 void r3xx_compile_vertex_program(struct r300_vertex_program_compiler *c)
966 {
967 int is_r500 = c->Base.is_r500;
968 int opt = !c->Base.disable_optimizations;
969
970 /* Lists of instruction transformations. */
971 struct radeon_program_transformation alu_rewrite_r500[] = {
972 { &r300_transform_vertex_alu, 0 },
973 { &r300_transform_trig_scale_vertex, 0 },
974 { 0, 0 }
975 };
976
977 struct radeon_program_transformation alu_rewrite_r300[] = {
978 { &r300_transform_vertex_alu, 0 },
979 { &r300_transform_trig_simple, 0 },
980 { 0, 0 }
981 };
982
983 /* Note: These passes have to be done seperately from ALU rewrite,
984 * otherwise non-native ALU instructions with source conflits
985 * or non-native modifiers will not be treated properly.
986 */
987 struct radeon_program_transformation emulate_modifiers[] = {
988 { &transform_nonnative_modifiers, 0 },
989 { 0, 0 }
990 };
991
992 struct radeon_program_transformation resolve_src_conflicts[] = {
993 { &transform_source_conflicts, 0 },
994 { 0, 0 }
995 };
996
997 /* List of compiler passes. */
998 struct radeon_compiler_pass vs_list[] = {
999 /* NAME DUMP PREDICATE FUNCTION PARAM */
1000 {"add artificial outputs", 0, 1, rc_vs_add_artificial_outputs, NULL},
1001 {"transform loops", 1, 1, rc_transform_loops, NULL},
1002 {"emulate branches", 1, !is_r500, rc_emulate_branches, NULL},
1003 {"emulate negative addressing", 1, 1, rc_emulate_negative_addressing, NULL},
1004 {"native rewrite", 1, is_r500, rc_local_transform, alu_rewrite_r500},
1005 {"native rewrite", 1, !is_r500, rc_local_transform, alu_rewrite_r300},
1006 {"emulate modifiers", 1, !is_r500, rc_local_transform, emulate_modifiers},
1007 {"deadcode", 1, opt, rc_dataflow_deadcode, dataflow_outputs_mark_used},
1008 {"dataflow optimize", 1, opt, rc_optimize, NULL},
1009 /* This pass must be done after optimizations. */
1010 {"source conflict resolve", 1, 1, rc_local_transform, resolve_src_conflicts},
1011 {"register allocation", 1, opt, allocate_temporary_registers, NULL},
1012 {"dead constants", 1, 1, rc_remove_unused_constants, &c->code->constants_remap_table},
1013 {"final code validation", 0, 1, rc_validate_final_shader, NULL},
1014 {"machine code generation", 0, 1, translate_vertex_program, NULL},
1015 {"dump machine code", 0, c->Base.Debug & RC_DBG_LOG, r300_vertex_program_dump, NULL},
1016 {NULL, 0, 0, NULL, NULL}
1017 };
1018
1019 c->Base.type = RC_VERTEX_PROGRAM;
1020 c->Base.SwizzleCaps = &r300_vertprog_swizzle_caps;
1021
1022 rc_run_compiler(&c->Base, vs_list);
1023
1024 c->code->InputsRead = c->Base.Program.InputsRead;
1025 c->code->OutputsWritten = c->Base.Program.OutputsWritten;
1026 rc_constants_copy(&c->code->constants, &c->Base.Program.Constants);
1027 }