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r300/compiler: use peephole and constant folding for vertex shaders too
[mesa.git] / src / mesa / drivers / dri / r300 / compiler / r3xx_vertprog.c
1 /*
2 * Copyright 2009 Nicolai Hähnle <nhaehnle@gmail.com>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE. */
22
23 #include "radeon_compiler.h"
24
25 #include <stdio.h>
26
27 #include "../r300_reg.h"
28
29 #include "radeon_dataflow.h"
30 #include "radeon_program_alu.h"
31 #include "radeon_swizzle.h"
32 #include "radeon_emulate_branches.h"
33 #include "radeon_emulate_loops.h"
34 #include "radeon_remove_constants.h"
35
36 struct loop {
37 int BgnLoop;
38
39 };
40
41 /*
42 * Take an already-setup and valid source then swizzle it appropriately to
43 * obtain a constant ZERO or ONE source.
44 */
45 #define __CONST(x, y) \
46 (PVS_SRC_OPERAND(t_src_index(vp, &vpi->SrcReg[x]), \
47 t_swizzle(y), \
48 t_swizzle(y), \
49 t_swizzle(y), \
50 t_swizzle(y), \
51 t_src_class(vpi->SrcReg[x].File), \
52 RC_MASK_NONE) | (vpi->SrcReg[x].RelAddr << 4))
53
54
55 static unsigned long t_dst_mask(unsigned int mask)
56 {
57 /* RC_MASK_* is equivalent to VSF_FLAG_* */
58 return mask & RC_MASK_XYZW;
59 }
60
61 static unsigned long t_dst_class(rc_register_file file)
62 {
63 switch (file) {
64 default:
65 fprintf(stderr, "%s: Bad register file %i\n", __FUNCTION__, file);
66 /* fall-through */
67 case RC_FILE_TEMPORARY:
68 return PVS_DST_REG_TEMPORARY;
69 case RC_FILE_OUTPUT:
70 return PVS_DST_REG_OUT;
71 case RC_FILE_ADDRESS:
72 return PVS_DST_REG_A0;
73 }
74 }
75
76 static unsigned long t_dst_index(struct r300_vertex_program_code *vp,
77 struct rc_dst_register *dst)
78 {
79 if (dst->File == RC_FILE_OUTPUT)
80 return vp->outputs[dst->Index];
81
82 return dst->Index;
83 }
84
85 static unsigned long t_src_class(rc_register_file file)
86 {
87 switch (file) {
88 default:
89 fprintf(stderr, "%s: Bad register file %i\n", __FUNCTION__, file);
90 /* fall-through */
91 case RC_FILE_NONE:
92 case RC_FILE_TEMPORARY:
93 return PVS_SRC_REG_TEMPORARY;
94 case RC_FILE_INPUT:
95 return PVS_SRC_REG_INPUT;
96 case RC_FILE_CONSTANT:
97 return PVS_SRC_REG_CONSTANT;
98 }
99 }
100
101 static int t_src_conflict(struct rc_src_register a, struct rc_src_register b)
102 {
103 unsigned long aclass = t_src_class(a.File);
104 unsigned long bclass = t_src_class(b.File);
105
106 if (aclass != bclass)
107 return 0;
108 if (aclass == PVS_SRC_REG_TEMPORARY)
109 return 0;
110
111 if (a.RelAddr || b.RelAddr)
112 return 1;
113 if (a.Index != b.Index)
114 return 1;
115
116 return 0;
117 }
118
119 static inline unsigned long t_swizzle(unsigned int swizzle)
120 {
121 /* this is in fact a NOP as the Mesa RC_SWIZZLE_* are all identical to VSF_IN_COMPONENT_* */
122 return swizzle;
123 }
124
125 static unsigned long t_src_index(struct r300_vertex_program_code *vp,
126 struct rc_src_register *src)
127 {
128 if (src->File == RC_FILE_INPUT) {
129 assert(vp->inputs[src->Index] != -1);
130 return vp->inputs[src->Index];
131 } else {
132 if (src->Index < 0) {
133 fprintf(stderr,
134 "negative offsets for indirect addressing do not work.\n");
135 return 0;
136 }
137 return src->Index;
138 }
139 }
140
141 /* these two functions should probably be merged... */
142
143 static unsigned long t_src(struct r300_vertex_program_code *vp,
144 struct rc_src_register *src)
145 {
146 /* src->Negate uses the RC_MASK_ flags from program_instruction.h,
147 * which equal our VSF_FLAGS_ values, so it's safe to just pass it here.
148 */
149 return PVS_SRC_OPERAND(t_src_index(vp, src),
150 t_swizzle(GET_SWZ(src->Swizzle, 0)),
151 t_swizzle(GET_SWZ(src->Swizzle, 1)),
152 t_swizzle(GET_SWZ(src->Swizzle, 2)),
153 t_swizzle(GET_SWZ(src->Swizzle, 3)),
154 t_src_class(src->File),
155 src->Negate) |
156 (src->RelAddr << 4) | (src->Abs << 3);
157 }
158
159 static unsigned long t_src_scalar(struct r300_vertex_program_code *vp,
160 struct rc_src_register *src)
161 {
162 /* src->Negate uses the RC_MASK_ flags from program_instruction.h,
163 * which equal our VSF_FLAGS_ values, so it's safe to just pass it here.
164 */
165 return PVS_SRC_OPERAND(t_src_index(vp, src),
166 t_swizzle(GET_SWZ(src->Swizzle, 0)),
167 t_swizzle(GET_SWZ(src->Swizzle, 0)),
168 t_swizzle(GET_SWZ(src->Swizzle, 0)),
169 t_swizzle(GET_SWZ(src->Swizzle, 0)),
170 t_src_class(src->File),
171 src->Negate ? RC_MASK_XYZW : RC_MASK_NONE) |
172 (src->RelAddr << 4) | (src->Abs << 3);
173 }
174
175 static int valid_dst(struct r300_vertex_program_code *vp,
176 struct rc_dst_register *dst)
177 {
178 if (dst->File == RC_FILE_OUTPUT && vp->outputs[dst->Index] == -1) {
179 return 0;
180 } else if (dst->File == RC_FILE_ADDRESS) {
181 assert(dst->Index == 0);
182 }
183
184 return 1;
185 }
186
187 static void ei_vector1(struct r300_vertex_program_code *vp,
188 unsigned int hw_opcode,
189 struct rc_sub_instruction *vpi,
190 unsigned int * inst)
191 {
192 inst[0] = PVS_OP_DST_OPERAND(hw_opcode,
193 0,
194 0,
195 t_dst_index(vp, &vpi->DstReg),
196 t_dst_mask(vpi->DstReg.WriteMask),
197 t_dst_class(vpi->DstReg.File));
198 inst[1] = t_src(vp, &vpi->SrcReg[0]);
199 inst[2] = __CONST(0, RC_SWIZZLE_ZERO);
200 inst[3] = __CONST(0, RC_SWIZZLE_ZERO);
201 }
202
203 static void ei_vector2(struct r300_vertex_program_code *vp,
204 unsigned int hw_opcode,
205 struct rc_sub_instruction *vpi,
206 unsigned int * inst)
207 {
208 inst[0] = PVS_OP_DST_OPERAND(hw_opcode,
209 0,
210 0,
211 t_dst_index(vp, &vpi->DstReg),
212 t_dst_mask(vpi->DstReg.WriteMask),
213 t_dst_class(vpi->DstReg.File));
214 inst[1] = t_src(vp, &vpi->SrcReg[0]);
215 inst[2] = t_src(vp, &vpi->SrcReg[1]);
216 inst[3] = __CONST(1, RC_SWIZZLE_ZERO);
217 }
218
219 static void ei_math1(struct r300_vertex_program_code *vp,
220 unsigned int hw_opcode,
221 struct rc_sub_instruction *vpi,
222 unsigned int * inst)
223 {
224 inst[0] = PVS_OP_DST_OPERAND(hw_opcode,
225 1,
226 0,
227 t_dst_index(vp, &vpi->DstReg),
228 t_dst_mask(vpi->DstReg.WriteMask),
229 t_dst_class(vpi->DstReg.File));
230 inst[1] = t_src_scalar(vp, &vpi->SrcReg[0]);
231 inst[2] = __CONST(0, RC_SWIZZLE_ZERO);
232 inst[3] = __CONST(0, RC_SWIZZLE_ZERO);
233 }
234
235 static void ei_lit(struct r300_vertex_program_code *vp,
236 struct rc_sub_instruction *vpi,
237 unsigned int * inst)
238 {
239 //LIT TMP 1.Y Z TMP 1{} {X W Z Y} TMP 1{} {Y W Z X} TMP 1{} {Y X Z W}
240
241 inst[0] = PVS_OP_DST_OPERAND(ME_LIGHT_COEFF_DX,
242 1,
243 0,
244 t_dst_index(vp, &vpi->DstReg),
245 t_dst_mask(vpi->DstReg.WriteMask),
246 t_dst_class(vpi->DstReg.File));
247 /* NOTE: Users swizzling might not work. */
248 inst[1] = PVS_SRC_OPERAND(t_src_index(vp, &vpi->SrcReg[0]), t_swizzle(GET_SWZ(vpi->SrcReg[0].Swizzle, 0)), // X
249 t_swizzle(GET_SWZ(vpi->SrcReg[0].Swizzle, 3)), // W
250 PVS_SRC_SELECT_FORCE_0, // Z
251 t_swizzle(GET_SWZ(vpi->SrcReg[0].Swizzle, 1)), // Y
252 t_src_class(vpi->SrcReg[0].File),
253 vpi->SrcReg[0].Negate ? RC_MASK_XYZW : RC_MASK_NONE) |
254 (vpi->SrcReg[0].RelAddr << 4);
255 inst[2] = PVS_SRC_OPERAND(t_src_index(vp, &vpi->SrcReg[0]), t_swizzle(GET_SWZ(vpi->SrcReg[0].Swizzle, 1)), // Y
256 t_swizzle(GET_SWZ(vpi->SrcReg[0].Swizzle, 3)), // W
257 PVS_SRC_SELECT_FORCE_0, // Z
258 t_swizzle(GET_SWZ(vpi->SrcReg[0].Swizzle, 0)), // X
259 t_src_class(vpi->SrcReg[0].File),
260 vpi->SrcReg[0].Negate ? RC_MASK_XYZW : RC_MASK_NONE) |
261 (vpi->SrcReg[0].RelAddr << 4);
262 inst[3] = PVS_SRC_OPERAND(t_src_index(vp, &vpi->SrcReg[0]), t_swizzle(GET_SWZ(vpi->SrcReg[0].Swizzle, 1)), // Y
263 t_swizzle(GET_SWZ(vpi->SrcReg[0].Swizzle, 0)), // X
264 PVS_SRC_SELECT_FORCE_0, // Z
265 t_swizzle(GET_SWZ(vpi->SrcReg[0].Swizzle, 3)), // W
266 t_src_class(vpi->SrcReg[0].File),
267 vpi->SrcReg[0].Negate ? RC_MASK_XYZW : RC_MASK_NONE) |
268 (vpi->SrcReg[0].RelAddr << 4);
269 }
270
271 static void ei_mad(struct r300_vertex_program_code *vp,
272 struct rc_sub_instruction *vpi,
273 unsigned int * inst)
274 {
275 /* Remarks about hardware limitations of MAD
276 * (please preserve this comment, as this information is _NOT_
277 * in the documentation provided by AMD).
278 *
279 * As described in the documentation, MAD with three unique temporary
280 * source registers requires the use of the macro version.
281 *
282 * However (and this is not mentioned in the documentation), apparently
283 * the macro version is _NOT_ a full superset of the normal version.
284 * In particular, the macro version does not always work when relative
285 * addressing is used in the source operands.
286 *
287 * This limitation caused incorrect rendering in Sauerbraten's OpenGL
288 * assembly shader path when using medium quality animations
289 * (i.e. animations with matrix blending instead of quaternion blending).
290 *
291 * Unfortunately, I (nha) have been unable to extract a Piglit regression
292 * test for this issue - for some reason, it is possible to have vertex
293 * programs whose prefix is *exactly* the same as the prefix of the
294 * offending program in Sauerbraten up to the offending instruction
295 * without causing any trouble.
296 *
297 * Bottom line: Only use the macro version only when really necessary;
298 * according to AMD docs, this should improve performance by one clock
299 * as a nice side bonus.
300 */
301 if (vpi->SrcReg[0].File == RC_FILE_TEMPORARY &&
302 vpi->SrcReg[1].File == RC_FILE_TEMPORARY &&
303 vpi->SrcReg[2].File == RC_FILE_TEMPORARY &&
304 vpi->SrcReg[0].Index != vpi->SrcReg[1].Index &&
305 vpi->SrcReg[0].Index != vpi->SrcReg[2].Index &&
306 vpi->SrcReg[1].Index != vpi->SrcReg[2].Index) {
307 inst[0] = PVS_OP_DST_OPERAND(PVS_MACRO_OP_2CLK_MADD,
308 0,
309 1,
310 t_dst_index(vp, &vpi->DstReg),
311 t_dst_mask(vpi->DstReg.WriteMask),
312 t_dst_class(vpi->DstReg.File));
313 } else {
314 inst[0] = PVS_OP_DST_OPERAND(VE_MULTIPLY_ADD,
315 0,
316 0,
317 t_dst_index(vp, &vpi->DstReg),
318 t_dst_mask(vpi->DstReg.WriteMask),
319 t_dst_class(vpi->DstReg.File));
320 }
321 inst[1] = t_src(vp, &vpi->SrcReg[0]);
322 inst[2] = t_src(vp, &vpi->SrcReg[1]);
323 inst[3] = t_src(vp, &vpi->SrcReg[2]);
324 }
325
326 static void ei_pow(struct r300_vertex_program_code *vp,
327 struct rc_sub_instruction *vpi,
328 unsigned int * inst)
329 {
330 inst[0] = PVS_OP_DST_OPERAND(ME_POWER_FUNC_FF,
331 1,
332 0,
333 t_dst_index(vp, &vpi->DstReg),
334 t_dst_mask(vpi->DstReg.WriteMask),
335 t_dst_class(vpi->DstReg.File));
336 inst[1] = t_src_scalar(vp, &vpi->SrcReg[0]);
337 inst[2] = __CONST(0, RC_SWIZZLE_ZERO);
338 inst[3] = t_src_scalar(vp, &vpi->SrcReg[1]);
339 }
340
341 static void mark_write(void * userdata, struct rc_instruction * inst,
342 rc_register_file file, unsigned int index, unsigned int mask)
343 {
344 unsigned int * writemasks = userdata;
345
346 if (file != RC_FILE_TEMPORARY)
347 return;
348
349 if (index >= R300_VS_MAX_TEMPS)
350 return;
351
352 writemasks[index] |= mask;
353 }
354
355 static unsigned long t_pred_src(struct r300_vertex_program_compiler * compiler)
356 {
357 return PVS_SRC_OPERAND(compiler->PredicateIndex,
358 t_swizzle(RC_SWIZZLE_ZERO),
359 t_swizzle(RC_SWIZZLE_ZERO),
360 t_swizzle(RC_SWIZZLE_ZERO),
361 t_swizzle(RC_SWIZZLE_W),
362 t_src_class(RC_FILE_TEMPORARY),
363 0);
364 }
365
366 static unsigned long t_pred_dst(struct r300_vertex_program_compiler * compiler,
367 unsigned int hw_opcode, int is_math)
368 {
369 return PVS_OP_DST_OPERAND(hw_opcode,
370 is_math,
371 0,
372 compiler->PredicateIndex,
373 RC_MASK_W,
374 t_dst_class(RC_FILE_TEMPORARY));
375
376 }
377
378 static void ei_if(struct r300_vertex_program_compiler * compiler,
379 struct rc_instruction *rci,
380 unsigned int * inst,
381 unsigned int branch_depth)
382 {
383 unsigned int predicate_opcode;
384 int is_math = 0;
385
386 if (!compiler->Base.is_r500) {
387 rc_error(&compiler->Base,"Opcode IF not supported\n");
388 return;
389 }
390
391 /* Reserve a temporary to use as our predicate stack counter, if we
392 * don't already have one. */
393 if (!compiler->PredicateMask) {
394 unsigned int writemasks[R300_VS_MAX_TEMPS];
395 memset(writemasks, 0, sizeof(writemasks));
396 struct rc_instruction * inst;
397 unsigned int i;
398 for(inst = compiler->Base.Program.Instructions.Next;
399 inst != &compiler->Base.Program.Instructions;
400 inst = inst->Next) {
401 rc_for_all_writes_mask(inst, mark_write, writemasks);
402 }
403 for(i = 0; i < R300_VS_MAX_TEMPS; i++) {
404 unsigned int mask = ~writemasks[i] & RC_MASK_XYZW;
405 /* Only the W component can be used fo the predicate
406 * stack counter. */
407 if (mask & RC_MASK_W) {
408 compiler->PredicateMask = RC_MASK_W;
409 compiler->PredicateIndex = i;
410 break;
411 }
412 }
413 if (i == R300_VS_MAX_TEMPS) {
414 rc_error(&compiler->Base, "No free temporary to use for"
415 " predicate stack counter.\n");
416 return;
417 }
418 }
419 predicate_opcode =
420 branch_depth ? VE_PRED_SET_NEQ_PUSH : ME_PRED_SET_NEQ;
421
422 rci->U.I.SrcReg[0].Swizzle = RC_MAKE_SWIZZLE_SMEAR(GET_SWZ(rci->U.I.SrcReg[0].Swizzle,0));
423 if (branch_depth == 0) {
424 is_math = 1;
425 predicate_opcode = ME_PRED_SET_NEQ;
426 inst[1] = t_src(compiler->code, &rci->U.I.SrcReg[0]);
427 inst[2] = 0;
428 } else {
429 predicate_opcode = VE_PRED_SET_NEQ_PUSH;
430 inst[1] = t_pred_src(compiler);
431 inst[2] = t_src(compiler->code, &rci->U.I.SrcReg[0]);
432 }
433
434 inst[0] = t_pred_dst(compiler, predicate_opcode, is_math);
435 inst[3] = 0;
436
437 }
438
439 static void ei_else(struct r300_vertex_program_compiler * compiler,
440 unsigned int * inst)
441 {
442 if (!compiler->Base.is_r500) {
443 rc_error(&compiler->Base,"Opcode ELSE not supported\n");
444 return;
445 }
446 inst[0] = t_pred_dst(compiler, ME_PRED_SET_INV, 1);
447 inst[1] = t_pred_src(compiler);
448 inst[2] = 0;
449 inst[3] = 0;
450 }
451
452 static void ei_endif(struct r300_vertex_program_compiler *compiler,
453 unsigned int * inst)
454 {
455 if (!compiler->Base.is_r500) {
456 rc_error(&compiler->Base,"Opcode ENDIF not supported\n");
457 return;
458 }
459 inst[0] = t_pred_dst(compiler, ME_PRED_SET_POP, 1);
460 inst[1] = t_pred_src(compiler);
461 inst[2] = 0;
462 inst[3] = 0;
463 }
464
465 static void translate_vertex_program(struct radeon_compiler *c, void *user)
466 {
467 struct r300_vertex_program_compiler *compiler = (struct r300_vertex_program_compiler*)c;
468 struct rc_instruction *rci;
469
470 struct loop * loops = NULL;
471 int current_loop_depth = 0;
472 int loops_reserved = 0;
473
474 unsigned int branch_depth = 0;
475
476 compiler->code->pos_end = 0; /* Not supported yet */
477 compiler->code->length = 0;
478
479 compiler->SetHwInputOutput(compiler);
480
481 for(rci = compiler->Base.Program.Instructions.Next; rci != &compiler->Base.Program.Instructions; rci = rci->Next) {
482 struct rc_sub_instruction *vpi = &rci->U.I;
483 unsigned int *inst = compiler->code->body.d + compiler->code->length;
484
485 /* Skip instructions writing to non-existing destination */
486 if (!valid_dst(compiler->code, &vpi->DstReg))
487 continue;
488
489 if (rc_get_opcode_info(vpi->Opcode)->HasDstReg) {
490 /* Relative addressing of destination operands is not supported yet. */
491 if (vpi->DstReg.RelAddr) {
492 rc_error(&compiler->Base, "Vertex program does not support relative "
493 "addressing of destination operands (yet).\n");
494 return;
495 }
496
497 /* Neither is Saturate. */
498 if (vpi->SaturateMode != RC_SATURATE_NONE) {
499 rc_error(&compiler->Base, "Vertex program does not support the Saturate "
500 "modifier (yet).\n");
501 }
502 }
503
504 if (compiler->code->length >= R500_VS_MAX_ALU_DWORDS ||
505 (compiler->code->length >= R300_VS_MAX_ALU_DWORDS && !compiler->Base.is_r500)) {
506 rc_error(&compiler->Base, "Vertex program has too many instructions\n");
507 return;
508 }
509
510 assert(compiler->Base.is_r500 ||
511 (vpi->Opcode != RC_OPCODE_SEQ &&
512 vpi->Opcode != RC_OPCODE_SNE));
513
514 switch (vpi->Opcode) {
515 case RC_OPCODE_ADD: ei_vector2(compiler->code, VE_ADD, vpi, inst); break;
516 case RC_OPCODE_ARL: ei_vector1(compiler->code, VE_FLT2FIX_DX, vpi, inst); break;
517 case RC_OPCODE_COS: ei_math1(compiler->code, ME_COS, vpi, inst); break;
518 case RC_OPCODE_DP4: ei_vector2(compiler->code, VE_DOT_PRODUCT, vpi, inst); break;
519 case RC_OPCODE_DST: ei_vector2(compiler->code, VE_DISTANCE_VECTOR, vpi, inst); break;
520 case RC_OPCODE_ELSE: ei_else(compiler, inst); break;
521 case RC_OPCODE_ENDIF: ei_endif(compiler, inst); branch_depth--; break;
522 case RC_OPCODE_EX2: ei_math1(compiler->code, ME_EXP_BASE2_FULL_DX, vpi, inst); break;
523 case RC_OPCODE_EXP: ei_math1(compiler->code, ME_EXP_BASE2_DX, vpi, inst); break;
524 case RC_OPCODE_FRC: ei_vector1(compiler->code, VE_FRACTION, vpi, inst); break;
525 case RC_OPCODE_IF: ei_if(compiler, rci, inst, branch_depth); branch_depth++; break;
526 case RC_OPCODE_LG2: ei_math1(compiler->code, ME_LOG_BASE2_FULL_DX, vpi, inst); break;
527 case RC_OPCODE_LIT: ei_lit(compiler->code, vpi, inst); break;
528 case RC_OPCODE_LOG: ei_math1(compiler->code, ME_LOG_BASE2_DX, vpi, inst); break;
529 case RC_OPCODE_MAD: ei_mad(compiler->code, vpi, inst); break;
530 case RC_OPCODE_MAX: ei_vector2(compiler->code, VE_MAXIMUM, vpi, inst); break;
531 case RC_OPCODE_MIN: ei_vector2(compiler->code, VE_MINIMUM, vpi, inst); break;
532 case RC_OPCODE_MOV: ei_vector1(compiler->code, VE_ADD, vpi, inst); break;
533 case RC_OPCODE_MUL: ei_vector2(compiler->code, VE_MULTIPLY, vpi, inst); break;
534 case RC_OPCODE_POW: ei_pow(compiler->code, vpi, inst); break;
535 case RC_OPCODE_RCP: ei_math1(compiler->code, ME_RECIP_DX, vpi, inst); break;
536 case RC_OPCODE_RSQ: ei_math1(compiler->code, ME_RECIP_SQRT_DX, vpi, inst); break;
537 case RC_OPCODE_SEQ: ei_vector2(compiler->code, VE_SET_EQUAL, vpi, inst); break;
538 case RC_OPCODE_SGE: ei_vector2(compiler->code, VE_SET_GREATER_THAN_EQUAL, vpi, inst); break;
539 case RC_OPCODE_SIN: ei_math1(compiler->code, ME_SIN, vpi, inst); break;
540 case RC_OPCODE_SLT: ei_vector2(compiler->code, VE_SET_LESS_THAN, vpi, inst); break;
541 case RC_OPCODE_SNE: ei_vector2(compiler->code, VE_SET_NOT_EQUAL, vpi, inst); break;
542 case RC_OPCODE_BGNLOOP:
543 {
544 struct loop * l;
545
546 if ((!compiler->Base.is_r500
547 && loops_reserved >= R300_VS_MAX_LOOP_DEPTH)
548 || loops_reserved >= R500_VS_MAX_FC_DEPTH) {
549 rc_error(&compiler->Base,
550 "Loops are nested too deep.");
551 return;
552 }
553 memory_pool_array_reserve(&compiler->Base.Pool,
554 struct loop, loops, current_loop_depth,
555 loops_reserved, 1);
556 l = &loops[current_loop_depth++];
557 memset(l , 0, sizeof(struct loop));
558 l->BgnLoop = (compiler->code->length / 4);
559 continue;
560 }
561 case RC_OPCODE_ENDLOOP:
562 {
563 struct loop * l;
564 unsigned int act_addr;
565 unsigned int last_addr;
566 unsigned int ret_addr;
567
568 assert(loops);
569 l = &loops[current_loop_depth - 1];
570 act_addr = l->BgnLoop - 1;
571 last_addr = (compiler->code->length / 4) - 1;
572 ret_addr = l->BgnLoop;
573
574 if (loops_reserved >= R300_VS_MAX_FC_OPS) {
575 rc_error(&compiler->Base,
576 "Too many flow control instructions.");
577 return;
578 }
579 if (compiler->Base.is_r500) {
580 compiler->code->fc_op_addrs.r500
581 [compiler->code->num_fc_ops].lw =
582 R500_PVS_FC_ACT_ADRS(act_addr)
583 | R500_PVS_FC_LOOP_CNT_JMP_INST(0xffff)
584 ;
585 compiler->code->fc_op_addrs.r500
586 [compiler->code->num_fc_ops].uw =
587 R500_PVS_FC_LAST_INST(last_addr)
588 | R500_PVS_FC_RTN_INST(ret_addr)
589 ;
590 } else {
591 compiler->code->fc_op_addrs.r300
592 [compiler->code->num_fc_ops] =
593 R300_PVS_FC_ACT_ADRS(act_addr)
594 | R300_PVS_FC_LOOP_CNT_JMP_INST(0xff)
595 | R300_PVS_FC_LAST_INST(last_addr)
596 | R300_PVS_FC_RTN_INST(ret_addr)
597 ;
598 }
599 compiler->code->fc_loop_index[compiler->code->num_fc_ops] =
600 R300_PVS_FC_LOOP_INIT_VAL(0x0)
601 | R300_PVS_FC_LOOP_STEP_VAL(0x1)
602 ;
603 compiler->code->fc_ops |= R300_VAP_PVS_FC_OPC_LOOP(
604 compiler->code->num_fc_ops);
605 compiler->code->num_fc_ops++;
606 current_loop_depth--;
607 continue;
608 }
609
610 default:
611 rc_error(&compiler->Base, "Unknown opcode %s\n", rc_get_opcode_info(vpi->Opcode)->Name);
612 return;
613 }
614
615 /* Non-flow control instructions that are inside an if statement
616 * need to pay attention to the predicate bit. */
617 if (branch_depth
618 && vpi->Opcode != RC_OPCODE_IF
619 && vpi->Opcode != RC_OPCODE_ELSE
620 && vpi->Opcode != RC_OPCODE_ENDIF) {
621
622 inst[0] |= (PVS_DST_PRED_ENABLE_MASK
623 << PVS_DST_PRED_ENABLE_SHIFT);
624 inst[0] |= (PVS_DST_PRED_SENSE_MASK
625 << PVS_DST_PRED_SENSE_SHIFT);
626 }
627
628 compiler->code->length += 4;
629
630 if (compiler->Base.Error)
631 return;
632 }
633 }
634
635 struct temporary_allocation {
636 unsigned int Allocated:1;
637 unsigned int HwTemp:15;
638 struct rc_instruction * LastRead;
639 };
640
641 static void allocate_temporary_registers(struct radeon_compiler *c, void *user)
642 {
643 struct r300_vertex_program_compiler *compiler = (struct r300_vertex_program_compiler*)c;
644 struct rc_instruction *inst;
645 struct rc_instruction *end_loop = NULL;
646 unsigned int num_orig_temps = 0;
647 char hwtemps[R300_VS_MAX_TEMPS];
648 struct temporary_allocation * ta;
649 unsigned int i, j;
650
651 memset(hwtemps, 0, sizeof(hwtemps));
652
653 /* Pass 1: Count original temporaries. */
654 for(inst = compiler->Base.Program.Instructions.Next; inst != &compiler->Base.Program.Instructions; inst = inst->Next) {
655 const struct rc_opcode_info * opcode = rc_get_opcode_info(inst->U.I.Opcode);
656
657 for (i = 0; i < opcode->NumSrcRegs; ++i) {
658 if (inst->U.I.SrcReg[i].File == RC_FILE_TEMPORARY) {
659 if (inst->U.I.SrcReg[i].Index >= num_orig_temps)
660 num_orig_temps = inst->U.I.SrcReg[i].Index + 1;
661 }
662 }
663
664 if (opcode->HasDstReg) {
665 if (inst->U.I.DstReg.File == RC_FILE_TEMPORARY) {
666 if (inst->U.I.DstReg.Index >= num_orig_temps)
667 num_orig_temps = inst->U.I.DstReg.Index + 1;
668 }
669 }
670 }
671 compiler->code->num_temporaries = num_orig_temps;
672
673 /* Pass 2: If there is relative addressing of temporaries, we cannot change register indices. Give up. */
674 for (inst = compiler->Base.Program.Instructions.Next; inst != &compiler->Base.Program.Instructions; inst = inst->Next) {
675 const struct rc_opcode_info *opcode = rc_get_opcode_info(inst->U.I.Opcode);
676
677 if (opcode->HasDstReg)
678 if (inst->U.I.DstReg.RelAddr)
679 return;
680
681 for (i = 0; i < opcode->NumSrcRegs; ++i) {
682 if (inst->U.I.SrcReg[i].File == RC_FILE_TEMPORARY &&
683 inst->U.I.SrcReg[i].RelAddr) {
684 return;
685 }
686 }
687 }
688
689 compiler->code->num_temporaries = 0;
690 ta = (struct temporary_allocation*)memory_pool_malloc(&compiler->Base.Pool,
691 sizeof(struct temporary_allocation) * num_orig_temps);
692 memset(ta, 0, sizeof(struct temporary_allocation) * num_orig_temps);
693
694 /* Pass 3: Determine original temporary lifetimes */
695 for(inst = compiler->Base.Program.Instructions.Next; inst != &compiler->Base.Program.Instructions; inst = inst->Next) {
696 const struct rc_opcode_info * opcode = rc_get_opcode_info(inst->U.I.Opcode);
697 /* Instructions inside of loops need to use the ENDLOOP
698 * instruction as their LastRead. */
699 if (!end_loop && inst->U.I.Opcode == RC_OPCODE_BGNLOOP) {
700 int endloops = 1;
701 struct rc_instruction * ptr;
702 for(ptr = inst->Next;
703 ptr != &compiler->Base.Program.Instructions;
704 ptr = ptr->Next){
705 if (ptr->U.I.Opcode == RC_OPCODE_BGNLOOP) {
706 endloops++;
707 } else if (ptr->U.I.Opcode == RC_OPCODE_ENDLOOP) {
708 endloops--;
709 if (endloops <= 0) {
710 end_loop = ptr;
711 break;
712 }
713 }
714 }
715 }
716
717 if (inst == end_loop) {
718 end_loop = NULL;
719 continue;
720 }
721
722 for (i = 0; i < opcode->NumSrcRegs; ++i) {
723 if (inst->U.I.SrcReg[i].File == RC_FILE_TEMPORARY)
724 ta[inst->U.I.SrcReg[i].Index].LastRead =
725 end_loop ? end_loop : inst;
726 }
727 }
728
729 /* Pass 4: Register allocation */
730 for(inst = compiler->Base.Program.Instructions.Next; inst != &compiler->Base.Program.Instructions; inst = inst->Next) {
731 const struct rc_opcode_info * opcode = rc_get_opcode_info(inst->U.I.Opcode);
732
733 for (i = 0; i < opcode->NumSrcRegs; ++i) {
734 if (inst->U.I.SrcReg[i].File == RC_FILE_TEMPORARY) {
735 unsigned int orig = inst->U.I.SrcReg[i].Index;
736 inst->U.I.SrcReg[i].Index = ta[orig].HwTemp;
737
738 if (ta[orig].Allocated && inst == ta[orig].LastRead)
739 hwtemps[ta[orig].HwTemp] = 0;
740 }
741 }
742
743 if (opcode->HasDstReg) {
744 if (inst->U.I.DstReg.File == RC_FILE_TEMPORARY) {
745 unsigned int orig = inst->U.I.DstReg.Index;
746
747 if (!ta[orig].Allocated) {
748 for(j = 0; j < R300_VS_MAX_TEMPS; ++j) {
749 if (!hwtemps[j])
750 break;
751 }
752 if (j >= R300_VS_MAX_TEMPS) {
753 fprintf(stderr, "Out of hw temporaries\n");
754 } else {
755 ta[orig].Allocated = 1;
756 ta[orig].HwTemp = j;
757 hwtemps[j] = 1;
758
759 if (j >= compiler->code->num_temporaries)
760 compiler->code->num_temporaries = j + 1;
761 }
762 }
763
764 inst->U.I.DstReg.Index = ta[orig].HwTemp;
765 }
766 }
767 }
768 }
769
770 /**
771 * R3xx-R4xx vertex engine does not support the Absolute source operand modifier
772 * and the Saturate opcode modifier. Only Absolute is currently transformed.
773 */
774 static int transform_nonnative_modifiers(
775 struct radeon_compiler *c,
776 struct rc_instruction *inst,
777 void* unused)
778 {
779 const struct rc_opcode_info *opcode = rc_get_opcode_info(inst->U.I.Opcode);
780 unsigned i;
781
782 /* Transform ABS(a) to MAX(a, -a). */
783 for (i = 0; i < opcode->NumSrcRegs; i++) {
784 if (inst->U.I.SrcReg[i].Abs) {
785 struct rc_instruction *new_inst;
786 unsigned temp;
787
788 inst->U.I.SrcReg[i].Abs = 0;
789
790 temp = rc_find_free_temporary(c);
791
792 new_inst = rc_insert_new_instruction(c, inst->Prev);
793 new_inst->U.I.Opcode = RC_OPCODE_MAX;
794 new_inst->U.I.DstReg.File = RC_FILE_TEMPORARY;
795 new_inst->U.I.DstReg.Index = temp;
796 new_inst->U.I.SrcReg[0] = inst->U.I.SrcReg[i];
797 new_inst->U.I.SrcReg[1] = inst->U.I.SrcReg[i];
798 new_inst->U.I.SrcReg[1].Negate ^= RC_MASK_XYZW;
799
800 memset(&inst->U.I.SrcReg[i], 0, sizeof(inst->U.I.SrcReg[i]));
801 inst->U.I.SrcReg[i].File = RC_FILE_TEMPORARY;
802 inst->U.I.SrcReg[i].Index = temp;
803 inst->U.I.SrcReg[i].Swizzle = RC_SWIZZLE_XYZW;
804 }
805 }
806 return 1;
807 }
808
809 /**
810 * Vertex engine cannot read two inputs or two constants at the same time.
811 * Introduce intermediate MOVs to temporary registers to account for this.
812 */
813 static int transform_source_conflicts(
814 struct radeon_compiler *c,
815 struct rc_instruction* inst,
816 void* unused)
817 {
818 const struct rc_opcode_info * opcode = rc_get_opcode_info(inst->U.I.Opcode);
819
820 if (opcode->NumSrcRegs == 3) {
821 if (t_src_conflict(inst->U.I.SrcReg[1], inst->U.I.SrcReg[2])
822 || t_src_conflict(inst->U.I.SrcReg[0], inst->U.I.SrcReg[2])) {
823 int tmpreg = rc_find_free_temporary(c);
824 struct rc_instruction * inst_mov = rc_insert_new_instruction(c, inst->Prev);
825 inst_mov->U.I.Opcode = RC_OPCODE_MOV;
826 inst_mov->U.I.DstReg.File = RC_FILE_TEMPORARY;
827 inst_mov->U.I.DstReg.Index = tmpreg;
828 inst_mov->U.I.SrcReg[0] = inst->U.I.SrcReg[2];
829
830 reset_srcreg(&inst->U.I.SrcReg[2]);
831 inst->U.I.SrcReg[2].File = RC_FILE_TEMPORARY;
832 inst->U.I.SrcReg[2].Index = tmpreg;
833 }
834 }
835
836 if (opcode->NumSrcRegs >= 2) {
837 if (t_src_conflict(inst->U.I.SrcReg[1], inst->U.I.SrcReg[0])) {
838 int tmpreg = rc_find_free_temporary(c);
839 struct rc_instruction * inst_mov = rc_insert_new_instruction(c, inst->Prev);
840 inst_mov->U.I.Opcode = RC_OPCODE_MOV;
841 inst_mov->U.I.DstReg.File = RC_FILE_TEMPORARY;
842 inst_mov->U.I.DstReg.Index = tmpreg;
843 inst_mov->U.I.SrcReg[0] = inst->U.I.SrcReg[1];
844
845 reset_srcreg(&inst->U.I.SrcReg[1]);
846 inst->U.I.SrcReg[1].File = RC_FILE_TEMPORARY;
847 inst->U.I.SrcReg[1].Index = tmpreg;
848 }
849 }
850
851 return 1;
852 }
853
854 static void rc_vs_add_artificial_outputs(struct radeon_compiler *c, void *user)
855 {
856 struct r300_vertex_program_compiler * compiler = (struct r300_vertex_program_compiler*)c;
857 int i;
858
859 for(i = 0; i < 32; ++i) {
860 if ((compiler->RequiredOutputs & (1 << i)) &&
861 !(compiler->Base.Program.OutputsWritten & (1 << i))) {
862 struct rc_instruction * inst = rc_insert_new_instruction(&compiler->Base, compiler->Base.Program.Instructions.Prev);
863 inst->U.I.Opcode = RC_OPCODE_MOV;
864
865 inst->U.I.DstReg.File = RC_FILE_OUTPUT;
866 inst->U.I.DstReg.Index = i;
867 inst->U.I.DstReg.WriteMask = RC_MASK_XYZW;
868
869 inst->U.I.SrcReg[0].File = RC_FILE_CONSTANT;
870 inst->U.I.SrcReg[0].Index = 0;
871 inst->U.I.SrcReg[0].Swizzle = RC_SWIZZLE_XYZW;
872
873 compiler->Base.Program.OutputsWritten |= 1 << i;
874 }
875 }
876 }
877
878 static void dataflow_outputs_mark_used(void * userdata, void * data,
879 void (*callback)(void *, unsigned int, unsigned int))
880 {
881 struct r300_vertex_program_compiler * c = userdata;
882 int i;
883
884 for(i = 0; i < 32; ++i) {
885 if (c->RequiredOutputs & (1 << i))
886 callback(data, i, RC_MASK_XYZW);
887 }
888 }
889
890 static int swizzle_is_native(rc_opcode opcode, struct rc_src_register reg)
891 {
892 (void) opcode;
893 (void) reg;
894
895 return 1;
896 }
897
898 static void transform_negative_addressing(struct r300_vertex_program_compiler *c,
899 struct rc_instruction *arl,
900 struct rc_instruction *end,
901 int min_offset)
902 {
903 struct rc_instruction *inst, *add;
904 unsigned const_swizzle;
905
906 /* Transform ARL */
907 add = rc_insert_new_instruction(&c->Base, arl->Prev);
908 add->U.I.Opcode = RC_OPCODE_ADD;
909 add->U.I.DstReg.File = RC_FILE_TEMPORARY;
910 add->U.I.DstReg.Index = rc_find_free_temporary(&c->Base);
911 add->U.I.DstReg.WriteMask = RC_MASK_X;
912 add->U.I.SrcReg[0] = arl->U.I.SrcReg[0];
913 add->U.I.SrcReg[1].File = RC_FILE_CONSTANT;
914 add->U.I.SrcReg[1].Index = rc_constants_add_immediate_scalar(&c->Base.Program.Constants,
915 min_offset, &const_swizzle);
916 add->U.I.SrcReg[1].Swizzle = const_swizzle;
917
918 arl->U.I.SrcReg[0].File = RC_FILE_TEMPORARY;
919 arl->U.I.SrcReg[0].Index = add->U.I.DstReg.Index;
920 arl->U.I.SrcReg[0].Swizzle = RC_SWIZZLE_XXXX;
921
922 /* Rewrite offsets up to and excluding inst. */
923 for (inst = arl->Next; inst != end; inst = inst->Next) {
924 const struct rc_opcode_info * opcode = rc_get_opcode_info(inst->U.I.Opcode);
925
926 for (unsigned i = 0; i < opcode->NumSrcRegs; i++)
927 if (inst->U.I.SrcReg[i].RelAddr)
928 inst->U.I.SrcReg[i].Index -= min_offset;
929 }
930 }
931
932 static void rc_emulate_negative_addressing(struct radeon_compiler *compiler, void *user)
933 {
934 struct r300_vertex_program_compiler * c = (struct r300_vertex_program_compiler*)compiler;
935 struct rc_instruction *inst, *lastARL = NULL;
936 int min_offset = 0;
937
938 for (inst = c->Base.Program.Instructions.Next; inst != &c->Base.Program.Instructions; inst = inst->Next) {
939 const struct rc_opcode_info * opcode = rc_get_opcode_info(inst->U.I.Opcode);
940
941 if (inst->U.I.Opcode == RC_OPCODE_ARL) {
942 if (lastARL != NULL && min_offset < 0)
943 transform_negative_addressing(c, lastARL, inst, min_offset);
944
945 lastARL = inst;
946 min_offset = 0;
947 continue;
948 }
949
950 for (unsigned i = 0; i < opcode->NumSrcRegs; i++) {
951 if (inst->U.I.SrcReg[i].RelAddr &&
952 inst->U.I.SrcReg[i].Index < 0) {
953 /* ARL must precede any indirect addressing. */
954 if (lastARL == NULL) {
955 rc_error(&c->Base, "Vertex shader: Found relative addressing without ARL.");
956 return;
957 }
958
959 if (inst->U.I.SrcReg[i].Index < min_offset)
960 min_offset = inst->U.I.SrcReg[i].Index;
961 }
962 }
963 }
964
965 if (lastARL != NULL && min_offset < 0)
966 transform_negative_addressing(c, lastARL, inst, min_offset);
967 }
968
969 static struct rc_swizzle_caps r300_vertprog_swizzle_caps = {
970 .IsNative = &swizzle_is_native,
971 .Split = 0 /* should never be called */
972 };
973
974 void r3xx_compile_vertex_program(struct r300_vertex_program_compiler *c)
975 {
976 int is_r500 = c->Base.is_r500;
977 int kill_consts = c->Base.remove_unused_constants;
978
979 /* Lists of instruction transformations. */
980 struct radeon_program_transformation alu_rewrite_r500[] = {
981 { &r300_transform_vertex_alu, 0 },
982 { &r300_transform_trig_scale_vertex, 0 },
983 { 0, 0 }
984 };
985
986 struct radeon_program_transformation alu_rewrite_r300[] = {
987 { &r300_transform_vertex_alu, 0 },
988 { &r300_transform_trig_simple, 0 },
989 { 0, 0 }
990 };
991
992 /* Note: These passes have to be done seperately from ALU rewrite,
993 * otherwise non-native ALU instructions with source conflits
994 * or non-native modifiers will not be treated properly.
995 */
996 struct radeon_program_transformation emulate_modifiers[] = {
997 { &transform_nonnative_modifiers, 0 },
998 { 0, 0 }
999 };
1000
1001 struct radeon_program_transformation resolve_src_conflicts[] = {
1002 { &transform_source_conflicts, 0 },
1003 { 0, 0 }
1004 };
1005
1006 /* List of compiler passes. */
1007 struct radeon_compiler_pass vs_list[] = {
1008 /* NAME DUMP PREDICATE FUNCTION PARAM */
1009 {"add artificial outputs", 0, 1, rc_vs_add_artificial_outputs, NULL},
1010 {"transform loops", 1, 1, rc_transform_loops, NULL},
1011 {"emulate branches", 1, !is_r500, rc_emulate_branches, NULL},
1012 {"emulate negative addressing", 1, 1, rc_emulate_negative_addressing, NULL},
1013 {"native rewrite", 1, is_r500, rc_local_transform, alu_rewrite_r500},
1014 {"native rewrite", 1, !is_r500, rc_local_transform, alu_rewrite_r300},
1015 {"emulate modifiers", 1, !is_r500, rc_local_transform, emulate_modifiers},
1016 {"deadcode", 1, 1, rc_dataflow_deadcode, dataflow_outputs_mark_used},
1017 {"dataflow optimize", 1, 1, rc_optimize, NULL},
1018 /* This pass must be done after optimizations. */
1019 {"source conflict resolve", 1, 1, rc_local_transform, resolve_src_conflicts},
1020 {"dataflow swizzles", 1, 1, rc_dataflow_swizzles, NULL},
1021 {"register allocation", 1, 1, allocate_temporary_registers, NULL},
1022 {"dead constants", 1, kill_consts, rc_remove_unused_constants, &c->code->constants_remap_table},
1023 {"final code validation", 0, 1, rc_validate_final_shader, NULL},
1024 {"machine code generation", 0, 1, translate_vertex_program, NULL},
1025 {"dump machine code", 0,c->Base.Debug,r300_vertex_program_dump, NULL},
1026 {NULL, 0, 0, NULL, NULL}
1027 };
1028
1029 c->Base.SwizzleCaps = &r300_vertprog_swizzle_caps;
1030
1031 rc_run_compiler(&c->Base, vs_list, "Vertex Program");
1032
1033 c->code->InputsRead = c->Base.Program.InputsRead;
1034 c->code->OutputsWritten = c->Base.Program.OutputsWritten;
1035 rc_constants_copy(&c->code->constants, &c->Base.Program.Constants);
1036 }