2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
6 * Permission is hereby granted, free of charge, to any person obtaining
7 * a copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sublicense, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial
16 * portions of the Software.
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
28 #include "r500_fragprog.h"
30 #include "../r300_reg.h"
32 static struct prog_src_register
shadow_ambient(struct gl_program
*program
, int tmu
)
34 gl_state_index fail_value_tokens
[STATE_LENGTH
] = {
35 STATE_INTERNAL
, STATE_SHADOW_AMBIENT
, 0, 0, 0
37 struct prog_src_register reg
= { 0, };
39 fail_value_tokens
[2] = tmu
;
40 reg
.File
= PROGRAM_STATE_VAR
;
41 reg
.Index
= _mesa_add_state_reference(program
->Parameters
, fail_value_tokens
);
42 reg
.Swizzle
= SWIZZLE_WWWW
;
47 * Transform TEX, TXP, TXB, and KIL instructions in the following way:
48 * - premultiply texture coordinates for RECT
49 * - extract operand swizzles
50 * - introduce a temporary register when write masks are needed
53 GLboolean
r500_transform_TEX(
54 struct radeon_transform_context
*t
,
55 struct prog_instruction
* orig_inst
, void* data
)
57 struct r300_fragment_program_compiler
*compiler
=
58 (struct r300_fragment_program_compiler
*)data
;
59 struct prog_instruction inst
= *orig_inst
;
60 struct prog_instruction
* tgt
;
61 GLboolean destredirect
= GL_FALSE
;
63 if (inst
.Opcode
!= OPCODE_TEX
&&
64 inst
.Opcode
!= OPCODE_TXB
&&
65 inst
.Opcode
!= OPCODE_TXP
&&
66 inst
.Opcode
!= OPCODE_KIL
)
69 /* ARB_shadow & EXT_shadow_funcs */
70 if (inst
.Opcode
!= OPCODE_KIL
&&
71 t
->Program
->ShadowSamplers
& (1 << inst
.TexSrcUnit
)) {
72 GLuint comparefunc
= GL_NEVER
+ compiler
->state
.unit
[inst
.TexSrcUnit
].texture_compare_func
;
74 if (comparefunc
== GL_NEVER
|| comparefunc
== GL_ALWAYS
) {
75 tgt
= radeonAppendInstructions(t
->Program
, 1);
77 tgt
->Opcode
= OPCODE_MOV
;
78 tgt
->DstReg
= inst
.DstReg
;
79 if (comparefunc
== GL_ALWAYS
) {
80 tgt
->SrcReg
[0].File
= PROGRAM_BUILTIN
;
81 tgt
->SrcReg
[0].Swizzle
= SWIZZLE_1111
;
83 tgt
->SrcReg
[0] = shadow_ambient(t
->Program
, inst
.TexSrcUnit
);
88 inst
.DstReg
.File
= PROGRAM_TEMPORARY
;
89 inst
.DstReg
.Index
= radeonFindFreeTemporary(t
);
90 inst
.DstReg
.WriteMask
= WRITEMASK_XYZW
;
91 } else if (inst
.Opcode
!= OPCODE_KIL
&& inst
.DstReg
.File
!= PROGRAM_TEMPORARY
) {
92 int tempreg
= radeonFindFreeTemporary(t
);
94 inst
.DstReg
.File
= PROGRAM_TEMPORARY
;
95 inst
.DstReg
.Index
= tempreg
;
96 inst
.DstReg
.WriteMask
= WRITEMASK_XYZW
;
97 destredirect
= GL_TRUE
;
100 if (inst
.SrcReg
[0].File
!= PROGRAM_TEMPORARY
&& inst
.SrcReg
[0].File
!= PROGRAM_INPUT
) {
101 int tmpreg
= radeonFindFreeTemporary(t
);
102 tgt
= radeonAppendInstructions(t
->Program
, 1);
103 tgt
->Opcode
= OPCODE_MOV
;
104 tgt
->DstReg
.File
= PROGRAM_TEMPORARY
;
105 tgt
->DstReg
.Index
= tmpreg
;
106 tgt
->SrcReg
[0] = inst
.SrcReg
[0];
108 reset_srcreg(&inst
.SrcReg
[0]);
109 inst
.SrcReg
[0].File
= PROGRAM_TEMPORARY
;
110 inst
.SrcReg
[0].Index
= tmpreg
;
113 tgt
= radeonAppendInstructions(t
->Program
, 1);
114 _mesa_copy_instructions(tgt
, &inst
, 1);
116 if (inst
.Opcode
!= OPCODE_KIL
&&
117 t
->Program
->ShadowSamplers
& (1 << inst
.TexSrcUnit
)) {
118 GLuint comparefunc
= GL_NEVER
+ compiler
->state
.unit
[inst
.TexSrcUnit
].texture_compare_func
;
119 GLuint depthmode
= compiler
->state
.unit
[inst
.TexSrcUnit
].depth_texture_mode
;
120 int rcptemp
= radeonFindFreeTemporary(t
);
123 tgt
= radeonAppendInstructions(t
->Program
, 3);
125 tgt
[0].Opcode
= OPCODE_RCP
;
126 tgt
[0].DstReg
.File
= PROGRAM_TEMPORARY
;
127 tgt
[0].DstReg
.Index
= rcptemp
;
128 tgt
[0].DstReg
.WriteMask
= WRITEMASK_W
;
129 tgt
[0].SrcReg
[0] = inst
.SrcReg
[0];
130 tgt
[0].SrcReg
[0].Swizzle
= SWIZZLE_WWWW
;
132 tgt
[1].Opcode
= OPCODE_MAD
;
133 tgt
[1].DstReg
= inst
.DstReg
;
134 tgt
[1].DstReg
.WriteMask
= orig_inst
->DstReg
.WriteMask
;
135 tgt
[1].SrcReg
[0] = inst
.SrcReg
[0];
136 tgt
[1].SrcReg
[0].Swizzle
= SWIZZLE_ZZZZ
;
137 tgt
[1].SrcReg
[1].File
= PROGRAM_TEMPORARY
;
138 tgt
[1].SrcReg
[1].Index
= rcptemp
;
139 tgt
[1].SrcReg
[1].Swizzle
= SWIZZLE_WWWW
;
140 tgt
[1].SrcReg
[2].File
= PROGRAM_TEMPORARY
;
141 tgt
[1].SrcReg
[2].Index
= inst
.DstReg
.Index
;
142 if (depthmode
== 0) /* GL_LUMINANCE */
143 tgt
[1].SrcReg
[2].Swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_Z
);
144 else if (depthmode
== 2) /* GL_ALPHA */
145 tgt
[1].SrcReg
[2].Swizzle
= SWIZZLE_WWWW
;
147 /* Recall that SrcReg[0] is tex, SrcReg[2] is r and:
148 * r < tex <=> -tex+r < 0
149 * r >= tex <=> not (-tex+r < 0 */
150 if (comparefunc
== GL_LESS
|| comparefunc
== GL_GEQUAL
)
151 tgt
[1].SrcReg
[2].Negate
= tgt
[0].SrcReg
[2].Negate
^ NEGATE_XYZW
;
153 tgt
[1].SrcReg
[0].Negate
= tgt
[0].SrcReg
[0].Negate
^ NEGATE_XYZW
;
155 tgt
[2].Opcode
= OPCODE_CMP
;
156 tgt
[2].DstReg
= orig_inst
->DstReg
;
157 tgt
[2].SrcReg
[0].File
= PROGRAM_TEMPORARY
;
158 tgt
[2].SrcReg
[0].Index
= tgt
[1].DstReg
.Index
;
160 if (comparefunc
== GL_LESS
|| comparefunc
== GL_GREATER
) {
168 tgt
[2].SrcReg
[pass
].File
= PROGRAM_BUILTIN
;
169 tgt
[2].SrcReg
[pass
].Swizzle
= SWIZZLE_1111
;
170 tgt
[2].SrcReg
[fail
] = shadow_ambient(t
->Program
, inst
.TexSrcUnit
);
171 } else if (destredirect
) {
172 tgt
= radeonAppendInstructions(t
->Program
, 1);
174 tgt
->Opcode
= OPCODE_MOV
;
175 tgt
->DstReg
= orig_inst
->DstReg
;
176 tgt
->SrcReg
[0].File
= PROGRAM_TEMPORARY
;
177 tgt
->SrcReg
[0].Index
= inst
.DstReg
.Index
;
183 GLboolean
r500FPIsNativeSwizzle(GLuint opcode
, struct prog_src_register reg
)
188 if (opcode
== OPCODE_TEX
||
189 opcode
== OPCODE_TXB
||
190 opcode
== OPCODE_TXP
||
191 opcode
== OPCODE_KIL
) {
195 if (opcode
== OPCODE_KIL
&& (reg
.Swizzle
!= SWIZZLE_NOOP
|| reg
.Negate
!= NEGATE_NONE
))
199 reg
.Negate
^= NEGATE_XYZW
;
201 for(i
= 0; i
< 4; ++i
) {
202 GLuint swz
= GET_SWZ(reg
.Swizzle
, i
);
203 if (swz
== SWIZZLE_NIL
) {
204 reg
.Negate
&= ~(1 << i
);
215 } else if (opcode
== OPCODE_DDX
|| opcode
== OPCODE_DDY
) {
216 /* DDX/MDH and DDY/MDV explicitly ignore incoming swizzles;
217 * if it doesn't fit perfectly into a .xyzw case... */
218 if (reg
.Swizzle
== SWIZZLE_NOOP
&& !reg
.Abs
&& !reg
.Negate
)
223 /* ALU instructions support almost everything */
228 for(i
= 0; i
< 3; ++i
) {
229 GLuint swz
= GET_SWZ(reg
.Swizzle
, i
);
230 if (swz
!= SWIZZLE_NIL
&& swz
!= SWIZZLE_ZERO
)
233 if ((reg
.Negate
& relevant
) && ((reg
.Negate
& relevant
) != relevant
))
241 * Implement a MOV with a potentially non-native swizzle.
243 * The only thing we *cannot* do in an ALU instruction is per-component
244 * negation. Therefore, we split the MOV into two instructions when necessary.
246 void r500FPBuildSwizzle(struct nqssadce_state
*s
, struct prog_dst_register dst
, struct prog_src_register src
)
248 struct prog_instruction
*inst
;
249 GLuint negatebase
[2] = { 0, 0 };
252 for(i
= 0; i
< 4; ++i
) {
253 GLuint swz
= GET_SWZ(src
.Swizzle
, i
);
254 if (swz
== SWIZZLE_NIL
)
256 negatebase
[GET_BIT(src
.Negate
, i
)] |= 1 << i
;
259 _mesa_insert_instructions(s
->Program
, s
->IP
, (negatebase
[0] ? 1 : 0) + (negatebase
[1] ? 1 : 0));
260 inst
= s
->Program
->Instructions
+ s
->IP
;
262 for(i
= 0; i
<= 1; ++i
) {
266 inst
->Opcode
= OPCODE_MOV
;
268 inst
->DstReg
.WriteMask
= negatebase
[i
];
269 inst
->SrcReg
[0] = src
;
270 inst
->SrcReg
[0].Negate
= (i
== 0) ? NEGATE_NONE
: NEGATE_XYZW
;
277 static char *toswiz(int swiz_val
) {
284 case 5: return "1/2";
291 static char *toop(int op_val
)
295 case 0: str
= "MAD"; break;
296 case 1: str
= "DP3"; break;
297 case 2: str
= "DP4"; break;
298 case 3: str
= "D2A"; break;
299 case 4: str
= "MIN"; break;
300 case 5: str
= "MAX"; break;
301 case 6: str
= "Reserved"; break;
302 case 7: str
= "CND"; break;
303 case 8: str
= "CMP"; break;
304 case 9: str
= "FRC"; break;
305 case 10: str
= "SOP"; break;
306 case 11: str
= "MDH"; break;
307 case 12: str
= "MDV"; break;
312 static char *to_alpha_op(int op_val
)
316 case 0: str
= "MAD"; break;
317 case 1: str
= "DP"; break;
318 case 2: str
= "MIN"; break;
319 case 3: str
= "MAX"; break;
320 case 4: str
= "Reserved"; break;
321 case 5: str
= "CND"; break;
322 case 6: str
= "CMP"; break;
323 case 7: str
= "FRC"; break;
324 case 8: str
= "EX2"; break;
325 case 9: str
= "LN2"; break;
326 case 10: str
= "RCP"; break;
327 case 11: str
= "RSQ"; break;
328 case 12: str
= "SIN"; break;
329 case 13: str
= "COS"; break;
330 case 14: str
= "MDH"; break;
331 case 15: str
= "MDV"; break;
336 static char *to_mask(int val
)
340 case 0: str
= "NONE"; break;
341 case 1: str
= "R"; break;
342 case 2: str
= "G"; break;
343 case 3: str
= "RG"; break;
344 case 4: str
= "B"; break;
345 case 5: str
= "RB"; break;
346 case 6: str
= "GB"; break;
347 case 7: str
= "RGB"; break;
348 case 8: str
= "A"; break;
349 case 9: str
= "AR"; break;
350 case 10: str
= "AG"; break;
351 case 11: str
= "ARG"; break;
352 case 12: str
= "AB"; break;
353 case 13: str
= "ARB"; break;
354 case 14: str
= "AGB"; break;
355 case 15: str
= "ARGB"; break;
360 static char *to_texop(int val
)
363 case 0: return "NOP";
365 case 2: return "TEXKILL";
366 case 3: return "PROJ";
367 case 4: return "LODBIAS";
368 case 5: return "LOD";
369 case 6: return "DXDY";
374 void r500FragmentProgramDump(struct rX00_fragment_program_code
*c
)
376 struct r500_fragment_program_code
*code
= &c
->code
.r500
;
377 fprintf(stderr
, "R500 Fragment Program:\n--------\n");
384 if (code
->const_nr
) {
385 fprintf(stderr
, "--------\nConstants:\n");
386 for (n
= 0; n
< code
->const_nr
; n
++) {
387 fprintf(stderr
, "Constant %d: %i[%i]\n", n
,
388 code
->constant
[n
].File
, code
->constant
[n
].Index
);
390 fprintf(stderr
, "--------\n");
393 for (n
= 0; n
< code
->inst_end
+1; n
++) {
394 inst0
= inst
= code
->inst
[n
].inst0
;
395 fprintf(stderr
,"%d\t0:CMN_INST 0x%08x:", n
, inst
);
397 case R500_INST_TYPE_ALU
: str
= "ALU"; break;
398 case R500_INST_TYPE_OUT
: str
= "OUT"; break;
399 case R500_INST_TYPE_FC
: str
= "FC"; break;
400 case R500_INST_TYPE_TEX
: str
= "TEX"; break;
402 fprintf(stderr
,"%s %s %s %s %s ", str
,
403 inst
& R500_INST_TEX_SEM_WAIT
? "TEX_WAIT" : "",
404 inst
& R500_INST_LAST
? "LAST" : "",
405 inst
& R500_INST_NOP
? "NOP" : "",
406 inst
& R500_INST_ALU_WAIT
? "ALU WAIT" : "");
407 fprintf(stderr
,"wmask: %s omask: %s\n", to_mask((inst
>> 11) & 0xf),
408 to_mask((inst
>> 15) & 0xf));
410 switch(inst0
& 0x3) {
413 fprintf(stderr
,"\t1:RGB_ADDR 0x%08x:", code
->inst
[n
].inst1
);
414 inst
= code
->inst
[n
].inst1
;
416 fprintf(stderr
,"Addr0: %d%c, Addr1: %d%c, Addr2: %d%c, srcp:%d\n",
417 inst
& 0xff, (inst
& (1<<8)) ? 'c' : 't',
418 (inst
>> 10) & 0xff, (inst
& (1<<18)) ? 'c' : 't',
419 (inst
>> 20) & 0xff, (inst
& (1<<28)) ? 'c' : 't',
422 fprintf(stderr
,"\t2:ALPHA_ADDR 0x%08x:", code
->inst
[n
].inst2
);
423 inst
= code
->inst
[n
].inst2
;
424 fprintf(stderr
,"Addr0: %d%c, Addr1: %d%c, Addr2: %d%c, srcp:%d\n",
425 inst
& 0xff, (inst
& (1<<8)) ? 'c' : 't',
426 (inst
>> 10) & 0xff, (inst
& (1<<18)) ? 'c' : 't',
427 (inst
>> 20) & 0xff, (inst
& (1<<28)) ? 'c' : 't',
429 fprintf(stderr
,"\t3 RGB_INST: 0x%08x:", code
->inst
[n
].inst3
);
430 inst
= code
->inst
[n
].inst3
;
431 fprintf(stderr
,"rgb_A_src:%d %s/%s/%s %d rgb_B_src:%d %s/%s/%s %d\n",
432 (inst
) & 0x3, toswiz((inst
>> 2) & 0x7), toswiz((inst
>> 5) & 0x7), toswiz((inst
>> 8) & 0x7),
434 (inst
>> 13) & 0x3, toswiz((inst
>> 15) & 0x7), toswiz((inst
>> 18) & 0x7), toswiz((inst
>> 21) & 0x7),
438 fprintf(stderr
,"\t4 ALPHA_INST:0x%08x:", code
->inst
[n
].inst4
);
439 inst
= code
->inst
[n
].inst4
;
440 fprintf(stderr
,"%s dest:%d%s alp_A_src:%d %s %d alp_B_src:%d %s %d w:%d\n", to_alpha_op(inst
& 0xf),
441 (inst
>> 4) & 0x7f, inst
& (1<<11) ? "(rel)":"",
442 (inst
>> 12) & 0x3, toswiz((inst
>> 14) & 0x7), (inst
>> 17) & 0x3,
443 (inst
>> 19) & 0x3, toswiz((inst
>> 21) & 0x7), (inst
>> 24) & 0x3,
446 fprintf(stderr
,"\t5 RGBA_INST: 0x%08x:", code
->inst
[n
].inst5
);
447 inst
= code
->inst
[n
].inst5
;
448 fprintf(stderr
,"%s dest:%d%s rgb_C_src:%d %s/%s/%s %d alp_C_src:%d %s %d\n", toop(inst
& 0xf),
449 (inst
>> 4) & 0x7f, inst
& (1<<11) ? "(rel)":"",
450 (inst
>> 12) & 0x3, toswiz((inst
>> 14) & 0x7), toswiz((inst
>> 17) & 0x7), toswiz((inst
>> 20) & 0x7),
452 (inst
>> 25) & 0x3, toswiz((inst
>> 27) & 0x7), (inst
>> 30) & 0x3);
457 inst
= code
->inst
[n
].inst1
;
458 fprintf(stderr
,"\t1:TEX_INST: 0x%08x: id: %d op:%s, %s, %s %s\n", inst
, (inst
>> 16) & 0xf,
459 to_texop((inst
>> 22) & 0x7), (inst
& (1<<25)) ? "ACQ" : "",
460 (inst
& (1<<26)) ? "IGNUNC" : "", (inst
& (1<<27)) ? "UNSCALED" : "SCALED");
461 inst
= code
->inst
[n
].inst2
;
462 fprintf(stderr
,"\t2:TEX_ADDR: 0x%08x: src: %d%s %s/%s/%s/%s dst: %d%s %s/%s/%s/%s\n", inst
,
463 inst
& 127, inst
& (1<<7) ? "(rel)" : "",
464 toswiz((inst
>> 8) & 0x3), toswiz((inst
>> 10) & 0x3),
465 toswiz((inst
>> 12) & 0x3), toswiz((inst
>> 14) & 0x3),
466 (inst
>> 16) & 127, inst
& (1<<23) ? "(rel)" : "",
467 toswiz((inst
>> 24) & 0x3), toswiz((inst
>> 26) & 0x3),
468 toswiz((inst
>> 28) & 0x3), toswiz((inst
>> 30) & 0x3));
470 fprintf(stderr
,"\t3:TEX_DXDY: 0x%08x\n", code
->inst
[n
].inst3
);
473 fprintf(stderr
,"\n");