fdc18caacb75fdc707ab669af2b7cad5da8f6ba5
[mesa.git] / src / mesa / drivers / dri / r300 / compiler / r500_fragprog.c
1 /*
2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
3 *
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining
7 * a copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sublicense, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial
16 * portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 */
27
28 #include "compiler/r500_fragprog.h"
29
30 #include "r300_reg.h"
31
32 static void reset_srcreg(struct prog_src_register* reg)
33 {
34 _mesa_bzero(reg, sizeof(*reg));
35 reg->Swizzle = SWIZZLE_NOOP;
36 }
37
38 static struct prog_src_register shadow_ambient(struct gl_program *program, int tmu)
39 {
40 gl_state_index fail_value_tokens[STATE_LENGTH] = {
41 STATE_INTERNAL, STATE_SHADOW_AMBIENT, 0, 0, 0
42 };
43 struct prog_src_register reg = { 0, };
44
45 fail_value_tokens[2] = tmu;
46 reg.File = PROGRAM_STATE_VAR;
47 reg.Index = _mesa_add_state_reference(program->Parameters, fail_value_tokens);
48 reg.Swizzle = SWIZZLE_WWWW;
49 return reg;
50 }
51
52 /**
53 * Transform TEX, TXP, TXB, and KIL instructions in the following way:
54 * - premultiply texture coordinates for RECT
55 * - extract operand swizzles
56 * - introduce a temporary register when write masks are needed
57 *
58 */
59 GLboolean r500_transform_TEX(
60 struct radeon_transform_context *t,
61 struct prog_instruction* orig_inst, void* data)
62 {
63 struct r300_fragment_program_compiler *compiler =
64 (struct r300_fragment_program_compiler*)data;
65 struct prog_instruction inst = *orig_inst;
66 struct prog_instruction* tgt;
67 GLboolean destredirect = GL_FALSE;
68
69 if (inst.Opcode != OPCODE_TEX &&
70 inst.Opcode != OPCODE_TXB &&
71 inst.Opcode != OPCODE_TXP &&
72 inst.Opcode != OPCODE_KIL)
73 return GL_FALSE;
74
75 /* ARB_shadow & EXT_shadow_funcs */
76 if (inst.Opcode != OPCODE_KIL &&
77 t->Program->ShadowSamplers & (1 << inst.TexSrcUnit)) {
78 GLuint comparefunc = GL_NEVER + compiler->state.unit[inst.TexSrcUnit].texture_compare_func;
79
80 if (comparefunc == GL_NEVER || comparefunc == GL_ALWAYS) {
81 tgt = radeonAppendInstructions(t->Program, 1);
82
83 tgt->Opcode = OPCODE_MOV;
84 tgt->DstReg = inst.DstReg;
85 if (comparefunc == GL_ALWAYS) {
86 tgt->SrcReg[0].File = PROGRAM_BUILTIN;
87 tgt->SrcReg[0].Swizzle = SWIZZLE_1111;
88 } else {
89 tgt->SrcReg[0] = shadow_ambient(t->Program, inst.TexSrcUnit);
90 }
91 return GL_TRUE;
92 }
93
94 inst.DstReg.File = PROGRAM_TEMPORARY;
95 inst.DstReg.Index = radeonFindFreeTemporary(t);
96 inst.DstReg.WriteMask = WRITEMASK_XYZW;
97 } else if (inst.Opcode != OPCODE_KIL && inst.DstReg.File != PROGRAM_TEMPORARY) {
98 int tempreg = radeonFindFreeTemporary(t);
99
100 inst.DstReg.File = PROGRAM_TEMPORARY;
101 inst.DstReg.Index = tempreg;
102 inst.DstReg.WriteMask = WRITEMASK_XYZW;
103 destredirect = GL_TRUE;
104 }
105
106 if (inst.SrcReg[0].File != PROGRAM_TEMPORARY && inst.SrcReg[0].File != PROGRAM_INPUT) {
107 int tmpreg = radeonFindFreeTemporary(t);
108 tgt = radeonAppendInstructions(t->Program, 1);
109 tgt->Opcode = OPCODE_MOV;
110 tgt->DstReg.File = PROGRAM_TEMPORARY;
111 tgt->DstReg.Index = tmpreg;
112 tgt->SrcReg[0] = inst.SrcReg[0];
113
114 reset_srcreg(&inst.SrcReg[0]);
115 inst.SrcReg[0].File = PROGRAM_TEMPORARY;
116 inst.SrcReg[0].Index = tmpreg;
117 }
118
119 tgt = radeonAppendInstructions(t->Program, 1);
120 _mesa_copy_instructions(tgt, &inst, 1);
121
122 if (inst.Opcode != OPCODE_KIL &&
123 t->Program->ShadowSamplers & (1 << inst.TexSrcUnit)) {
124 GLuint comparefunc = GL_NEVER + compiler->state.unit[inst.TexSrcUnit].texture_compare_func;
125 GLuint depthmode = compiler->state.unit[inst.TexSrcUnit].depth_texture_mode;
126 int rcptemp = radeonFindFreeTemporary(t);
127 int pass, fail;
128
129 tgt = radeonAppendInstructions(t->Program, 3);
130
131 tgt[0].Opcode = OPCODE_RCP;
132 tgt[0].DstReg.File = PROGRAM_TEMPORARY;
133 tgt[0].DstReg.Index = rcptemp;
134 tgt[0].DstReg.WriteMask = WRITEMASK_W;
135 tgt[0].SrcReg[0] = inst.SrcReg[0];
136 tgt[0].SrcReg[0].Swizzle = SWIZZLE_WWWW;
137
138 tgt[1].Opcode = OPCODE_MAD;
139 tgt[1].DstReg = inst.DstReg;
140 tgt[1].DstReg.WriteMask = orig_inst->DstReg.WriteMask;
141 tgt[1].SrcReg[0] = inst.SrcReg[0];
142 tgt[1].SrcReg[0].Swizzle = SWIZZLE_ZZZZ;
143 tgt[1].SrcReg[1].File = PROGRAM_TEMPORARY;
144 tgt[1].SrcReg[1].Index = rcptemp;
145 tgt[1].SrcReg[1].Swizzle = SWIZZLE_WWWW;
146 tgt[1].SrcReg[2].File = PROGRAM_TEMPORARY;
147 tgt[1].SrcReg[2].Index = inst.DstReg.Index;
148 if (depthmode == 0) /* GL_LUMINANCE */
149 tgt[1].SrcReg[2].Swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_Z);
150 else if (depthmode == 2) /* GL_ALPHA */
151 tgt[1].SrcReg[2].Swizzle = SWIZZLE_WWWW;
152
153 /* Recall that SrcReg[0] is tex, SrcReg[2] is r and:
154 * r < tex <=> -tex+r < 0
155 * r >= tex <=> not (-tex+r < 0 */
156 if (comparefunc == GL_LESS || comparefunc == GL_GEQUAL)
157 tgt[1].SrcReg[2].Negate = tgt[0].SrcReg[2].Negate ^ NEGATE_XYZW;
158 else
159 tgt[1].SrcReg[0].Negate = tgt[0].SrcReg[0].Negate ^ NEGATE_XYZW;
160
161 tgt[2].Opcode = OPCODE_CMP;
162 tgt[2].DstReg = orig_inst->DstReg;
163 tgt[2].SrcReg[0].File = PROGRAM_TEMPORARY;
164 tgt[2].SrcReg[0].Index = tgt[1].DstReg.Index;
165
166 if (comparefunc == GL_LESS || comparefunc == GL_GREATER) {
167 pass = 1;
168 fail = 2;
169 } else {
170 pass = 2;
171 fail = 1;
172 }
173
174 tgt[2].SrcReg[pass].File = PROGRAM_BUILTIN;
175 tgt[2].SrcReg[pass].Swizzle = SWIZZLE_1111;
176 tgt[2].SrcReg[fail] = shadow_ambient(t->Program, inst.TexSrcUnit);
177 } else if (destredirect) {
178 tgt = radeonAppendInstructions(t->Program, 1);
179
180 tgt->Opcode = OPCODE_MOV;
181 tgt->DstReg = orig_inst->DstReg;
182 tgt->SrcReg[0].File = PROGRAM_TEMPORARY;
183 tgt->SrcReg[0].Index = inst.DstReg.Index;
184 }
185
186 return GL_TRUE;
187 }
188
189 GLboolean r500FPIsNativeSwizzle(GLuint opcode, struct prog_src_register reg)
190 {
191 GLuint relevant;
192 int i;
193
194 if (opcode == OPCODE_TEX ||
195 opcode == OPCODE_TXB ||
196 opcode == OPCODE_TXP ||
197 opcode == OPCODE_KIL) {
198 if (reg.Abs)
199 return GL_FALSE;
200
201 if (opcode == OPCODE_KIL && (reg.Swizzle != SWIZZLE_NOOP || reg.Negate != NEGATE_NONE))
202 return GL_FALSE;
203
204 if (reg.Negate)
205 reg.Negate ^= NEGATE_XYZW;
206
207 for(i = 0; i < 4; ++i) {
208 GLuint swz = GET_SWZ(reg.Swizzle, i);
209 if (swz == SWIZZLE_NIL) {
210 reg.Negate &= ~(1 << i);
211 continue;
212 }
213 if (swz >= 4)
214 return GL_FALSE;
215 }
216
217 if (reg.Negate)
218 return GL_FALSE;
219
220 return GL_TRUE;
221 } else if (opcode == OPCODE_DDX || opcode == OPCODE_DDY) {
222 /* DDX/MDH and DDY/MDV explicitly ignore incoming swizzles;
223 * if it doesn't fit perfectly into a .xyzw case... */
224 if (reg.Swizzle == SWIZZLE_NOOP && !reg.Abs && !reg.Negate)
225 return GL_TRUE;
226
227 return GL_FALSE;
228 } else {
229 /* ALU instructions support almost everything */
230 if (reg.Abs)
231 return GL_TRUE;
232
233 relevant = 0;
234 for(i = 0; i < 3; ++i) {
235 GLuint swz = GET_SWZ(reg.Swizzle, i);
236 if (swz != SWIZZLE_NIL && swz != SWIZZLE_ZERO)
237 relevant |= 1 << i;
238 }
239 if ((reg.Negate & relevant) && ((reg.Negate & relevant) != relevant))
240 return GL_FALSE;
241
242 return GL_TRUE;
243 }
244 }
245
246 /**
247 * Implement a MOV with a potentially non-native swizzle.
248 *
249 * The only thing we *cannot* do in an ALU instruction is per-component
250 * negation. Therefore, we split the MOV into two instructions when necessary.
251 */
252 void r500FPBuildSwizzle(struct nqssadce_state *s, struct prog_dst_register dst, struct prog_src_register src)
253 {
254 struct prog_instruction *inst;
255 GLuint negatebase[2] = { 0, 0 };
256 int i;
257
258 for(i = 0; i < 4; ++i) {
259 GLuint swz = GET_SWZ(src.Swizzle, i);
260 if (swz == SWIZZLE_NIL)
261 continue;
262 negatebase[GET_BIT(src.Negate, i)] |= 1 << i;
263 }
264
265 _mesa_insert_instructions(s->Program, s->IP, (negatebase[0] ? 1 : 0) + (negatebase[1] ? 1 : 0));
266 inst = s->Program->Instructions + s->IP;
267
268 for(i = 0; i <= 1; ++i) {
269 if (!negatebase[i])
270 continue;
271
272 inst->Opcode = OPCODE_MOV;
273 inst->DstReg = dst;
274 inst->DstReg.WriteMask = negatebase[i];
275 inst->SrcReg[0] = src;
276 inst->SrcReg[0].Negate = (i == 0) ? NEGATE_NONE : NEGATE_XYZW;
277 inst++;
278 s->IP++;
279 }
280 }
281
282
283 static char *toswiz(int swiz_val) {
284 switch(swiz_val) {
285 case 0: return "R";
286 case 1: return "G";
287 case 2: return "B";
288 case 3: return "A";
289 case 4: return "0";
290 case 5: return "1/2";
291 case 6: return "1";
292 case 7: return "U";
293 }
294 return NULL;
295 }
296
297 static char *toop(int op_val)
298 {
299 char *str = NULL;
300 switch (op_val) {
301 case 0: str = "MAD"; break;
302 case 1: str = "DP3"; break;
303 case 2: str = "DP4"; break;
304 case 3: str = "D2A"; break;
305 case 4: str = "MIN"; break;
306 case 5: str = "MAX"; break;
307 case 6: str = "Reserved"; break;
308 case 7: str = "CND"; break;
309 case 8: str = "CMP"; break;
310 case 9: str = "FRC"; break;
311 case 10: str = "SOP"; break;
312 case 11: str = "MDH"; break;
313 case 12: str = "MDV"; break;
314 }
315 return str;
316 }
317
318 static char *to_alpha_op(int op_val)
319 {
320 char *str = NULL;
321 switch (op_val) {
322 case 0: str = "MAD"; break;
323 case 1: str = "DP"; break;
324 case 2: str = "MIN"; break;
325 case 3: str = "MAX"; break;
326 case 4: str = "Reserved"; break;
327 case 5: str = "CND"; break;
328 case 6: str = "CMP"; break;
329 case 7: str = "FRC"; break;
330 case 8: str = "EX2"; break;
331 case 9: str = "LN2"; break;
332 case 10: str = "RCP"; break;
333 case 11: str = "RSQ"; break;
334 case 12: str = "SIN"; break;
335 case 13: str = "COS"; break;
336 case 14: str = "MDH"; break;
337 case 15: str = "MDV"; break;
338 }
339 return str;
340 }
341
342 static char *to_mask(int val)
343 {
344 char *str = NULL;
345 switch(val) {
346 case 0: str = "NONE"; break;
347 case 1: str = "R"; break;
348 case 2: str = "G"; break;
349 case 3: str = "RG"; break;
350 case 4: str = "B"; break;
351 case 5: str = "RB"; break;
352 case 6: str = "GB"; break;
353 case 7: str = "RGB"; break;
354 case 8: str = "A"; break;
355 case 9: str = "AR"; break;
356 case 10: str = "AG"; break;
357 case 11: str = "ARG"; break;
358 case 12: str = "AB"; break;
359 case 13: str = "ARB"; break;
360 case 14: str = "AGB"; break;
361 case 15: str = "ARGB"; break;
362 }
363 return str;
364 }
365
366 static char *to_texop(int val)
367 {
368 switch(val) {
369 case 0: return "NOP";
370 case 1: return "LD";
371 case 2: return "TEXKILL";
372 case 3: return "PROJ";
373 case 4: return "LODBIAS";
374 case 5: return "LOD";
375 case 6: return "DXDY";
376 }
377 return NULL;
378 }
379
380 void r500FragmentProgramDump(struct rX00_fragment_program_code *c)
381 {
382 struct r500_fragment_program_code *code = &c->code.r500;
383 fprintf(stderr, "R500 Fragment Program:\n--------\n");
384
385 int n;
386 uint32_t inst;
387 uint32_t inst0;
388 char *str = NULL;
389
390 if (code->const_nr) {
391 fprintf(stderr, "--------\nConstants:\n");
392 for (n = 0; n < code->const_nr; n++) {
393 fprintf(stderr, "Constant %d: %i[%i]\n", n,
394 code->constant[n].File, code->constant[n].Index);
395 }
396 fprintf(stderr, "--------\n");
397 }
398
399 for (n = 0; n < code->inst_end+1; n++) {
400 inst0 = inst = code->inst[n].inst0;
401 fprintf(stderr,"%d\t0:CMN_INST 0x%08x:", n, inst);
402 switch(inst & 0x3) {
403 case R500_INST_TYPE_ALU: str = "ALU"; break;
404 case R500_INST_TYPE_OUT: str = "OUT"; break;
405 case R500_INST_TYPE_FC: str = "FC"; break;
406 case R500_INST_TYPE_TEX: str = "TEX"; break;
407 };
408 fprintf(stderr,"%s %s %s %s %s ", str,
409 inst & R500_INST_TEX_SEM_WAIT ? "TEX_WAIT" : "",
410 inst & R500_INST_LAST ? "LAST" : "",
411 inst & R500_INST_NOP ? "NOP" : "",
412 inst & R500_INST_ALU_WAIT ? "ALU WAIT" : "");
413 fprintf(stderr,"wmask: %s omask: %s\n", to_mask((inst >> 11) & 0xf),
414 to_mask((inst >> 15) & 0xf));
415
416 switch(inst0 & 0x3) {
417 case 0:
418 case 1:
419 fprintf(stderr,"\t1:RGB_ADDR 0x%08x:", code->inst[n].inst1);
420 inst = code->inst[n].inst1;
421
422 fprintf(stderr,"Addr0: %d%c, Addr1: %d%c, Addr2: %d%c, srcp:%d\n",
423 inst & 0xff, (inst & (1<<8)) ? 'c' : 't',
424 (inst >> 10) & 0xff, (inst & (1<<18)) ? 'c' : 't',
425 (inst >> 20) & 0xff, (inst & (1<<28)) ? 'c' : 't',
426 (inst >> 30));
427
428 fprintf(stderr,"\t2:ALPHA_ADDR 0x%08x:", code->inst[n].inst2);
429 inst = code->inst[n].inst2;
430 fprintf(stderr,"Addr0: %d%c, Addr1: %d%c, Addr2: %d%c, srcp:%d\n",
431 inst & 0xff, (inst & (1<<8)) ? 'c' : 't',
432 (inst >> 10) & 0xff, (inst & (1<<18)) ? 'c' : 't',
433 (inst >> 20) & 0xff, (inst & (1<<28)) ? 'c' : 't',
434 (inst >> 30));
435 fprintf(stderr,"\t3 RGB_INST: 0x%08x:", code->inst[n].inst3);
436 inst = code->inst[n].inst3;
437 fprintf(stderr,"rgb_A_src:%d %s/%s/%s %d rgb_B_src:%d %s/%s/%s %d\n",
438 (inst) & 0x3, toswiz((inst >> 2) & 0x7), toswiz((inst >> 5) & 0x7), toswiz((inst >> 8) & 0x7),
439 (inst >> 11) & 0x3,
440 (inst >> 13) & 0x3, toswiz((inst >> 15) & 0x7), toswiz((inst >> 18) & 0x7), toswiz((inst >> 21) & 0x7),
441 (inst >> 24) & 0x3);
442
443
444 fprintf(stderr,"\t4 ALPHA_INST:0x%08x:", code->inst[n].inst4);
445 inst = code->inst[n].inst4;
446 fprintf(stderr,"%s dest:%d%s alp_A_src:%d %s %d alp_B_src:%d %s %d w:%d\n", to_alpha_op(inst & 0xf),
447 (inst >> 4) & 0x7f, inst & (1<<11) ? "(rel)":"",
448 (inst >> 12) & 0x3, toswiz((inst >> 14) & 0x7), (inst >> 17) & 0x3,
449 (inst >> 19) & 0x3, toswiz((inst >> 21) & 0x7), (inst >> 24) & 0x3,
450 (inst >> 31) & 0x1);
451
452 fprintf(stderr,"\t5 RGBA_INST: 0x%08x:", code->inst[n].inst5);
453 inst = code->inst[n].inst5;
454 fprintf(stderr,"%s dest:%d%s rgb_C_src:%d %s/%s/%s %d alp_C_src:%d %s %d\n", toop(inst & 0xf),
455 (inst >> 4) & 0x7f, inst & (1<<11) ? "(rel)":"",
456 (inst >> 12) & 0x3, toswiz((inst >> 14) & 0x7), toswiz((inst >> 17) & 0x7), toswiz((inst >> 20) & 0x7),
457 (inst >> 23) & 0x3,
458 (inst >> 25) & 0x3, toswiz((inst >> 27) & 0x7), (inst >> 30) & 0x3);
459 break;
460 case 2:
461 break;
462 case 3:
463 inst = code->inst[n].inst1;
464 fprintf(stderr,"\t1:TEX_INST: 0x%08x: id: %d op:%s, %s, %s %s\n", inst, (inst >> 16) & 0xf,
465 to_texop((inst >> 22) & 0x7), (inst & (1<<25)) ? "ACQ" : "",
466 (inst & (1<<26)) ? "IGNUNC" : "", (inst & (1<<27)) ? "UNSCALED" : "SCALED");
467 inst = code->inst[n].inst2;
468 fprintf(stderr,"\t2:TEX_ADDR: 0x%08x: src: %d%s %s/%s/%s/%s dst: %d%s %s/%s/%s/%s\n", inst,
469 inst & 127, inst & (1<<7) ? "(rel)" : "",
470 toswiz((inst >> 8) & 0x3), toswiz((inst >> 10) & 0x3),
471 toswiz((inst >> 12) & 0x3), toswiz((inst >> 14) & 0x3),
472 (inst >> 16) & 127, inst & (1<<23) ? "(rel)" : "",
473 toswiz((inst >> 24) & 0x3), toswiz((inst >> 26) & 0x3),
474 toswiz((inst >> 28) & 0x3), toswiz((inst >> 30) & 0x3));
475
476 fprintf(stderr,"\t3:TEX_DXDY: 0x%08x\n", code->inst[n].inst3);
477 break;
478 }
479 fprintf(stderr,"\n");
480 }
481
482 }