src/mesa/drivers/dri/r300/compiler/r500_fragprog.c

   1 /*
   2  * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
   3  *
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining
   7  * a copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sublicense, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial
  16  * portions of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  */
  27
  28 #include "r500_fragprog.h"
  29
  30 #include <stdio.h>
  31
  32 #include "../r300_reg.h"
  33
  34 /**
  35  * Rewrite IF instructions to use the ALU result special register.
  36  */
  37 int r500_transform_IF(
  38         struct radeon_compiler * c,
  39         struct rc_instruction * inst,
  40         void* data)
  41 {
  42         if (inst->U.I.Opcode != RC_OPCODE_IF)
  43                 return 0;
  44
  45         struct rc_instruction * inst_mov = rc_insert_new_instruction(c, inst->Prev);
  46         inst_mov->U.I.Opcode = RC_OPCODE_MOV;
  47         inst_mov->U.I.DstReg.WriteMask = 0;
  48         inst_mov->U.I.WriteALUResult = RC_ALURESULT_W;
  49         inst_mov->U.I.ALUResultCompare = RC_COMPARE_FUNC_NOTEQUAL;
  50         inst_mov->U.I.SrcReg[0] = inst->U.I.SrcReg[0];
  51         inst_mov->U.I.SrcReg[0].Swizzle = combine_swizzles4(inst_mov->U.I.SrcReg[0].Swizzle,
  52                         RC_SWIZZLE_UNUSED, RC_SWIZZLE_UNUSED, RC_SWIZZLE_UNUSED, RC_SWIZZLE_X);
  53
  54         inst->U.I.SrcReg[0].File = RC_FILE_SPECIAL;
  55         inst->U.I.SrcReg[0].Index = RC_SPECIAL_ALU_RESULT;
  56         inst->U.I.SrcReg[0].Swizzle = RC_SWIZZLE_XYZW;
  57         inst->U.I.SrcReg[0].Negate = 0;
  58
  59         return 1;
  60 }
  61
  62 static int r500_swizzle_is_native(rc_opcode opcode, struct rc_src_register reg)
  63 {
  64         unsigned int relevant;
  65         int i;
  66
  67         if (opcode == RC_OPCODE_TEX ||
  68             opcode == RC_OPCODE_TXB ||
  69             opcode == RC_OPCODE_TXP ||
  70             opcode == RC_OPCODE_KIL) {
  71                 if (reg.Abs)
  72                         return 0;
  73
  74                 if (opcode == RC_OPCODE_KIL && (reg.Swizzle != RC_SWIZZLE_XYZW || reg.Negate != RC_MASK_NONE))
  75                         return 0;
  76
  77                 if (reg.Negate)
  78                         reg.Negate ^= RC_MASK_XYZW;
  79
  80                 for(i = 0; i < 4; ++i) {
  81                         unsigned int swz = GET_SWZ(reg.Swizzle, i);
  82                         if (swz == RC_SWIZZLE_UNUSED) {
  83                                 reg.Negate &= ~(1 << i);
  84                                 continue;
  85                         }
  86                         if (swz >= 4)
  87                                 return 0;
  88                 }
  89
  90                 if (reg.Negate)
  91                         return 0;
  92
  93                 return 1;
  94         } else if (opcode == RC_OPCODE_DDX || opcode == RC_OPCODE_DDY) {
  95                 /* DDX/MDH and DDY/MDV explicitly ignore incoming swizzles;
  96                  * if it doesn't fit perfectly into a .xyzw case... */
  97                 if (reg.Swizzle == RC_SWIZZLE_XYZW && !reg.Abs && !reg.Negate)
  98                         return 1;
  99
 100                 return 0;
 101         } else {
 102                 /* ALU instructions support almost everything */
 103                 if (reg.Abs)
 104                         return 1;
 105
 106                 relevant = 0;
 107                 for(i = 0; i < 3; ++i) {
 108                         unsigned int swz = GET_SWZ(reg.Swizzle, i);
 109                         if (swz != RC_SWIZZLE_UNUSED && swz != RC_SWIZZLE_ZERO)
 110                                 relevant |= 1 << i;
 111                 }
 112                 if ((reg.Negate & relevant) && ((reg.Negate & relevant) != relevant))
 113                         return 0;
 114
 115                 return 1;
 116         }
 117 }
 118
 119 /**
 120  * Split source register access.
 121  *
 122  * The only thing we *cannot* do in an ALU instruction is per-component
 123  * negation.
 124  */
 125 static void r500_swizzle_split(struct rc_src_register src, unsigned int usemask,
 126                 struct rc_swizzle_split * split)
 127 {
 128         unsigned int negatebase[2] = { 0, 0 };
 129         int i;
 130
 131         for(i = 0; i < 4; ++i) {
 132                 unsigned int swz = GET_SWZ(src.Swizzle, i);
 133                 if (swz == RC_SWIZZLE_UNUSED || !GET_BIT(usemask, i))
 134                         continue;
 135                 negatebase[GET_BIT(src.Negate, i)] |= 1 << i;
 136         }
 137
 138         split->NumPhases = 0;
 139
 140         for(i = 0; i <= 1; ++i) {
 141                 if (!negatebase[i])
 142                         continue;
 143
 144                 split->Phase[split->NumPhases++] = negatebase[i];
 145         }
 146 }
 147
 148 struct rc_swizzle_caps r500_swizzle_caps = {
 149         .IsNative = r500_swizzle_is_native,
 150         .Split = r500_swizzle_split
 151 };
 152
 153 static char *toswiz(int swiz_val) {
 154   switch(swiz_val) {
 155   case 0: return "R";
 156   case 1: return "G";
 157   case 2: return "B";
 158   case 3: return "A";
 159   case 4: return "0";
 160   case 5: return "H";
 161   case 6: return "1";
 162   case 7: return "U";
 163   }
 164   return NULL;
 165 }
 166
 167 static char *toop(int op_val)
 168 {
 169   char *str = NULL;
 170   switch (op_val) {
 171   case 0: str = "MAD"; break;
 172   case 1: str = "DP3"; break;
 173   case 2: str = "DP4"; break;
 174   case 3: str = "D2A"; break;
 175   case 4: str = "MIN"; break;
 176   case 5: str = "MAX"; break;
 177   case 6: str = "Reserved"; break;
 178   case 7: str = "CND"; break;
 179   case 8: str = "CMP"; break;
 180   case 9: str = "FRC"; break;
 181   case 10: str = "SOP"; break;
 182   case 11: str = "MDH"; break;
 183   case 12: str = "MDV"; break;
 184   }
 185   return str;
 186 }
 187
 188 static char *to_alpha_op(int op_val)
 189 {
 190   char *str = NULL;
 191   switch (op_val) {
 192   case 0: str = "MAD"; break;
 193   case 1: str = "DP"; break;
 194   case 2: str = "MIN"; break;
 195   case 3: str = "MAX"; break;
 196   case 4: str = "Reserved"; break;
 197   case 5: str = "CND"; break;
 198   case 6: str = "CMP"; break;
 199   case 7: str = "FRC"; break;
 200   case 8: str = "EX2"; break;
 201   case 9: str = "LN2"; break;
 202   case 10: str = "RCP"; break;
 203   case 11: str = "RSQ"; break;
 204   case 12: str = "SIN"; break;
 205   case 13: str = "COS"; break;
 206   case 14: str = "MDH"; break;
 207   case 15: str = "MDV"; break;
 208   }
 209   return str;
 210 }
 211
 212 static char *to_mask(int val)
 213 {
 214   char *str = NULL;
 215   switch(val) {
 216   case 0: str = "NONE"; break;
 217   case 1: str = "R"; break;
 218   case 2: str = "G"; break;
 219   case 3: str = "RG"; break;
 220   case 4: str = "B"; break;
 221   case 5: str = "RB"; break;
 222   case 6: str = "GB"; break;
 223   case 7: str = "RGB"; break;
 224   case 8: str = "A"; break;
 225   case 9: str = "AR"; break;
 226   case 10: str = "AG"; break;
 227   case 11: str = "ARG"; break;
 228   case 12: str = "AB"; break;
 229   case 13: str = "ARB"; break;
 230   case 14: str = "AGB"; break;
 231   case 15: str = "ARGB"; break;
 232   }
 233   return str;
 234 }
 235
 236 static char *to_texop(int val)
 237 {
 238   switch(val) {
 239   case 0: return "NOP";
 240   case 1: return "LD";
 241   case 2: return "TEXKILL";
 242   case 3: return "PROJ";
 243   case 4: return "LODBIAS";
 244   case 5: return "LOD";
 245   case 6: return "DXDY";
 246   }
 247   return NULL;
 248 }
 249
 250 void r500FragmentProgramDump(struct radeon_compiler *c, void *user)
 251 {
 252   struct r300_fragment_program_compiler *compiler = (struct r300_fragment_program_compiler*)c;
 253   struct r500_fragment_program_code *code = &compiler->code->code.r500;
 254   fprintf(stderr, "R500 Fragment Program:\n--------\n");
 255
 256   int n, i;
 257   uint32_t inst;
 258   uint32_t inst0;
 259   char *str = NULL;
 260
 261   for (n = 0; n < code->inst_end+1; n++) {
 262     inst0 = inst = code->inst[n].inst0;
 263     fprintf(stderr,"%d\t0:CMN_INST   0x%08x:", n, inst);
 264     switch(inst & 0x3) {
 265     case R500_INST_TYPE_ALU: str = "ALU"; break;
 266     case R500_INST_TYPE_OUT: str = "OUT"; break;
 267     case R500_INST_TYPE_FC: str = "FC"; break;
 268     case R500_INST_TYPE_TEX: str = "TEX"; break;
 269     };
 270     fprintf(stderr,"%s %s %s %s %s ", str,
 271             inst & R500_INST_TEX_SEM_WAIT ? "TEX_WAIT" : "",
 272             inst & R500_INST_LAST ? "LAST" : "",
 273             inst & R500_INST_NOP ? "NOP" : "",
 274             inst & R500_INST_ALU_WAIT ? "ALU WAIT" : "");
 275     fprintf(stderr,"wmask: %s omask: %s\n", to_mask((inst >> 11) & 0xf),
 276             to_mask((inst >> 15) & 0xf));
 277
 278     switch(inst0 & 0x3) {
 279     case R500_INST_TYPE_ALU:
 280     case R500_INST_TYPE_OUT:
 281       fprintf(stderr,"\t1:RGB_ADDR   0x%08x:", code->inst[n].inst1);
 282       inst = code->inst[n].inst1;
 283
 284       fprintf(stderr,"Addr0: %d%c, Addr1: %d%c, Addr2: %d%c, srcp:%d\n",
 285               inst & 0xff, (inst & (1<<8)) ? 'c' : 't',
 286               (inst >> 10) & 0xff, (inst & (1<<18)) ? 'c' : 't',
 287               (inst >> 20) & 0xff, (inst & (1<<28)) ? 'c' : 't',
 288               (inst >> 30));
 289
 290       fprintf(stderr,"\t2:ALPHA_ADDR 0x%08x:", code->inst[n].inst2);
 291       inst = code->inst[n].inst2;
 292       fprintf(stderr,"Addr0: %d%c, Addr1: %d%c, Addr2: %d%c, srcp:%d\n",
 293               inst & 0xff, (inst & (1<<8)) ? 'c' : 't',
 294               (inst >> 10) & 0xff, (inst & (1<<18)) ? 'c' : 't',
 295               (inst >> 20) & 0xff, (inst & (1<<28)) ? 'c' : 't',
 296               (inst >> 30));
 297       fprintf(stderr,"\t3 RGB_INST:  0x%08x:", code->inst[n].inst3);
 298       inst = code->inst[n].inst3;
 299       fprintf(stderr,"rgb_A_src:%d %s/%s/%s %d rgb_B_src:%d %s/%s/%s %d targ: %d\n",
 300               (inst) & 0x3, toswiz((inst >> 2) & 0x7), toswiz((inst >> 5) & 0x7), toswiz((inst >> 8) & 0x7),
 301               (inst >> 11) & 0x3,
 302               (inst >> 13) & 0x3, toswiz((inst >> 15) & 0x7), toswiz((inst >> 18) & 0x7), toswiz((inst >> 21) & 0x7),
 303               (inst >> 24) & 0x3, (inst >> 29) & 0x3);
 304
 305
 306       fprintf(stderr,"\t4 ALPHA_INST:0x%08x:", code->inst[n].inst4);
 307       inst = code->inst[n].inst4;
 308       fprintf(stderr,"%s dest:%d%s alp_A_src:%d %s %d alp_B_src:%d %s %d targ %d w:%d\n", to_alpha_op(inst & 0xf),
 309               (inst >> 4) & 0x7f, inst & (1<<11) ? "(rel)":"",
 310               (inst >> 12) & 0x3, toswiz((inst >> 14) & 0x7), (inst >> 17) & 0x3,
 311               (inst >> 19) & 0x3, toswiz((inst >> 21) & 0x7), (inst >> 24) & 0x3,
 312               (inst >> 29) & 0x3,
 313               (inst >> 31) & 0x1);
 314
 315       fprintf(stderr,"\t5 RGBA_INST: 0x%08x:", code->inst[n].inst5);
 316       inst = code->inst[n].inst5;
 317       fprintf(stderr,"%s dest:%d%s rgb_C_src:%d %s/%s/%s %d alp_C_src:%d %s %d\n", toop(inst & 0xf),
 318               (inst >> 4) & 0x7f, inst & (1<<11) ? "(rel)":"",
 319               (inst >> 12) & 0x3, toswiz((inst >> 14) & 0x7), toswiz((inst >> 17) & 0x7), toswiz((inst >> 20) & 0x7),
 320               (inst >> 23) & 0x3,
 321               (inst >> 25) & 0x3, toswiz((inst >> 27) & 0x7), (inst >> 30) & 0x3);
 322       break;
 323     case R500_INST_TYPE_FC:
 324       fprintf(stderr, "\t2:FC_INST    0x%08x:", code->inst[n].inst2);
 325       inst = code->inst[n].inst2;
 326       /* JUMP_FUNC JUMP_ANY*/
 327       fprintf(stderr, "0x%02x %1x ", inst >> 8 & 0xff,
 328           (inst & R500_FC_JUMP_ANY) >> 5);
 329
 330       /* OP */
 331       switch(inst & 0x7){
 332       case R500_FC_OP_JUMP:
 333         fprintf(stderr, "JUMP");
 334         break;
 335       case R500_FC_OP_LOOP:
 336         fprintf(stderr, "LOOP");
 337         break;
 338       case R500_FC_OP_ENDLOOP:
 339         fprintf(stderr, "ENDLOOP");
 340         break;
 341       case R500_FC_OP_REP:
 342         fprintf(stderr, "REP");
 343         break;
 344       case R500_FC_OP_ENDREP:
 345         fprintf(stderr, "ENDREP");
 346         break;
 347       case R500_FC_OP_BREAKLOOP:
 348         fprintf(stderr, "BREAKLOOP");
 349         break;
 350       case R500_FC_OP_BREAKREP:
 351         fprintf(stderr, "BREAKREP");
 352         break;
 353       case R500_FC_OP_CONTINUE:
 354         fprintf(stderr, "CONTINUE");
 355         break;
 356       }
 357       fprintf(stderr," ");
 358       /* A_OP */
 359       switch(inst & (0x3 << 6)){
 360       case R500_FC_A_OP_NONE:
 361         fprintf(stderr, "NONE");
 362         break;
 363       case R500_FC_A_OP_POP:
 364         fprintf(stderr, "POP");
 365         break;
 366       case R500_FC_A_OP_PUSH:
 367         fprintf(stderr, "PUSH");
 368         break;
 369       }
 370       /* B_OP0 B_OP1 */
 371       for(i=0; i<2; i++){
 372         fprintf(stderr, " ");
 373         switch(inst & (0x3 << (24 + (i * 2)))){
 374         /* R500_FC_B_OP0_NONE
 375          * R500_FC_B_OP1_NONE */
 376         case 0:
 377           fprintf(stderr, "NONE");
 378           break;
 379         case R500_FC_B_OP0_DECR:
 380         case R500_FC_B_OP1_DECR:
 381           fprintf(stderr, "DECR");
 382           break;
 383         case R500_FC_B_OP0_INCR:
 384         case R500_FC_B_OP1_INCR:
 385           fprintf(stderr, "INCR");
 386           break;
 387         }
 388       }
 389       /*POP_CNT B_ELSE */
 390       fprintf(stderr, " %d %1x", (inst >> 16) & 0x1f, (inst & R500_FC_B_ELSE) >> 4);
 391       inst = code->inst[n].inst3;
 392       /* JUMP_ADDR */
 393       fprintf(stderr, " %d", inst >> 16);
 394
 395       if(code->inst[n].inst2 & R500_FC_IGNORE_UNCOVERED){
 396         fprintf(stderr, " IGN_UNC");
 397       }
 398       inst = code->inst[n].inst3;
 399       fprintf(stderr, "\n\t3:FC_ADDR    0x%08x:", inst);
 400       fprintf(stderr, "BOOL: 0x%02x, INT: 0x%02x, JUMP_ADDR: %d, JMP_GLBL: %1x\n",
 401       inst & 0x1f, (inst >> 8) & 0x1f, (inst >> 16) & 0x1ff, inst >> 31);
 402       break;
 403     case R500_INST_TYPE_TEX:
 404       inst = code->inst[n].inst1;
 405       fprintf(stderr,"\t1:TEX_INST:  0x%08x: id: %d op:%s, %s, %s %s\n", inst, (inst >> 16) & 0xf,
 406               to_texop((inst >> 22) & 0x7), (inst & (1<<25)) ? "ACQ" : "",
 407               (inst & (1<<26)) ? "IGNUNC" : "", (inst & (1<<27)) ? "UNSCALED" : "SCALED");
 408       inst = code->inst[n].inst2;
 409       fprintf(stderr,"\t2:TEX_ADDR:  0x%08x: src: %d%s %s/%s/%s/%s dst: %d%s %s/%s/%s/%s\n", inst,
 410               inst & 127, inst & (1<<7) ? "(rel)" : "",
 411               toswiz((inst >> 8) & 0x3), toswiz((inst >> 10) & 0x3),
 412               toswiz((inst >> 12) & 0x3), toswiz((inst >> 14) & 0x3),
 413               (inst >> 16) & 127, inst & (1<<23) ? "(rel)" : "",
 414               toswiz((inst >> 24) & 0x3), toswiz((inst >> 26) & 0x3),
 415               toswiz((inst >> 28) & 0x3), toswiz((inst >> 30) & 0x3));
 416
 417       fprintf(stderr,"\t3:TEX_DXDY:  0x%08x\n", code->inst[n].inst3);
 418       break;
 419     }
 420     fprintf(stderr,"\n");
 421   }
 422
 423 }