src/mesa/drivers/dri/r300/compiler/r500_fragprog_emit.c

   1 /*
   2  * Copyright (C) 2005 Ben Skeggs.
   3  *
   4  * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
   5  * Adaptation and modification for ATI/AMD Radeon R500 GPU chipsets.
   6  *
   7  * All Rights Reserved.
   8  *
   9  * Permission is hereby granted, free of charge, to any person obtaining
  10  * a copy of this software and associated documentation files (the
  11  * "Software"), to deal in the Software without restriction, including
  12  * without limitation the rights to use, copy, modify, merge, publish,
  13  * distribute, sublicense, and/or sell copies of the Software, and to
  14  * permit persons to whom the Software is furnished to do so, subject to
  15  * the following conditions:
  16  *
  17  * The above copyright notice and this permission notice (including the
  18  * next paragraph) shall be included in all copies or substantial
  19  * portions of the Software.
  20  *
  21  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  22  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  23  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  24  * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  25  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  26  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  27  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  28  *
  29  */
  30
  31 /**
  32  * \file
  33  *
  34  * \author Ben Skeggs <darktama@iinet.net.au>
  35  *
  36  * \author Jerome Glisse <j.glisse@gmail.com>
  37  *
  38  * \author Corbin Simpson <MostAwesomeDude@gmail.com>
  39  *
  40  */
  41
  42 #include "r500_fragprog.h"
  43
  44 #include "../r300_reg.h"
  45
  46 #include "radeon_program_pair.h"
  47
  48 #define MAX_BRANCH_DEPTH_FULL 32
  49 #define MAX_BRANCH_DEPTH_PARTIAL 4
  50
  51 #define PROG_CODE \
  52         struct r500_fragment_program_code *code = &c->code->code.r500
  53
  54 #define error(fmt, args...) do {                        \
  55                 rc_error(&c->Base, "%s::%s(): " fmt "\n",       \
  56                         __FILE__, __FUNCTION__, ##args);        \
  57         } while(0)
  58
  59
  60 struct branch_info {
  61         int If;
  62         int Else;
  63         int Endif;
  64 };
  65
  66 struct loop_info {
  67         int BgnLoop;
  68
  69         int BranchDepth;
  70         int * Brks;
  71         int BrkCount;
  72         int BrkReserved;
  73
  74         int * Conts;
  75         int ContCount;
  76         int ContReserved;
  77 };
  78
  79 struct emit_state {
  80         struct radeon_compiler * C;
  81         struct r500_fragment_program_code * Code;
  82
  83         struct branch_info * Branches;
  84         unsigned int CurrentBranchDepth;
  85         unsigned int BranchesReserved;
  86
  87         struct loop_info * Loops;
  88         unsigned int CurrentLoopDepth;
  89         unsigned int LoopsReserved;
  90
  91         unsigned int MaxBranchDepth;
  92
  93 };
  94
  95 static unsigned int translate_rgb_op(struct r300_fragment_program_compiler *c, rc_opcode opcode)
  96 {
  97         switch(opcode) {
  98         case RC_OPCODE_CMP: return R500_ALU_RGBA_OP_CMP;
  99         case RC_OPCODE_DDX: return R500_ALU_RGBA_OP_MDH;
 100         case RC_OPCODE_DDY: return R500_ALU_RGBA_OP_MDV;
 101         case RC_OPCODE_DP3: return R500_ALU_RGBA_OP_DP3;
 102         case RC_OPCODE_DP4: return R500_ALU_RGBA_OP_DP4;
 103         case RC_OPCODE_FRC: return R500_ALU_RGBA_OP_FRC;
 104         default:
 105                 error("translate_rgb_op: unknown opcode %s\n", rc_get_opcode_info(opcode)->Name);
 106                 /* fall through */
 107         case RC_OPCODE_NOP:
 108                 /* fall through */
 109         case RC_OPCODE_MAD: return R500_ALU_RGBA_OP_MAD;
 110         case RC_OPCODE_MAX: return R500_ALU_RGBA_OP_MAX;
 111         case RC_OPCODE_MIN: return R500_ALU_RGBA_OP_MIN;
 112         case RC_OPCODE_REPL_ALPHA: return R500_ALU_RGBA_OP_SOP;
 113         }
 114 }
 115
 116 static unsigned int translate_alpha_op(struct r300_fragment_program_compiler *c, rc_opcode opcode)
 117 {
 118         switch(opcode) {
 119         case RC_OPCODE_CMP: return R500_ALPHA_OP_CMP;
 120         case RC_OPCODE_COS: return R500_ALPHA_OP_COS;
 121         case RC_OPCODE_DDX: return R500_ALPHA_OP_MDH;
 122         case RC_OPCODE_DDY: return R500_ALPHA_OP_MDV;
 123         case RC_OPCODE_DP3: return R500_ALPHA_OP_DP;
 124         case RC_OPCODE_DP4: return R500_ALPHA_OP_DP;
 125         case RC_OPCODE_EX2: return R500_ALPHA_OP_EX2;
 126         case RC_OPCODE_FRC: return R500_ALPHA_OP_FRC;
 127         case RC_OPCODE_LG2: return R500_ALPHA_OP_LN2;
 128         default:
 129                 error("translate_alpha_op: unknown opcode %s\n", rc_get_opcode_info(opcode)->Name);
 130                 /* fall through */
 131         case RC_OPCODE_NOP:
 132                 /* fall through */
 133         case RC_OPCODE_MAD: return R500_ALPHA_OP_MAD;
 134         case RC_OPCODE_MAX: return R500_ALPHA_OP_MAX;
 135         case RC_OPCODE_MIN: return R500_ALPHA_OP_MIN;
 136         case RC_OPCODE_RCP: return R500_ALPHA_OP_RCP;
 137         case RC_OPCODE_RSQ: return R500_ALPHA_OP_RSQ;
 138         case RC_OPCODE_SIN: return R500_ALPHA_OP_SIN;
 139         }
 140 }
 141
 142 static unsigned int fix_hw_swizzle(unsigned int swz)
 143 {
 144     switch (swz) {
 145         case RC_SWIZZLE_ZERO:
 146         case RC_SWIZZLE_UNUSED:
 147             swz = 4;
 148             break;
 149         case RC_SWIZZLE_HALF:
 150             swz = 5;
 151             break;
 152         case RC_SWIZZLE_ONE:
 153             swz = 6;
 154             break;
 155     }
 156
 157         return swz;
 158 }
 159
 160 static unsigned int translate_arg_rgb(struct rc_pair_instruction *inst, int arg)
 161 {
 162         unsigned int t = inst->RGB.Arg[arg].Source;
 163         int comp;
 164         t |= inst->RGB.Arg[arg].Negate << 11;
 165         t |= inst->RGB.Arg[arg].Abs << 12;
 166
 167         for(comp = 0; comp < 3; ++comp)
 168                 t |= fix_hw_swizzle(GET_SWZ(inst->RGB.Arg[arg].Swizzle, comp)) << (3*comp + 2);
 169
 170         return t;
 171 }
 172
 173 static unsigned int translate_arg_alpha(struct rc_pair_instruction *inst, int i)
 174 {
 175         unsigned int t = inst->Alpha.Arg[i].Source;
 176         t |= fix_hw_swizzle(inst->Alpha.Arg[i].Swizzle) << 2;
 177         t |= inst->Alpha.Arg[i].Negate << 5;
 178         t |= inst->Alpha.Arg[i].Abs << 6;
 179         return t;
 180 }
 181
 182 static uint32_t translate_alu_result_op(struct r300_fragment_program_compiler * c, rc_compare_func func)
 183 {
 184         switch(func) {
 185         case RC_COMPARE_FUNC_EQUAL: return R500_INST_ALU_RESULT_OP_EQ;
 186         case RC_COMPARE_FUNC_LESS: return R500_INST_ALU_RESULT_OP_LT;
 187         case RC_COMPARE_FUNC_GEQUAL: return R500_INST_ALU_RESULT_OP_GE;
 188         case RC_COMPARE_FUNC_NOTEQUAL: return R500_INST_ALU_RESULT_OP_NE;
 189         default:
 190                 rc_error(&c->Base, "%s: unsupported compare func %i\n", __FUNCTION__, func);
 191                 return 0;
 192         }
 193 }
 194
 195 static void use_temporary(struct r500_fragment_program_code* code, unsigned int index)
 196 {
 197         if (index > code->max_temp_idx)
 198                 code->max_temp_idx = index;
 199 }
 200
 201 static unsigned int use_source(struct r500_fragment_program_code* code, struct radeon_pair_instruction_source src)
 202 {
 203         if (src.File == RC_FILE_CONSTANT) {
 204                 return src.Index | 0x100;
 205         } else if (src.File == RC_FILE_TEMPORARY) {
 206                 use_temporary(code, src.Index);
 207                 return src.Index;
 208         }
 209
 210         return 0;
 211 }
 212
 213 /**
 214  * NOP the specified instruction if it is not a texture lookup.
 215  */
 216 static void alu_nop(struct r300_fragment_program_compiler *c, int ip)
 217 {
 218         PROG_CODE;
 219
 220         if ((code->inst[ip].inst0 & 0x3) != R500_INST_TYPE_TEX) {
 221                 code->inst[ip].inst0 |= R500_INST_NOP;
 222         }
 223 }
 224
 225 /**
 226  * Emit a paired ALU instruction.
 227  */
 228 static void emit_paired(struct r300_fragment_program_compiler *c, struct rc_pair_instruction *inst)
 229 {
 230         PROG_CODE;
 231
 232         if (code->inst_end >= 511) {
 233                 error("emit_alu: Too many instructions");
 234                 return;
 235         }
 236
 237         int ip = ++code->inst_end;
 238
 239         /* Quirk: MDH/MDV (DDX/DDY) need a NOP on previous non-TEX instructions. */
 240         if (inst->RGB.Opcode == RC_OPCODE_DDX || inst->Alpha.Opcode == RC_OPCODE_DDX ||
 241                 inst->RGB.Opcode == RC_OPCODE_DDY || inst->Alpha.Opcode == RC_OPCODE_DDY) {
 242                 if (ip > 0) {
 243                         alu_nop(c, ip - 1);
 244                 }
 245         }
 246
 247         code->inst[ip].inst5 = translate_rgb_op(c, inst->RGB.Opcode);
 248         code->inst[ip].inst4 = translate_alpha_op(c, inst->Alpha.Opcode);
 249
 250         if (inst->RGB.OutputWriteMask || inst->Alpha.OutputWriteMask || inst->Alpha.DepthWriteMask) {
 251                 code->inst[ip].inst0 = R500_INST_TYPE_OUT;
 252                 if (inst->WriteALUResult) {
 253                         error("%s: cannot write output and ALU result at the same time");
 254                         return;
 255                 }
 256         } else {
 257                 code->inst[ip].inst0 = R500_INST_TYPE_ALU;
 258         }
 259         code->inst[ip].inst0 |= R500_INST_TEX_SEM_WAIT;
 260
 261         code->inst[ip].inst0 |= (inst->RGB.WriteMask << 11) | (inst->Alpha.WriteMask << 14);
 262         code->inst[ip].inst0 |= (inst->RGB.OutputWriteMask << 15) | (inst->Alpha.OutputWriteMask << 18);
 263         if (inst->Alpha.DepthWriteMask) {
 264                 code->inst[ip].inst4 |= R500_ALPHA_W_OMASK;
 265                 c->code->writes_depth = 1;
 266         }
 267
 268         code->inst[ip].inst4 |= R500_ALPHA_ADDRD(inst->Alpha.DestIndex);
 269         code->inst[ip].inst5 |= R500_ALU_RGBA_ADDRD(inst->RGB.DestIndex);
 270         use_temporary(code, inst->Alpha.DestIndex);
 271         use_temporary(code, inst->RGB.DestIndex);
 272
 273         if (inst->RGB.Saturate)
 274                 code->inst[ip].inst0 |= R500_INST_RGB_CLAMP;
 275         if (inst->Alpha.Saturate)
 276                 code->inst[ip].inst0 |= R500_INST_ALPHA_CLAMP;
 277
 278         code->inst[ip].inst1 |= R500_RGB_ADDR0(use_source(code, inst->RGB.Src[0]));
 279         code->inst[ip].inst1 |= R500_RGB_ADDR1(use_source(code, inst->RGB.Src[1]));
 280         code->inst[ip].inst1 |= R500_RGB_ADDR2(use_source(code, inst->RGB.Src[2]));
 281
 282         code->inst[ip].inst2 |= R500_ALPHA_ADDR0(use_source(code, inst->Alpha.Src[0]));
 283         code->inst[ip].inst2 |= R500_ALPHA_ADDR1(use_source(code, inst->Alpha.Src[1]));
 284         code->inst[ip].inst2 |= R500_ALPHA_ADDR2(use_source(code, inst->Alpha.Src[2]));
 285
 286         code->inst[ip].inst3 |= translate_arg_rgb(inst, 0) << R500_ALU_RGB_SEL_A_SHIFT;
 287         code->inst[ip].inst3 |= translate_arg_rgb(inst, 1) << R500_ALU_RGB_SEL_B_SHIFT;
 288         code->inst[ip].inst5 |= translate_arg_rgb(inst, 2) << R500_ALU_RGBA_SEL_C_SHIFT;
 289
 290         code->inst[ip].inst4 |= translate_arg_alpha(inst, 0) << R500_ALPHA_SEL_A_SHIFT;
 291         code->inst[ip].inst4 |= translate_arg_alpha(inst, 1) << R500_ALPHA_SEL_B_SHIFT;
 292         code->inst[ip].inst5 |= translate_arg_alpha(inst, 2) << R500_ALU_RGBA_ALPHA_SEL_C_SHIFT;
 293
 294         code->inst[ip].inst3 |= R500_ALU_RGB_TARGET(inst->RGB.Target);
 295         code->inst[ip].inst4 |= R500_ALPHA_TARGET(inst->Alpha.Target);
 296
 297         if (inst->WriteALUResult) {
 298                 code->inst[ip].inst3 |= R500_ALU_RGB_WMASK;
 299
 300                 if (inst->WriteALUResult == RC_ALURESULT_X)
 301                         code->inst[ip].inst0 |= R500_INST_ALU_RESULT_SEL_RED;
 302                 else
 303                         code->inst[ip].inst0 |= R500_INST_ALU_RESULT_SEL_ALPHA;
 304
 305                 code->inst[ip].inst0 |= translate_alu_result_op(c, inst->ALUResultCompare);
 306         }
 307 }
 308
 309 static unsigned int translate_strq_swizzle(unsigned int swizzle)
 310 {
 311         unsigned int swiz = 0;
 312         int i;
 313         for (i = 0; i < 4; i++)
 314                 swiz |= (GET_SWZ(swizzle, i) & 0x3) << i*2;
 315         return swiz;
 316 }
 317
 318 /**
 319  * Emit a single TEX instruction
 320  */
 321 static int emit_tex(struct r300_fragment_program_compiler *c, struct rc_sub_instruction *inst)
 322 {
 323         PROG_CODE;
 324
 325         if (code->inst_end >= 511) {
 326                 error("emit_tex: Too many instructions");
 327                 return 0;
 328         }
 329
 330         int ip = ++code->inst_end;
 331
 332         code->inst[ip].inst0 = R500_INST_TYPE_TEX
 333                 | (inst->DstReg.WriteMask << 11)
 334                 | R500_INST_TEX_SEM_WAIT;
 335         code->inst[ip].inst1 = R500_TEX_ID(inst->TexSrcUnit)
 336                 | R500_TEX_SEM_ACQUIRE | R500_TEX_IGNORE_UNCOVERED;
 337
 338         if (inst->TexSrcTarget == RC_TEXTURE_RECT)
 339                 code->inst[ip].inst1 |= R500_TEX_UNSCALED;
 340
 341         switch (inst->Opcode) {
 342         case RC_OPCODE_KIL:
 343                 code->inst[ip].inst1 |= R500_TEX_INST_TEXKILL;
 344                 break;
 345         case RC_OPCODE_TEX:
 346                 code->inst[ip].inst1 |= R500_TEX_INST_LD;
 347                 break;
 348         case RC_OPCODE_TXB:
 349                 code->inst[ip].inst1 |= R500_TEX_INST_LODBIAS;
 350                 break;
 351         case RC_OPCODE_TXP:
 352                 code->inst[ip].inst1 |= R500_TEX_INST_PROJ;
 353                 break;
 354         default:
 355                 error("emit_tex can't handle opcode %s\n", rc_get_opcode_info(inst->Opcode)->Name);
 356         }
 357
 358         use_temporary(code, inst->SrcReg[0].Index);
 359         if (inst->Opcode != RC_OPCODE_KIL)
 360                 use_temporary(code, inst->DstReg.Index);
 361
 362         code->inst[ip].inst2 = R500_TEX_SRC_ADDR(inst->SrcReg[0].Index)
 363                 | (translate_strq_swizzle(inst->SrcReg[0].Swizzle) << 8)
 364                 | R500_TEX_DST_ADDR(inst->DstReg.Index)
 365                 | R500_TEX_DST_R_SWIZ_R | R500_TEX_DST_G_SWIZ_G
 366                 | R500_TEX_DST_B_SWIZ_B | R500_TEX_DST_A_SWIZ_A;
 367
 368         return 1;
 369 }
 370
 371 static void emit_flowcontrol(struct emit_state * s, struct rc_instruction * inst)
 372 {
 373         if (s->Code->inst_end >= 511) {
 374                 rc_error(s->C, "emit_tex: Too many instructions");
 375                 return;
 376         }
 377
 378         unsigned int newip = ++s->Code->inst_end;
 379
 380         /* Currently all loops use the same integer constant to intialize
 381          * the loop variables. */
 382         if(!s->Code->int_constants[0]) {
 383                 s->Code->int_constants[0] = R500_FC_INT_CONST_KR(0xff);
 384                 s->Code->int_constant_count = 1;
 385         }
 386         s->Code->inst[newip].inst0 = R500_INST_TYPE_FC | R500_INST_ALU_WAIT;
 387
 388         switch(inst->U.I.Opcode){
 389         struct branch_info * branch;
 390         struct loop_info * loop;
 391         case RC_OPCODE_BGNLOOP:
 392                 memory_pool_array_reserve(&s->C->Pool, struct loop_info,
 393                         s->Loops, s->CurrentLoopDepth, s->LoopsReserved, 1);
 394
 395                 loop = &s->Loops[s->CurrentLoopDepth++];
 396                 memset(loop, 0, sizeof(struct loop_info));
 397                 loop->BranchDepth = s->CurrentBranchDepth;
 398                 loop->BgnLoop = newip;
 399
 400                 s->Code->inst[newip].inst2 = R500_FC_OP_LOOP
 401                         | R500_FC_JUMP_FUNC(0x00)
 402                         | R500_FC_IGNORE_UNCOVERED
 403                         ;
 404                 break;
 405         case RC_OPCODE_BRK:
 406                 loop = &s->Loops[s->CurrentLoopDepth - 1];
 407                 memory_pool_array_reserve(&s->C->Pool, int, loop->Brks,
 408                                         loop->BrkCount, loop->BrkReserved, 1);
 409
 410                 loop->Brks[loop->BrkCount++] = newip;
 411                 s->Code->inst[newip].inst2 = R500_FC_OP_BREAKLOOP
 412                         | R500_FC_JUMP_FUNC(0xff)
 413                         | R500_FC_B_OP1_DECR
 414                         | R500_FC_B_POP_CNT(
 415                                 s->CurrentBranchDepth - loop->BranchDepth)
 416                         | R500_FC_IGNORE_UNCOVERED
 417                         ;
 418                 break;
 419
 420         case RC_OPCODE_CONT:
 421                 loop = &s->Loops[s->CurrentLoopDepth - 1];
 422                 memory_pool_array_reserve(&s->C->Pool, int, loop->Conts,
 423                                         loop->ContCount, loop->ContReserved, 1);
 424                 loop->Conts[loop->ContCount++] = newip;
 425                 s->Code->inst[newip].inst2 = R500_FC_OP_CONTINUE
 426                         | R500_FC_JUMP_FUNC(0xff)
 427                         | R500_FC_B_OP1_DECR
 428                         | R500_FC_B_POP_CNT(
 429                                 s->CurrentBranchDepth - loop->BranchDepth)
 430                         | R500_FC_IGNORE_UNCOVERED
 431                         ;
 432                 break;
 433
 434         case RC_OPCODE_ENDLOOP:
 435         {
 436                 unsigned int i;
 437                 loop = &s->Loops[s->CurrentLoopDepth - 1];
 438                 /* Emit ENDLOOP */
 439                 s->Code->inst[newip].inst2 = R500_FC_OP_ENDLOOP
 440                         | R500_FC_JUMP_FUNC(0xff)
 441                         | R500_FC_JUMP_ANY
 442                         | R500_FC_IGNORE_UNCOVERED
 443                         ;
 444                 /* The constant integer at index 0 is used by all loops. */
 445                 s->Code->inst[newip].inst3 = R500_FC_INT_ADDR(0)
 446                         | R500_FC_JUMP_ADDR(loop->BgnLoop + 1)
 447                         ;
 448
 449                 /* Set jump address and int constant for BGNLOOP */
 450                 s->Code->inst[loop->BgnLoop].inst3 = R500_FC_INT_ADDR(0)
 451                         | R500_FC_JUMP_ADDR(newip)
 452                         ;
 453
 454                 /* Set jump address for the BRK instructions. */
 455                 while(loop->BrkCount--) {
 456                         s->Code->inst[loop->Brks[loop->BrkCount]].inst3 =
 457                                                 R500_FC_JUMP_ADDR(newip + 1);
 458                 }
 459
 460                 /* Set jump address for CONT instructions. */
 461                 while(loop->ContCount--) {
 462                         s->Code->inst[loop->Conts[loop->ContCount]].inst3 =
 463                                                 R500_FC_JUMP_ADDR(newip);
 464                 }
 465                 s->CurrentLoopDepth--;
 466                 break;
 467         }
 468         case RC_OPCODE_IF:
 469                 if ( s->CurrentBranchDepth >= MAX_BRANCH_DEPTH_FULL) {
 470                         rc_error(s->C, "Branch depth exceeds hardware limit");
 471                         return;
 472                 }
 473                 memory_pool_array_reserve(&s->C->Pool, struct branch_info,
 474                                 s->Branches, s->CurrentBranchDepth, s->BranchesReserved, 1);
 475
 476                 branch = &s->Branches[s->CurrentBranchDepth++];
 477                 branch->If = newip;
 478                 branch->Else = -1;
 479                 branch->Endif = -1;
 480
 481                 if (s->CurrentBranchDepth > s->MaxBranchDepth)
 482                         s->MaxBranchDepth = s->CurrentBranchDepth;
 483
 484                 /* actual instruction is filled in at ENDIF time */
 485                 break;
 486
 487         case RC_OPCODE_ELSE:
 488                 if (!s->CurrentBranchDepth) {
 489                         rc_error(s->C, "%s: got ELSE outside a branch", __FUNCTION__);
 490                         return;
 491                 }
 492
 493                 branch = &s->Branches[s->CurrentBranchDepth - 1];
 494                 branch->Else = newip;
 495
 496                 /* actual instruction is filled in at ENDIF time */
 497                 break;
 498
 499         case RC_OPCODE_ENDIF:
 500                 if (!s->CurrentBranchDepth) {
 501                         rc_error(s->C, "%s: got ELSE outside a branch", __FUNCTION__);
 502                         return;
 503                 }
 504
 505                 branch = &s->Branches[s->CurrentBranchDepth - 1];
 506                 branch->Endif = newip;
 507
 508                 s->Code->inst[branch->Endif].inst2 = R500_FC_OP_JUMP
 509                         | R500_FC_A_OP_NONE /* no address stack */
 510                         | R500_FC_JUMP_ANY /* docs says set this, but I don't understand why */
 511                         | R500_FC_B_OP0_DECR /* decrement branch counter if stay */
 512                         | R500_FC_B_OP1_NONE /* no branch counter if stay */
 513                         | R500_FC_B_POP_CNT(1)
 514                         ;
 515                 s->Code->inst[branch->Endif].inst3 = R500_FC_JUMP_ADDR(branch->Endif + 1);
 516                 s->Code->inst[branch->If].inst2 = R500_FC_OP_JUMP
 517                         | R500_FC_A_OP_NONE /* no address stack */
 518                         | R500_FC_JUMP_FUNC(0x0f) /* jump if ALU result is false */
 519                         | R500_FC_B_OP0_INCR /* increment branch counter if stay */
 520                         | R500_FC_IGNORE_UNCOVERED
 521                 ;
 522
 523                 if (branch->Else >= 0) {
 524                         /* increment branch counter also if jump */
 525                         s->Code->inst[branch->If].inst2 |= R500_FC_B_OP1_INCR;
 526                         s->Code->inst[branch->If].inst3 = R500_FC_JUMP_ADDR(branch->Else + 1);
 527
 528                         s->Code->inst[branch->Else].inst2 = R500_FC_OP_JUMP
 529                                 | R500_FC_A_OP_NONE /* no address stack */
 530                                 | R500_FC_B_ELSE /* all active pixels want to jump */
 531                                 | R500_FC_B_OP0_NONE /* no counter op if stay */
 532                                 | R500_FC_B_OP1_DECR /* decrement branch counter if jump */
 533                                 | R500_FC_B_POP_CNT(1)
 534                         ;
 535                         s->Code->inst[branch->Else].inst3 = R500_FC_JUMP_ADDR(branch->Endif + 1);
 536                 } else {
 537                         /* don't touch branch counter on jump */
 538                         s->Code->inst[branch->If].inst2 |= R500_FC_B_OP1_NONE;
 539                         s->Code->inst[branch->If].inst3 = R500_FC_JUMP_ADDR(branch->Endif + 1);
 540                 }
 541
 542
 543                 s->CurrentBranchDepth--;
 544                 break;
 545         default:
 546                 rc_error(s->C, "%s: unknown opcode %s\n", __FUNCTION__, rc_get_opcode_info(inst->U.I.Opcode)->Name);
 547         }
 548 }
 549
 550 void r500BuildFragmentProgramHwCode(struct r300_fragment_program_compiler *compiler)
 551 {
 552         struct emit_state s;
 553         struct r500_fragment_program_code *code = &compiler->code->code.r500;
 554
 555         memset(&s, 0, sizeof(s));
 556         s.C = &compiler->Base;
 557         s.Code = code;
 558
 559         memset(code, 0, sizeof(*code));
 560         code->max_temp_idx = 1;
 561         code->inst_end = -1;
 562
 563         for(struct rc_instruction * inst = compiler->Base.Program.Instructions.Next;
 564             inst != &compiler->Base.Program.Instructions && !compiler->Base.Error;
 565             inst = inst->Next) {
 566                 if (inst->Type == RC_INSTRUCTION_NORMAL) {
 567                         const struct rc_opcode_info * opcode = rc_get_opcode_info(inst->U.I.Opcode);
 568
 569                         if (opcode->IsFlowControl) {
 570                                 emit_flowcontrol(&s, inst);
 571                         } else if (inst->U.I.Opcode == RC_OPCODE_BEGIN_TEX) {
 572                                 continue;
 573                         } else {
 574                                 emit_tex(compiler, &inst->U.I);
 575                         }
 576                 } else {
 577                         emit_paired(compiler, &inst->U.P);
 578                 }
 579         }
 580
 581         if (code->max_temp_idx >= 128)
 582                 rc_error(&compiler->Base, "Too many hardware temporaries used");
 583
 584         if (compiler->Base.Error)
 585                 return;
 586
 587         if (code->inst_end == -1 ||
 588             (code->inst[code->inst_end].inst0 & R500_INST_TYPE_MASK) != R500_INST_TYPE_OUT) {
 589                 /* This may happen when dead-code elimination is disabled or
 590                  * when most of the fragment program logic is leading to a KIL */
 591                 if (code->inst_end >= 511) {
 592                         rc_error(&compiler->Base, "Introducing fake OUT: Too many instructions");
 593                         return;
 594                 }
 595
 596                 int ip = ++code->inst_end;
 597                 code->inst[ip].inst0 = R500_INST_TYPE_OUT | R500_INST_TEX_SEM_WAIT;
 598         }
 599
 600         /* Enable full flow control mode if we are using loops or have if
 601          * statements nested at least four deep. */
 602         if (s.MaxBranchDepth >= 4 || s.LoopsReserved > 0) {
 603                 if (code->max_temp_idx < 1)
 604                         code->max_temp_idx = 1;
 605
 606                 code->us_fc_ctrl |= R500_FC_FULL_FC_EN;
 607         }
 608 }