src/mesa/drivers/dri/r300/compiler/r500_fragprog_emit.c

   1 /*
   2  * Copyright (C) 2005 Ben Skeggs.
   3  *
   4  * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
   5  * Adaptation and modification for ATI/AMD Radeon R500 GPU chipsets.
   6  *
   7  * All Rights Reserved.
   8  *
   9  * Permission is hereby granted, free of charge, to any person obtaining
  10  * a copy of this software and associated documentation files (the
  11  * "Software"), to deal in the Software without restriction, including
  12  * without limitation the rights to use, copy, modify, merge, publish,
  13  * distribute, sublicense, and/or sell copies of the Software, and to
  14  * permit persons to whom the Software is furnished to do so, subject to
  15  * the following conditions:
  16  *
  17  * The above copyright notice and this permission notice (including the
  18  * next paragraph) shall be included in all copies or substantial
  19  * portions of the Software.
  20  *
  21  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  22  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  23  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  24  * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  25  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  26  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  27  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  28  *
  29  */
  30
  31 /**
  32  * \file
  33  *
  34  * \author Ben Skeggs <darktama@iinet.net.au>
  35  *
  36  * \author Jerome Glisse <j.glisse@gmail.com>
  37  *
  38  * \author Corbin Simpson <MostAwesomeDude@gmail.com>
  39  *
  40  */
  41
  42 #include "r500_fragprog.h"
  43
  44 #include "../r300_reg.h"
  45
  46 #include "radeon_program_pair.h"
  47
  48
  49 #define PROG_CODE \
  50         struct r500_fragment_program_code *code = &c->code->code.r500
  51
  52 #define error(fmt, args...) do {                        \
  53                 rc_error(&c->Base, "%s::%s(): " fmt "\n",       \
  54                         __FILE__, __FUNCTION__, ##args);        \
  55         } while(0)
  56
  57
  58 struct branch_info {
  59         int If;
  60         int Else;
  61         int Endif;
  62 };
  63
  64 struct emit_state {
  65         struct radeon_compiler * C;
  66         struct r500_fragment_program_code * Code;
  67
  68         struct branch_info * Branches;
  69         unsigned int CurrentBranchDepth;
  70         unsigned int BranchesReserved;
  71
  72         unsigned int MaxBranchDepth;
  73 };
  74
  75 static unsigned int translate_rgb_op(struct r300_fragment_program_compiler *c, rc_opcode opcode)
  76 {
  77         switch(opcode) {
  78         case RC_OPCODE_CMP: return R500_ALU_RGBA_OP_CMP;
  79         case RC_OPCODE_DDX: return R500_ALU_RGBA_OP_MDH;
  80         case RC_OPCODE_DDY: return R500_ALU_RGBA_OP_MDV;
  81         case RC_OPCODE_DP3: return R500_ALU_RGBA_OP_DP3;
  82         case RC_OPCODE_DP4: return R500_ALU_RGBA_OP_DP4;
  83         case RC_OPCODE_FRC: return R500_ALU_RGBA_OP_FRC;
  84         default:
  85                 error("translate_rgb_op(%d): unknown opcode\n", opcode);
  86                 /* fall through */
  87         case RC_OPCODE_NOP:
  88                 /* fall through */
  89         case RC_OPCODE_MAD: return R500_ALU_RGBA_OP_MAD;
  90         case RC_OPCODE_MAX: return R500_ALU_RGBA_OP_MAX;
  91         case RC_OPCODE_MIN: return R500_ALU_RGBA_OP_MIN;
  92         case RC_OPCODE_REPL_ALPHA: return R500_ALU_RGBA_OP_SOP;
  93         }
  94 }
  95
  96 static unsigned int translate_alpha_op(struct r300_fragment_program_compiler *c, rc_opcode opcode)
  97 {
  98         switch(opcode) {
  99         case RC_OPCODE_CMP: return R500_ALPHA_OP_CMP;
 100         case RC_OPCODE_COS: return R500_ALPHA_OP_COS;
 101         case RC_OPCODE_DDX: return R500_ALPHA_OP_MDH;
 102         case RC_OPCODE_DDY: return R500_ALPHA_OP_MDV;
 103         case RC_OPCODE_DP3: return R500_ALPHA_OP_DP;
 104         case RC_OPCODE_DP4: return R500_ALPHA_OP_DP;
 105         case RC_OPCODE_EX2: return R500_ALPHA_OP_EX2;
 106         case RC_OPCODE_FRC: return R500_ALPHA_OP_FRC;
 107         case RC_OPCODE_LG2: return R500_ALPHA_OP_LN2;
 108         default:
 109                 error("translate_alpha_op(%d): unknown opcode\n", opcode);
 110                 /* fall through */
 111         case RC_OPCODE_NOP:
 112                 /* fall through */
 113         case RC_OPCODE_MAD: return R500_ALPHA_OP_MAD;
 114         case RC_OPCODE_MAX: return R500_ALPHA_OP_MAX;
 115         case RC_OPCODE_MIN: return R500_ALPHA_OP_MIN;
 116         case RC_OPCODE_RCP: return R500_ALPHA_OP_RCP;
 117         case RC_OPCODE_RSQ: return R500_ALPHA_OP_RSQ;
 118         case RC_OPCODE_SIN: return R500_ALPHA_OP_SIN;
 119         }
 120 }
 121
 122 static unsigned int fix_hw_swizzle(unsigned int swz)
 123 {
 124         if (swz == 5) swz = 6;
 125         if (swz == RC_SWIZZLE_UNUSED) swz = 4;
 126         return swz;
 127 }
 128
 129 static unsigned int translate_arg_rgb(struct rc_pair_instruction *inst, int arg)
 130 {
 131         unsigned int t = inst->RGB.Arg[arg].Source;
 132         int comp;
 133         t |= inst->RGB.Arg[arg].Negate << 11;
 134         t |= inst->RGB.Arg[arg].Abs << 12;
 135
 136         for(comp = 0; comp < 3; ++comp)
 137                 t |= fix_hw_swizzle(GET_SWZ(inst->RGB.Arg[arg].Swizzle, comp)) << (3*comp + 2);
 138
 139         return t;
 140 }
 141
 142 static unsigned int translate_arg_alpha(struct rc_pair_instruction *inst, int i)
 143 {
 144         unsigned int t = inst->Alpha.Arg[i].Source;
 145         t |= fix_hw_swizzle(inst->Alpha.Arg[i].Swizzle) << 2;
 146         t |= inst->Alpha.Arg[i].Negate << 5;
 147         t |= inst->Alpha.Arg[i].Abs << 6;
 148         return t;
 149 }
 150
 151 static uint32_t translate_alu_result_op(struct r300_fragment_program_compiler * c, rc_compare_func func)
 152 {
 153         switch(func) {
 154         case RC_COMPARE_FUNC_EQUAL: return R500_INST_ALU_RESULT_OP_EQ;
 155         case RC_COMPARE_FUNC_LESS: return R500_INST_ALU_RESULT_OP_LT;
 156         case RC_COMPARE_FUNC_GEQUAL: return R500_INST_ALU_RESULT_OP_GE;
 157         case RC_COMPARE_FUNC_NOTEQUAL: return R500_INST_ALU_RESULT_OP_NE;
 158         default:
 159                 rc_error(&c->Base, "%s: unsupported compare func %i\n", __FUNCTION__, func);
 160                 return 0;
 161         }
 162 }
 163
 164 static void use_temporary(struct r500_fragment_program_code* code, unsigned int index)
 165 {
 166         if (index > code->max_temp_idx)
 167                 code->max_temp_idx = index;
 168 }
 169
 170 static unsigned int use_source(struct r500_fragment_program_code* code, struct radeon_pair_instruction_source src)
 171 {
 172         if (src.File == RC_FILE_CONSTANT) {
 173                 return src.Index | 0x100;
 174         } else if (src.File == RC_FILE_TEMPORARY) {
 175                 use_temporary(code, src.Index);
 176                 return src.Index;
 177         }
 178
 179         return 0;
 180 }
 181
 182
 183 /**
 184  * Emit a paired ALU instruction.
 185  */
 186 static void emit_paired(struct r300_fragment_program_compiler *c, struct rc_pair_instruction *inst)
 187 {
 188         PROG_CODE;
 189
 190         if (code->inst_end >= 511) {
 191                 error("emit_alu: Too many instructions");
 192                 return;
 193         }
 194
 195         int ip = ++code->inst_end;
 196
 197         code->inst[ip].inst5 = translate_rgb_op(c, inst->RGB.Opcode);
 198         code->inst[ip].inst4 = translate_alpha_op(c, inst->Alpha.Opcode);
 199
 200         if (inst->RGB.OutputWriteMask || inst->Alpha.OutputWriteMask || inst->Alpha.DepthWriteMask) {
 201                 code->inst[ip].inst0 = R500_INST_TYPE_OUT;
 202                 if (inst->WriteALUResult) {
 203                         error("%s: cannot write output and ALU result at the same time");
 204                         return;
 205                 }
 206         } else {
 207                 code->inst[ip].inst0 = R500_INST_TYPE_ALU;
 208         }
 209         code->inst[ip].inst0 |= R500_INST_TEX_SEM_WAIT;
 210
 211         code->inst[ip].inst0 |= (inst->RGB.WriteMask << 11) | (inst->Alpha.WriteMask << 14);
 212         code->inst[ip].inst0 |= (inst->RGB.OutputWriteMask << 15) | (inst->Alpha.OutputWriteMask << 18);
 213         if (inst->Alpha.DepthWriteMask) {
 214                 code->inst[ip].inst4 |= R500_ALPHA_W_OMASK;
 215                 c->code->writes_depth = 1;
 216         }
 217
 218         code->inst[ip].inst4 |= R500_ALPHA_ADDRD(inst->Alpha.DestIndex);
 219         code->inst[ip].inst5 |= R500_ALU_RGBA_ADDRD(inst->RGB.DestIndex);
 220         use_temporary(code, inst->Alpha.DestIndex);
 221         use_temporary(code, inst->RGB.DestIndex);
 222
 223         if (inst->RGB.Saturate)
 224                 code->inst[ip].inst0 |= R500_INST_RGB_CLAMP;
 225         if (inst->Alpha.Saturate)
 226                 code->inst[ip].inst0 |= R500_INST_ALPHA_CLAMP;
 227
 228         code->inst[ip].inst1 |= R500_RGB_ADDR0(use_source(code, inst->RGB.Src[0]));
 229         code->inst[ip].inst1 |= R500_RGB_ADDR1(use_source(code, inst->RGB.Src[1]));
 230         code->inst[ip].inst1 |= R500_RGB_ADDR2(use_source(code, inst->RGB.Src[2]));
 231
 232         code->inst[ip].inst2 |= R500_ALPHA_ADDR0(use_source(code, inst->Alpha.Src[0]));
 233         code->inst[ip].inst2 |= R500_ALPHA_ADDR1(use_source(code, inst->Alpha.Src[1]));
 234         code->inst[ip].inst2 |= R500_ALPHA_ADDR2(use_source(code, inst->Alpha.Src[2]));
 235
 236         code->inst[ip].inst3 |= translate_arg_rgb(inst, 0) << R500_ALU_RGB_SEL_A_SHIFT;
 237         code->inst[ip].inst3 |= translate_arg_rgb(inst, 1) << R500_ALU_RGB_SEL_B_SHIFT;
 238         code->inst[ip].inst5 |= translate_arg_rgb(inst, 2) << R500_ALU_RGBA_SEL_C_SHIFT;
 239
 240         code->inst[ip].inst4 |= translate_arg_alpha(inst, 0) << R500_ALPHA_SEL_A_SHIFT;
 241         code->inst[ip].inst4 |= translate_arg_alpha(inst, 1) << R500_ALPHA_SEL_B_SHIFT;
 242         code->inst[ip].inst5 |= translate_arg_alpha(inst, 2) << R500_ALU_RGBA_ALPHA_SEL_C_SHIFT;
 243
 244     code->inst[ip].inst3 |= R500_ALU_RGB_TARGET(inst->RGB.Target);
 245     code->inst[ip].inst4 |= R500_ALPHA_TARGET(inst->Alpha.Target);
 246
 247         if (inst->WriteALUResult) {
 248                 code->inst[ip].inst3 |= R500_ALU_RGB_WMASK;
 249
 250                 if (inst->WriteALUResult == RC_ALURESULT_X)
 251                         code->inst[ip].inst0 |= R500_INST_ALU_RESULT_SEL_RED;
 252                 else
 253                         code->inst[ip].inst0 |= R500_INST_ALU_RESULT_SEL_ALPHA;
 254
 255                 code->inst[ip].inst0 |= translate_alu_result_op(c, inst->ALUResultCompare);
 256         }
 257 }
 258
 259 static unsigned int translate_strq_swizzle(unsigned int swizzle)
 260 {
 261         unsigned int swiz = 0;
 262         int i;
 263         for (i = 0; i < 4; i++)
 264                 swiz |= (GET_SWZ(swizzle, i) & 0x3) << i*2;
 265         return swiz;
 266 }
 267
 268 /**
 269  * Emit a single TEX instruction
 270  */
 271 static int emit_tex(struct r300_fragment_program_compiler *c, struct rc_sub_instruction *inst)
 272 {
 273         PROG_CODE;
 274
 275         if (code->inst_end >= 511) {
 276                 error("emit_tex: Too many instructions");
 277                 return 0;
 278         }
 279
 280         int ip = ++code->inst_end;
 281
 282         code->inst[ip].inst0 = R500_INST_TYPE_TEX
 283                 | (inst->DstReg.WriteMask << 11)
 284                 | R500_INST_TEX_SEM_WAIT;
 285         code->inst[ip].inst1 = R500_TEX_ID(inst->TexSrcUnit)
 286                 | R500_TEX_SEM_ACQUIRE | R500_TEX_IGNORE_UNCOVERED;
 287
 288         if (inst->TexSrcTarget == RC_TEXTURE_RECT)
 289                 code->inst[ip].inst1 |= R500_TEX_UNSCALED;
 290
 291         switch (inst->Opcode) {
 292         case RC_OPCODE_KIL:
 293                 code->inst[ip].inst1 |= R500_TEX_INST_TEXKILL;
 294                 break;
 295         case RC_OPCODE_TEX:
 296                 code->inst[ip].inst1 |= R500_TEX_INST_LD;
 297                 break;
 298         case RC_OPCODE_TXB:
 299                 code->inst[ip].inst1 |= R500_TEX_INST_LODBIAS;
 300                 break;
 301         case RC_OPCODE_TXP:
 302                 code->inst[ip].inst1 |= R500_TEX_INST_PROJ;
 303                 break;
 304         default:
 305                 error("emit_tex can't handle opcode %x\n", inst->Opcode);
 306         }
 307
 308         use_temporary(code, inst->SrcReg[0].Index);
 309         if (inst->Opcode != RC_OPCODE_KIL)
 310                 use_temporary(code, inst->DstReg.Index);
 311
 312         code->inst[ip].inst2 = R500_TEX_SRC_ADDR(inst->SrcReg[0].Index)
 313                 | (translate_strq_swizzle(inst->SrcReg[0].Swizzle) << 8)
 314                 | R500_TEX_DST_ADDR(inst->DstReg.Index)
 315                 | R500_TEX_DST_R_SWIZ_R | R500_TEX_DST_G_SWIZ_G
 316                 | R500_TEX_DST_B_SWIZ_B | R500_TEX_DST_A_SWIZ_A;
 317
 318         return 1;
 319 }
 320
 321 static void grow_branches(struct emit_state * s)
 322 {
 323         unsigned int newreserved = s->BranchesReserved * 2;
 324         struct branch_info * newbranches;
 325
 326         if (!newreserved)
 327                 newreserved = 4;
 328
 329         newbranches = memory_pool_malloc(&s->C->Pool, newreserved*sizeof(struct branch_info));
 330         memcpy(newbranches, s->Branches, s->CurrentBranchDepth*sizeof(struct branch_info));
 331
 332         s->Branches = newbranches;
 333         s->BranchesReserved = newreserved;
 334 }
 335
 336 static void emit_flowcontrol(struct emit_state * s, struct rc_instruction * inst)
 337 {
 338         if (s->Code->inst_end >= 511) {
 339                 rc_error(s->C, "emit_tex: Too many instructions");
 340                 return;
 341         }
 342
 343         unsigned int newip = ++s->Code->inst_end;
 344
 345         s->Code->inst[newip].inst0 = R500_INST_TYPE_FC | R500_INST_ALU_WAIT;
 346
 347         if (inst->U.I.Opcode == RC_OPCODE_IF) {
 348                 if (s->CurrentBranchDepth >= 32) {
 349                         rc_error(s->C, "Branch depth exceeds hardware limit");
 350                         return;
 351                 }
 352
 353                 if (s->CurrentBranchDepth >= s->BranchesReserved)
 354                         grow_branches(s);
 355
 356                 struct branch_info * branch = &s->Branches[s->CurrentBranchDepth++];
 357                 branch->If = newip;
 358                 branch->Else = -1;
 359                 branch->Endif = -1;
 360
 361                 if (s->CurrentBranchDepth > s->MaxBranchDepth)
 362                         s->MaxBranchDepth = s->CurrentBranchDepth;
 363
 364                 /* actual instruction is filled in at ENDIF time */
 365         } else if (inst->U.I.Opcode == RC_OPCODE_ELSE) {
 366                 if (!s->CurrentBranchDepth) {
 367                         rc_error(s->C, "%s: got ELSE outside a branch", __FUNCTION__);
 368                         return;
 369                 }
 370
 371                 struct branch_info * branch = &s->Branches[s->CurrentBranchDepth - 1];
 372                 branch->Else = newip;
 373
 374                 /* actual instruction is filled in at ENDIF time */
 375         } else if (inst->U.I.Opcode == RC_OPCODE_ENDIF) {
 376                 if (!s->CurrentBranchDepth) {
 377                         rc_error(s->C, "%s: got ELSE outside a branch", __FUNCTION__);
 378                         return;
 379                 }
 380
 381                 struct branch_info * branch = &s->Branches[s->CurrentBranchDepth - 1];
 382                 branch->Endif = newip;
 383
 384                 s->Code->inst[branch->If].inst2 = R500_FC_OP_JUMP
 385                         | R500_FC_A_OP_NONE /* no address stack */
 386                         | R500_FC_JUMP_FUNC(0x0f) /* jump if ALU result is false */
 387                         | R500_FC_B_OP0_INCR /* increment branch counter if stay */
 388                 ;
 389
 390                 if (branch->Else >= 0) {
 391                         /* increment branch counter also if jump */
 392                         s->Code->inst[branch->If].inst2 |= R500_FC_B_OP1_INCR;
 393                         s->Code->inst[branch->If].inst3 = R500_FC_JUMP_ADDR(branch->Else + 1);
 394
 395                         s->Code->inst[branch->Else].inst2 = R500_FC_OP_JUMP
 396                                 | R500_FC_A_OP_NONE /* no address stack */
 397                                 | R500_FC_B_ELSE /* all active pixels want to jump */
 398                                 | R500_FC_B_OP0_NONE /* no counter op if stay */
 399                                 | R500_FC_B_OP1_DECR /* decrement branch counter if jump */
 400                                 | R500_FC_B_POP_CNT(1)
 401                         ;
 402                         s->Code->inst[branch->Else].inst3 = R500_FC_JUMP_ADDR(branch->Endif + 1);
 403                 } else {
 404                         /* don't touch branch counter on jump */
 405                         s->Code->inst[branch->If].inst2 |= R500_FC_B_OP1_NONE;
 406                         s->Code->inst[branch->If].inst3 = R500_FC_JUMP_ADDR(branch->Endif + 1);
 407                 }
 408
 409                 s->Code->inst[branch->Endif].inst2 = R500_FC_OP_JUMP
 410                         | R500_FC_A_OP_NONE /* no address stack */
 411                         | R500_FC_JUMP_ANY /* docs says set this, but I don't understand why */
 412                         | R500_FC_B_OP0_DECR /* decrement branch counter if stay */
 413                         | R500_FC_B_OP1_NONE /* no branch counter if stay */
 414                         | R500_FC_B_POP_CNT(1)
 415                 ;
 416                 s->Code->inst[branch->Endif].inst3 = R500_FC_JUMP_ADDR(branch->Endif + 1);
 417
 418                 s->CurrentBranchDepth--;
 419         } else {
 420                 rc_error(s->C, "%s: unknown opcode %i\n", __FUNCTION__, inst->U.I.Opcode);
 421         }
 422 }
 423
 424 void r500BuildFragmentProgramHwCode(struct r300_fragment_program_compiler *compiler)
 425 {
 426         struct emit_state s;
 427         struct r500_fragment_program_code *code = &compiler->code->code.r500;
 428
 429         memset(&s, 0, sizeof(s));
 430         s.C = &compiler->Base;
 431         s.Code = code;
 432
 433         memset(code, 0, sizeof(*code));
 434         code->max_temp_idx = 1;
 435         code->inst_end = -1;
 436
 437         for(struct rc_instruction * inst = compiler->Base.Program.Instructions.Next;
 438             inst != &compiler->Base.Program.Instructions && !compiler->Base.Error;
 439             inst = inst->Next) {
 440                 if (inst->Type == RC_INSTRUCTION_NORMAL) {
 441                         const struct rc_opcode_info * opcode = rc_get_opcode_info(inst->U.I.Opcode);
 442
 443                         if (opcode->IsFlowControl) {
 444                                 emit_flowcontrol(&s, inst);
 445                         } else if (inst->U.I.Opcode == RC_OPCODE_BEGIN_TEX) {
 446                                 continue;
 447                         } else {
 448                                 emit_tex(compiler, &inst->U.I);
 449                         }
 450                 } else {
 451                         emit_paired(compiler, &inst->U.P);
 452                 }
 453         }
 454
 455         if (code->max_temp_idx >= 128)
 456                 rc_error(&compiler->Base, "Too many hardware temporaries used");
 457
 458         if (compiler->Base.Error)
 459                 return;
 460
 461         if ((code->inst[code->inst_end].inst0 & R500_INST_TYPE_MASK) != R500_INST_TYPE_OUT) {
 462                 /* This may happen when dead-code elimination is disabled or
 463                  * when most of the fragment program logic is leading to a KIL */
 464                 if (code->inst_end >= 511) {
 465                         rc_error(&compiler->Base, "Introducing fake OUT: Too many instructions");
 466                         return;
 467                 }
 468
 469                 int ip = ++code->inst_end;
 470                 code->inst[ip].inst0 = R500_INST_TYPE_OUT | R500_INST_TEX_SEM_WAIT;
 471         }
 472
 473         if (s.MaxBranchDepth >= 4) {
 474                 if (code->max_temp_idx < 1)
 475                         code->max_temp_idx = 1;
 476
 477                 code->us_fc_ctrl |= R500_FC_FULL_FC_EN;
 478         }
 479 }