2 * Copyright (C) 2005 Ben Skeggs.
4 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
5 * Adaptation and modification for ATI/AMD Radeon R500 GPU chipsets.
9 * Permission is hereby granted, free of charge, to any person obtaining
10 * a copy of this software and associated documentation files (the
11 * "Software"), to deal in the Software without restriction, including
12 * without limitation the rights to use, copy, modify, merge, publish,
13 * distribute, sublicense, and/or sell copies of the Software, and to
14 * permit persons to whom the Software is furnished to do so, subject to
15 * the following conditions:
17 * The above copyright notice and this permission notice (including the
18 * next paragraph) shall be included in all copies or substantial
19 * portions of the Software.
21 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
22 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
23 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
24 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
25 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
26 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
27 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
34 * \author Ben Skeggs <darktama@iinet.net.au>
36 * \author Jerome Glisse <j.glisse@gmail.com>
38 * \author Corbin Simpson <MostAwesomeDude@gmail.com>
42 #include "r500_fragprog.h"
44 #include "../r300_reg.h"
46 #include "radeon_program_pair.h"
48 #define MAX_BRANCH_DEPTH_FULL 32
49 #define MAX_BRANCH_DEPTH_PARTIAL 4
52 struct r500_fragment_program_code *code = &c->code->code.r500
54 #define error(fmt, args...) do { \
55 rc_error(&c->Base, "%s::%s(): " fmt "\n", \
56 __FILE__, __FUNCTION__, ##args); \
80 struct radeon_compiler
* C
;
81 struct r500_fragment_program_code
* Code
;
83 struct branch_info
* Branches
;
84 unsigned int CurrentBranchDepth
;
85 unsigned int BranchesReserved
;
87 struct loop_info
* Loops
;
88 unsigned int CurrentLoopDepth
;
89 unsigned int LoopsReserved
;
91 unsigned int MaxBranchDepth
;
95 static unsigned int translate_rgb_op(struct r300_fragment_program_compiler
*c
, rc_opcode opcode
)
98 case RC_OPCODE_CMP
: return R500_ALU_RGBA_OP_CMP
;
99 case RC_OPCODE_DDX
: return R500_ALU_RGBA_OP_MDH
;
100 case RC_OPCODE_DDY
: return R500_ALU_RGBA_OP_MDV
;
101 case RC_OPCODE_DP3
: return R500_ALU_RGBA_OP_DP3
;
102 case RC_OPCODE_DP4
: return R500_ALU_RGBA_OP_DP4
;
103 case RC_OPCODE_FRC
: return R500_ALU_RGBA_OP_FRC
;
105 error("translate_rgb_op: unknown opcode %s\n", rc_get_opcode_info(opcode
)->Name
);
109 case RC_OPCODE_MAD
: return R500_ALU_RGBA_OP_MAD
;
110 case RC_OPCODE_MAX
: return R500_ALU_RGBA_OP_MAX
;
111 case RC_OPCODE_MIN
: return R500_ALU_RGBA_OP_MIN
;
112 case RC_OPCODE_REPL_ALPHA
: return R500_ALU_RGBA_OP_SOP
;
116 static unsigned int translate_alpha_op(struct r300_fragment_program_compiler
*c
, rc_opcode opcode
)
119 case RC_OPCODE_CMP
: return R500_ALPHA_OP_CMP
;
120 case RC_OPCODE_COS
: return R500_ALPHA_OP_COS
;
121 case RC_OPCODE_DDX
: return R500_ALPHA_OP_MDH
;
122 case RC_OPCODE_DDY
: return R500_ALPHA_OP_MDV
;
123 case RC_OPCODE_DP3
: return R500_ALPHA_OP_DP
;
124 case RC_OPCODE_DP4
: return R500_ALPHA_OP_DP
;
125 case RC_OPCODE_EX2
: return R500_ALPHA_OP_EX2
;
126 case RC_OPCODE_FRC
: return R500_ALPHA_OP_FRC
;
127 case RC_OPCODE_LG2
: return R500_ALPHA_OP_LN2
;
129 error("translate_alpha_op: unknown opcode %s\n", rc_get_opcode_info(opcode
)->Name
);
133 case RC_OPCODE_MAD
: return R500_ALPHA_OP_MAD
;
134 case RC_OPCODE_MAX
: return R500_ALPHA_OP_MAX
;
135 case RC_OPCODE_MIN
: return R500_ALPHA_OP_MIN
;
136 case RC_OPCODE_RCP
: return R500_ALPHA_OP_RCP
;
137 case RC_OPCODE_RSQ
: return R500_ALPHA_OP_RSQ
;
138 case RC_OPCODE_SIN
: return R500_ALPHA_OP_SIN
;
142 static unsigned int fix_hw_swizzle(unsigned int swz
)
145 case RC_SWIZZLE_ZERO
:
146 case RC_SWIZZLE_UNUSED
:
149 case RC_SWIZZLE_HALF
:
160 static unsigned int translate_arg_rgb(struct rc_pair_instruction
*inst
, int arg
)
162 unsigned int t
= inst
->RGB
.Arg
[arg
].Source
;
164 t
|= inst
->RGB
.Arg
[arg
].Negate
<< 11;
165 t
|= inst
->RGB
.Arg
[arg
].Abs
<< 12;
167 for(comp
= 0; comp
< 3; ++comp
)
168 t
|= fix_hw_swizzle(GET_SWZ(inst
->RGB
.Arg
[arg
].Swizzle
, comp
)) << (3*comp
+ 2);
173 static unsigned int translate_arg_alpha(struct rc_pair_instruction
*inst
, int i
)
175 unsigned int t
= inst
->Alpha
.Arg
[i
].Source
;
176 t
|= fix_hw_swizzle(inst
->Alpha
.Arg
[i
].Swizzle
) << 2;
177 t
|= inst
->Alpha
.Arg
[i
].Negate
<< 5;
178 t
|= inst
->Alpha
.Arg
[i
].Abs
<< 6;
182 static uint32_t translate_alu_result_op(struct r300_fragment_program_compiler
* c
, rc_compare_func func
)
185 case RC_COMPARE_FUNC_EQUAL
: return R500_INST_ALU_RESULT_OP_EQ
;
186 case RC_COMPARE_FUNC_LESS
: return R500_INST_ALU_RESULT_OP_LT
;
187 case RC_COMPARE_FUNC_GEQUAL
: return R500_INST_ALU_RESULT_OP_GE
;
188 case RC_COMPARE_FUNC_NOTEQUAL
: return R500_INST_ALU_RESULT_OP_NE
;
190 rc_error(&c
->Base
, "%s: unsupported compare func %i\n", __FUNCTION__
, func
);
195 static void use_temporary(struct r500_fragment_program_code
* code
, unsigned int index
)
197 if (index
> code
->max_temp_idx
)
198 code
->max_temp_idx
= index
;
201 static unsigned int use_source(struct r500_fragment_program_code
* code
, struct radeon_pair_instruction_source src
)
203 if (src
.File
== RC_FILE_CONSTANT
) {
204 return src
.Index
| 0x100;
205 } else if (src
.File
== RC_FILE_TEMPORARY
) {
206 use_temporary(code
, src
.Index
);
214 * NOP the specified instruction if it is not a texture lookup.
216 static void alu_nop(struct r300_fragment_program_compiler
*c
, int ip
)
220 if ((code
->inst
[ip
].inst0
& 0x3) != R500_INST_TYPE_TEX
) {
221 code
->inst
[ip
].inst0
|= R500_INST_NOP
;
226 * Emit a paired ALU instruction.
228 static void emit_paired(struct r300_fragment_program_compiler
*c
, struct rc_pair_instruction
*inst
)
232 if (code
->inst_end
>= 511) {
233 error("emit_alu: Too many instructions");
237 int ip
= ++code
->inst_end
;
239 /* Quirk: MDH/MDV (DDX/DDY) need a NOP on previous non-TEX instructions. */
240 if (inst
->RGB
.Opcode
== RC_OPCODE_DDX
|| inst
->Alpha
.Opcode
== RC_OPCODE_DDX
||
241 inst
->RGB
.Opcode
== RC_OPCODE_DDY
|| inst
->Alpha
.Opcode
== RC_OPCODE_DDY
) {
247 code
->inst
[ip
].inst5
= translate_rgb_op(c
, inst
->RGB
.Opcode
);
248 code
->inst
[ip
].inst4
= translate_alpha_op(c
, inst
->Alpha
.Opcode
);
250 if (inst
->RGB
.OutputWriteMask
|| inst
->Alpha
.OutputWriteMask
|| inst
->Alpha
.DepthWriteMask
) {
251 code
->inst
[ip
].inst0
= R500_INST_TYPE_OUT
;
252 if (inst
->WriteALUResult
) {
253 error("%s: cannot write output and ALU result at the same time");
257 code
->inst
[ip
].inst0
= R500_INST_TYPE_ALU
;
259 code
->inst
[ip
].inst0
|= R500_INST_TEX_SEM_WAIT
;
261 code
->inst
[ip
].inst0
|= (inst
->RGB
.WriteMask
<< 11) | (inst
->Alpha
.WriteMask
<< 14);
262 code
->inst
[ip
].inst0
|= (inst
->RGB
.OutputWriteMask
<< 15) | (inst
->Alpha
.OutputWriteMask
<< 18);
263 if (inst
->Alpha
.DepthWriteMask
) {
264 code
->inst
[ip
].inst4
|= R500_ALPHA_W_OMASK
;
265 c
->code
->writes_depth
= 1;
268 code
->inst
[ip
].inst4
|= R500_ALPHA_ADDRD(inst
->Alpha
.DestIndex
);
269 code
->inst
[ip
].inst5
|= R500_ALU_RGBA_ADDRD(inst
->RGB
.DestIndex
);
270 use_temporary(code
, inst
->Alpha
.DestIndex
);
271 use_temporary(code
, inst
->RGB
.DestIndex
);
273 if (inst
->RGB
.Saturate
)
274 code
->inst
[ip
].inst0
|= R500_INST_RGB_CLAMP
;
275 if (inst
->Alpha
.Saturate
)
276 code
->inst
[ip
].inst0
|= R500_INST_ALPHA_CLAMP
;
278 code
->inst
[ip
].inst1
|= R500_RGB_ADDR0(use_source(code
, inst
->RGB
.Src
[0]));
279 code
->inst
[ip
].inst1
|= R500_RGB_ADDR1(use_source(code
, inst
->RGB
.Src
[1]));
280 code
->inst
[ip
].inst1
|= R500_RGB_ADDR2(use_source(code
, inst
->RGB
.Src
[2]));
282 code
->inst
[ip
].inst2
|= R500_ALPHA_ADDR0(use_source(code
, inst
->Alpha
.Src
[0]));
283 code
->inst
[ip
].inst2
|= R500_ALPHA_ADDR1(use_source(code
, inst
->Alpha
.Src
[1]));
284 code
->inst
[ip
].inst2
|= R500_ALPHA_ADDR2(use_source(code
, inst
->Alpha
.Src
[2]));
286 code
->inst
[ip
].inst3
|= translate_arg_rgb(inst
, 0) << R500_ALU_RGB_SEL_A_SHIFT
;
287 code
->inst
[ip
].inst3
|= translate_arg_rgb(inst
, 1) << R500_ALU_RGB_SEL_B_SHIFT
;
288 code
->inst
[ip
].inst5
|= translate_arg_rgb(inst
, 2) << R500_ALU_RGBA_SEL_C_SHIFT
;
290 code
->inst
[ip
].inst4
|= translate_arg_alpha(inst
, 0) << R500_ALPHA_SEL_A_SHIFT
;
291 code
->inst
[ip
].inst4
|= translate_arg_alpha(inst
, 1) << R500_ALPHA_SEL_B_SHIFT
;
292 code
->inst
[ip
].inst5
|= translate_arg_alpha(inst
, 2) << R500_ALU_RGBA_ALPHA_SEL_C_SHIFT
;
294 code
->inst
[ip
].inst3
|= R500_ALU_RGB_TARGET(inst
->RGB
.Target
);
295 code
->inst
[ip
].inst4
|= R500_ALPHA_TARGET(inst
->Alpha
.Target
);
297 if (inst
->WriteALUResult
) {
298 code
->inst
[ip
].inst3
|= R500_ALU_RGB_WMASK
;
300 if (inst
->WriteALUResult
== RC_ALURESULT_X
)
301 code
->inst
[ip
].inst0
|= R500_INST_ALU_RESULT_SEL_RED
;
303 code
->inst
[ip
].inst0
|= R500_INST_ALU_RESULT_SEL_ALPHA
;
305 code
->inst
[ip
].inst0
|= translate_alu_result_op(c
, inst
->ALUResultCompare
);
309 static unsigned int translate_strq_swizzle(unsigned int swizzle
)
311 unsigned int swiz
= 0;
313 for (i
= 0; i
< 4; i
++)
314 swiz
|= (GET_SWZ(swizzle
, i
) & 0x3) << i
*2;
319 * Emit a single TEX instruction
321 static int emit_tex(struct r300_fragment_program_compiler
*c
, struct rc_sub_instruction
*inst
)
325 if (code
->inst_end
>= 511) {
326 error("emit_tex: Too many instructions");
330 int ip
= ++code
->inst_end
;
332 code
->inst
[ip
].inst0
= R500_INST_TYPE_TEX
333 | (inst
->DstReg
.WriteMask
<< 11)
334 | R500_INST_TEX_SEM_WAIT
;
335 code
->inst
[ip
].inst1
= R500_TEX_ID(inst
->TexSrcUnit
)
336 | R500_TEX_SEM_ACQUIRE
| R500_TEX_IGNORE_UNCOVERED
;
338 if (inst
->TexSrcTarget
== RC_TEXTURE_RECT
)
339 code
->inst
[ip
].inst1
|= R500_TEX_UNSCALED
;
341 switch (inst
->Opcode
) {
343 code
->inst
[ip
].inst1
|= R500_TEX_INST_TEXKILL
;
346 code
->inst
[ip
].inst1
|= R500_TEX_INST_LD
;
349 code
->inst
[ip
].inst1
|= R500_TEX_INST_LODBIAS
;
352 code
->inst
[ip
].inst1
|= R500_TEX_INST_PROJ
;
355 error("emit_tex can't handle opcode %s\n", rc_get_opcode_info(inst
->Opcode
)->Name
);
358 use_temporary(code
, inst
->SrcReg
[0].Index
);
359 if (inst
->Opcode
!= RC_OPCODE_KIL
)
360 use_temporary(code
, inst
->DstReg
.Index
);
362 code
->inst
[ip
].inst2
= R500_TEX_SRC_ADDR(inst
->SrcReg
[0].Index
)
363 | (translate_strq_swizzle(inst
->SrcReg
[0].Swizzle
) << 8)
364 | R500_TEX_DST_ADDR(inst
->DstReg
.Index
)
365 | R500_TEX_DST_R_SWIZ_R
| R500_TEX_DST_G_SWIZ_G
366 | R500_TEX_DST_B_SWIZ_B
| R500_TEX_DST_A_SWIZ_A
;
371 static void emit_flowcontrol(struct emit_state
* s
, struct rc_instruction
* inst
)
373 if (s
->Code
->inst_end
>= 511) {
374 rc_error(s
->C
, "emit_tex: Too many instructions");
378 unsigned int newip
= ++s
->Code
->inst_end
;
380 /* Currently all loops use the same integer constant to intialize
381 * the loop variables. */
382 if(!s
->Code
->int_constants
[0]) {
383 s
->Code
->int_constants
[0] = R500_FC_INT_CONST_KR(0xff);
384 s
->Code
->int_constant_count
= 1;
386 s
->Code
->inst
[newip
].inst0
= R500_INST_TYPE_FC
| R500_INST_ALU_WAIT
;
388 switch(inst
->U
.I
.Opcode
){
389 struct branch_info
* branch
;
390 struct loop_info
* loop
;
391 case RC_OPCODE_BGNLOOP
:
392 memory_pool_array_reserve(&s
->C
->Pool
, struct loop_info
,
393 s
->Loops
, s
->CurrentLoopDepth
, s
->LoopsReserved
, 1);
395 loop
= &s
->Loops
[s
->CurrentLoopDepth
++];
396 memset(loop
, 0, sizeof(struct loop_info
));
397 loop
->BranchDepth
= s
->CurrentBranchDepth
;
398 loop
->BgnLoop
= newip
;
400 s
->Code
->inst
[newip
].inst2
= R500_FC_OP_LOOP
401 | R500_FC_JUMP_FUNC(0x00)
402 | R500_FC_IGNORE_UNCOVERED
406 loop
= &s
->Loops
[s
->CurrentLoopDepth
- 1];
407 memory_pool_array_reserve(&s
->C
->Pool
, int, loop
->Brks
,
408 loop
->BrkCount
, loop
->BrkReserved
, 1);
410 loop
->Brks
[loop
->BrkCount
++] = newip
;
411 s
->Code
->inst
[newip
].inst2
= R500_FC_OP_BREAKLOOP
412 | R500_FC_JUMP_FUNC(0xff)
415 s
->CurrentBranchDepth
- loop
->BranchDepth
)
416 | R500_FC_IGNORE_UNCOVERED
421 loop
= &s
->Loops
[s
->CurrentLoopDepth
- 1];
422 memory_pool_array_reserve(&s
->C
->Pool
, int, loop
->Conts
,
423 loop
->ContCount
, loop
->ContReserved
, 1);
424 loop
->Conts
[loop
->ContCount
++] = newip
;
425 s
->Code
->inst
[newip
].inst2
= R500_FC_OP_CONTINUE
426 | R500_FC_JUMP_FUNC(0xff)
429 s
->CurrentBranchDepth
- loop
->BranchDepth
)
430 | R500_FC_IGNORE_UNCOVERED
434 case RC_OPCODE_ENDLOOP
:
436 loop
= &s
->Loops
[s
->CurrentLoopDepth
- 1];
438 s
->Code
->inst
[newip
].inst2
= R500_FC_OP_ENDLOOP
439 | R500_FC_JUMP_FUNC(0xff)
441 | R500_FC_IGNORE_UNCOVERED
443 /* The constant integer at index 0 is used by all loops. */
444 s
->Code
->inst
[newip
].inst3
= R500_FC_INT_ADDR(0)
445 | R500_FC_JUMP_ADDR(loop
->BgnLoop
+ 1)
448 /* Set jump address and int constant for BGNLOOP */
449 s
->Code
->inst
[loop
->BgnLoop
].inst3
= R500_FC_INT_ADDR(0)
450 | R500_FC_JUMP_ADDR(newip
)
453 /* Set jump address for the BRK instructions. */
454 while(loop
->BrkCount
--) {
455 s
->Code
->inst
[loop
->Brks
[loop
->BrkCount
]].inst3
=
456 R500_FC_JUMP_ADDR(newip
+ 1);
459 /* Set jump address for CONT instructions. */
460 while(loop
->ContCount
--) {
461 s
->Code
->inst
[loop
->Conts
[loop
->ContCount
]].inst3
=
462 R500_FC_JUMP_ADDR(newip
);
464 s
->CurrentLoopDepth
--;
468 if ( s
->CurrentBranchDepth
>= MAX_BRANCH_DEPTH_FULL
) {
469 rc_error(s
->C
, "Branch depth exceeds hardware limit");
472 memory_pool_array_reserve(&s
->C
->Pool
, struct branch_info
,
473 s
->Branches
, s
->CurrentBranchDepth
, s
->BranchesReserved
, 1);
475 branch
= &s
->Branches
[s
->CurrentBranchDepth
++];
480 if (s
->CurrentBranchDepth
> s
->MaxBranchDepth
)
481 s
->MaxBranchDepth
= s
->CurrentBranchDepth
;
483 /* actual instruction is filled in at ENDIF time */
487 if (!s
->CurrentBranchDepth
) {
488 rc_error(s
->C
, "%s: got ELSE outside a branch", __FUNCTION__
);
492 branch
= &s
->Branches
[s
->CurrentBranchDepth
- 1];
493 branch
->Else
= newip
;
495 /* actual instruction is filled in at ENDIF time */
498 case RC_OPCODE_ENDIF
:
499 if (!s
->CurrentBranchDepth
) {
500 rc_error(s
->C
, "%s: got ELSE outside a branch", __FUNCTION__
);
504 branch
= &s
->Branches
[s
->CurrentBranchDepth
- 1];
505 branch
->Endif
= newip
;
507 s
->Code
->inst
[branch
->Endif
].inst2
= R500_FC_OP_JUMP
508 | R500_FC_A_OP_NONE
/* no address stack */
509 | R500_FC_JUMP_ANY
/* docs says set this, but I don't understand why */
510 | R500_FC_B_OP0_DECR
/* decrement branch counter if stay */
511 | R500_FC_B_OP1_NONE
/* no branch counter if stay */
512 | R500_FC_B_POP_CNT(1)
514 s
->Code
->inst
[branch
->Endif
].inst3
= R500_FC_JUMP_ADDR(branch
->Endif
+ 1);
515 s
->Code
->inst
[branch
->If
].inst2
= R500_FC_OP_JUMP
516 | R500_FC_A_OP_NONE
/* no address stack */
517 | R500_FC_JUMP_FUNC(0x0f) /* jump if ALU result is false */
518 | R500_FC_B_OP0_INCR
/* increment branch counter if stay */
519 | R500_FC_IGNORE_UNCOVERED
522 if (branch
->Else
>= 0) {
523 /* increment branch counter also if jump */
524 s
->Code
->inst
[branch
->If
].inst2
|= R500_FC_B_OP1_INCR
;
525 s
->Code
->inst
[branch
->If
].inst3
= R500_FC_JUMP_ADDR(branch
->Else
+ 1);
527 s
->Code
->inst
[branch
->Else
].inst2
= R500_FC_OP_JUMP
528 | R500_FC_A_OP_NONE
/* no address stack */
529 | R500_FC_B_ELSE
/* all active pixels want to jump */
530 | R500_FC_B_OP0_NONE
/* no counter op if stay */
531 | R500_FC_B_OP1_DECR
/* decrement branch counter if jump */
532 | R500_FC_B_POP_CNT(1)
534 s
->Code
->inst
[branch
->Else
].inst3
= R500_FC_JUMP_ADDR(branch
->Endif
+ 1);
536 /* don't touch branch counter on jump */
537 s
->Code
->inst
[branch
->If
].inst2
|= R500_FC_B_OP1_NONE
;
538 s
->Code
->inst
[branch
->If
].inst3
= R500_FC_JUMP_ADDR(branch
->Endif
+ 1);
542 s
->CurrentBranchDepth
--;
545 rc_error(s
->C
, "%s: unknown opcode %s\n", __FUNCTION__
, rc_get_opcode_info(inst
->U
.I
.Opcode
)->Name
);
549 void r500BuildFragmentProgramHwCode(struct r300_fragment_program_compiler
*compiler
)
552 struct r500_fragment_program_code
*code
= &compiler
->code
->code
.r500
;
554 memset(&s
, 0, sizeof(s
));
555 s
.C
= &compiler
->Base
;
558 memset(code
, 0, sizeof(*code
));
559 code
->max_temp_idx
= 1;
562 for(struct rc_instruction
* inst
= compiler
->Base
.Program
.Instructions
.Next
;
563 inst
!= &compiler
->Base
.Program
.Instructions
&& !compiler
->Base
.Error
;
565 if (inst
->Type
== RC_INSTRUCTION_NORMAL
) {
566 const struct rc_opcode_info
* opcode
= rc_get_opcode_info(inst
->U
.I
.Opcode
);
568 if (opcode
->IsFlowControl
) {
569 emit_flowcontrol(&s
, inst
);
570 } else if (inst
->U
.I
.Opcode
== RC_OPCODE_BEGIN_TEX
) {
573 emit_tex(compiler
, &inst
->U
.I
);
576 emit_paired(compiler
, &inst
->U
.P
);
580 if (code
->max_temp_idx
>= 128)
581 rc_error(&compiler
->Base
, "Too many hardware temporaries used");
583 if (compiler
->Base
.Error
)
586 if (code
->inst_end
== -1 ||
587 (code
->inst
[code
->inst_end
].inst0
& R500_INST_TYPE_MASK
) != R500_INST_TYPE_OUT
) {
588 /* This may happen when dead-code elimination is disabled or
589 * when most of the fragment program logic is leading to a KIL */
590 if (code
->inst_end
>= 511) {
591 rc_error(&compiler
->Base
, "Introducing fake OUT: Too many instructions");
595 int ip
= ++code
->inst_end
;
596 code
->inst
[ip
].inst0
= R500_INST_TYPE_OUT
| R500_INST_TEX_SEM_WAIT
;
599 /* Enable full flow control mode if we are using loops or have if
600 * statements nested at least four deep. */
601 if (s
.MaxBranchDepth
>= 4 || s
.LoopsReserved
> 0) {
602 if (code
->max_temp_idx
< 1)
603 code
->max_temp_idx
= 1;
605 code
->us_fc_ctrl
|= R500_FC_FULL_FC_EN
;