src/mesa/drivers/dri/r300/compiler/r500_fragprog_emit.c

   1 /*
   2  * Copyright (C) 2005 Ben Skeggs.
   3  *
   4  * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
   5  * Adaptation and modification for ATI/AMD Radeon R500 GPU chipsets.
   6  *
   7  * All Rights Reserved.
   8  *
   9  * Permission is hereby granted, free of charge, to any person obtaining
  10  * a copy of this software and associated documentation files (the
  11  * "Software"), to deal in the Software without restriction, including
  12  * without limitation the rights to use, copy, modify, merge, publish,
  13  * distribute, sublicense, and/or sell copies of the Software, and to
  14  * permit persons to whom the Software is furnished to do so, subject to
  15  * the following conditions:
  16  *
  17  * The above copyright notice and this permission notice (including the
  18  * next paragraph) shall be included in all copies or substantial
  19  * portions of the Software.
  20  *
  21  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  22  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  23  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  24  * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  25  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  26  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  27  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  28  *
  29  */
  30
  31 /**
  32  * \file
  33  *
  34  * \author Ben Skeggs <darktama@iinet.net.au>
  35  *
  36  * \author Jerome Glisse <j.glisse@gmail.com>
  37  *
  38  * \author Corbin Simpson <MostAwesomeDude@gmail.com>
  39  *
  40  * \todo Depth write, WPOS/FOGC inputs
  41  *
  42  * \todo FogOption
  43  *
  44  */
  45
  46 #include "r500_fragprog.h"
  47
  48 #include "../r300_reg.h"
  49
  50 #include "radeon_program_pair.h"
  51
  52
  53 #define PROG_CODE \
  54         struct r300_fragment_program_compiler *c = (struct r300_fragment_program_compiler*)data; \
  55         struct r500_fragment_program_code *code = &c->code->code.r500
  56
  57 #define error(fmt, args...) do {                        \
  58                 rc_error(&c->Base, "%s::%s(): " fmt "\n",       \
  59                         __FILE__, __FUNCTION__, ##args);        \
  60         } while(0)
  61
  62
  63 static GLuint translate_rgb_op(struct r300_fragment_program_compiler *c, GLuint opcode)
  64 {
  65         switch(opcode) {
  66         case OPCODE_CMP: return R500_ALU_RGBA_OP_CMP;
  67         case OPCODE_DDX: return R500_ALU_RGBA_OP_MDH;
  68         case OPCODE_DDY: return R500_ALU_RGBA_OP_MDV;
  69         case OPCODE_DP3: return R500_ALU_RGBA_OP_DP3;
  70         case OPCODE_DP4: return R500_ALU_RGBA_OP_DP4;
  71         case OPCODE_FRC: return R500_ALU_RGBA_OP_FRC;
  72         default:
  73                 error("translate_rgb_op(%d): unknown opcode\n", opcode);
  74                 /* fall through */
  75         case OPCODE_NOP:
  76                 /* fall through */
  77         case OPCODE_MAD: return R500_ALU_RGBA_OP_MAD;
  78         case OPCODE_MAX: return R500_ALU_RGBA_OP_MAX;
  79         case OPCODE_MIN: return R500_ALU_RGBA_OP_MIN;
  80         case OPCODE_REPL_ALPHA: return R500_ALU_RGBA_OP_SOP;
  81         }
  82 }
  83
  84 static GLuint translate_alpha_op(struct r300_fragment_program_compiler *c, GLuint opcode)
  85 {
  86         switch(opcode) {
  87         case OPCODE_CMP: return R500_ALPHA_OP_CMP;
  88         case OPCODE_COS: return R500_ALPHA_OP_COS;
  89         case OPCODE_DDX: return R500_ALPHA_OP_MDH;
  90         case OPCODE_DDY: return R500_ALPHA_OP_MDV;
  91         case OPCODE_DP3: return R500_ALPHA_OP_DP;
  92         case OPCODE_DP4: return R500_ALPHA_OP_DP;
  93         case OPCODE_EX2: return R500_ALPHA_OP_EX2;
  94         case OPCODE_FRC: return R500_ALPHA_OP_FRC;
  95         case OPCODE_LG2: return R500_ALPHA_OP_LN2;
  96         default:
  97                 error("translate_alpha_op(%d): unknown opcode\n", opcode);
  98                 /* fall through */
  99         case OPCODE_NOP:
 100                 /* fall through */
 101         case OPCODE_MAD: return R500_ALPHA_OP_MAD;
 102         case OPCODE_MAX: return R500_ALPHA_OP_MAX;
 103         case OPCODE_MIN: return R500_ALPHA_OP_MIN;
 104         case OPCODE_RCP: return R500_ALPHA_OP_RCP;
 105         case OPCODE_RSQ: return R500_ALPHA_OP_RSQ;
 106         case OPCODE_SIN: return R500_ALPHA_OP_SIN;
 107         }
 108 }
 109
 110 static GLuint fix_hw_swizzle(GLuint swz)
 111 {
 112         if (swz == 5) swz = 6;
 113         if (swz == SWIZZLE_NIL) swz = 4;
 114         return swz;
 115 }
 116
 117 static GLuint translate_arg_rgb(struct radeon_pair_instruction *inst, int arg)
 118 {
 119         GLuint t = inst->RGB.Arg[arg].Source;
 120         int comp;
 121         t |= inst->RGB.Arg[arg].Negate << 11;
 122         t |= inst->RGB.Arg[arg].Abs << 12;
 123
 124         for(comp = 0; comp < 3; ++comp)
 125                 t |= fix_hw_swizzle(GET_SWZ(inst->RGB.Arg[arg].Swizzle, comp)) << (3*comp + 2);
 126
 127         return t;
 128 }
 129
 130 static GLuint translate_arg_alpha(struct radeon_pair_instruction *inst, int i)
 131 {
 132         GLuint t = inst->Alpha.Arg[i].Source;
 133         t |= fix_hw_swizzle(inst->Alpha.Arg[i].Swizzle) << 2;
 134         t |= inst->Alpha.Arg[i].Negate << 5;
 135         t |= inst->Alpha.Arg[i].Abs << 6;
 136         return t;
 137 }
 138
 139 static void use_temporary(struct r500_fragment_program_code* code, GLuint index)
 140 {
 141         if (index > code->max_temp_idx)
 142                 code->max_temp_idx = index;
 143 }
 144
 145 static GLuint use_source(struct r500_fragment_program_code* code, struct radeon_pair_instruction_source src)
 146 {
 147         if (!src.Constant)
 148                 use_temporary(code, src.Index);
 149         return src.Index | src.Constant << 8;
 150 }
 151
 152
 153 /**
 154  * Emit a paired ALU instruction.
 155  */
 156 static GLboolean emit_paired(void *data, struct radeon_pair_instruction *inst)
 157 {
 158         PROG_CODE;
 159
 160         if (code->inst_end >= 511) {
 161                 error("emit_alu: Too many instructions");
 162                 return GL_FALSE;
 163         }
 164
 165         int ip = ++code->inst_end;
 166
 167         code->inst[ip].inst5 = translate_rgb_op(c, inst->RGB.Opcode);
 168         code->inst[ip].inst4 = translate_alpha_op(c, inst->Alpha.Opcode);
 169
 170         if (inst->RGB.OutputWriteMask || inst->Alpha.OutputWriteMask || inst->Alpha.DepthWriteMask)
 171                 code->inst[ip].inst0 = R500_INST_TYPE_OUT;
 172         else
 173                 code->inst[ip].inst0 = R500_INST_TYPE_ALU;
 174         code->inst[ip].inst0 |= R500_INST_TEX_SEM_WAIT;
 175
 176         code->inst[ip].inst0 |= (inst->RGB.WriteMask << 11) | (inst->Alpha.WriteMask << 14);
 177         code->inst[ip].inst0 |= (inst->RGB.OutputWriteMask << 15) | (inst->Alpha.OutputWriteMask << 18);
 178         if (inst->Alpha.DepthWriteMask) {
 179                 code->inst[ip].inst4 |= R500_ALPHA_W_OMASK;
 180                 c->code->writes_depth = GL_TRUE;
 181         }
 182
 183         code->inst[ip].inst4 |= R500_ALPHA_ADDRD(inst->Alpha.DestIndex);
 184         code->inst[ip].inst5 |= R500_ALU_RGBA_ADDRD(inst->RGB.DestIndex);
 185         use_temporary(code, inst->Alpha.DestIndex);
 186         use_temporary(code, inst->RGB.DestIndex);
 187
 188         if (inst->RGB.Saturate)
 189                 code->inst[ip].inst0 |= R500_INST_RGB_CLAMP;
 190         if (inst->Alpha.Saturate)
 191                 code->inst[ip].inst0 |= R500_INST_ALPHA_CLAMP;
 192
 193         code->inst[ip].inst1 |= R500_RGB_ADDR0(use_source(code, inst->RGB.Src[0]));
 194         code->inst[ip].inst1 |= R500_RGB_ADDR1(use_source(code, inst->RGB.Src[1]));
 195         code->inst[ip].inst1 |= R500_RGB_ADDR2(use_source(code, inst->RGB.Src[2]));
 196
 197         code->inst[ip].inst2 |= R500_ALPHA_ADDR0(use_source(code, inst->Alpha.Src[0]));
 198         code->inst[ip].inst2 |= R500_ALPHA_ADDR1(use_source(code, inst->Alpha.Src[1]));
 199         code->inst[ip].inst2 |= R500_ALPHA_ADDR2(use_source(code, inst->Alpha.Src[2]));
 200
 201         code->inst[ip].inst3 |= translate_arg_rgb(inst, 0) << R500_ALU_RGB_SEL_A_SHIFT;
 202         code->inst[ip].inst3 |= translate_arg_rgb(inst, 1) << R500_ALU_RGB_SEL_B_SHIFT;
 203         code->inst[ip].inst5 |= translate_arg_rgb(inst, 2) << R500_ALU_RGBA_SEL_C_SHIFT;
 204
 205         code->inst[ip].inst4 |= translate_arg_alpha(inst, 0) << R500_ALPHA_SEL_A_SHIFT;
 206         code->inst[ip].inst4 |= translate_arg_alpha(inst, 1) << R500_ALPHA_SEL_B_SHIFT;
 207         code->inst[ip].inst5 |= translate_arg_alpha(inst, 2) << R500_ALU_RGBA_ALPHA_SEL_C_SHIFT;
 208
 209         return GL_TRUE;
 210 }
 211
 212 static GLuint translate_strq_swizzle(GLuint swizzle)
 213 {
 214         GLuint swiz = 0;
 215         int i;
 216         for (i = 0; i < 4; i++)
 217                 swiz |= (GET_SWZ(swizzle, i) & 0x3) << i*2;
 218         return swiz;
 219 }
 220
 221 /**
 222  * Emit a single TEX instruction
 223  */
 224 static GLboolean emit_tex(void *data, struct radeon_pair_texture_instruction *inst)
 225 {
 226         PROG_CODE;
 227
 228         if (code->inst_end >= 511) {
 229                 error("emit_tex: Too many instructions");
 230                 return GL_FALSE;
 231         }
 232
 233         int ip = ++code->inst_end;
 234
 235         code->inst[ip].inst0 = R500_INST_TYPE_TEX
 236                 | (inst->WriteMask << 11)
 237                 | R500_INST_TEX_SEM_WAIT;
 238         code->inst[ip].inst1 = R500_TEX_ID(inst->TexSrcUnit)
 239                 | R500_TEX_SEM_ACQUIRE | R500_TEX_IGNORE_UNCOVERED;
 240
 241         if (inst->TexSrcTarget == TEXTURE_RECT_INDEX)
 242                 code->inst[ip].inst1 |= R500_TEX_UNSCALED;
 243
 244         switch (inst->Opcode) {
 245         case RADEON_OPCODE_KIL:
 246                 code->inst[ip].inst1 |= R500_TEX_INST_TEXKILL;
 247                 break;
 248         case RADEON_OPCODE_TEX:
 249                 code->inst[ip].inst1 |= R500_TEX_INST_LD;
 250                 break;
 251         case RADEON_OPCODE_TXB:
 252                 code->inst[ip].inst1 |= R500_TEX_INST_LODBIAS;
 253                 break;
 254         case RADEON_OPCODE_TXP:
 255                 code->inst[ip].inst1 |= R500_TEX_INST_PROJ;
 256                 break;
 257         default:
 258                 error("emit_tex can't handle opcode %x\n", inst->Opcode);
 259         }
 260
 261         code->inst[ip].inst2 = R500_TEX_SRC_ADDR(inst->SrcIndex)
 262                 | (translate_strq_swizzle(inst->SrcSwizzle) << 8)
 263                 | R500_TEX_DST_ADDR(inst->DestIndex)
 264                 | R500_TEX_DST_R_SWIZ_R | R500_TEX_DST_G_SWIZ_G
 265                 | R500_TEX_DST_B_SWIZ_B | R500_TEX_DST_A_SWIZ_A;
 266
 267         return GL_TRUE;
 268 }
 269
 270 static const struct radeon_pair_handler pair_handler = {
 271         .EmitPaired = emit_paired,
 272         .EmitTex = emit_tex,
 273         .MaxHwTemps = 128
 274 };
 275
 276 void r500BuildFragmentProgramHwCode(struct r300_fragment_program_compiler *compiler)
 277 {
 278         struct r500_fragment_program_code *code = &compiler->code->code.r500;
 279
 280         _mesa_bzero(code, sizeof(*code));
 281         code->max_temp_idx = 1;
 282         code->inst_end = -1;
 283
 284         radeonPairProgram(compiler, &pair_handler, compiler);
 285         if (compiler->Base.Error)
 286                 return;
 287
 288         if ((code->inst[code->inst_end].inst0 & R500_INST_TYPE_MASK) != R500_INST_TYPE_OUT) {
 289                 /* This may happen when dead-code elimination is disabled or
 290                  * when most of the fragment program logic is leading to a KIL */
 291                 if (code->inst_end >= 511) {
 292                         rc_error(&compiler->Base, "Introducing fake OUT: Too many instructions");
 293                         return;
 294                 }
 295
 296                 int ip = ++code->inst_end;
 297                 code->inst[ip].inst0 = R500_INST_TYPE_OUT | R500_INST_TEX_SEM_WAIT;
 298         }
 299 }