2 * Copyright (C) 2009 Nicolai Haehnle.
6 * Permission is hereby granted, free of charge, to any person obtaining
7 * a copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sublicense, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial
16 * portions of the Software.
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
28 #include "radeon_opcodes.h"
29 #include "radeon_program.h"
31 #include "radeon_program_constants.h"
33 struct rc_opcode_info rc_opcodes
[MAX_RC_OPCODE
] = {
35 .Opcode
= RC_OPCODE_NOP
,
39 .Opcode
= RC_OPCODE_ILLEGAL_OPCODE
,
40 .Name
= "ILLEGAL OPCODE"
43 .Opcode
= RC_OPCODE_ABS
,
50 .Opcode
= RC_OPCODE_ADD
,
57 .Opcode
= RC_OPCODE_ARL
,
63 .Opcode
= RC_OPCODE_CEIL
,
70 .Opcode
= RC_OPCODE_CLAMP
,
77 .Opcode
= RC_OPCODE_CMP
,
84 .Opcode
= RC_OPCODE_COS
,
91 .Opcode
= RC_OPCODE_DDX
,
98 .Opcode
= RC_OPCODE_DDY
,
105 .Opcode
= RC_OPCODE_DP2
,
111 .Opcode
= RC_OPCODE_DP3
,
117 .Opcode
= RC_OPCODE_DP4
,
123 .Opcode
= RC_OPCODE_DPH
,
129 .Opcode
= RC_OPCODE_DST
,
135 .Opcode
= RC_OPCODE_EX2
,
139 .IsStandardScalar
= 1
142 .Opcode
= RC_OPCODE_EXP
,
148 .Opcode
= RC_OPCODE_FLR
,
155 .Opcode
= RC_OPCODE_FRC
,
162 .Opcode
= RC_OPCODE_KIL
,
167 .Opcode
= RC_OPCODE_LG2
,
171 .IsStandardScalar
= 1
174 .Opcode
= RC_OPCODE_LIT
,
180 .Opcode
= RC_OPCODE_LOG
,
186 .Opcode
= RC_OPCODE_LRP
,
193 .Opcode
= RC_OPCODE_MAD
,
200 .Opcode
= RC_OPCODE_MAX
,
207 .Opcode
= RC_OPCODE_MIN
,
214 .Opcode
= RC_OPCODE_MOV
,
221 .Opcode
= RC_OPCODE_MUL
,
228 .Opcode
= RC_OPCODE_POW
,
232 .IsStandardScalar
= 1
235 .Opcode
= RC_OPCODE_RCP
,
239 .IsStandardScalar
= 1
242 .Opcode
= RC_OPCODE_RSQ
,
246 .IsStandardScalar
= 1
249 .Opcode
= RC_OPCODE_SCS
,
255 .Opcode
= RC_OPCODE_SEQ
,
262 .Opcode
= RC_OPCODE_SFL
,
269 .Opcode
= RC_OPCODE_SGE
,
276 .Opcode
= RC_OPCODE_SGT
,
283 .Opcode
= RC_OPCODE_SIN
,
287 .IsStandardScalar
= 1
290 .Opcode
= RC_OPCODE_SLE
,
297 .Opcode
= RC_OPCODE_SLT
,
304 .Opcode
= RC_OPCODE_SNE
,
311 .Opcode
= RC_OPCODE_SSG
,
318 .Opcode
= RC_OPCODE_SUB
,
325 .Opcode
= RC_OPCODE_SWZ
,
332 .Opcode
= RC_OPCODE_XPD
,
338 .Opcode
= RC_OPCODE_TEX
,
345 .Opcode
= RC_OPCODE_TXB
,
352 .Opcode
= RC_OPCODE_TXD
,
359 .Opcode
= RC_OPCODE_TXL
,
366 .Opcode
= RC_OPCODE_TXP
,
373 .Opcode
= RC_OPCODE_IF
,
379 .Opcode
= RC_OPCODE_ELSE
,
385 .Opcode
= RC_OPCODE_ENDIF
,
391 .Opcode
= RC_OPCODE_BGNLOOP
,
397 .Opcode
= RC_OPCODE_BRK
,
403 .Opcode
= RC_OPCODE_ENDLOOP
,
409 .Opcode
= RC_OPCODE_CONT
,
415 .Opcode
= RC_OPCODE_REPL_ALPHA
,
416 .Name
= "REPL_ALPHA",
420 .Opcode
= RC_OPCODE_BEGIN_TEX
,
424 .Opcode
= RC_OPCODE_KILP
,
429 void rc_compute_sources_for_writemask(
430 const struct rc_instruction
*inst
,
431 unsigned int writemask
,
432 unsigned int *srcmasks
)
434 const struct rc_opcode_info
* opcode
= rc_get_opcode_info(inst
->U
.I
.Opcode
);
439 if (opcode
->Opcode
== RC_OPCODE_KIL
)
440 srcmasks
[0] |= RC_MASK_XYZW
;
441 else if (opcode
->Opcode
== RC_OPCODE_IF
)
442 srcmasks
[0] |= RC_MASK_X
;
447 if (opcode
->IsComponentwise
) {
448 for(unsigned int src
= 0; src
< opcode
->NumSrcRegs
; ++src
)
449 srcmasks
[src
] |= writemask
;
450 } else if (opcode
->IsStandardScalar
) {
451 for(unsigned int src
= 0; src
< opcode
->NumSrcRegs
; ++src
)
452 srcmasks
[src
] |= RC_MASK_X
;
454 switch(opcode
->Opcode
) {
456 srcmasks
[0] |= RC_MASK_X
;
459 srcmasks
[0] |= RC_MASK_XY
;
460 srcmasks
[1] |= RC_MASK_XY
;
464 srcmasks
[0] |= RC_MASK_XYZ
;
465 srcmasks
[1] |= RC_MASK_XYZ
;
468 srcmasks
[0] |= RC_MASK_XYZW
;
469 srcmasks
[1] |= RC_MASK_XYZW
;
472 srcmasks
[0] |= RC_MASK_XYZ
;
473 srcmasks
[1] |= RC_MASK_XYZW
;
477 srcmasks
[0] |= RC_MASK_W
;
480 switch (inst
->U
.I
.TexSrcTarget
) {
482 srcmasks
[0] |= RC_MASK_X
;
485 case RC_TEXTURE_RECT
:
486 case RC_TEXTURE_1D_ARRAY
:
487 srcmasks
[0] |= RC_MASK_XY
;
490 case RC_TEXTURE_CUBE
:
491 case RC_TEXTURE_2D_ARRAY
:
492 srcmasks
[0] |= RC_MASK_XYZ
;
497 srcmasks
[0] |= RC_MASK_Y
| RC_MASK_Z
;
498 srcmasks
[1] |= RC_MASK_Y
| RC_MASK_W
;
502 srcmasks
[0] |= RC_MASK_XY
;
505 srcmasks
[0] |= RC_MASK_X
| RC_MASK_Y
| RC_MASK_W
;