2 * Copyright (C) 2008 Nicolai Haehnle.
6 * Permission is hereby granted, free of charge, to any person obtaining
7 * a copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sublicense, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial
16 * portions of the Software.
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
31 * Perform temporary register allocation and attempt to pair off instructions
32 * in RGB and Alpha pairs. Also attempts to optimize the TEX instruction
33 * vs. ALU instruction scheduling.
36 #include "radeon_program_pair.h"
38 #include "radeon_common.h"
40 #include "memory_pool.h"
41 #include "shader/prog_print.h"
43 #define error(fmt, args...) do { \
44 fprintf(stderr, "r300 driver problem: %s::%s(): " fmt "\n", \
45 __FILE__, __FUNCTION__, ##args); \
49 struct pair_state_instruction
{
50 struct prog_instruction Instruction
;
51 GLuint IP
; /**< Position of this instruction in original program */
53 GLuint IsTex
:1; /**< Is a texture instruction */
54 GLuint NeedRGB
:1; /**< Needs the RGB ALU */
55 GLuint NeedAlpha
:1; /**< Needs the Alpha ALU */
56 GLuint IsTranscendent
:1; /**< Is a special transcendent instruction */
59 * Number of (read and write) dependencies that must be resolved before
60 * this instruction can be scheduled.
62 GLuint NumDependencies
:5;
65 * Next instruction in the linked list of ready instructions.
67 struct pair_state_instruction
*NextReady
;
70 * Values that this instruction writes
72 struct reg_value
*Values
[4];
77 * Used to keep track of which instructions read a value.
79 struct reg_value_reader
{
80 struct pair_state_instruction
*Reader
;
81 struct reg_value_reader
*Next
;
85 * Used to keep track which values are stored in each component of a
89 struct pair_state_instruction
*Writer
;
90 struct reg_value
*Next
; /**< Pointer to the next value to be written to the same PROGRAM_TEMPORARY component */
93 * Unordered linked list of instructions that read from this value.
95 struct reg_value_reader
*Readers
;
98 * Number of readers of this value. This is calculated during @ref scan_instructions
99 * and continually decremented during code emission.
100 * When this count reaches zero, the instruction that writes the @ref Next value
107 * Used to translate a PROGRAM_INPUT or PROGRAM_TEMPORARY Mesa register
108 * to the proper hardware temporary.
110 struct pair_register_translation
{
113 GLuint RefCount
:23; /**< # of times this occurs in an unscheduled instruction SrcReg or DstReg */
116 * Notes the value that is currently contained in each component
117 * (only used for PROGRAM_TEMPORARY registers).
119 struct reg_value
*Value
[4];
123 struct memory_pool Pool
;
124 struct gl_program
*Program
;
125 const struct radeon_pair_handler
*Handler
;
132 * Translate Mesa registers to hardware registers
134 struct pair_register_translation Inputs
[FRAG_ATTRIB_MAX
];
135 struct pair_register_translation Temps
[MAX_PROGRAM_TEMPS
];
138 GLuint RefCount
; /**< # of times this occurs in an unscheduled SrcReg or DstReg */
142 * Linked list of instructions that can be scheduled right now,
143 * based on which ALU/TEX resources they require.
145 struct pair_state_instruction
*ReadyFullALU
;
146 struct pair_state_instruction
*ReadyRGB
;
147 struct pair_state_instruction
*ReadyAlpha
;
148 struct pair_state_instruction
*ReadyTEX
;
152 static struct pair_register_translation
*get_register(struct pair_state
*s
, GLuint file
, GLuint index
)
155 case PROGRAM_TEMPORARY
: return &s
->Temps
[index
];
156 case PROGRAM_INPUT
: return &s
->Inputs
[index
];
161 static void alloc_hw_reg(struct pair_state
*s
, GLuint file
, GLuint index
, GLuint hwindex
)
163 struct pair_register_translation
*t
= get_register(s
, file
, index
);
164 ASSERT(!s
->HwTemps
[hwindex
].RefCount
);
165 ASSERT(!t
->Allocated
);
166 s
->HwTemps
[hwindex
].RefCount
= t
->RefCount
;
168 t
->HwIndex
= hwindex
;
171 static GLuint
get_hw_reg(struct pair_state
*s
, GLuint file
, GLuint index
)
175 struct pair_register_translation
*t
= get_register(s
, file
, index
);
177 error("get_hw_reg: %i[%i]\n", file
, index
);
184 for(hwindex
= 0; hwindex
< s
->Handler
->MaxHwTemps
; ++hwindex
)
185 if (!s
->HwTemps
[hwindex
].RefCount
)
188 if (hwindex
>= s
->Handler
->MaxHwTemps
) {
189 error("Ran out of hardware temporaries");
193 alloc_hw_reg(s
, file
, index
, hwindex
);
198 static void deref_hw_reg(struct pair_state
*s
, GLuint hwindex
)
200 if (!s
->HwTemps
[hwindex
].RefCount
) {
201 error("Hwindex %i refcount error", hwindex
);
205 s
->HwTemps
[hwindex
].RefCount
--;
208 static void add_pairinst_to_list(struct pair_state_instruction
**list
, struct pair_state_instruction
*pairinst
)
210 pairinst
->NextReady
= *list
;
215 * The given instruction has become ready. Link it into the ready
218 static void instruction_ready(struct pair_state
*s
, struct pair_state_instruction
*pairinst
)
221 _mesa_printf("instruction_ready(%i)\n", pairinst
->IP
);
224 add_pairinst_to_list(&s
->ReadyTEX
, pairinst
);
225 else if (!pairinst
->NeedAlpha
)
226 add_pairinst_to_list(&s
->ReadyRGB
, pairinst
);
227 else if (!pairinst
->NeedRGB
)
228 add_pairinst_to_list(&s
->ReadyAlpha
, pairinst
);
230 add_pairinst_to_list(&s
->ReadyFullALU
, pairinst
);
235 * Finally rewrite ADD, MOV, MUL as the appropriate native instruction
236 * and reverse the order of arguments for CMP.
238 static void final_rewrite(struct pair_state
*s
, struct prog_instruction
*inst
)
240 struct prog_src_register tmp
;
242 switch(inst
->Opcode
) {
244 inst
->SrcReg
[2] = inst
->SrcReg
[1];
245 inst
->SrcReg
[1].File
= PROGRAM_BUILTIN
;
246 inst
->SrcReg
[1].Swizzle
= SWIZZLE_1111
;
247 inst
->SrcReg
[1].Negate
= NEGATE_NONE
;
248 inst
->Opcode
= OPCODE_MAD
;
251 tmp
= inst
->SrcReg
[2];
252 inst
->SrcReg
[2] = inst
->SrcReg
[0];
253 inst
->SrcReg
[0] = tmp
;
256 /* AMD say we should use CMP.
257 * However, when we transform
260 * CMP tmp, -r0, -r0, 0;
262 * we get incorrect behaviour on R500 when r0 == 0.0.
263 * It appears that the R500 KIL hardware treats -0.0 as less
266 inst
->SrcReg
[1].File
= PROGRAM_BUILTIN
;
267 inst
->SrcReg
[1].Swizzle
= SWIZZLE_1111
;
268 inst
->SrcReg
[2].File
= PROGRAM_BUILTIN
;
269 inst
->SrcReg
[2].Swizzle
= SWIZZLE_0000
;
270 inst
->Opcode
= OPCODE_MAD
;
273 inst
->SrcReg
[2].File
= PROGRAM_BUILTIN
;
274 inst
->SrcReg
[2].Swizzle
= SWIZZLE_0000
;
275 inst
->Opcode
= OPCODE_MAD
;
285 * Classify an instruction according to which ALUs etc. it needs
287 static void classify_instruction(struct pair_state
*s
,
288 struct pair_state_instruction
*psi
)
290 psi
->NeedRGB
= (psi
->Instruction
.DstReg
.WriteMask
& WRITEMASK_XYZ
) ? 1 : 0;
291 psi
->NeedAlpha
= (psi
->Instruction
.DstReg
.WriteMask
& WRITEMASK_W
) ? 1 : 0;
293 switch(psi
->Instruction
.Opcode
) {
311 psi
->IsTranscendent
= 1;
328 error("Unknown opcode %d\n", psi
->Instruction
.Opcode
);
335 * Count which (input, temporary) register is read and written how often,
336 * and scan the instruction stream to find dependencies.
338 static void scan_instructions(struct pair_state
*s
)
340 struct prog_instruction
*source
;
343 for(source
= s
->Program
->Instructions
, ip
= 0;
344 source
->Opcode
!= OPCODE_END
;
346 struct pair_state_instruction
*pairinst
= memory_pool_malloc(&s
->Pool
, sizeof(*pairinst
));
347 memset(pairinst
, 0, sizeof(struct pair_state_instruction
));
349 pairinst
->Instruction
= *source
;
351 final_rewrite(s
, &pairinst
->Instruction
);
352 classify_instruction(s
, pairinst
);
354 int nsrc
= _mesa_num_inst_src_regs(pairinst
->Instruction
.Opcode
);
356 for(j
= 0; j
< nsrc
; j
++) {
357 struct pair_register_translation
*t
=
358 get_register(s
, pairinst
->Instruction
.SrcReg
[j
].File
, pairinst
->Instruction
.SrcReg
[j
].Index
);
364 if (pairinst
->Instruction
.SrcReg
[j
].File
== PROGRAM_TEMPORARY
) {
366 for(i
= 0; i
< 4; ++i
) {
367 GLuint swz
= GET_SWZ(pairinst
->Instruction
.SrcReg
[j
].Swizzle
, i
);
369 continue; /* constant or NIL swizzle */
371 continue; /* this is an undefined read */
373 /* Do not add a dependency if this instruction
374 * also rewrites the value. The code below adds
375 * a dependency for the DstReg, which is a superset
376 * of the SrcReg dependency. */
377 if (pairinst
->Instruction
.DstReg
.File
== PROGRAM_TEMPORARY
&&
378 pairinst
->Instruction
.DstReg
.Index
== pairinst
->Instruction
.SrcReg
[j
].Index
&&
379 GET_BIT(pairinst
->Instruction
.DstReg
.WriteMask
, swz
))
382 struct reg_value_reader
* r
= memory_pool_malloc(&s
->Pool
, sizeof(*r
));
383 pairinst
->NumDependencies
++;
384 t
->Value
[swz
]->NumReaders
++;
385 r
->Reader
= pairinst
;
386 r
->Next
= t
->Value
[swz
]->Readers
;
387 t
->Value
[swz
]->Readers
= r
;
392 int ndst
= _mesa_num_inst_dst_regs(pairinst
->Instruction
.Opcode
);
394 struct pair_register_translation
*t
=
395 get_register(s
, pairinst
->Instruction
.DstReg
.File
, pairinst
->Instruction
.DstReg
.Index
);
399 if (pairinst
->Instruction
.DstReg
.File
== PROGRAM_TEMPORARY
) {
401 for(j
= 0; j
< 4; ++j
) {
402 if (!GET_BIT(pairinst
->Instruction
.DstReg
.WriteMask
, j
))
405 struct reg_value
* v
= memory_pool_malloc(&s
->Pool
, sizeof(*v
));
406 memset(v
, 0, sizeof(struct reg_value
));
407 v
->Writer
= pairinst
;
409 pairinst
->NumDependencies
++;
410 t
->Value
[j
]->Next
= v
;
413 pairinst
->Values
[j
] = v
;
420 _mesa_printf("scan(%i): NumDeps = %i\n", ip
, pairinst
->NumDependencies
);
422 if (!pairinst
->NumDependencies
)
423 instruction_ready(s
, pairinst
);
426 /* Clear the PROGRAM_TEMPORARY state */
428 for(i
= 0; i
< MAX_PROGRAM_TEMPS
; ++i
) {
429 for(j
= 0; j
< 4; ++j
)
430 s
->Temps
[i
].Value
[j
] = 0;
436 * Reserve hardware temporary registers for the program inputs.
438 * @note This allocation is performed explicitly, because the order of inputs
439 * is determined by the RS hardware.
441 static void allocate_input_registers(struct pair_state
*s
)
443 GLuint InputsRead
= s
->Program
->InputsRead
;
448 if (InputsRead
& FRAG_BIT_COL0
)
449 alloc_hw_reg(s
, PROGRAM_INPUT
, FRAG_ATTRIB_COL0
, hwindex
++);
450 InputsRead
&= ~FRAG_BIT_COL0
;
452 /* Secondary color */
453 if (InputsRead
& FRAG_BIT_COL1
)
454 alloc_hw_reg(s
, PROGRAM_INPUT
, FRAG_ATTRIB_COL1
, hwindex
++);
455 InputsRead
&= ~FRAG_BIT_COL1
;
458 for (i
= 0; i
< 8; i
++) {
459 if (InputsRead
& (FRAG_BIT_TEX0
<< i
))
460 alloc_hw_reg(s
, PROGRAM_INPUT
, FRAG_ATTRIB_TEX0
+i
, hwindex
++);
462 InputsRead
&= ~FRAG_BITS_TEX_ANY
;
464 /* Fogcoords treated as a texcoord */
465 if (InputsRead
& FRAG_BIT_FOGC
)
466 alloc_hw_reg(s
, PROGRAM_INPUT
, FRAG_ATTRIB_FOGC
, hwindex
++);
467 InputsRead
&= ~FRAG_BIT_FOGC
;
469 /* fragment position treated as a texcoord */
470 if (InputsRead
& FRAG_BIT_WPOS
)
471 alloc_hw_reg(s
, PROGRAM_INPUT
, FRAG_ATTRIB_WPOS
, hwindex
++);
472 InputsRead
&= ~FRAG_BIT_WPOS
;
476 error("Don't know how to handle inputs 0x%x\n", InputsRead
);
480 static void decrement_dependencies(struct pair_state
*s
, struct pair_state_instruction
*pairinst
)
482 ASSERT(pairinst
->NumDependencies
> 0);
483 if (!--pairinst
->NumDependencies
)
484 instruction_ready(s
, pairinst
);
488 * Update the dependency tracking state based on what the instruction
489 * at the given IP does.
491 static void commit_instruction(struct pair_state
*s
, struct pair_state_instruction
*pairinst
)
493 struct prog_instruction
*inst
= &pairinst
->Instruction
;
496 _mesa_printf("commit_instruction(%i)\n", pairinst
->IP
);
498 if (inst
->DstReg
.File
== PROGRAM_TEMPORARY
) {
499 struct pair_register_translation
*t
= &s
->Temps
[inst
->DstReg
.Index
];
500 deref_hw_reg(s
, t
->HwIndex
);
503 for(i
= 0; i
< 4; ++i
) {
504 if (!GET_BIT(inst
->DstReg
.WriteMask
, i
))
507 t
->Value
[i
] = pairinst
->Values
[i
];
508 if (t
->Value
[i
]->NumReaders
) {
509 struct reg_value_reader
*r
;
510 for(r
= pairinst
->Values
[i
]->Readers
; r
; r
= r
->Next
)
511 decrement_dependencies(s
, r
->Reader
);
512 } else if (t
->Value
[i
]->Next
) {
513 /* This happens when the only reader writes
514 * the register at the same time */
515 decrement_dependencies(s
, t
->Value
[i
]->Next
->Writer
);
520 int nsrc
= _mesa_num_inst_src_regs(inst
->Opcode
);
522 for(i
= 0; i
< nsrc
; i
++) {
523 struct pair_register_translation
*t
= get_register(s
, inst
->SrcReg
[i
].File
, inst
->SrcReg
[i
].Index
);
527 deref_hw_reg(s
, get_hw_reg(s
, inst
->SrcReg
[i
].File
, inst
->SrcReg
[i
].Index
));
529 if (inst
->SrcReg
[i
].File
!= PROGRAM_TEMPORARY
)
533 for(j
= 0; j
< 4; ++j
) {
534 GLuint swz
= GET_SWZ(inst
->SrcReg
[i
].Swizzle
, j
);
540 /* Do not free a dependency if this instruction
541 * also rewrites the value. See scan_instructions. */
542 if (inst
->DstReg
.File
== PROGRAM_TEMPORARY
&&
543 inst
->DstReg
.Index
== inst
->SrcReg
[i
].Index
&&
544 GET_BIT(inst
->DstReg
.WriteMask
, swz
))
547 if (!--t
->Value
[swz
]->NumReaders
) {
548 if (t
->Value
[swz
]->Next
)
549 decrement_dependencies(s
, t
->Value
[swz
]->Next
->Writer
);
557 * Emit all ready texture instructions in a single block.
559 * Emit as a single block to (hopefully) sample many textures in parallel,
560 * and to avoid hardware indirections on R300.
562 * In R500, we don't really know when the result of a texture instruction
563 * arrives. So allocate all destinations first, to make sure they do not
564 * arrive early and overwrite a texture coordinate we're going to use later
567 static void emit_all_tex(struct pair_state
*s
)
569 struct pair_state_instruction
*readytex
;
570 struct pair_state_instruction
*pairinst
;
574 // Don't let the ready list change under us!
575 readytex
= s
->ReadyTEX
;
578 // Allocate destination hardware registers in one block to avoid conflicts.
579 for(pairinst
= readytex
; pairinst
; pairinst
= pairinst
->NextReady
) {
580 struct prog_instruction
*inst
= &pairinst
->Instruction
;
581 if (inst
->Opcode
!= OPCODE_KIL
)
582 get_hw_reg(s
, inst
->DstReg
.File
, inst
->DstReg
.Index
);
586 _mesa_printf(" BEGIN_TEX\n");
588 if (s
->Handler
->BeginTexBlock
)
589 s
->Error
= s
->Error
|| !s
->Handler
->BeginTexBlock(s
->UserData
);
591 for(pairinst
= readytex
; pairinst
; pairinst
= pairinst
->NextReady
) {
592 struct prog_instruction
*inst
= &pairinst
->Instruction
;
593 commit_instruction(s
, pairinst
);
595 if (inst
->Opcode
!= OPCODE_KIL
)
596 inst
->DstReg
.Index
= get_hw_reg(s
, inst
->DstReg
.File
, inst
->DstReg
.Index
);
597 inst
->SrcReg
[0].Index
= get_hw_reg(s
, inst
->SrcReg
[0].File
, inst
->SrcReg
[0].Index
);
601 _mesa_print_instruction(inst
);
605 struct radeon_pair_texture_instruction rpti
;
607 switch(inst
->Opcode
) {
608 case OPCODE_TEX
: rpti
.Opcode
= RADEON_OPCODE_TEX
; break;
609 case OPCODE_TXB
: rpti
.Opcode
= RADEON_OPCODE_TXB
; break;
610 case OPCODE_TXP
: rpti
.Opcode
= RADEON_OPCODE_TXP
; break;
612 case OPCODE_KIL
: rpti
.Opcode
= RADEON_OPCODE_KIL
; break;
615 rpti
.DestIndex
= inst
->DstReg
.Index
;
616 rpti
.WriteMask
= inst
->DstReg
.WriteMask
;
617 rpti
.TexSrcUnit
= inst
->TexSrcUnit
;
618 rpti
.TexSrcTarget
= inst
->TexSrcTarget
;
619 rpti
.SrcIndex
= inst
->SrcReg
[0].Index
;
620 rpti
.SrcSwizzle
= inst
->SrcReg
[0].Swizzle
;
622 s
->Error
= s
->Error
|| !s
->Handler
->EmitTex(s
->UserData
, &rpti
);
626 _mesa_printf(" END_TEX\n");
630 static int alloc_pair_source(struct pair_state
*s
, struct radeon_pair_instruction
*pair
,
631 struct prog_src_register src
, GLboolean rgb
, GLboolean alpha
)
634 int candidate_quality
= -1;
643 if (src
.File
== PROGRAM_TEMPORARY
|| src
.File
== PROGRAM_INPUT
) {
645 index
= get_hw_reg(s
, src
.File
, src
.Index
);
648 s
->Error
|= !s
->Handler
->EmitConst(s
->UserData
, src
.File
, src
.Index
, &index
);
651 for(i
= 0; i
< 3; ++i
) {
654 if (pair
->RGB
.Src
[i
].Used
) {
655 if (pair
->RGB
.Src
[i
].Constant
!= constant
||
656 pair
->RGB
.Src
[i
].Index
!= index
)
662 if (pair
->Alpha
.Src
[i
].Used
) {
663 if (pair
->Alpha
.Src
[i
].Constant
!= constant
||
664 pair
->Alpha
.Src
[i
].Index
!= index
)
669 if (q
> candidate_quality
) {
670 candidate_quality
= q
;
675 if (candidate
>= 0) {
677 pair
->RGB
.Src
[candidate
].Used
= 1;
678 pair
->RGB
.Src
[candidate
].Constant
= constant
;
679 pair
->RGB
.Src
[candidate
].Index
= index
;
682 pair
->Alpha
.Src
[candidate
].Used
= 1;
683 pair
->Alpha
.Src
[candidate
].Constant
= constant
;
684 pair
->Alpha
.Src
[candidate
].Index
= index
;
692 * Fill the given ALU instruction's opcodes and source operands into the given pair,
695 static GLboolean
fill_instruction_into_pair(
696 struct pair_state
*s
,
697 struct radeon_pair_instruction
*pair
,
698 struct pair_state_instruction
*pairinst
)
700 struct prog_instruction
*inst
= &pairinst
->Instruction
;
702 ASSERT(!pairinst
->NeedRGB
|| pair
->RGB
.Opcode
== OPCODE_NOP
);
703 ASSERT(!pairinst
->NeedAlpha
|| pair
->Alpha
.Opcode
== OPCODE_NOP
);
705 if (pairinst
->NeedRGB
) {
706 if (pairinst
->IsTranscendent
)
707 pair
->RGB
.Opcode
= OPCODE_REPL_ALPHA
;
709 pair
->RGB
.Opcode
= inst
->Opcode
;
710 if (inst
->SaturateMode
== SATURATE_ZERO_ONE
)
711 pair
->RGB
.Saturate
= 1;
713 if (pairinst
->NeedAlpha
) {
714 pair
->Alpha
.Opcode
= inst
->Opcode
;
715 if (inst
->SaturateMode
== SATURATE_ZERO_ONE
)
716 pair
->Alpha
.Saturate
= 1;
719 int nargs
= _mesa_num_inst_src_regs(inst
->Opcode
);
722 /* Special case for DDX/DDY (MDH/MDV). */
723 if (inst
->Opcode
== OPCODE_DDX
|| inst
->Opcode
== OPCODE_DDY
) {
724 if (pair
->RGB
.Src
[0].Used
|| pair
->Alpha
.Src
[0].Used
)
730 for(i
= 0; i
< nargs
; ++i
) {
732 if (pairinst
->NeedRGB
&& !pairinst
->IsTranscendent
) {
733 GLboolean srcrgb
= GL_FALSE
;
734 GLboolean srcalpha
= GL_FALSE
;
736 for(j
= 0; j
< 3; ++j
) {
737 GLuint swz
= GET_SWZ(inst
->SrcReg
[i
].Swizzle
, j
);
743 source
= alloc_pair_source(s
, pair
, inst
->SrcReg
[i
], srcrgb
, srcalpha
);
746 pair
->RGB
.Arg
[i
].Source
= source
;
747 pair
->RGB
.Arg
[i
].Swizzle
= inst
->SrcReg
[i
].Swizzle
& 0x1ff;
748 pair
->RGB
.Arg
[i
].Abs
= inst
->SrcReg
[i
].Abs
;
749 pair
->RGB
.Arg
[i
].Negate
= !!(inst
->SrcReg
[i
].Negate
& (NEGATE_X
| NEGATE_Y
| NEGATE_Z
));
751 if (pairinst
->NeedAlpha
) {
752 GLboolean srcrgb
= GL_FALSE
;
753 GLboolean srcalpha
= GL_FALSE
;
754 GLuint swz
= GET_SWZ(inst
->SrcReg
[i
].Swizzle
, pairinst
->IsTranscendent
? 0 : 3);
759 source
= alloc_pair_source(s
, pair
, inst
->SrcReg
[i
], srcrgb
, srcalpha
);
762 pair
->Alpha
.Arg
[i
].Source
= source
;
763 pair
->Alpha
.Arg
[i
].Swizzle
= swz
;
764 pair
->Alpha
.Arg
[i
].Abs
= inst
->SrcReg
[i
].Abs
;
765 pair
->Alpha
.Arg
[i
].Negate
= !!(inst
->SrcReg
[i
].Negate
& NEGATE_W
);
774 * Fill in the destination register information.
776 * This is split from filling in source registers because we want
777 * to avoid allocating hardware temporaries for destinations until
778 * we are absolutely certain that we're going to emit a certain
779 * instruction pairing.
781 static void fill_dest_into_pair(
782 struct pair_state
*s
,
783 struct radeon_pair_instruction
*pair
,
784 struct pair_state_instruction
*pairinst
)
786 struct prog_instruction
*inst
= &pairinst
->Instruction
;
788 if (inst
->DstReg
.File
== PROGRAM_OUTPUT
) {
789 if (inst
->DstReg
.Index
== FRAG_RESULT_COLOR
) {
790 pair
->RGB
.OutputWriteMask
|= inst
->DstReg
.WriteMask
& WRITEMASK_XYZ
;
791 pair
->Alpha
.OutputWriteMask
|= GET_BIT(inst
->DstReg
.WriteMask
, 3);
792 } else if (inst
->DstReg
.Index
== FRAG_RESULT_DEPTH
) {
793 pair
->Alpha
.DepthWriteMask
|= GET_BIT(inst
->DstReg
.WriteMask
, 3);
796 GLuint hwindex
= get_hw_reg(s
, inst
->DstReg
.File
, inst
->DstReg
.Index
);
797 if (pairinst
->NeedRGB
) {
798 pair
->RGB
.DestIndex
= hwindex
;
799 pair
->RGB
.WriteMask
|= inst
->DstReg
.WriteMask
& WRITEMASK_XYZ
;
801 if (pairinst
->NeedAlpha
) {
802 pair
->Alpha
.DestIndex
= hwindex
;
803 pair
->Alpha
.WriteMask
|= GET_BIT(inst
->DstReg
.WriteMask
, 3);
810 * Find a good ALU instruction or pair of ALU instruction and emit it.
812 * Prefer emitting full ALU instructions, so that when we reach a point
813 * where no full ALU instruction can be emitted, we have more candidates
814 * for RGB/Alpha pairing.
816 static void emit_alu(struct pair_state
*s
)
818 struct radeon_pair_instruction pair
;
819 struct pair_state_instruction
*psi
;
821 if (s
->ReadyFullALU
|| !(s
->ReadyRGB
&& s
->ReadyAlpha
)) {
822 if (s
->ReadyFullALU
) {
823 psi
= s
->ReadyFullALU
;
824 s
->ReadyFullALU
= s
->ReadyFullALU
->NextReady
;
825 } else if (s
->ReadyRGB
) {
827 s
->ReadyRGB
= s
->ReadyRGB
->NextReady
;
830 s
->ReadyAlpha
= s
->ReadyAlpha
->NextReady
;
833 _mesa_bzero(&pair
, sizeof(pair
));
834 fill_instruction_into_pair(s
, &pair
, psi
);
835 fill_dest_into_pair(s
, &pair
, psi
);
836 commit_instruction(s
, psi
);
838 struct pair_state_instruction
**prgb
;
839 struct pair_state_instruction
**palpha
;
841 /* Some pairings might fail because they require too
842 * many source slots; try all possible pairings if necessary */
843 for(prgb
= &s
->ReadyRGB
; *prgb
; prgb
= &(*prgb
)->NextReady
) {
844 for(palpha
= &s
->ReadyAlpha
; *palpha
; palpha
= &(*palpha
)->NextReady
) {
845 struct pair_state_instruction
* psirgb
= *prgb
;
846 struct pair_state_instruction
* psialpha
= *palpha
;
847 _mesa_bzero(&pair
, sizeof(pair
));
848 fill_instruction_into_pair(s
, &pair
, psirgb
);
849 if (!fill_instruction_into_pair(s
, &pair
, psialpha
))
851 *prgb
= (*prgb
)->NextReady
;
852 *palpha
= (*palpha
)->NextReady
;
853 fill_dest_into_pair(s
, &pair
, psirgb
);
854 fill_dest_into_pair(s
, &pair
, psialpha
);
855 commit_instruction(s
, psirgb
);
856 commit_instruction(s
, psialpha
);
861 /* No success in pairing; just take the first RGB instruction */
863 s
->ReadyRGB
= s
->ReadyRGB
->NextReady
;
865 _mesa_bzero(&pair
, sizeof(pair
));
866 fill_instruction_into_pair(s
, &pair
, psi
);
867 fill_dest_into_pair(s
, &pair
, psi
);
868 commit_instruction(s
, psi
);
873 radeonPrintPairInstruction(&pair
);
875 s
->Error
= s
->Error
|| !s
->Handler
->EmitPaired(s
->UserData
, &pair
);
879 GLboolean
radeonPairProgram(struct gl_program
*program
,
880 const struct radeon_pair_handler
* handler
, void *userdata
)
884 _mesa_bzero(&s
, sizeof(s
));
885 memory_pool_init(&s
.Pool
);
888 s
.UserData
= userdata
;
889 s
.Debug
= (RADEON_DEBUG
& DEBUG_PIXEL
) ? GL_TRUE
: GL_FALSE
;
890 s
.Verbose
= GL_FALSE
&& s
.Debug
;
893 _mesa_printf("Emit paired program\n");
895 scan_instructions(&s
);
896 allocate_input_registers(&s
);
899 (s
.ReadyTEX
|| s
.ReadyRGB
|| s
.ReadyAlpha
|| s
.ReadyFullALU
)) {
903 while(s
.ReadyFullALU
|| s
.ReadyRGB
|| s
.ReadyAlpha
)
908 _mesa_printf(" END\n");
910 memory_pool_destroy(&s
.Pool
);
916 static void print_pair_src(int i
, struct radeon_pair_instruction_source
* src
)
918 _mesa_printf(" Src%i = %s[%i]", i
, src
->Constant
? "CNST" : "TEMP", src
->Index
);
921 static const char* opcode_string(GLuint opcode
)
923 if (opcode
== OPCODE_REPL_ALPHA
)
926 return _mesa_opcode_string(opcode
);
929 static int num_pairinst_args(GLuint opcode
)
931 if (opcode
== OPCODE_REPL_ALPHA
)
934 return _mesa_num_inst_src_regs(opcode
);
937 static char swizzle_char(GLuint swz
)
940 case SWIZZLE_X
: return 'x';
941 case SWIZZLE_Y
: return 'y';
942 case SWIZZLE_Z
: return 'z';
943 case SWIZZLE_W
: return 'w';
944 case SWIZZLE_ZERO
: return '0';
945 case SWIZZLE_ONE
: return '1';
946 case SWIZZLE_NIL
: return '_';
951 void radeonPrintPairInstruction(struct radeon_pair_instruction
*inst
)
956 _mesa_printf(" RGB: ");
957 for(i
= 0; i
< 3; ++i
) {
958 if (inst
->RGB
.Src
[i
].Used
)
959 print_pair_src(i
, inst
->RGB
.Src
+ i
);
962 _mesa_printf(" Alpha:");
963 for(i
= 0; i
< 3; ++i
) {
964 if (inst
->Alpha
.Src
[i
].Used
)
965 print_pair_src(i
, inst
->Alpha
.Src
+ i
);
969 _mesa_printf(" %s%s", opcode_string(inst
->RGB
.Opcode
), inst
->RGB
.Saturate
? "_SAT" : "");
970 if (inst
->RGB
.WriteMask
)
971 _mesa_printf(" TEMP[%i].%s%s%s", inst
->RGB
.DestIndex
,
972 (inst
->RGB
.WriteMask
& 1) ? "x" : "",
973 (inst
->RGB
.WriteMask
& 2) ? "y" : "",
974 (inst
->RGB
.WriteMask
& 4) ? "z" : "");
975 if (inst
->RGB
.OutputWriteMask
)
976 _mesa_printf(" COLOR.%s%s%s",
977 (inst
->RGB
.OutputWriteMask
& 1) ? "x" : "",
978 (inst
->RGB
.OutputWriteMask
& 2) ? "y" : "",
979 (inst
->RGB
.OutputWriteMask
& 4) ? "z" : "");
980 nargs
= num_pairinst_args(inst
->RGB
.Opcode
);
981 for(i
= 0; i
< nargs
; ++i
) {
982 const char* abs
= inst
->RGB
.Arg
[i
].Abs
? "|" : "";
983 const char* neg
= inst
->RGB
.Arg
[i
].Negate
? "-" : "";
984 _mesa_printf(", %s%sSrc%i.%c%c%c%s", neg
, abs
, inst
->RGB
.Arg
[i
].Source
,
985 swizzle_char(GET_SWZ(inst
->RGB
.Arg
[i
].Swizzle
, 0)),
986 swizzle_char(GET_SWZ(inst
->RGB
.Arg
[i
].Swizzle
, 1)),
987 swizzle_char(GET_SWZ(inst
->RGB
.Arg
[i
].Swizzle
, 2)),
992 _mesa_printf(" %s%s", opcode_string(inst
->Alpha
.Opcode
), inst
->Alpha
.Saturate
? "_SAT" : "");
993 if (inst
->Alpha
.WriteMask
)
994 _mesa_printf(" TEMP[%i].w", inst
->Alpha
.DestIndex
);
995 if (inst
->Alpha
.OutputWriteMask
)
996 _mesa_printf(" COLOR.w");
997 if (inst
->Alpha
.DepthWriteMask
)
998 _mesa_printf(" DEPTH.w");
999 nargs
= num_pairinst_args(inst
->Alpha
.Opcode
);
1000 for(i
= 0; i
< nargs
; ++i
) {
1001 const char* abs
= inst
->Alpha
.Arg
[i
].Abs
? "|" : "";
1002 const char* neg
= inst
->Alpha
.Arg
[i
].Negate
? "-" : "";
1003 _mesa_printf(", %s%sSrc%i.%c%s", neg
, abs
, inst
->Alpha
.Arg
[i
].Source
,
1004 swizzle_char(inst
->Alpha
.Arg
[i
].Swizzle
), abs
);