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r300/fragprog: No longer rely on hardcoded FRAG_RESULT_xxx constants
[mesa.git] / src / mesa / drivers / dri / r300 / compiler / radeon_program_pair.c
1 /*
2 * Copyright (C) 2008 Nicolai Haehnle.
3 *
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining
7 * a copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sublicense, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial
16 * portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 */
27
28 /**
29 * @file
30 *
31 * Perform temporary register allocation and attempt to pair off instructions
32 * in RGB and Alpha pairs. Also attempts to optimize the TEX instruction
33 * vs. ALU instruction scheduling.
34 */
35
36 #include "radeon_program_pair.h"
37
38 #include "memory_pool.h"
39 #include "radeon_compiler.h"
40 #include "shader/prog_print.h"
41
42 #define error(fmt, args...) do { \
43 rc_error(&s->Compiler->Base, "%s::%s(): " fmt "\n", \
44 __FILE__, __FUNCTION__, ##args); \
45 } while(0)
46
47 struct pair_state_instruction {
48 struct prog_instruction Instruction;
49 GLuint IP; /**< Position of this instruction in original program */
50
51 GLuint IsTex:1; /**< Is a texture instruction */
52 GLuint NeedRGB:1; /**< Needs the RGB ALU */
53 GLuint NeedAlpha:1; /**< Needs the Alpha ALU */
54 GLuint IsTranscendent:1; /**< Is a special transcendent instruction */
55
56 /**
57 * Number of (read and write) dependencies that must be resolved before
58 * this instruction can be scheduled.
59 */
60 GLuint NumDependencies:5;
61
62 /**
63 * Next instruction in the linked list of ready instructions.
64 */
65 struct pair_state_instruction *NextReady;
66
67 /**
68 * Values that this instruction writes
69 */
70 struct reg_value *Values[4];
71 };
72
73
74 /**
75 * Used to keep track of which instructions read a value.
76 */
77 struct reg_value_reader {
78 struct pair_state_instruction *Reader;
79 struct reg_value_reader *Next;
80 };
81
82 /**
83 * Used to keep track which values are stored in each component of a
84 * PROGRAM_TEMPORARY.
85 */
86 struct reg_value {
87 struct pair_state_instruction *Writer;
88 struct reg_value *Next; /**< Pointer to the next value to be written to the same PROGRAM_TEMPORARY component */
89
90 /**
91 * Unordered linked list of instructions that read from this value.
92 */
93 struct reg_value_reader *Readers;
94
95 /**
96 * Number of readers of this value. This is calculated during @ref scan_instructions
97 * and continually decremented during code emission.
98 * When this count reaches zero, the instruction that writes the @ref Next value
99 * can be scheduled.
100 */
101 GLuint NumReaders;
102 };
103
104 /**
105 * Used to translate a PROGRAM_INPUT or PROGRAM_TEMPORARY Mesa register
106 * to the proper hardware temporary.
107 */
108 struct pair_register_translation {
109 GLuint Allocated:1;
110 GLuint HwIndex:8;
111 GLuint RefCount:23; /**< # of times this occurs in an unscheduled instruction SrcReg or DstReg */
112
113 /**
114 * Notes the value that is currently contained in each component
115 * (only used for PROGRAM_TEMPORARY registers).
116 */
117 struct reg_value *Value[4];
118 };
119
120 struct pair_state {
121 struct r300_fragment_program_compiler * Compiler;
122 const struct radeon_pair_handler *Handler;
123 GLboolean Verbose;
124 void *UserData;
125
126 /**
127 * Translate Mesa registers to hardware registers
128 */
129 struct pair_register_translation Inputs[FRAG_ATTRIB_MAX];
130 struct pair_register_translation Temps[MAX_PROGRAM_TEMPS];
131
132 struct {
133 GLuint RefCount; /**< # of times this occurs in an unscheduled SrcReg or DstReg */
134 } HwTemps[128];
135
136 /**
137 * Linked list of instructions that can be scheduled right now,
138 * based on which ALU/TEX resources they require.
139 */
140 struct pair_state_instruction *ReadyFullALU;
141 struct pair_state_instruction *ReadyRGB;
142 struct pair_state_instruction *ReadyAlpha;
143 struct pair_state_instruction *ReadyTEX;
144 };
145
146
147 static struct pair_register_translation *get_register(struct pair_state *s, GLuint file, GLuint index)
148 {
149 switch(file) {
150 case PROGRAM_TEMPORARY: return &s->Temps[index];
151 case PROGRAM_INPUT: return &s->Inputs[index];
152 default: return 0;
153 }
154 }
155
156 static void alloc_hw_reg(struct pair_state *s, GLuint file, GLuint index, GLuint hwindex)
157 {
158 struct pair_register_translation *t = get_register(s, file, index);
159 ASSERT(!s->HwTemps[hwindex].RefCount);
160 ASSERT(!t->Allocated);
161 s->HwTemps[hwindex].RefCount = t->RefCount;
162 t->Allocated = 1;
163 t->HwIndex = hwindex;
164 }
165
166 static GLuint get_hw_reg(struct pair_state *s, GLuint file, GLuint index)
167 {
168 GLuint hwindex;
169
170 struct pair_register_translation *t = get_register(s, file, index);
171 if (!t) {
172 error("get_hw_reg: %i[%i]\n", file, index);
173 return 0;
174 }
175
176 if (t->Allocated)
177 return t->HwIndex;
178
179 for(hwindex = 0; hwindex < s->Handler->MaxHwTemps; ++hwindex)
180 if (!s->HwTemps[hwindex].RefCount)
181 break;
182
183 if (hwindex >= s->Handler->MaxHwTemps) {
184 error("Ran out of hardware temporaries");
185 return 0;
186 }
187
188 alloc_hw_reg(s, file, index, hwindex);
189 return hwindex;
190 }
191
192
193 static void deref_hw_reg(struct pair_state *s, GLuint hwindex)
194 {
195 if (!s->HwTemps[hwindex].RefCount) {
196 error("Hwindex %i refcount error", hwindex);
197 return;
198 }
199
200 s->HwTemps[hwindex].RefCount--;
201 }
202
203 static void add_pairinst_to_list(struct pair_state_instruction **list, struct pair_state_instruction *pairinst)
204 {
205 pairinst->NextReady = *list;
206 *list = pairinst;
207 }
208
209 /**
210 * The given instruction has become ready. Link it into the ready
211 * instructions.
212 */
213 static void instruction_ready(struct pair_state *s, struct pair_state_instruction *pairinst)
214 {
215 if (s->Verbose)
216 _mesa_printf("instruction_ready(%i)\n", pairinst->IP);
217
218 if (pairinst->IsTex)
219 add_pairinst_to_list(&s->ReadyTEX, pairinst);
220 else if (!pairinst->NeedAlpha)
221 add_pairinst_to_list(&s->ReadyRGB, pairinst);
222 else if (!pairinst->NeedRGB)
223 add_pairinst_to_list(&s->ReadyAlpha, pairinst);
224 else
225 add_pairinst_to_list(&s->ReadyFullALU, pairinst);
226 }
227
228
229 /**
230 * Finally rewrite ADD, MOV, MUL as the appropriate native instruction
231 * and reverse the order of arguments for CMP.
232 */
233 static void final_rewrite(struct pair_state *s, struct prog_instruction *inst)
234 {
235 struct prog_src_register tmp;
236
237 switch(inst->Opcode) {
238 case OPCODE_ADD:
239 inst->SrcReg[2] = inst->SrcReg[1];
240 inst->SrcReg[1].File = PROGRAM_BUILTIN;
241 inst->SrcReg[1].Swizzle = SWIZZLE_1111;
242 inst->SrcReg[1].Negate = NEGATE_NONE;
243 inst->Opcode = OPCODE_MAD;
244 break;
245 case OPCODE_CMP:
246 tmp = inst->SrcReg[2];
247 inst->SrcReg[2] = inst->SrcReg[0];
248 inst->SrcReg[0] = tmp;
249 break;
250 case OPCODE_MOV:
251 /* AMD say we should use CMP.
252 * However, when we transform
253 * KIL -r0;
254 * into
255 * CMP tmp, -r0, -r0, 0;
256 * KIL tmp;
257 * we get incorrect behaviour on R500 when r0 == 0.0.
258 * It appears that the R500 KIL hardware treats -0.0 as less
259 * than zero.
260 */
261 inst->SrcReg[1].File = PROGRAM_BUILTIN;
262 inst->SrcReg[1].Swizzle = SWIZZLE_1111;
263 inst->SrcReg[2].File = PROGRAM_BUILTIN;
264 inst->SrcReg[2].Swizzle = SWIZZLE_0000;
265 inst->Opcode = OPCODE_MAD;
266 break;
267 case OPCODE_MUL:
268 inst->SrcReg[2].File = PROGRAM_BUILTIN;
269 inst->SrcReg[2].Swizzle = SWIZZLE_0000;
270 inst->Opcode = OPCODE_MAD;
271 break;
272 default:
273 /* nothing to do */
274 break;
275 }
276 }
277
278
279 /**
280 * Classify an instruction according to which ALUs etc. it needs
281 */
282 static void classify_instruction(struct pair_state *s,
283 struct pair_state_instruction *psi)
284 {
285 psi->NeedRGB = (psi->Instruction.DstReg.WriteMask & WRITEMASK_XYZ) ? 1 : 0;
286 psi->NeedAlpha = (psi->Instruction.DstReg.WriteMask & WRITEMASK_W) ? 1 : 0;
287
288 switch(psi->Instruction.Opcode) {
289 case OPCODE_ADD:
290 case OPCODE_CMP:
291 case OPCODE_DDX:
292 case OPCODE_DDY:
293 case OPCODE_FRC:
294 case OPCODE_MAD:
295 case OPCODE_MAX:
296 case OPCODE_MIN:
297 case OPCODE_MOV:
298 case OPCODE_MUL:
299 break;
300 case OPCODE_COS:
301 case OPCODE_EX2:
302 case OPCODE_LG2:
303 case OPCODE_RCP:
304 case OPCODE_RSQ:
305 case OPCODE_SIN:
306 psi->IsTranscendent = 1;
307 psi->NeedAlpha = 1;
308 break;
309 case OPCODE_DP4:
310 psi->NeedAlpha = 1;
311 /* fall through */
312 case OPCODE_DP3:
313 psi->NeedRGB = 1;
314 break;
315 case OPCODE_KIL:
316 case OPCODE_TEX:
317 case OPCODE_TXB:
318 case OPCODE_TXP:
319 case OPCODE_END:
320 psi->IsTex = 1;
321 break;
322 default:
323 error("Unknown opcode %d\n", psi->Instruction.Opcode);
324 break;
325 }
326 }
327
328
329 /**
330 * Count which (input, temporary) register is read and written how often,
331 * and scan the instruction stream to find dependencies.
332 */
333 static void scan_instructions(struct pair_state *s)
334 {
335 struct rc_instruction *source;
336 GLuint ip;
337
338 for(source = s->Compiler->Base.Program.Instructions.Next, ip = 0;
339 source != &s->Compiler->Base.Program.Instructions;
340 source = source->Next, ++ip) {
341 struct pair_state_instruction *pairinst = memory_pool_malloc(&s->Compiler->Base.Pool, sizeof(*pairinst));
342 memset(pairinst, 0, sizeof(struct pair_state_instruction));
343
344 pairinst->Instruction = source->I;
345 pairinst->IP = ip;
346 final_rewrite(s, &pairinst->Instruction);
347 classify_instruction(s, pairinst);
348
349 int nsrc = _mesa_num_inst_src_regs(pairinst->Instruction.Opcode);
350 int j;
351 for(j = 0; j < nsrc; j++) {
352 struct pair_register_translation *t =
353 get_register(s, pairinst->Instruction.SrcReg[j].File, pairinst->Instruction.SrcReg[j].Index);
354 if (!t)
355 continue;
356
357 t->RefCount++;
358
359 if (pairinst->Instruction.SrcReg[j].File == PROGRAM_TEMPORARY) {
360 int i;
361 for(i = 0; i < 4; ++i) {
362 GLuint swz = GET_SWZ(pairinst->Instruction.SrcReg[j].Swizzle, i);
363 if (swz >= 4)
364 continue; /* constant or NIL swizzle */
365 if (!t->Value[swz])
366 continue; /* this is an undefined read */
367
368 /* Do not add a dependency if this instruction
369 * also rewrites the value. The code below adds
370 * a dependency for the DstReg, which is a superset
371 * of the SrcReg dependency. */
372 if (pairinst->Instruction.DstReg.File == PROGRAM_TEMPORARY &&
373 pairinst->Instruction.DstReg.Index == pairinst->Instruction.SrcReg[j].Index &&
374 GET_BIT(pairinst->Instruction.DstReg.WriteMask, swz))
375 continue;
376
377 struct reg_value_reader* r = memory_pool_malloc(&s->Compiler->Base.Pool, sizeof(*r));
378 pairinst->NumDependencies++;
379 t->Value[swz]->NumReaders++;
380 r->Reader = pairinst;
381 r->Next = t->Value[swz]->Readers;
382 t->Value[swz]->Readers = r;
383 }
384 }
385 }
386
387 int ndst = _mesa_num_inst_dst_regs(pairinst->Instruction.Opcode);
388 if (ndst) {
389 struct pair_register_translation *t =
390 get_register(s, pairinst->Instruction.DstReg.File, pairinst->Instruction.DstReg.Index);
391 if (t) {
392 t->RefCount++;
393
394 if (pairinst->Instruction.DstReg.File == PROGRAM_TEMPORARY) {
395 int j;
396 for(j = 0; j < 4; ++j) {
397 if (!GET_BIT(pairinst->Instruction.DstReg.WriteMask, j))
398 continue;
399
400 struct reg_value* v = memory_pool_malloc(&s->Compiler->Base.Pool, sizeof(*v));
401 memset(v, 0, sizeof(struct reg_value));
402 v->Writer = pairinst;
403 if (t->Value[j]) {
404 pairinst->NumDependencies++;
405 t->Value[j]->Next = v;
406 }
407 t->Value[j] = v;
408 pairinst->Values[j] = v;
409 }
410 }
411 }
412 }
413
414 if (s->Verbose)
415 _mesa_printf("scan(%i): NumDeps = %i\n", ip, pairinst->NumDependencies);
416
417 if (!pairinst->NumDependencies)
418 instruction_ready(s, pairinst);
419 }
420
421 /* Clear the PROGRAM_TEMPORARY state */
422 int i, j;
423 for(i = 0; i < MAX_PROGRAM_TEMPS; ++i) {
424 for(j = 0; j < 4; ++j)
425 s->Temps[i].Value[j] = 0;
426 }
427 }
428
429
430 /**
431 * Reserve hardware temporary registers for the program inputs.
432 *
433 * @note This allocation is performed explicitly, because the order of inputs
434 * is determined by the RS hardware.
435 */
436 static void allocate_input_registers(struct pair_state *s)
437 {
438 GLuint InputsRead = s->Compiler->Base.Program.InputsRead;
439 int i;
440 GLuint hwindex = 0;
441
442 /* Primary colour */
443 if (InputsRead & FRAG_BIT_COL0)
444 alloc_hw_reg(s, PROGRAM_INPUT, FRAG_ATTRIB_COL0, hwindex++);
445 InputsRead &= ~FRAG_BIT_COL0;
446
447 /* Secondary color */
448 if (InputsRead & FRAG_BIT_COL1)
449 alloc_hw_reg(s, PROGRAM_INPUT, FRAG_ATTRIB_COL1, hwindex++);
450 InputsRead &= ~FRAG_BIT_COL1;
451
452 /* Texcoords */
453 for (i = 0; i < 8; i++) {
454 if (InputsRead & (FRAG_BIT_TEX0 << i))
455 alloc_hw_reg(s, PROGRAM_INPUT, FRAG_ATTRIB_TEX0+i, hwindex++);
456 }
457 InputsRead &= ~FRAG_BITS_TEX_ANY;
458
459 /* Fogcoords treated as a texcoord */
460 if (InputsRead & FRAG_BIT_FOGC)
461 alloc_hw_reg(s, PROGRAM_INPUT, FRAG_ATTRIB_FOGC, hwindex++);
462 InputsRead &= ~FRAG_BIT_FOGC;
463
464 /* fragment position treated as a texcoord */
465 if (InputsRead & FRAG_BIT_WPOS)
466 alloc_hw_reg(s, PROGRAM_INPUT, FRAG_ATTRIB_WPOS, hwindex++);
467 InputsRead &= ~FRAG_BIT_WPOS;
468
469 /* Anything else */
470 if (InputsRead)
471 error("Don't know how to handle inputs 0x%x\n", InputsRead);
472 }
473
474
475 static void decrement_dependencies(struct pair_state *s, struct pair_state_instruction *pairinst)
476 {
477 ASSERT(pairinst->NumDependencies > 0);
478 if (!--pairinst->NumDependencies)
479 instruction_ready(s, pairinst);
480 }
481
482 /**
483 * Update the dependency tracking state based on what the instruction
484 * at the given IP does.
485 */
486 static void commit_instruction(struct pair_state *s, struct pair_state_instruction *pairinst)
487 {
488 struct prog_instruction *inst = &pairinst->Instruction;
489
490 if (s->Verbose)
491 _mesa_printf("commit_instruction(%i)\n", pairinst->IP);
492
493 if (inst->DstReg.File == PROGRAM_TEMPORARY) {
494 struct pair_register_translation *t = &s->Temps[inst->DstReg.Index];
495 deref_hw_reg(s, t->HwIndex);
496
497 int i;
498 for(i = 0; i < 4; ++i) {
499 if (!GET_BIT(inst->DstReg.WriteMask, i))
500 continue;
501
502 t->Value[i] = pairinst->Values[i];
503 if (t->Value[i]->NumReaders) {
504 struct reg_value_reader *r;
505 for(r = pairinst->Values[i]->Readers; r; r = r->Next)
506 decrement_dependencies(s, r->Reader);
507 } else if (t->Value[i]->Next) {
508 /* This happens when the only reader writes
509 * the register at the same time */
510 decrement_dependencies(s, t->Value[i]->Next->Writer);
511 }
512 }
513 }
514
515 int nsrc = _mesa_num_inst_src_regs(inst->Opcode);
516 int i;
517 for(i = 0; i < nsrc; i++) {
518 struct pair_register_translation *t = get_register(s, inst->SrcReg[i].File, inst->SrcReg[i].Index);
519 if (!t)
520 continue;
521
522 deref_hw_reg(s, get_hw_reg(s, inst->SrcReg[i].File, inst->SrcReg[i].Index));
523
524 if (inst->SrcReg[i].File != PROGRAM_TEMPORARY)
525 continue;
526
527 int j;
528 for(j = 0; j < 4; ++j) {
529 GLuint swz = GET_SWZ(inst->SrcReg[i].Swizzle, j);
530 if (swz >= 4)
531 continue;
532 if (!t->Value[swz])
533 continue;
534
535 /* Do not free a dependency if this instruction
536 * also rewrites the value. See scan_instructions. */
537 if (inst->DstReg.File == PROGRAM_TEMPORARY &&
538 inst->DstReg.Index == inst->SrcReg[i].Index &&
539 GET_BIT(inst->DstReg.WriteMask, swz))
540 continue;
541
542 if (!--t->Value[swz]->NumReaders) {
543 if (t->Value[swz]->Next)
544 decrement_dependencies(s, t->Value[swz]->Next->Writer);
545 }
546 }
547 }
548 }
549
550
551 /**
552 * Emit all ready texture instructions in a single block.
553 *
554 * Emit as a single block to (hopefully) sample many textures in parallel,
555 * and to avoid hardware indirections on R300.
556 *
557 * In R500, we don't really know when the result of a texture instruction
558 * arrives. So allocate all destinations first, to make sure they do not
559 * arrive early and overwrite a texture coordinate we're going to use later
560 * in the block.
561 */
562 static void emit_all_tex(struct pair_state *s)
563 {
564 struct pair_state_instruction *readytex;
565 struct pair_state_instruction *pairinst;
566
567 ASSERT(s->ReadyTEX);
568
569 // Don't let the ready list change under us!
570 readytex = s->ReadyTEX;
571 s->ReadyTEX = 0;
572
573 // Allocate destination hardware registers in one block to avoid conflicts.
574 for(pairinst = readytex; pairinst; pairinst = pairinst->NextReady) {
575 struct prog_instruction *inst = &pairinst->Instruction;
576 if (inst->Opcode != OPCODE_KIL)
577 get_hw_reg(s, inst->DstReg.File, inst->DstReg.Index);
578 }
579
580 if (s->Compiler->Base.Debug)
581 _mesa_printf(" BEGIN_TEX\n");
582
583 if (s->Handler->BeginTexBlock)
584 s->Compiler->Base.Error = s->Compiler->Base.Error || !s->Handler->BeginTexBlock(s->UserData);
585
586 for(pairinst = readytex; pairinst; pairinst = pairinst->NextReady) {
587 struct prog_instruction *inst = &pairinst->Instruction;
588 commit_instruction(s, pairinst);
589
590 if (inst->Opcode != OPCODE_KIL)
591 inst->DstReg.Index = get_hw_reg(s, inst->DstReg.File, inst->DstReg.Index);
592 inst->SrcReg[0].Index = get_hw_reg(s, inst->SrcReg[0].File, inst->SrcReg[0].Index);
593
594 if (s->Compiler->Base.Debug) {
595 _mesa_printf(" ");
596 _mesa_print_instruction(inst);
597 fflush(stdout);
598 }
599
600 struct radeon_pair_texture_instruction rpti;
601
602 switch(inst->Opcode) {
603 case OPCODE_TEX: rpti.Opcode = RADEON_OPCODE_TEX; break;
604 case OPCODE_TXB: rpti.Opcode = RADEON_OPCODE_TXB; break;
605 case OPCODE_TXP: rpti.Opcode = RADEON_OPCODE_TXP; break;
606 default:
607 case OPCODE_KIL: rpti.Opcode = RADEON_OPCODE_KIL; break;
608 }
609
610 rpti.DestIndex = inst->DstReg.Index;
611 rpti.WriteMask = inst->DstReg.WriteMask;
612 rpti.TexSrcUnit = inst->TexSrcUnit;
613 rpti.TexSrcTarget = inst->TexSrcTarget;
614 rpti.SrcIndex = inst->SrcReg[0].Index;
615 rpti.SrcSwizzle = inst->SrcReg[0].Swizzle;
616
617 s->Compiler->Base.Error = s->Compiler->Base.Error || !s->Handler->EmitTex(s->UserData, &rpti);
618 }
619
620 if (s->Compiler->Base.Debug)
621 _mesa_printf(" END_TEX\n");
622 }
623
624
625 static int alloc_pair_source(struct pair_state *s, struct radeon_pair_instruction *pair,
626 struct prog_src_register src, GLboolean rgb, GLboolean alpha)
627 {
628 int candidate = -1;
629 int candidate_quality = -1;
630 int i;
631
632 if (!rgb && !alpha)
633 return 0;
634
635 GLuint constant;
636 GLuint index;
637
638 if (src.File == PROGRAM_TEMPORARY || src.File == PROGRAM_INPUT) {
639 constant = 0;
640 index = get_hw_reg(s, src.File, src.Index);
641 } else {
642 constant = 1;
643 index = src.Index;
644 }
645
646 for(i = 0; i < 3; ++i) {
647 int q = 0;
648 if (rgb) {
649 if (pair->RGB.Src[i].Used) {
650 if (pair->RGB.Src[i].Constant != constant ||
651 pair->RGB.Src[i].Index != index)
652 continue;
653 q++;
654 }
655 }
656 if (alpha) {
657 if (pair->Alpha.Src[i].Used) {
658 if (pair->Alpha.Src[i].Constant != constant ||
659 pair->Alpha.Src[i].Index != index)
660 continue;
661 q++;
662 }
663 }
664 if (q > candidate_quality) {
665 candidate_quality = q;
666 candidate = i;
667 }
668 }
669
670 if (candidate >= 0) {
671 if (rgb) {
672 pair->RGB.Src[candidate].Used = 1;
673 pair->RGB.Src[candidate].Constant = constant;
674 pair->RGB.Src[candidate].Index = index;
675 }
676 if (alpha) {
677 pair->Alpha.Src[candidate].Used = 1;
678 pair->Alpha.Src[candidate].Constant = constant;
679 pair->Alpha.Src[candidate].Index = index;
680 }
681 }
682
683 return candidate;
684 }
685
686 /**
687 * Fill the given ALU instruction's opcodes and source operands into the given pair,
688 * if possible.
689 */
690 static GLboolean fill_instruction_into_pair(
691 struct pair_state *s,
692 struct radeon_pair_instruction *pair,
693 struct pair_state_instruction *pairinst)
694 {
695 struct prog_instruction *inst = &pairinst->Instruction;
696
697 ASSERT(!pairinst->NeedRGB || pair->RGB.Opcode == OPCODE_NOP);
698 ASSERT(!pairinst->NeedAlpha || pair->Alpha.Opcode == OPCODE_NOP);
699
700 if (pairinst->NeedRGB) {
701 if (pairinst->IsTranscendent)
702 pair->RGB.Opcode = OPCODE_REPL_ALPHA;
703 else
704 pair->RGB.Opcode = inst->Opcode;
705 if (inst->SaturateMode == SATURATE_ZERO_ONE)
706 pair->RGB.Saturate = 1;
707 }
708 if (pairinst->NeedAlpha) {
709 pair->Alpha.Opcode = inst->Opcode;
710 if (inst->SaturateMode == SATURATE_ZERO_ONE)
711 pair->Alpha.Saturate = 1;
712 }
713
714 int nargs = _mesa_num_inst_src_regs(inst->Opcode);
715 int i;
716
717 /* Special case for DDX/DDY (MDH/MDV). */
718 if (inst->Opcode == OPCODE_DDX || inst->Opcode == OPCODE_DDY) {
719 if (pair->RGB.Src[0].Used || pair->Alpha.Src[0].Used)
720 return GL_FALSE;
721 else
722 nargs++;
723 }
724
725 for(i = 0; i < nargs; ++i) {
726 int source;
727 if (pairinst->NeedRGB && !pairinst->IsTranscendent) {
728 GLboolean srcrgb = GL_FALSE;
729 GLboolean srcalpha = GL_FALSE;
730 int j;
731 for(j = 0; j < 3; ++j) {
732 GLuint swz = GET_SWZ(inst->SrcReg[i].Swizzle, j);
733 if (swz < 3)
734 srcrgb = GL_TRUE;
735 else if (swz < 4)
736 srcalpha = GL_TRUE;
737 }
738 source = alloc_pair_source(s, pair, inst->SrcReg[i], srcrgb, srcalpha);
739 if (source < 0)
740 return GL_FALSE;
741 pair->RGB.Arg[i].Source = source;
742 pair->RGB.Arg[i].Swizzle = inst->SrcReg[i].Swizzle & 0x1ff;
743 pair->RGB.Arg[i].Abs = inst->SrcReg[i].Abs;
744 pair->RGB.Arg[i].Negate = !!(inst->SrcReg[i].Negate & (NEGATE_X | NEGATE_Y | NEGATE_Z));
745 }
746 if (pairinst->NeedAlpha) {
747 GLboolean srcrgb = GL_FALSE;
748 GLboolean srcalpha = GL_FALSE;
749 GLuint swz = GET_SWZ(inst->SrcReg[i].Swizzle, pairinst->IsTranscendent ? 0 : 3);
750 if (swz < 3)
751 srcrgb = GL_TRUE;
752 else if (swz < 4)
753 srcalpha = GL_TRUE;
754 source = alloc_pair_source(s, pair, inst->SrcReg[i], srcrgb, srcalpha);
755 if (source < 0)
756 return GL_FALSE;
757 pair->Alpha.Arg[i].Source = source;
758 pair->Alpha.Arg[i].Swizzle = swz;
759 pair->Alpha.Arg[i].Abs = inst->SrcReg[i].Abs;
760 pair->Alpha.Arg[i].Negate = !!(inst->SrcReg[i].Negate & NEGATE_W);
761 }
762 }
763
764 return GL_TRUE;
765 }
766
767
768 /**
769 * Fill in the destination register information.
770 *
771 * This is split from filling in source registers because we want
772 * to avoid allocating hardware temporaries for destinations until
773 * we are absolutely certain that we're going to emit a certain
774 * instruction pairing.
775 */
776 static void fill_dest_into_pair(
777 struct pair_state *s,
778 struct radeon_pair_instruction *pair,
779 struct pair_state_instruction *pairinst)
780 {
781 struct prog_instruction *inst = &pairinst->Instruction;
782
783 if (inst->DstReg.File == PROGRAM_OUTPUT) {
784 if (inst->DstReg.Index == s->Compiler->OutputColor) {
785 pair->RGB.OutputWriteMask |= inst->DstReg.WriteMask & WRITEMASK_XYZ;
786 pair->Alpha.OutputWriteMask |= GET_BIT(inst->DstReg.WriteMask, 3);
787 } else if (inst->DstReg.Index == s->Compiler->OutputDepth) {
788 pair->Alpha.DepthWriteMask |= GET_BIT(inst->DstReg.WriteMask, 3);
789 }
790 } else {
791 GLuint hwindex = get_hw_reg(s, inst->DstReg.File, inst->DstReg.Index);
792 if (pairinst->NeedRGB) {
793 pair->RGB.DestIndex = hwindex;
794 pair->RGB.WriteMask |= inst->DstReg.WriteMask & WRITEMASK_XYZ;
795 }
796 if (pairinst->NeedAlpha) {
797 pair->Alpha.DestIndex = hwindex;
798 pair->Alpha.WriteMask |= GET_BIT(inst->DstReg.WriteMask, 3);
799 }
800 }
801 }
802
803
804 /**
805 * Find a good ALU instruction or pair of ALU instruction and emit it.
806 *
807 * Prefer emitting full ALU instructions, so that when we reach a point
808 * where no full ALU instruction can be emitted, we have more candidates
809 * for RGB/Alpha pairing.
810 */
811 static void emit_alu(struct pair_state *s)
812 {
813 struct radeon_pair_instruction pair;
814 struct pair_state_instruction *psi;
815
816 if (s->ReadyFullALU || !(s->ReadyRGB && s->ReadyAlpha)) {
817 if (s->ReadyFullALU) {
818 psi = s->ReadyFullALU;
819 s->ReadyFullALU = s->ReadyFullALU->NextReady;
820 } else if (s->ReadyRGB) {
821 psi = s->ReadyRGB;
822 s->ReadyRGB = s->ReadyRGB->NextReady;
823 } else {
824 psi = s->ReadyAlpha;
825 s->ReadyAlpha = s->ReadyAlpha->NextReady;
826 }
827
828 _mesa_bzero(&pair, sizeof(pair));
829 fill_instruction_into_pair(s, &pair, psi);
830 fill_dest_into_pair(s, &pair, psi);
831 commit_instruction(s, psi);
832 } else {
833 struct pair_state_instruction **prgb;
834 struct pair_state_instruction **palpha;
835
836 /* Some pairings might fail because they require too
837 * many source slots; try all possible pairings if necessary */
838 for(prgb = &s->ReadyRGB; *prgb; prgb = &(*prgb)->NextReady) {
839 for(palpha = &s->ReadyAlpha; *palpha; palpha = &(*palpha)->NextReady) {
840 struct pair_state_instruction * psirgb = *prgb;
841 struct pair_state_instruction * psialpha = *palpha;
842 _mesa_bzero(&pair, sizeof(pair));
843 fill_instruction_into_pair(s, &pair, psirgb);
844 if (!fill_instruction_into_pair(s, &pair, psialpha))
845 continue;
846 *prgb = (*prgb)->NextReady;
847 *palpha = (*palpha)->NextReady;
848 fill_dest_into_pair(s, &pair, psirgb);
849 fill_dest_into_pair(s, &pair, psialpha);
850 commit_instruction(s, psirgb);
851 commit_instruction(s, psialpha);
852 goto success;
853 }
854 }
855
856 /* No success in pairing; just take the first RGB instruction */
857 psi = s->ReadyRGB;
858 s->ReadyRGB = s->ReadyRGB->NextReady;
859
860 _mesa_bzero(&pair, sizeof(pair));
861 fill_instruction_into_pair(s, &pair, psi);
862 fill_dest_into_pair(s, &pair, psi);
863 commit_instruction(s, psi);
864 success: ;
865 }
866
867 if (s->Compiler->Base.Debug)
868 radeonPrintPairInstruction(&pair);
869
870 s->Compiler->Base.Error = s->Compiler->Base.Error || !s->Handler->EmitPaired(s->UserData, &pair);
871 }
872
873
874 void radeonPairProgram(
875 struct r300_fragment_program_compiler * compiler,
876 const struct radeon_pair_handler* handler, void *userdata)
877 {
878 struct pair_state s;
879
880 _mesa_bzero(&s, sizeof(s));
881 s.Compiler = compiler;
882 s.Handler = handler;
883 s.UserData = userdata;
884 s.Verbose = GL_FALSE && s.Compiler->Base.Debug;
885
886 if (s.Compiler->Base.Debug)
887 _mesa_printf("Emit paired program\n");
888
889 scan_instructions(&s);
890 allocate_input_registers(&s);
891
892 while(!s.Compiler->Base.Error &&
893 (s.ReadyTEX || s.ReadyRGB || s.ReadyAlpha || s.ReadyFullALU)) {
894 if (s.ReadyTEX)
895 emit_all_tex(&s);
896
897 while(s.ReadyFullALU || s.ReadyRGB || s.ReadyAlpha)
898 emit_alu(&s);
899 }
900
901 if (s.Compiler->Base.Debug)
902 _mesa_printf(" END\n");
903 }
904
905
906 static void print_pair_src(int i, struct radeon_pair_instruction_source* src)
907 {
908 _mesa_printf(" Src%i = %s[%i]", i, src->Constant ? "CNST" : "TEMP", src->Index);
909 }
910
911 static const char* opcode_string(GLuint opcode)
912 {
913 if (opcode == OPCODE_REPL_ALPHA)
914 return "SOP";
915 else
916 return _mesa_opcode_string(opcode);
917 }
918
919 static int num_pairinst_args(GLuint opcode)
920 {
921 if (opcode == OPCODE_REPL_ALPHA)
922 return 0;
923 else
924 return _mesa_num_inst_src_regs(opcode);
925 }
926
927 static char swizzle_char(GLuint swz)
928 {
929 switch(swz) {
930 case SWIZZLE_X: return 'x';
931 case SWIZZLE_Y: return 'y';
932 case SWIZZLE_Z: return 'z';
933 case SWIZZLE_W: return 'w';
934 case SWIZZLE_ZERO: return '0';
935 case SWIZZLE_ONE: return '1';
936 case SWIZZLE_NIL: return '_';
937 default: return '?';
938 }
939 }
940
941 void radeonPrintPairInstruction(struct radeon_pair_instruction *inst)
942 {
943 int nargs;
944 int i;
945
946 _mesa_printf(" RGB: ");
947 for(i = 0; i < 3; ++i) {
948 if (inst->RGB.Src[i].Used)
949 print_pair_src(i, inst->RGB.Src + i);
950 }
951 _mesa_printf("\n");
952 _mesa_printf(" Alpha:");
953 for(i = 0; i < 3; ++i) {
954 if (inst->Alpha.Src[i].Used)
955 print_pair_src(i, inst->Alpha.Src + i);
956 }
957 _mesa_printf("\n");
958
959 _mesa_printf(" %s%s", opcode_string(inst->RGB.Opcode), inst->RGB.Saturate ? "_SAT" : "");
960 if (inst->RGB.WriteMask)
961 _mesa_printf(" TEMP[%i].%s%s%s", inst->RGB.DestIndex,
962 (inst->RGB.WriteMask & 1) ? "x" : "",
963 (inst->RGB.WriteMask & 2) ? "y" : "",
964 (inst->RGB.WriteMask & 4) ? "z" : "");
965 if (inst->RGB.OutputWriteMask)
966 _mesa_printf(" COLOR.%s%s%s",
967 (inst->RGB.OutputWriteMask & 1) ? "x" : "",
968 (inst->RGB.OutputWriteMask & 2) ? "y" : "",
969 (inst->RGB.OutputWriteMask & 4) ? "z" : "");
970 nargs = num_pairinst_args(inst->RGB.Opcode);
971 for(i = 0; i < nargs; ++i) {
972 const char* abs = inst->RGB.Arg[i].Abs ? "|" : "";
973 const char* neg = inst->RGB.Arg[i].Negate ? "-" : "";
974 _mesa_printf(", %s%sSrc%i.%c%c%c%s", neg, abs, inst->RGB.Arg[i].Source,
975 swizzle_char(GET_SWZ(inst->RGB.Arg[i].Swizzle, 0)),
976 swizzle_char(GET_SWZ(inst->RGB.Arg[i].Swizzle, 1)),
977 swizzle_char(GET_SWZ(inst->RGB.Arg[i].Swizzle, 2)),
978 abs);
979 }
980 _mesa_printf("\n");
981
982 _mesa_printf(" %s%s", opcode_string(inst->Alpha.Opcode), inst->Alpha.Saturate ? "_SAT" : "");
983 if (inst->Alpha.WriteMask)
984 _mesa_printf(" TEMP[%i].w", inst->Alpha.DestIndex);
985 if (inst->Alpha.OutputWriteMask)
986 _mesa_printf(" COLOR.w");
987 if (inst->Alpha.DepthWriteMask)
988 _mesa_printf(" DEPTH.w");
989 nargs = num_pairinst_args(inst->Alpha.Opcode);
990 for(i = 0; i < nargs; ++i) {
991 const char* abs = inst->Alpha.Arg[i].Abs ? "|" : "";
992 const char* neg = inst->Alpha.Arg[i].Negate ? "-" : "";
993 _mesa_printf(", %s%sSrc%i.%c%s", neg, abs, inst->Alpha.Arg[i].Source,
994 swizzle_char(inst->Alpha.Arg[i].Swizzle), abs);
995 }
996 _mesa_printf("\n");
997 }