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[mesa.git] / src / mesa / drivers / dri / r300 / r300_blit.c
1 /*
2 * Copyright (C) 2009 Maciej Cencora <m.cencora@gmail.com>
3 *
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining
7 * a copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sublicense, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial
16 * portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 */
27
28 #include "radeon_common.h"
29 #include "r300_context.h"
30
31 #include "r300_blit.h"
32 #include "r300_cmdbuf.h"
33 #include "r300_emit.h"
34 #include "r300_tex.h"
35 #include "compiler/radeon_compiler.h"
36 #include "compiler/radeon_opcodes.h"
37
38 static void vp_ins_outs(struct r300_vertex_program_compiler *c)
39 {
40 c->code->inputs[VERT_ATTRIB_POS] = 0;
41 c->code->inputs[VERT_ATTRIB_TEX0] = 1;
42 c->code->outputs[VERT_RESULT_HPOS] = 0;
43 c->code->outputs[VERT_RESULT_TEX0] = 1;
44 }
45
46 static void fp_allocate_hw_inputs(
47 struct r300_fragment_program_compiler * c,
48 void (*allocate)(void * data, unsigned input, unsigned hwreg),
49 void * mydata)
50 {
51 allocate(mydata, FRAG_ATTRIB_TEX0, 0);
52 }
53
54 static void create_vertex_program(struct r300_context *r300)
55 {
56 struct r300_vertex_program_compiler compiler;
57 struct rc_instruction *inst;
58
59 rc_init(&compiler.Base);
60
61 inst = rc_insert_new_instruction(&compiler.Base, compiler.Base.Program.Instructions.Prev);
62 inst->U.I.Opcode = RC_OPCODE_MOV;
63 inst->U.I.DstReg.File = RC_FILE_OUTPUT;
64 inst->U.I.DstReg.Index = VERT_RESULT_HPOS;
65 inst->U.I.DstReg.RelAddr = 0;
66 inst->U.I.DstReg.WriteMask = RC_MASK_XYZW;
67 inst->U.I.SrcReg[0].Abs = 0;
68 inst->U.I.SrcReg[0].File = RC_FILE_INPUT;
69 inst->U.I.SrcReg[0].Index = VERT_ATTRIB_POS;
70 inst->U.I.SrcReg[0].Negate = 0;
71 inst->U.I.SrcReg[0].RelAddr = 0;
72 inst->U.I.SrcReg[0].Swizzle = RC_SWIZZLE_XYZW;
73
74 inst = rc_insert_new_instruction(&compiler.Base, compiler.Base.Program.Instructions.Prev);
75 inst->U.I.Opcode = RC_OPCODE_MOV;
76 inst->U.I.DstReg.File = RC_FILE_OUTPUT;
77 inst->U.I.DstReg.Index = VERT_RESULT_TEX0;
78 inst->U.I.DstReg.RelAddr = 0;
79 inst->U.I.DstReg.WriteMask = RC_MASK_XYZW;
80 inst->U.I.SrcReg[0].Abs = 0;
81 inst->U.I.SrcReg[0].File = RC_FILE_INPUT;
82 inst->U.I.SrcReg[0].Index = VERT_ATTRIB_TEX0;
83 inst->U.I.SrcReg[0].Negate = 0;
84 inst->U.I.SrcReg[0].RelAddr = 0;
85 inst->U.I.SrcReg[0].Swizzle = RC_SWIZZLE_XYZW;
86
87 compiler.Base.Program.InputsRead = (1 << VERT_ATTRIB_POS) | (1 << VERT_ATTRIB_TEX0);
88 compiler.RequiredOutputs = compiler.Base.Program.OutputsWritten = (1 << VERT_RESULT_HPOS) | (1 << VERT_RESULT_TEX0);
89 compiler.SetHwInputOutput = vp_ins_outs;
90 compiler.code = &r300->blit.vp_code;
91 compiler.Base.is_r500 = r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515;
92 compiler.Base.max_temp_regs = 32;
93 compiler.Base.max_alu_insts = compiler.Base.is_r500 ? 1024 : 256;
94
95 r3xx_compile_vertex_program(&compiler);
96 }
97
98 static void create_fragment_program(struct r300_context *r300)
99 {
100 struct r300_fragment_program_compiler compiler;
101 struct rc_instruction *inst;
102
103 memset(&compiler, 0, sizeof(struct r300_fragment_program_compiler));
104 rc_init(&compiler.Base);
105
106 inst = rc_insert_new_instruction(&compiler.Base, compiler.Base.Program.Instructions.Prev);
107 inst->U.I.Opcode = RC_OPCODE_TEX;
108 inst->U.I.TexSrcTarget = RC_TEXTURE_2D;
109 inst->U.I.TexSrcUnit = 0;
110 inst->U.I.DstReg.File = RC_FILE_OUTPUT;
111 inst->U.I.DstReg.Index = FRAG_RESULT_COLOR;
112 inst->U.I.DstReg.WriteMask = RC_MASK_XYZW;
113 inst->U.I.SrcReg[0].Abs = 0;
114 inst->U.I.SrcReg[0].File = RC_FILE_INPUT;
115 inst->U.I.SrcReg[0].Index = FRAG_ATTRIB_TEX0;
116 inst->U.I.SrcReg[0].Negate = 0;
117 inst->U.I.SrcReg[0].RelAddr = 0;
118 inst->U.I.SrcReg[0].Swizzle = RC_SWIZZLE_XYZW;
119
120 compiler.Base.Program.InputsRead = (1 << FRAG_ATTRIB_TEX0);
121 compiler.OutputColor[0] = FRAG_RESULT_COLOR;
122 compiler.OutputDepth = FRAG_RESULT_DEPTH;
123 compiler.enable_shadow_ambient = GL_TRUE;
124 compiler.Base.is_r500 = (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515);
125 compiler.Base.max_temp_regs = (compiler.Base.is_r500) ? 128 : 32;
126 compiler.Base.max_alu_insts = compiler.Base.is_r500 ? 512 : 64;
127 compiler.code = &r300->blit.fp_code;
128 compiler.AllocateHwInputs = fp_allocate_hw_inputs;
129
130 r3xx_compile_fragment_program(&compiler);
131 }
132
133 void r300_blit_init(struct r300_context *r300)
134 {
135 if (r300->options.hw_tcl_enabled)
136 create_vertex_program(r300);
137 create_fragment_program(r300);
138 }
139
140 static void r300_emit_tx_setup(struct r300_context *r300,
141 gl_format mesa_format,
142 struct radeon_bo *bo,
143 intptr_t offset,
144 unsigned width,
145 unsigned height,
146 unsigned pitch)
147 {
148 int is_r500 = r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515;
149 BATCH_LOCALS(&r300->radeon);
150
151 assert(is_r500 ? width <= 4096 : width <= 2048);
152 assert(is_r500 ? height <= 4096 : height <= 2048);
153 assert(r300TranslateTexFormat(mesa_format) >= 0);
154 assert(offset % 32 == 0);
155
156 BEGIN_BATCH(17);
157 OUT_BATCH_REGVAL(R300_TX_FILTER0_0,
158 (R300_TX_CLAMP_TO_EDGE << R300_TX_WRAP_S_SHIFT) |
159 (R300_TX_CLAMP_TO_EDGE << R300_TX_WRAP_T_SHIFT) |
160 (R300_TX_CLAMP_TO_EDGE << R300_TX_WRAP_R_SHIFT) |
161 R300_TX_MIN_FILTER_MIP_NONE |
162 R300_TX_MIN_FILTER_NEAREST |
163 R300_TX_MAG_FILTER_NEAREST |
164 (0 << 28));
165 OUT_BATCH_REGVAL(R300_TX_FILTER1_0, 0);
166 OUT_BATCH_REGVAL(R300_TX_SIZE_0,
167 (((width - 1) & 0x7ff) << R300_TX_WIDTHMASK_SHIFT) |
168 (((height - 1) & 0x7ff) << R300_TX_HEIGHTMASK_SHIFT) |
169 (0 << R300_TX_DEPTHMASK_SHIFT) |
170 (0 << R300_TX_MAX_MIP_LEVEL_SHIFT) |
171 R300_TX_SIZE_TXPITCH_EN);
172
173 OUT_BATCH_REGVAL(R300_TX_FORMAT_0, r300TranslateTexFormat(mesa_format));
174 OUT_BATCH_REGVAL(R300_TX_FORMAT2_0,
175 (pitch - 1) |
176 (is_r500 && width > 2048 ? R500_TXWIDTH_BIT11 : 0) |
177 (is_r500 && height > 2048 ? R500_TXHEIGHT_BIT11 : 0));
178 OUT_BATCH_REGSEQ(R300_TX_OFFSET_0, 1);
179 OUT_BATCH_RELOC(0, bo, offset, RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
180
181 OUT_BATCH_REGSEQ(R300_TX_INVALTAGS, 2);
182 OUT_BATCH(0);
183 OUT_BATCH(1);
184
185 END_BATCH();
186 }
187
188 #define EASY_US_FORMAT(FMT, C0, C1, C2, C3, SIGN) \
189 (FMT | R500_C0_SEL_##C0 | R500_C1_SEL_##C1 | \
190 R500_C2_SEL_##C2 | R500_C3_SEL_##C3 | R500_OUT_SIGN(SIGN))
191
192 static uint32_t mesa_format_to_us_format(gl_format mesa_format)
193 {
194 switch(mesa_format)
195 {
196 case MESA_FORMAT_RGBA8888: // x
197 return EASY_US_FORMAT(R500_OUT_FMT_C4_8, A, B, G, R, 0);
198 case MESA_FORMAT_RGB565: // x
199 case MESA_FORMAT_ARGB1555: // x
200 case MESA_FORMAT_RGBA8888_REV: // x
201 return EASY_US_FORMAT(R500_OUT_FMT_C4_8, R, G, B, A, 0);
202 case MESA_FORMAT_ARGB8888: // x
203 return EASY_US_FORMAT(R500_OUT_FMT_C4_8, B, G, R, A, 0);
204 case MESA_FORMAT_ARGB8888_REV:
205 return EASY_US_FORMAT(R500_OUT_FMT_C4_8, A, R, G, B, 0);
206 case MESA_FORMAT_XRGB8888:
207 return EASY_US_FORMAT(R500_OUT_FMT_C4_8, A, R, G, B, 0);
208
209 case MESA_FORMAT_RGB332:
210 return EASY_US_FORMAT(R500_OUT_FMT_C_3_3_2, A, R, G, B, 0);
211
212 case MESA_FORMAT_RGBA_FLOAT32:
213 return EASY_US_FORMAT(R500_OUT_FMT_C4_32_FP, R, G, B, A, 0);
214 case MESA_FORMAT_RGBA_FLOAT16:
215 return EASY_US_FORMAT(R500_OUT_FMT_C4_16_FP, R, G, B, A, 0);
216 case MESA_FORMAT_ALPHA_FLOAT32:
217 return EASY_US_FORMAT(R500_OUT_FMT_C_32_FP, A, A, A, A, 0);
218 case MESA_FORMAT_ALPHA_FLOAT16:
219 return EASY_US_FORMAT(R500_OUT_FMT_C_16_FP, A, A, A, A, 0);
220
221 case MESA_FORMAT_SIGNED_RGBA8888:
222 return EASY_US_FORMAT(R500_OUT_FMT_C4_8, R, G, B, A, 0xf);
223 case MESA_FORMAT_SIGNED_RGBA8888_REV:
224 return EASY_US_FORMAT(R500_OUT_FMT_C4_8, A, B, G, R, 0xf);
225 case MESA_FORMAT_SIGNED_RGBA_16:
226 return EASY_US_FORMAT(R500_OUT_FMT_C4_16, R, G, B, A, 0xf);
227
228 default:
229 fprintf(stderr, "Unsupported format %s for US output\n", _mesa_get_format_name(mesa_format));
230 assert(0);
231 return 0;
232 }
233 }
234 #undef EASY_US_FORMAT
235
236 static void r500_emit_fp_setup(struct r300_context *r300,
237 struct r500_fragment_program_code *fp,
238 gl_format dst_format)
239 {
240 r500_emit_fp(r300, (uint32_t *)fp->inst, (fp->inst_end + 1) * 6, 0, 0, 0);
241 BATCH_LOCALS(&r300->radeon);
242
243 BEGIN_BATCH(10);
244 OUT_BATCH_REGSEQ(R500_US_CODE_ADDR, 3);
245 OUT_BATCH(R500_US_CODE_START_ADDR(0) | R500_US_CODE_END_ADDR(fp->inst_end));
246 OUT_BATCH(R500_US_CODE_RANGE_ADDR(0) | R500_US_CODE_RANGE_SIZE(fp->inst_end));
247 OUT_BATCH(0);
248 OUT_BATCH_REGVAL(R500_US_CONFIG, 0);
249 OUT_BATCH_REGVAL(R500_US_OUT_FMT_0, mesa_format_to_us_format(dst_format));
250 OUT_BATCH_REGVAL(R500_US_PIXSIZE, fp->max_temp_idx);
251 END_BATCH();
252 }
253
254 static void r500_emit_rs_setup(struct r300_context *r300)
255 {
256 BATCH_LOCALS(&r300->radeon);
257
258 BEGIN_BATCH(7);
259 OUT_BATCH_REGSEQ(R300_RS_COUNT, 2);
260 OUT_BATCH((4 << R300_IT_COUNT_SHIFT) | R300_HIRES_EN);
261 OUT_BATCH(0);
262 OUT_BATCH_REGVAL(R500_RS_INST_0,
263 (0 << R500_RS_INST_TEX_ID_SHIFT) |
264 (0 << R500_RS_INST_TEX_ADDR_SHIFT) |
265 R500_RS_INST_TEX_CN_WRITE |
266 R500_RS_INST_COL_CN_NO_WRITE);
267 OUT_BATCH_REGVAL(R500_RS_IP_0,
268 (0 << R500_RS_IP_TEX_PTR_S_SHIFT) |
269 (1 << R500_RS_IP_TEX_PTR_T_SHIFT) |
270 (2 << R500_RS_IP_TEX_PTR_R_SHIFT) |
271 (3 << R500_RS_IP_TEX_PTR_Q_SHIFT));
272 END_BATCH();
273 }
274
275 static void r300_emit_fp_setup(struct r300_context *r300,
276 struct r300_fragment_program_code *code,
277 gl_format dst_format)
278 {
279 unsigned i;
280 BATCH_LOCALS(&r300->radeon);
281
282 BEGIN_BATCH((code->alu.length + 1) * 4 + code->tex.length + 1 + 11);
283
284 OUT_BATCH_REGSEQ(R300_US_ALU_RGB_INST_0, code->alu.length);
285 for (i = 0; i < code->alu.length; i++) {
286 OUT_BATCH(code->alu.inst[i].rgb_inst);
287 }
288 OUT_BATCH_REGSEQ(R300_US_ALU_RGB_ADDR_0, code->alu.length);
289 for (i = 0; i < code->alu.length; i++) {
290 OUT_BATCH(code->alu.inst[i].rgb_addr);
291 }
292 OUT_BATCH_REGSEQ(R300_US_ALU_ALPHA_INST_0, code->alu.length);
293 for (i = 0; i < code->alu.length; i++) {
294 OUT_BATCH(code->alu.inst[i].alpha_inst);
295 }
296 OUT_BATCH_REGSEQ(R300_US_ALU_ALPHA_ADDR_0, code->alu.length);
297 for (i = 0; i < code->alu.length; i++) {
298 OUT_BATCH(code->alu.inst[i].alpha_addr);
299 }
300
301 OUT_BATCH_REGSEQ(R300_US_TEX_INST_0, code->tex.length);
302 OUT_BATCH_TABLE(code->tex.inst, code->tex.length);
303
304 OUT_BATCH_REGSEQ(R300_US_CONFIG, 3);
305 OUT_BATCH(R300_PFS_CNTL_FIRST_NODE_HAS_TEX);
306 OUT_BATCH(code->pixsize);
307 OUT_BATCH(code->code_offset);
308 OUT_BATCH_REGSEQ(R300_US_CODE_ADDR_0, 4);
309 OUT_BATCH_TABLE(code->code_addr, 4);
310 OUT_BATCH_REGVAL(R500_US_OUT_FMT_0, mesa_format_to_us_format(dst_format));
311 END_BATCH();
312 }
313
314 static void r300_emit_rs_setup(struct r300_context *r300)
315 {
316 BATCH_LOCALS(&r300->radeon);
317
318 BEGIN_BATCH(7);
319 OUT_BATCH_REGSEQ(R300_RS_COUNT, 2);
320 OUT_BATCH((4 << R300_IT_COUNT_SHIFT) | R300_HIRES_EN);
321 OUT_BATCH(0);
322 OUT_BATCH_REGVAL(R300_RS_INST_0,
323 R300_RS_INST_TEX_ID(0) |
324 R300_RS_INST_TEX_ADDR(0) |
325 R300_RS_INST_TEX_CN_WRITE);
326 OUT_BATCH_REGVAL(R300_RS_IP_0,
327 R300_RS_TEX_PTR(0) |
328 R300_RS_SEL_S(R300_RS_SEL_C0) |
329 R300_RS_SEL_T(R300_RS_SEL_C1) |
330 R300_RS_SEL_R(R300_RS_SEL_K0) |
331 R300_RS_SEL_Q(R300_RS_SEL_K1));
332 END_BATCH();
333 }
334
335 static void emit_pvs_setup(struct r300_context *r300,
336 uint32_t *vp_code,
337 unsigned vp_len)
338 {
339 BATCH_LOCALS(&r300->radeon);
340
341 r300_emit_vpu(r300, vp_code, vp_len * 4, R300_PVS_CODE_START);
342
343 BEGIN_BATCH(4);
344 OUT_BATCH_REGSEQ(R300_VAP_PVS_CODE_CNTL_0, 3);
345 OUT_BATCH((0 << R300_PVS_FIRST_INST_SHIFT) |
346 ((vp_len - 1) << R300_PVS_XYZW_VALID_INST_SHIFT) |
347 ((vp_len - 1)<< R300_PVS_LAST_INST_SHIFT));
348 OUT_BATCH(0);
349 OUT_BATCH((vp_len - 1) << R300_PVS_LAST_VTX_SRC_INST_SHIFT);
350 END_BATCH();
351 }
352
353 static void emit_vap_setup(struct r300_context *r300)
354 {
355 int tex_offset;
356 BATCH_LOCALS(&r300->radeon);
357
358 if (r300->options.hw_tcl_enabled)
359 tex_offset = 1;
360 else
361 tex_offset = 6;
362
363 BEGIN_BATCH(12);
364 OUT_BATCH_REGSEQ(R300_SE_VTE_CNTL, 2);
365 OUT_BATCH(R300_VTX_XY_FMT | R300_VTX_Z_FMT);
366 OUT_BATCH(4);
367
368 OUT_BATCH_REGVAL(R300_VAP_PSC_SGN_NORM_CNTL, 0xaaaaaaaa);
369 OUT_BATCH_REGVAL(R300_VAP_PROG_STREAM_CNTL_0,
370 ((R300_DATA_TYPE_FLOAT_2 | (0 << R300_DST_VEC_LOC_SHIFT)) << 0) |
371 (((tex_offset << R300_DST_VEC_LOC_SHIFT) | R300_DATA_TYPE_FLOAT_2 | R300_LAST_VEC) << 16));
372 OUT_BATCH_REGVAL(R300_VAP_PROG_STREAM_CNTL_EXT_0,
373 ((((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_SHIFT) |
374 (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_SHIFT) |
375 (R300_SWIZZLE_SELECT_FP_ZERO << R300_SWIZZLE_SELECT_Z_SHIFT) |
376 (R300_SWIZZLE_SELECT_FP_ONE << R300_SWIZZLE_SELECT_W_SHIFT) |
377 (0xf << R300_WRITE_ENA_SHIFT) ) << 0) |
378 (((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_SHIFT) |
379 (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_SHIFT) |
380 (R300_SWIZZLE_SELECT_FP_ZERO << R300_SWIZZLE_SELECT_Z_SHIFT) |
381 (R300_SWIZZLE_SELECT_FP_ONE << R300_SWIZZLE_SELECT_W_SHIFT) |
382 (0xf << R300_WRITE_ENA_SHIFT) ) << 16) ) );
383 OUT_BATCH_REGSEQ(R300_VAP_OUTPUT_VTX_FMT_0, 2);
384 OUT_BATCH(R300_VAP_OUTPUT_VTX_FMT_0__POS_PRESENT);
385 OUT_BATCH(R300_VAP_OUTPUT_VTX_FMT_1__4_COMPONENTS);
386 END_BATCH();
387 }
388
389 static GLboolean validate_buffers(struct r300_context *r300,
390 struct radeon_bo *src_bo,
391 struct radeon_bo *dst_bo)
392 {
393 int ret;
394
395 radeon_cs_space_reset_bos(r300->radeon.cmdbuf.cs);
396
397 ret = radeon_cs_space_check_with_bo(r300->radeon.cmdbuf.cs,
398 src_bo, RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT, 0);
399 if (ret)
400 return GL_FALSE;
401
402 ret = radeon_cs_space_check_with_bo(r300->radeon.cmdbuf.cs,
403 dst_bo, 0, RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT);
404 if (ret)
405 return GL_FALSE;
406
407 return GL_TRUE;
408 }
409
410 /**
411 * Calculate texcoords for given image region.
412 * Output values are [minx, maxx, miny, maxy]
413 */
414 static void calc_tex_coords(float img_width, float img_height,
415 float x, float y,
416 float reg_width, float reg_height,
417 unsigned flip_y, float *buf)
418 {
419 buf[0] = x / img_width;
420 buf[1] = buf[0] + reg_width / img_width;
421 buf[2] = y / img_height;
422 buf[3] = buf[2] + reg_height / img_height;
423 if (flip_y)
424 {
425 buf[2] = 1.0 - buf[2];
426 buf[3] = 1.0 - buf[3];
427 }
428 }
429
430 static void emit_draw_packet(struct r300_context *r300,
431 unsigned src_width, unsigned src_height,
432 unsigned src_x_offset, unsigned src_y_offset,
433 unsigned dst_x_offset, unsigned dst_y_offset,
434 unsigned reg_width, unsigned reg_height,
435 unsigned flip_y)
436 {
437 float texcoords[4];
438
439 calc_tex_coords(src_width, src_height,
440 src_x_offset, src_y_offset,
441 reg_width, reg_height,
442 flip_y, texcoords);
443
444 float verts[] = { dst_x_offset, dst_y_offset,
445 texcoords[0], texcoords[2],
446 dst_x_offset, dst_y_offset + reg_height,
447 texcoords[0], texcoords[3],
448 dst_x_offset + reg_width, dst_y_offset + reg_height,
449 texcoords[1], texcoords[3],
450 dst_x_offset + reg_width, dst_y_offset,
451 texcoords[1], texcoords[2] };
452
453 BATCH_LOCALS(&r300->radeon);
454
455 BEGIN_BATCH(19);
456 OUT_BATCH_PACKET3(R300_PACKET3_3D_DRAW_IMMD_2, 16);
457 OUT_BATCH(R300_VAP_VF_CNTL__PRIM_WALK_VERTEX_EMBEDDED |
458 (4 << 16) | R300_VAP_VF_CNTL__PRIM_QUADS);
459 OUT_BATCH_TABLE(verts, 16);
460 END_BATCH();
461 }
462
463 static void other_stuff(struct r300_context *r300)
464 {
465 BATCH_LOCALS(&r300->radeon);
466
467 BEGIN_BATCH(13);
468 OUT_BATCH_REGVAL(R300_GA_POLY_MODE,
469 R300_GA_POLY_MODE_FRONT_PTYPE_TRI | R300_GA_POLY_MODE_BACK_PTYPE_TRI);
470 OUT_BATCH_REGVAL(R300_SU_CULL_MODE, R300_FRONT_FACE_CCW);
471 OUT_BATCH_REGVAL(R300_FG_FOG_BLEND, 0);
472 OUT_BATCH_REGVAL(R300_FG_ALPHA_FUNC, 0);
473 OUT_BATCH_REGSEQ(R300_RB3D_CBLEND, 2);
474 OUT_BATCH(0x0);
475 OUT_BATCH(0x0);
476 OUT_BATCH_REGVAL(R300_ZB_CNTL, 0);
477 END_BATCH();
478 if (r300->options.hw_tcl_enabled) {
479 BEGIN_BATCH(2);
480 OUT_BATCH_REGVAL(R300_VAP_CLIP_CNTL, R300_CLIP_DISABLE);
481 END_BATCH();
482 }
483 }
484
485 static void emit_cb_setup(struct r300_context *r300,
486 struct radeon_bo *bo,
487 intptr_t offset,
488 gl_format mesa_format,
489 unsigned pitch,
490 unsigned width,
491 unsigned height)
492 {
493 BATCH_LOCALS(&r300->radeon);
494
495 unsigned x1, y1, x2, y2;
496 x1 = 0;
497 y1 = 0;
498 x2 = width - 1;
499 y2 = height - 1;
500
501 if (r300->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV515) {
502 x1 += R300_SCISSORS_OFFSET;
503 y1 += R300_SCISSORS_OFFSET;
504 x2 += R300_SCISSORS_OFFSET;
505 y2 += R300_SCISSORS_OFFSET;
506 }
507
508 r300_emit_cb_setup(r300, bo, offset, mesa_format,
509 _mesa_get_format_bytes(mesa_format),
510 _mesa_format_row_stride(mesa_format, pitch));
511
512 BEGIN_BATCH_NO_AUTOSTATE(5);
513 OUT_BATCH_REGSEQ(R300_SC_SCISSORS_TL, 2);
514 OUT_BATCH((x1 << R300_SCISSORS_X_SHIFT)|(y1 << R300_SCISSORS_Y_SHIFT));
515 OUT_BATCH((x2 << R300_SCISSORS_X_SHIFT)|(y2 << R300_SCISSORS_Y_SHIFT));
516 OUT_BATCH_REGVAL(R300_RB3D_CCTL, 0);
517 END_BATCH();
518 }
519
520 unsigned r300_check_blit(gl_format dst_format)
521 {
522 switch (dst_format) {
523 case MESA_FORMAT_RGB565:
524 case MESA_FORMAT_ARGB1555:
525 case MESA_FORMAT_RGBA8888:
526 case MESA_FORMAT_RGBA8888_REV:
527 case MESA_FORMAT_ARGB8888:
528 case MESA_FORMAT_ARGB8888_REV:
529 case MESA_FORMAT_XRGB8888:
530 break;
531 default:
532 return 0;
533 }
534
535 if (_mesa_get_format_bits(dst_format, GL_DEPTH_BITS) > 0)
536 return 0;
537
538 return 1;
539 }
540
541 /**
542 * Copy a region of [@a width x @a height] pixels from source buffer
543 * to destination buffer.
544 * @param[in] r300 r300 context
545 * @param[in] src_bo source radeon buffer object
546 * @param[in] src_offset offset of the source image in the @a src_bo
547 * @param[in] src_mesaformat source image format
548 * @param[in] src_pitch aligned source image width
549 * @param[in] src_width source image width
550 * @param[in] src_height source image height
551 * @param[in] src_x_offset x offset in the source image
552 * @param[in] src_y_offset y offset in the source image
553 * @param[in] dst_bo destination radeon buffer object
554 * @param[in] dst_offset offset of the destination image in the @a dst_bo
555 * @param[in] dst_mesaformat destination image format
556 * @param[in] dst_pitch aligned destination image width
557 * @param[in] dst_width destination image width
558 * @param[in] dst_height destination image height
559 * @param[in] dst_x_offset x offset in the destination image
560 * @param[in] dst_y_offset y offset in the destination image
561 * @param[in] width region width
562 * @param[in] height region height
563 * @param[in] flip_y set if y coords of the source image need to be flipped
564 */
565 unsigned r300_blit(GLcontext *ctx,
566 struct radeon_bo *src_bo,
567 intptr_t src_offset,
568 gl_format src_mesaformat,
569 unsigned src_pitch,
570 unsigned src_width,
571 unsigned src_height,
572 unsigned src_x_offset,
573 unsigned src_y_offset,
574 struct radeon_bo *dst_bo,
575 intptr_t dst_offset,
576 gl_format dst_mesaformat,
577 unsigned dst_pitch,
578 unsigned dst_width,
579 unsigned dst_height,
580 unsigned dst_x_offset,
581 unsigned dst_y_offset,
582 unsigned reg_width,
583 unsigned reg_height,
584 unsigned flip_y)
585 {
586 r300ContextPtr r300 = R300_CONTEXT(ctx);
587
588 if (!r300_check_blit(dst_mesaformat))
589 return 0;
590
591 /* Make sure that colorbuffer has even width - hw limitation */
592 if (dst_pitch % 2 > 0)
593 ++dst_pitch;
594
595 /* Need to clamp the region size to make sure
596 * we don't read outside of the source buffer
597 * or write outside of the destination buffer.
598 */
599 if (reg_width + src_x_offset > src_width)
600 reg_width = src_width - src_x_offset;
601 if (reg_height + src_y_offset > src_height)
602 reg_height = src_height - src_y_offset;
603 if (reg_width + dst_x_offset > dst_width)
604 reg_width = dst_width - dst_x_offset;
605 if (reg_height + dst_y_offset > dst_height)
606 reg_height = dst_height - dst_y_offset;
607
608 if (src_bo == dst_bo) {
609 return 0;
610 }
611
612 if (src_offset % 32 || dst_offset % 32) {
613 return GL_FALSE;
614 }
615
616 if (0) {
617 fprintf(stderr, "src: size [%d x %d], pitch %d, "
618 "offset [%d x %d], format %s, bo %p\n",
619 src_width, src_height, src_pitch,
620 src_x_offset, src_y_offset,
621 _mesa_get_format_name(src_mesaformat),
622 src_bo);
623 fprintf(stderr, "dst: pitch %d, offset[%d x %d], format %s, bo %p\n",
624 dst_pitch, dst_x_offset, dst_y_offset,
625 _mesa_get_format_name(dst_mesaformat), dst_bo);
626 fprintf(stderr, "region: %d x %d\n", reg_width, reg_height);
627 }
628
629 /* Flush is needed to make sure that source buffer has correct data */
630 radeonFlush(r300->radeon.glCtx);
631
632 if (!validate_buffers(r300, src_bo, dst_bo))
633 return 0;
634
635 rcommonEnsureCmdBufSpace(&r300->radeon, 200, __FUNCTION__);
636
637 other_stuff(r300);
638
639 r300_emit_tx_setup(r300, src_mesaformat, src_bo, src_offset, src_width, src_height, src_pitch);
640
641 if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) {
642 r500_emit_fp_setup(r300, &r300->blit.fp_code.code.r500, dst_mesaformat);
643 r500_emit_rs_setup(r300);
644 } else {
645 r300_emit_fp_setup(r300, &r300->blit.fp_code.code.r300, dst_mesaformat);
646 r300_emit_rs_setup(r300);
647 }
648
649 if (r300->options.hw_tcl_enabled)
650 emit_pvs_setup(r300, r300->blit.vp_code.body.d, 2);
651
652 emit_vap_setup(r300);
653
654 emit_cb_setup(r300, dst_bo, dst_offset, dst_mesaformat, dst_pitch, dst_width, dst_height);
655
656 emit_draw_packet(r300, src_width, src_height,
657 src_x_offset, src_y_offset,
658 dst_x_offset, dst_y_offset,
659 reg_width, reg_height,
660 flip_y);
661
662 r300EmitCacheFlush(r300);
663
664 radeonFlush(r300->radeon.glCtx);
665
666 return 1;
667 }