2 Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
4 The Weather Channel (TM) funded Tungsten Graphics to develop the
5 initial release of the Radeon 8500 driver under the XFree86 license.
6 This notice must be preserved.
8 Permission is hereby granted, free of charge, to any person obtaining
9 a copy of this software and associated documentation files (the
10 "Software"), to deal in the Software without restriction, including
11 without limitation the rights to use, copy, modify, merge, publish,
12 distribute, sublicense, and/or sell copies of the Software, and to
13 permit persons to whom the Software is furnished to do so, subject to
14 the following conditions:
16 The above copyright notice and this permission notice (including the
17 next paragraph) shall be included in all copies or substantial
18 portions of the Software.
20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
28 **************************************************************************/
33 * \author Nicolai Haehnle <prefect_@gmx.net>
36 #include "main/glheader.h"
37 #include "main/state.h"
38 #include "main/imports.h"
39 #include "main/macros.h"
40 #include "main/context.h"
41 #include "main/simple_list.h"
42 #include "swrast/swrast.h"
45 #include "radeon_drm.h"
47 #include "r300_context.h"
48 #include "r300_ioctl.h"
49 #include "radeon_reg.h"
51 #include "r300_cmdbuf.h"
52 #include "r300_emit.h"
53 #include "radeon_bocs_wrapper.h"
54 #include "radeon_mipmap_tree.h"
55 #include "r300_state.h"
56 #include "radeon_reg.h"
58 /** # of dwords reserved for additional instructions that may need to be written
61 #define SPACE_FOR_FLUSHING 4
63 static unsigned packet0_count(r300ContextPtr r300
, uint32_t *pkt
)
65 if (r300
->radeon
.radeonScreen
->kernel_mm
) {
66 return ((((*pkt
) >> 16) & 0x3FFF) + 1);
68 drm_r300_cmd_header_t
*t
= (drm_r300_cmd_header_t
*)pkt
;
69 return t
->packet0
.count
;
73 #define vpu_count(ptr) (((drm_r300_cmd_header_t*)(ptr))->vpu.count)
74 #define r500fp_count(ptr) (((drm_r300_cmd_header_t*)(ptr))->r500fp.count)
76 void emit_vpu(GLcontext
*ctx
, struct radeon_state_atom
* atom
)
78 r300ContextPtr r300
= R300_CONTEXT(ctx
);
79 BATCH_LOCALS(&r300
->radeon
);
80 drm_r300_cmd_header_t cmd
;
81 uint32_t addr
, ndw
, i
;
83 if (!r300
->radeon
.radeonScreen
->kernel_mm
) {
85 dwords
= (*atom
->check
) (ctx
, atom
);
86 BEGIN_BATCH_NO_AUTOSTATE(dwords
);
87 OUT_BATCH_TABLE(atom
->cmd
, dwords
);
93 addr
= (cmd
.vpu
.adrhi
<< 8) | cmd
.vpu
.adrlo
;
94 ndw
= cmd
.vpu
.count
* 4;
97 if (r300
->vap_flush_needed
) {
98 BEGIN_BATCH_NO_AUTOSTATE(15 + ndw
);
100 /* flush processing vertices */
101 OUT_BATCH_REGVAL(R300_SC_SCREENDOOR
, 0);
102 OUT_BATCH_REGVAL(R300_RB3D_DSTCACHE_CTLSTAT
, R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D
);
103 OUT_BATCH_REGVAL(RADEON_WAIT_UNTIL
, RADEON_WAIT_3D_IDLECLEAN
);
104 OUT_BATCH_REGVAL(R300_SC_SCREENDOOR
, 0xffffff);
105 OUT_BATCH_REGVAL(R300_VAP_PVS_STATE_FLUSH_REG
, 0);
106 r300
->vap_flush_needed
= GL_FALSE
;
108 BEGIN_BATCH_NO_AUTOSTATE(5 + ndw
);
110 OUT_BATCH_REGVAL(R300_VAP_PVS_VECTOR_INDX_REG
, addr
);
111 OUT_BATCH(CP_PACKET0(R300_VAP_PVS_UPLOAD_DATA
, ndw
-1) | RADEON_ONE_REG_WR
);
112 for (i
= 0; i
< ndw
; i
++) {
113 OUT_BATCH(atom
->cmd
[i
+1]);
115 OUT_BATCH_REGVAL(R300_VAP_PVS_STATE_FLUSH_REG
, 0);
120 void emit_r500fp(GLcontext
*ctx
, struct radeon_state_atom
* atom
)
122 r300ContextPtr r300
= R300_CONTEXT(ctx
);
123 BATCH_LOCALS(&r300
->radeon
);
124 drm_r300_cmd_header_t cmd
;
125 uint32_t addr
, ndw
, i
, sz
;
126 int type
, clamp
, stride
;
128 if (!r300
->radeon
.radeonScreen
->kernel_mm
) {
130 dwords
= (*atom
->check
) (ctx
, atom
);
131 BEGIN_BATCH_NO_AUTOSTATE(dwords
);
132 OUT_BATCH_TABLE(atom
->cmd
, dwords
);
137 cmd
.u
= atom
->cmd
[0];
138 sz
= cmd
.r500fp
.count
;
139 addr
= ((cmd
.r500fp
.adrhi_flags
& 1) << 8) | cmd
.r500fp
.adrlo
;
140 type
= !!(cmd
.r500fp
.adrhi_flags
& R500FP_CONSTANT_TYPE
);
141 clamp
= !!(cmd
.r500fp
.adrhi_flags
& R500FP_CONSTANT_CLAMP
);
143 addr
|= (type
<< 16);
144 addr
|= (clamp
<< 17);
146 stride
= type
? 4 : 6;
151 BEGIN_BATCH_NO_AUTOSTATE(3 + ndw
);
152 OUT_BATCH(CP_PACKET0(R500_GA_US_VECTOR_INDEX
, 0));
154 OUT_BATCH(CP_PACKET0(R500_GA_US_VECTOR_DATA
, ndw
-1) | RADEON_ONE_REG_WR
);
155 for (i
= 0; i
< ndw
; i
++) {
156 OUT_BATCH(atom
->cmd
[i
+1]);
162 static void emit_tex_offsets(GLcontext
*ctx
, struct radeon_state_atom
* atom
)
164 r300ContextPtr r300
= R300_CONTEXT(ctx
);
165 BATCH_LOCALS(&r300
->radeon
);
166 int numtmus
= packet0_count(r300
, r300
->hw
.tex
.offset
.cmd
);
172 for(i
= 0; i
< numtmus
; ++i
) {
173 radeonTexObj
*t
= r300
->hw
.textures
[i
];
179 if (r300
->radeon
.radeonScreen
->kernel_mm
&& notexture
) {
182 for(i
= 0; i
< numtmus
; ++i
) {
183 radeonTexObj
*t
= r300
->hw
.textures
[i
];
184 if (t
&& !t
->image_override
) {
185 BEGIN_BATCH_NO_AUTOSTATE(4);
186 OUT_BATCH_REGSEQ(R300_TX_OFFSET_0
+ (i
* 4), 1);
187 OUT_BATCH_RELOC(t
->tile_bits
, t
->mt
->bo
, 0,
188 RADEON_GEM_DOMAIN_GTT
|RADEON_GEM_DOMAIN_VRAM
, 0, 0);
191 /* Texture unit hasn't a texture bound nothings to do */
192 } else { /* override cases */
194 BEGIN_BATCH_NO_AUTOSTATE(4);
195 OUT_BATCH_REGSEQ(R300_TX_OFFSET_0
+ (i
* 4), 1);
196 OUT_BATCH_RELOC(t
->tile_bits
, t
->bo
, 0,
197 RADEON_GEM_DOMAIN_GTT
|RADEON_GEM_DOMAIN_VRAM
, 0, 0);
199 } else if (!r300
->radeon
.radeonScreen
->kernel_mm
) {
200 BEGIN_BATCH_NO_AUTOSTATE(2);
201 OUT_BATCH_REGSEQ(R300_TX_OFFSET_0
+ (i
* 4), 1);
202 OUT_BATCH(t
->override_offset
);
205 /* Texture unit hasn't a texture bound nothings to do */
212 void r300_emit_scissor(GLcontext
*ctx
)
214 r300ContextPtr r300
= R300_CONTEXT(ctx
);
215 BATCH_LOCALS(&r300
->radeon
);
216 unsigned x1
, y1
, x2
, y2
;
217 struct radeon_renderbuffer
*rrb
;
219 if (!r300
->radeon
.radeonScreen
->driScreen
->dri2
.enabled
) {
222 rrb
= radeon_get_colorbuffer(&r300
->radeon
);
223 if (!rrb
|| !rrb
->bo
) {
224 fprintf(stderr
, "no rrb\n");
227 if (r300
->radeon
.state
.scissor
.enabled
) {
228 x1
= r300
->radeon
.state
.scissor
.rect
.x1
;
229 y1
= r300
->radeon
.state
.scissor
.rect
.y1
;
230 x2
= r300
->radeon
.state
.scissor
.rect
.x2
- 1;
231 y2
= r300
->radeon
.state
.scissor
.rect
.y2
- 1;
236 y2
= rrb
->height
- 1;
238 if (r300
->radeon
.radeonScreen
->chip_family
< CHIP_FAMILY_RV515
) {
239 x1
+= R300_SCISSORS_OFFSET
;
240 y1
+= R300_SCISSORS_OFFSET
;
241 x2
+= R300_SCISSORS_OFFSET
;
242 y2
+= R300_SCISSORS_OFFSET
;
244 BEGIN_BATCH_NO_AUTOSTATE(3);
245 OUT_BATCH_REGSEQ(R300_SC_SCISSORS_TL
, 2);
246 OUT_BATCH((x1
<< R300_SCISSORS_X_SHIFT
)|(y1
<< R300_SCISSORS_Y_SHIFT
));
247 OUT_BATCH((x2
<< R300_SCISSORS_X_SHIFT
)|(y2
<< R300_SCISSORS_Y_SHIFT
));
251 static void emit_cb_offset(GLcontext
*ctx
, struct radeon_state_atom
* atom
)
253 r300ContextPtr r300
= R300_CONTEXT(ctx
);
254 BATCH_LOCALS(&r300
->radeon
);
255 struct radeon_renderbuffer
*rrb
;
257 uint32_t offset
= r300
->radeon
.state
.color
.draw_offset
;
261 rrb
= radeon_get_colorbuffer(&r300
->radeon
);
262 if (!rrb
|| !rrb
->bo
) {
263 fprintf(stderr
, "no rrb\n");
267 cbpitch
= (rrb
->pitch
/ rrb
->cpp
);
269 cbpitch
|= R300_COLOR_FORMAT_ARGB8888
;
271 cbpitch
|= R300_COLOR_FORMAT_RGB565
;
273 if (rrb
->bo
->flags
& RADEON_BO_FLAGS_MACRO_TILE
)
274 cbpitch
|= R300_COLOR_TILE_ENABLE
;
276 if (r300
->radeon
.radeonScreen
->kernel_mm
)
278 BEGIN_BATCH_NO_AUTOSTATE(dw
);
279 OUT_BATCH_REGSEQ(R300_RB3D_COLOROFFSET0
, 1);
280 OUT_BATCH_RELOC(offset
, rrb
->bo
, offset
, 0, RADEON_GEM_DOMAIN_VRAM
, 0);
281 OUT_BATCH_REGSEQ(R300_RB3D_COLORPITCH0
, 1);
282 if (!r300
->radeon
.radeonScreen
->kernel_mm
)
285 OUT_BATCH_RELOC(cbpitch
, rrb
->bo
, cbpitch
, 0, RADEON_GEM_DOMAIN_VRAM
, 0);
287 if (r300
->radeon
.radeonScreen
->driScreen
->dri2
.enabled
) {
288 if (r300
->radeon
.radeonScreen
->chip_family
>= CHIP_FAMILY_RV515
) {
289 BEGIN_BATCH_NO_AUTOSTATE(3);
290 OUT_BATCH_REGSEQ(R300_SC_SCISSORS_TL
, 2);
292 OUT_BATCH(((rrb
->width
- 1) << R300_SCISSORS_X_SHIFT
) |
293 ((rrb
->height
- 1) << R300_SCISSORS_Y_SHIFT
));
295 BEGIN_BATCH_NO_AUTOSTATE(16);
296 for (i
= 0; i
< 4; i
++) {
297 OUT_BATCH_REGSEQ(R300_SC_CLIPRECT_TL_0
+ (i
* 8), 2);
298 OUT_BATCH((0 << R300_CLIPRECT_X_SHIFT
) | (0 << R300_CLIPRECT_Y_SHIFT
));
299 OUT_BATCH(((rrb
->width
- 1) << R300_CLIPRECT_X_SHIFT
) | ((rrb
->height
- 1) << R300_CLIPRECT_Y_SHIFT
));
301 OUT_BATCH_REGSEQ(R300_SC_CLIP_RULE
, 1);
303 OUT_BATCH_REGSEQ(R300_SC_SCREENDOOR
, 1);
307 BEGIN_BATCH_NO_AUTOSTATE(3);
308 OUT_BATCH_REGSEQ(R300_SC_SCISSORS_TL
, 2);
309 OUT_BATCH((R300_SCISSORS_OFFSET
<< R300_SCISSORS_X_SHIFT
) |
310 (R300_SCISSORS_OFFSET
<< R300_SCISSORS_Y_SHIFT
));
311 OUT_BATCH(((rrb
->width
+ R300_SCISSORS_OFFSET
- 1) << R300_SCISSORS_X_SHIFT
) |
312 ((rrb
->height
+ R300_SCISSORS_OFFSET
- 1) << R300_SCISSORS_Y_SHIFT
));
314 BEGIN_BATCH_NO_AUTOSTATE(16);
315 for (i
= 0; i
< 4; i
++) {
316 OUT_BATCH_REGSEQ(R300_SC_CLIPRECT_TL_0
+ (i
* 8), 2);
317 OUT_BATCH((R300_SCISSORS_OFFSET
<< R300_CLIPRECT_X_SHIFT
) | (R300_SCISSORS_OFFSET
<< R300_CLIPRECT_Y_SHIFT
));
318 OUT_BATCH(((R300_SCISSORS_OFFSET
+ rrb
->width
- 1) << R300_CLIPRECT_X_SHIFT
) |
319 ((R300_SCISSORS_OFFSET
+ rrb
->height
- 1) << R300_CLIPRECT_Y_SHIFT
));
321 OUT_BATCH_REGSEQ(R300_SC_CLIP_RULE
, 1);
323 OUT_BATCH_REGSEQ(R300_SC_SCREENDOOR
, 1);
330 static void emit_zb_offset(GLcontext
*ctx
, struct radeon_state_atom
* atom
)
332 r300ContextPtr r300
= R300_CONTEXT(ctx
);
333 BATCH_LOCALS(&r300
->radeon
);
334 struct radeon_renderbuffer
*rrb
;
337 rrb
= radeon_get_depthbuffer(&r300
->radeon
);
341 zbpitch
= (rrb
->pitch
/ rrb
->cpp
);
342 if (rrb
->bo
->flags
& RADEON_BO_FLAGS_MACRO_TILE
) {
343 zbpitch
|= R300_DEPTHMACROTILE_ENABLE
;
345 if (rrb
->bo
->flags
& RADEON_BO_FLAGS_MICRO_TILE
){
346 zbpitch
|= R300_DEPTHMICROTILE_TILED
;
349 BEGIN_BATCH_NO_AUTOSTATE(6);
350 OUT_BATCH_REGSEQ(R300_ZB_DEPTHOFFSET
, 1);
351 OUT_BATCH_RELOC(0, rrb
->bo
, 0, 0, RADEON_GEM_DOMAIN_VRAM
, 0);
352 OUT_BATCH_REGVAL(R300_ZB_DEPTHPITCH
, zbpitch
);
356 static void emit_gb_misc(GLcontext
*ctx
, struct radeon_state_atom
* atom
)
358 r300ContextPtr r300
= R300_CONTEXT(ctx
);
359 BATCH_LOCALS(&r300
->radeon
);
360 if (!r300
->radeon
.radeonScreen
->driScreen
->dri2
.enabled
) {
361 BEGIN_BATCH_NO_AUTOSTATE(4);
362 OUT_BATCH(atom
->cmd
[0]);
363 OUT_BATCH(atom
->cmd
[1]);
364 OUT_BATCH(atom
->cmd
[2]);
365 OUT_BATCH(atom
->cmd
[3]);
370 static void emit_threshold_misc(GLcontext
*ctx
, struct radeon_state_atom
* atom
)
372 r300ContextPtr r300
= R300_CONTEXT(ctx
);
373 BATCH_LOCALS(&r300
->radeon
);
374 if (r300
->radeon
.radeonScreen
->chip_family
>= CHIP_FAMILY_RV515
) {
375 BEGIN_BATCH_NO_AUTOSTATE(3);
376 OUT_BATCH(atom
->cmd
[0]);
377 OUT_BATCH(atom
->cmd
[1]);
378 OUT_BATCH(atom
->cmd
[2]);
383 static void emit_shade_misc(GLcontext
*ctx
, struct radeon_state_atom
* atom
)
385 r300ContextPtr r300
= R300_CONTEXT(ctx
);
386 BATCH_LOCALS(&r300
->radeon
);
388 if (!r300
->radeon
.radeonScreen
->driScreen
->dri2
.enabled
) {
389 BEGIN_BATCH_NO_AUTOSTATE(2);
390 OUT_BATCH(atom
->cmd
[0]);
391 OUT_BATCH(atom
->cmd
[1]);
396 static void emit_zstencil_format(GLcontext
*ctx
, struct radeon_state_atom
* atom
)
398 r300ContextPtr r300
= R300_CONTEXT(ctx
);
399 BATCH_LOCALS(&r300
->radeon
);
400 struct radeon_renderbuffer
*rrb
;
403 rrb
= radeon_get_depthbuffer(&r300
->radeon
);
408 format
= R300_DEPTHFORMAT_16BIT_INT_Z
;
409 else if (rrb
->cpp
== 4)
410 format
= R300_DEPTHFORMAT_24BIT_INT_Z_8BIT_STENCIL
;
413 OUT_BATCH(atom
->cmd
[0]);
414 atom
->cmd
[1] &= ~0xf;
415 atom
->cmd
[1] |= format
;
416 OUT_BATCH(atom
->cmd
[1]);
417 OUT_BATCH(atom
->cmd
[2]);
418 OUT_BATCH(atom
->cmd
[3]);
419 OUT_BATCH(atom
->cmd
[4]);
422 static int check_always(GLcontext
*ctx
, struct radeon_state_atom
*atom
)
424 return atom
->cmd_size
;
427 static int check_variable(GLcontext
*ctx
, struct radeon_state_atom
*atom
)
429 r300ContextPtr r300
= R300_CONTEXT(ctx
);
431 if (atom
->cmd
[0] == CP_PACKET2
) {
434 cnt
= packet0_count(r300
, atom
->cmd
);
435 return cnt
? cnt
+ 1 : 0;
438 int check_vpu(GLcontext
*ctx
, struct radeon_state_atom
*atom
)
442 cnt
= vpu_count(atom
->cmd
);
443 return cnt
? (cnt
* 4) + 1 : 0;
446 int check_r500fp(GLcontext
*ctx
, struct radeon_state_atom
*atom
)
450 cnt
= r500fp_count(atom
->cmd
);
451 return cnt
? (cnt
* 6) + 1 : 0;
454 int check_r500fp_const(GLcontext
*ctx
, struct radeon_state_atom
*atom
)
458 cnt
= r500fp_count(atom
->cmd
);
459 return cnt
? (cnt
* 4) + 1 : 0;
462 #define ALLOC_STATE( ATOM, CHK, SZ, IDX ) \
464 r300->hw.ATOM.cmd_size = (SZ); \
465 r300->hw.ATOM.cmd = (uint32_t*)CALLOC((SZ) * sizeof(uint32_t)); \
466 r300->hw.ATOM.name = #ATOM; \
467 r300->hw.ATOM.idx = (IDX); \
468 r300->hw.ATOM.check = check_##CHK; \
469 r300->hw.ATOM.dirty = GL_FALSE; \
470 r300->radeon.hw.max_state_size += (SZ); \
471 insert_at_tail(&r300->radeon.hw.atomlist, &r300->hw.ATOM); \
474 * Allocate memory for the command buffer and initialize the state atom
475 * list. Note that the initial hardware state is set by r300InitState().
477 void r300InitCmdBuf(r300ContextPtr r300
)
483 has_tcl
= r300
->options
.hw_tcl_enabled
;
485 if (r300
->radeon
.radeonScreen
->chip_family
>= CHIP_FAMILY_RV515
)
488 r300
->radeon
.hw
.max_state_size
= 2 + 2; /* reserve extra space for WAIT_IDLE and tex cache flush */
490 mtu
= r300
->radeon
.glCtx
->Const
.MaxTextureUnits
;
491 if (RADEON_DEBUG
& DEBUG_TEXTURE
) {
492 fprintf(stderr
, "Using %d maximum texture units..\n", mtu
);
495 /* Setup the atom linked list */
496 make_empty_list(&r300
->radeon
.hw
.atomlist
);
497 r300
->radeon
.hw
.atomlist
.name
= "atom-list";
499 /* Initialize state atoms */
500 ALLOC_STATE(vpt
, always
, R300_VPT_CMDSIZE
, 0);
501 r300
->hw
.vpt
.cmd
[R300_VPT_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_SE_VPORT_XSCALE
, 6);
502 ALLOC_STATE(vap_cntl
, always
, R300_VAP_CNTL_SIZE
, 0);
503 r300
->hw
.vap_cntl
.cmd
[R300_VAP_CNTL_FLUSH
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_VAP_PVS_STATE_FLUSH_REG
, 1);
504 r300
->hw
.vap_cntl
.cmd
[R300_VAP_CNTL_FLUSH_1
] = 0;
505 r300
->hw
.vap_cntl
.cmd
[R300_VAP_CNTL_CMD
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_VAP_CNTL
, 1);
507 ALLOC_STATE(vap_index_offset
, always
, 2, 0);
508 r300
->hw
.vap_index_offset
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R500_VAP_INDEX_OFFSET
, 1);
509 r300
->hw
.vap_index_offset
.cmd
[1] = 0;
511 ALLOC_STATE(vte
, always
, 3, 0);
512 r300
->hw
.vte
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_SE_VTE_CNTL
, 2);
513 ALLOC_STATE(vap_vf_max_vtx_indx
, always
, 3, 0);
514 r300
->hw
.vap_vf_max_vtx_indx
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_VAP_VF_MAX_VTX_INDX
, 2);
515 ALLOC_STATE(vap_cntl_status
, always
, 2, 0);
516 r300
->hw
.vap_cntl_status
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_VAP_CNTL_STATUS
, 1);
517 ALLOC_STATE(vir
[0], variable
, R300_VIR_CMDSIZE
, 0);
518 r300
->hw
.vir
[0].cmd
[R300_VIR_CMD_0
] =
519 cmdpacket0(r300
->radeon
.radeonScreen
, R300_VAP_PROG_STREAM_CNTL_0
, 1);
520 ALLOC_STATE(vir
[1], variable
, R300_VIR_CMDSIZE
, 1);
521 r300
->hw
.vir
[1].cmd
[R300_VIR_CMD_0
] =
522 cmdpacket0(r300
->radeon
.radeonScreen
, R300_VAP_PROG_STREAM_CNTL_EXT_0
, 1);
523 ALLOC_STATE(vic
, always
, R300_VIC_CMDSIZE
, 0);
524 r300
->hw
.vic
.cmd
[R300_VIC_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_VAP_VTX_STATE_CNTL
, 2);
525 ALLOC_STATE(vap_psc_sgn_norm_cntl
, always
, 2, 0);
526 r300
->hw
.vap_psc_sgn_norm_cntl
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_VAP_PSC_SGN_NORM_CNTL
, SGN_NORM_ZERO_CLAMP_MINUS_ONE
);
529 ALLOC_STATE(vap_clip_cntl
, always
, 2, 0);
530 r300
->hw
.vap_clip_cntl
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_VAP_CLIP_CNTL
, 1);
531 ALLOC_STATE(vap_clip
, always
, 5, 0);
532 r300
->hw
.vap_clip
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_VAP_GB_VERT_CLIP_ADJ
, 4);
533 ALLOC_STATE(vap_pvs_vtx_timeout_reg
, always
, 2, 0);
534 r300
->hw
.vap_pvs_vtx_timeout_reg
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, VAP_PVS_VTX_TIMEOUT_REG
, 1);
537 ALLOC_STATE(vof
, always
, R300_VOF_CMDSIZE
, 0);
538 r300
->hw
.vof
.cmd
[R300_VOF_CMD_0
] =
539 cmdpacket0(r300
->radeon
.radeonScreen
, R300_VAP_OUTPUT_VTX_FMT_0
, 2);
542 ALLOC_STATE(pvs
, always
, R300_PVS_CMDSIZE
, 0);
543 r300
->hw
.pvs
.cmd
[R300_PVS_CMD_0
] =
544 cmdpacket0(r300
->radeon
.radeonScreen
, R300_VAP_PVS_CODE_CNTL_0
, 3);
547 ALLOC_STATE(gb_enable
, always
, 2, 0);
548 r300
->hw
.gb_enable
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_GB_ENABLE
, 1);
549 ALLOC_STATE(gb_misc
, always
, R300_GB_MISC_CMDSIZE
, 0);
550 r300
->hw
.gb_misc
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_GB_MSPOS0
, 3);
551 r300
->hw
.gb_misc
.emit
= emit_gb_misc
;
552 ALLOC_STATE(gb_misc2
, always
, R300_GB_MISC2_CMDSIZE
, 0);
553 r300
->hw
.gb_misc2
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, 0x401C, 2);
554 ALLOC_STATE(txe
, always
, R300_TXE_CMDSIZE
, 0);
555 r300
->hw
.txe
.cmd
[R300_TXE_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_TX_ENABLE
, 1);
556 ALLOC_STATE(ga_point_s0
, always
, 5, 0);
557 r300
->hw
.ga_point_s0
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_GA_POINT_S0
, 4);
558 ALLOC_STATE(ga_triangle_stipple
, always
, 2, 0);
559 r300
->hw
.ga_triangle_stipple
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_GA_TRIANGLE_STIPPLE
, 1);
560 ALLOC_STATE(ps
, always
, R300_PS_CMDSIZE
, 0);
561 r300
->hw
.ps
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_GA_POINT_SIZE
, 1);
562 ALLOC_STATE(ga_point_minmax
, always
, 4, 0);
563 r300
->hw
.ga_point_minmax
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_GA_POINT_MINMAX
, 3);
564 ALLOC_STATE(lcntl
, always
, 2, 0);
565 r300
->hw
.lcntl
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_GA_LINE_CNTL
, 1);
566 ALLOC_STATE(ga_line_stipple
, always
, 4, 0);
567 r300
->hw
.ga_line_stipple
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_GA_LINE_STIPPLE_VALUE
, 3);
568 ALLOC_STATE(shade
, always
, 2, 0);
569 r300
->hw
.shade
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_GA_ENHANCE
, 1);
570 r300
->hw
.shade
.emit
= emit_shade_misc
;
571 ALLOC_STATE(shade2
, always
, 4, 0);
572 r300
->hw
.shade2
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, 0x4278, 3);
573 ALLOC_STATE(polygon_mode
, always
, 4, 0);
574 r300
->hw
.polygon_mode
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_GA_POLY_MODE
, 3);
575 ALLOC_STATE(fogp
, always
, 3, 0);
576 r300
->hw
.fogp
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_GA_FOG_SCALE
, 2);
577 ALLOC_STATE(zbias_cntl
, always
, 2, 0);
578 r300
->hw
.zbias_cntl
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_SU_TEX_WRAP
, 1);
579 ALLOC_STATE(zbs
, always
, R300_ZBS_CMDSIZE
, 0);
580 r300
->hw
.zbs
.cmd
[R300_ZBS_CMD_0
] =
581 cmdpacket0(r300
->radeon
.radeonScreen
, R300_SU_POLY_OFFSET_FRONT_SCALE
, 4);
582 ALLOC_STATE(occlusion_cntl
, always
, 2, 0);
583 r300
->hw
.occlusion_cntl
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_SU_POLY_OFFSET_ENABLE
, 1);
584 ALLOC_STATE(cul
, always
, R300_CUL_CMDSIZE
, 0);
585 r300
->hw
.cul
.cmd
[R300_CUL_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_SU_CULL_MODE
, 1);
586 ALLOC_STATE(su_depth_scale
, always
, 3, 0);
587 r300
->hw
.su_depth_scale
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_SU_DEPTH_SCALE
, 2);
588 ALLOC_STATE(rc
, always
, R300_RC_CMDSIZE
, 0);
589 r300
->hw
.rc
.cmd
[R300_RC_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_RS_COUNT
, 2);
591 ALLOC_STATE(ri
, variable
, R500_RI_CMDSIZE
, 0);
592 r300
->hw
.ri
.cmd
[R300_RI_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R500_RS_IP_0
, 16);
593 ALLOC_STATE(rr
, variable
, R300_RR_CMDSIZE
, 0);
594 r300
->hw
.rr
.cmd
[R300_RR_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R500_RS_INST_0
, 1);
596 ALLOC_STATE(ri
, variable
, R300_RI_CMDSIZE
, 0);
597 r300
->hw
.ri
.cmd
[R300_RI_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_RS_IP_0
, 8);
598 ALLOC_STATE(rr
, variable
, R300_RR_CMDSIZE
, 0);
599 r300
->hw
.rr
.cmd
[R300_RR_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_RS_INST_0
, 1);
601 ALLOC_STATE(sc_hyperz
, always
, 3, 0);
602 r300
->hw
.sc_hyperz
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_SC_HYPERZ
, 2);
603 ALLOC_STATE(sc_screendoor
, always
, 2, 0);
604 r300
->hw
.sc_screendoor
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_SC_SCREENDOOR
, 1);
605 ALLOC_STATE(us_out_fmt
, always
, 6, 0);
606 r300
->hw
.us_out_fmt
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_US_OUT_FMT
, 5);
609 ALLOC_STATE(fp
, always
, R500_FP_CMDSIZE
, 0);
610 r300
->hw
.fp
.cmd
[R500_FP_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R500_US_CONFIG
, 2);
611 r300
->hw
.fp
.cmd
[R500_FP_CNTL
] = R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO
;
612 r300
->hw
.fp
.cmd
[R500_FP_CMD_1
] = cmdpacket0(r300
->radeon
.radeonScreen
, R500_US_CODE_ADDR
, 3);
613 r300
->hw
.fp
.cmd
[R500_FP_CMD_2
] = cmdpacket0(r300
->radeon
.radeonScreen
, R500_US_FC_CTRL
, 1);
614 r300
->hw
.fp
.cmd
[R500_FP_FC_CNTL
] = 0; /* FIXME when we add flow control */
616 ALLOC_STATE(r500fp
, r500fp
, R500_FPI_CMDSIZE
, 0);
617 r300
->hw
.r500fp
.cmd
[R300_FPI_CMD_0
] =
618 cmdr500fp(r300
->radeon
.radeonScreen
, 0, 0, 0, 0);
619 r300
->hw
.r500fp
.emit
= emit_r500fp
;
620 ALLOC_STATE(r500fp_const
, r500fp_const
, R500_FPP_CMDSIZE
, 0);
621 r300
->hw
.r500fp_const
.cmd
[R300_FPI_CMD_0
] =
622 cmdr500fp(r300
->radeon
.radeonScreen
, 0, 0, 1, 0);
623 r300
->hw
.r500fp_const
.emit
= emit_r500fp
;
625 ALLOC_STATE(fp
, always
, R300_FP_CMDSIZE
, 0);
626 r300
->hw
.fp
.cmd
[R300_FP_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_US_CONFIG
, 3);
627 r300
->hw
.fp
.cmd
[R300_FP_CMD_1
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_US_CODE_ADDR_0
, 4);
629 ALLOC_STATE(fpt
, variable
, R300_FPT_CMDSIZE
, 0);
630 r300
->hw
.fpt
.cmd
[R300_FPT_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_US_TEX_INST_0
, 0);
632 ALLOC_STATE(fpi
[0], variable
, R300_FPI_CMDSIZE
, 0);
633 r300
->hw
.fpi
[0].cmd
[R300_FPI_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_US_ALU_RGB_INST_0
, 1);
634 ALLOC_STATE(fpi
[1], variable
, R300_FPI_CMDSIZE
, 1);
635 r300
->hw
.fpi
[1].cmd
[R300_FPI_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_US_ALU_RGB_ADDR_0
, 1);
636 ALLOC_STATE(fpi
[2], variable
, R300_FPI_CMDSIZE
, 2);
637 r300
->hw
.fpi
[2].cmd
[R300_FPI_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_US_ALU_ALPHA_INST_0
, 1);
638 ALLOC_STATE(fpi
[3], variable
, R300_FPI_CMDSIZE
, 3);
639 r300
->hw
.fpi
[3].cmd
[R300_FPI_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_US_ALU_ALPHA_ADDR_0
, 1);
640 ALLOC_STATE(fpp
, variable
, R300_FPP_CMDSIZE
, 0);
641 r300
->hw
.fpp
.cmd
[R300_FPP_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_PFS_PARAM_0_X
, 0);
643 ALLOC_STATE(fogs
, always
, R300_FOGS_CMDSIZE
, 0);
644 r300
->hw
.fogs
.cmd
[R300_FOGS_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_FG_FOG_BLEND
, 1);
645 ALLOC_STATE(fogc
, always
, R300_FOGC_CMDSIZE
, 0);
646 r300
->hw
.fogc
.cmd
[R300_FOGC_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_FG_FOG_COLOR_R
, 3);
647 ALLOC_STATE(at
, always
, R300_AT_CMDSIZE
, 0);
648 r300
->hw
.at
.cmd
[R300_AT_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_FG_ALPHA_FUNC
, 2);
649 ALLOC_STATE(fg_depth_src
, always
, 2, 0);
650 r300
->hw
.fg_depth_src
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_FG_DEPTH_SRC
, 1);
651 ALLOC_STATE(rb3d_cctl
, always
, 2, 0);
652 r300
->hw
.rb3d_cctl
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_RB3D_CCTL
, 1);
653 ALLOC_STATE(bld
, always
, R300_BLD_CMDSIZE
, 0);
654 r300
->hw
.bld
.cmd
[R300_BLD_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_RB3D_CBLEND
, 2);
655 ALLOC_STATE(cmk
, always
, R300_CMK_CMDSIZE
, 0);
656 r300
->hw
.cmk
.cmd
[R300_CMK_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, RB3D_COLOR_CHANNEL_MASK
, 1);
658 ALLOC_STATE(blend_color
, always
, 3, 0);
659 r300
->hw
.blend_color
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R500_RB3D_CONSTANT_COLOR_AR
, 2);
661 ALLOC_STATE(blend_color
, always
, 2, 0);
662 r300
->hw
.blend_color
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_RB3D_BLEND_COLOR
, 1);
664 ALLOC_STATE(rop
, always
, 2, 0);
665 r300
->hw
.rop
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_RB3D_ROPCNTL
, 1);
666 ALLOC_STATE(cb
, always
, R300_CB_CMDSIZE
, 0);
667 r300
->hw
.cb
.emit
= &emit_cb_offset
;
668 ALLOC_STATE(rb3d_dither_ctl
, always
, 10, 0);
669 r300
->hw
.rb3d_dither_ctl
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_RB3D_DITHER_CTL
, 9);
670 ALLOC_STATE(rb3d_aaresolve_ctl
, always
, 2, 0);
671 r300
->hw
.rb3d_aaresolve_ctl
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_RB3D_AARESOLVE_CTL
, 1);
672 ALLOC_STATE(rb3d_discard_src_pixel_lte_threshold
, always
, 3, 0);
673 r300
->hw
.rb3d_discard_src_pixel_lte_threshold
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R500_RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD
, 2);
674 r300
->hw
.rb3d_discard_src_pixel_lte_threshold
.emit
= emit_threshold_misc
;
675 ALLOC_STATE(zs
, always
, R300_ZS_CMDSIZE
, 0);
676 r300
->hw
.zs
.cmd
[R300_ZS_CMD_0
] =
677 cmdpacket0(r300
->radeon
.radeonScreen
, R300_ZB_CNTL
, 3);
679 ALLOC_STATE(zstencil_format
, always
, 5, 0);
680 r300
->hw
.zstencil_format
.cmd
[0] =
681 cmdpacket0(r300
->radeon
.radeonScreen
, R300_ZB_FORMAT
, 4);
682 r300
->hw
.zstencil_format
.emit
= emit_zstencil_format
;
684 ALLOC_STATE(zb
, always
, R300_ZB_CMDSIZE
, 0);
685 r300
->hw
.zb
.emit
= emit_zb_offset
;
686 ALLOC_STATE(zb_depthclearvalue
, always
, 2, 0);
687 r300
->hw
.zb_depthclearvalue
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_ZB_DEPTHCLEARVALUE
, 1);
688 ALLOC_STATE(zb_zmask
, always
, 3, 0);
689 r300
->hw
.zb_zmask
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_ZB_ZMASK_OFFSET
, 2);
690 ALLOC_STATE(zb_hiz_offset
, always
, 2, 0);
691 r300
->hw
.zb_hiz_offset
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_ZB_HIZ_OFFSET
, 1);
692 ALLOC_STATE(zb_hiz_pitch
, always
, 2, 0);
693 r300
->hw
.zb_hiz_pitch
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_ZB_HIZ_PITCH
, 1);
695 /* VPU only on TCL */
698 ALLOC_STATE(vpi
, vpu
, R300_VPI_CMDSIZE
, 0);
699 r300
->hw
.vpi
.cmd
[0] =
700 cmdvpu(r300
->radeon
.radeonScreen
, R300_PVS_CODE_START
, 0);
701 r300
->hw
.vpi
.emit
= emit_vpu
;
704 ALLOC_STATE(vpp
, vpu
, R300_VPP_CMDSIZE
, 0);
705 r300
->hw
.vpp
.cmd
[0] =
706 cmdvpu(r300
->radeon
.radeonScreen
, R500_PVS_CONST_START
, 0);
707 r300
->hw
.vpp
.emit
= emit_vpu
;
709 ALLOC_STATE(vps
, vpu
, R300_VPS_CMDSIZE
, 0);
710 r300
->hw
.vps
.cmd
[0] =
711 cmdvpu(r300
->radeon
.radeonScreen
, R500_POINT_VPORT_SCALE_OFFSET
, 1);
712 r300
->hw
.vps
.emit
= emit_vpu
;
714 for (i
= 0; i
< 6; i
++) {
715 ALLOC_STATE(vpucp
[i
], vpu
, R300_VPUCP_CMDSIZE
, 0);
716 r300
->hw
.vpucp
[i
].cmd
[0] =
717 cmdvpu(r300
->radeon
.radeonScreen
,
718 R500_PVS_UCP_START
+ i
, 1);
719 r300
->hw
.vpucp
[i
].emit
= emit_vpu
;
722 ALLOC_STATE(vpp
, vpu
, R300_VPP_CMDSIZE
, 0);
723 r300
->hw
.vpp
.cmd
[0] =
724 cmdvpu(r300
->radeon
.radeonScreen
, R300_PVS_CONST_START
, 0);
725 r300
->hw
.vpp
.emit
= emit_vpu
;
727 ALLOC_STATE(vps
, vpu
, R300_VPS_CMDSIZE
, 0);
728 r300
->hw
.vps
.cmd
[0] =
729 cmdvpu(r300
->radeon
.radeonScreen
, R300_POINT_VPORT_SCALE_OFFSET
, 1);
730 r300
->hw
.vps
.emit
= emit_vpu
;
732 for (i
= 0; i
< 6; i
++) {
733 ALLOC_STATE(vpucp
[i
], vpu
, R300_VPUCP_CMDSIZE
, 0);
734 r300
->hw
.vpucp
[i
].cmd
[0] =
735 cmdvpu(r300
->radeon
.radeonScreen
,
736 R300_PVS_UCP_START
+ i
, 1);
737 r300
->hw
.vpucp
[i
].emit
= emit_vpu
;
743 ALLOC_STATE(tex
.filter
, variable
, mtu
+ 1, 0);
744 r300
->hw
.tex
.filter
.cmd
[R300_TEX_CMD_0
] =
745 cmdpacket0(r300
->radeon
.radeonScreen
, R300_TX_FILTER0_0
, 0);
747 ALLOC_STATE(tex
.filter_1
, variable
, mtu
+ 1, 0);
748 r300
->hw
.tex
.filter_1
.cmd
[R300_TEX_CMD_0
] =
749 cmdpacket0(r300
->radeon
.radeonScreen
, R300_TX_FILTER1_0
, 0);
751 ALLOC_STATE(tex
.size
, variable
, mtu
+ 1, 0);
752 r300
->hw
.tex
.size
.cmd
[R300_TEX_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_TX_SIZE_0
, 0);
754 ALLOC_STATE(tex
.format
, variable
, mtu
+ 1, 0);
755 r300
->hw
.tex
.format
.cmd
[R300_TEX_CMD_0
] =
756 cmdpacket0(r300
->radeon
.radeonScreen
, R300_TX_FORMAT_0
, 0);
758 ALLOC_STATE(tex
.pitch
, variable
, mtu
+ 1, 0);
759 r300
->hw
.tex
.pitch
.cmd
[R300_TEX_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_TX_FORMAT2_0
, 0);
761 ALLOC_STATE(tex
.offset
, variable
, 1, 0);
762 r300
->hw
.tex
.offset
.cmd
[R300_TEX_CMD_0
] =
763 cmdpacket0(r300
->radeon
.radeonScreen
, R300_TX_OFFSET_0
, 0);
764 r300
->hw
.tex
.offset
.emit
= &emit_tex_offsets
;
766 ALLOC_STATE(tex
.chroma_key
, variable
, mtu
+ 1, 0);
767 r300
->hw
.tex
.chroma_key
.cmd
[R300_TEX_CMD_0
] =
768 cmdpacket0(r300
->radeon
.radeonScreen
, R300_TX_CHROMA_KEY_0
, 0);
770 ALLOC_STATE(tex
.border_color
, variable
, mtu
+ 1, 0);
771 r300
->hw
.tex
.border_color
.cmd
[R300_TEX_CMD_0
] =
772 cmdpacket0(r300
->radeon
.radeonScreen
, R300_TX_BORDER_COLOR_0
, 0);
774 r300
->radeon
.hw
.is_dirty
= GL_TRUE
;
775 r300
->radeon
.hw
.all_dirty
= GL_TRUE
;
777 rcommonInitCmdBuf(&r300
->radeon
);