2 Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
4 The Weather Channel (TM) funded Tungsten Graphics to develop the
5 initial release of the Radeon 8500 driver under the XFree86 license.
6 This notice must be preserved.
8 Permission is hereby granted, free of charge, to any person obtaining
9 a copy of this software and associated documentation files (the
10 "Software"), to deal in the Software without restriction, including
11 without limitation the rights to use, copy, modify, merge, publish,
12 distribute, sublicense, and/or sell copies of the Software, and to
13 permit persons to whom the Software is furnished to do so, subject to
14 the following conditions:
16 The above copyright notice and this permission notice (including the
17 next paragraph) shall be included in all copies or substantial
18 portions of the Software.
20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
28 **************************************************************************/
33 * \author Nicolai Haehnle <prefect_@gmx.net>
36 #include "main/glheader.h"
37 #include "main/state.h"
38 #include "main/imports.h"
39 #include "main/macros.h"
40 #include "main/context.h"
41 #include "main/simple_list.h"
42 #include "swrast/swrast.h"
45 #include "radeon_drm.h"
47 #include "r300_context.h"
48 #include "r300_ioctl.h"
49 #include "radeon_reg.h"
51 #include "r300_cmdbuf.h"
52 #include "r300_emit.h"
53 #include "radeon_bocs_wrapper.h"
54 #include "radeon_mipmap_tree.h"
55 #include "r300_state.h"
56 #include "radeon_reg.h"
57 #include "radeon_queryobj.h"
59 /** # of dwords reserved for additional instructions that may need to be written
62 #define SPACE_FOR_FLUSHING 4
64 static unsigned packet0_count(r300ContextPtr r300
, uint32_t *pkt
)
66 if (r300
->radeon
.radeonScreen
->kernel_mm
) {
67 return ((((*pkt
) >> 16) & 0x3FFF) + 1);
69 drm_r300_cmd_header_t
*t
= (drm_r300_cmd_header_t
*)pkt
;
70 return t
->packet0
.count
;
74 #define vpu_count(ptr) (((drm_r300_cmd_header_t*)(ptr))->vpu.count)
75 #define r500fp_count(ptr) (((drm_r300_cmd_header_t*)(ptr))->r500fp.count)
77 int check_vpu(GLcontext
*ctx
, struct radeon_state_atom
*atom
)
79 r300ContextPtr r300
= R300_CONTEXT(ctx
);
82 cnt
= vpu_count(atom
->cmd
);
84 if (r300
->radeon
.radeonScreen
->kernel_mm
) {
88 return cnt
? (cnt
* 4) + extra
: 0;
92 void emit_vpu(GLcontext
*ctx
, struct radeon_state_atom
* atom
)
94 r300ContextPtr r300
= R300_CONTEXT(ctx
);
95 BATCH_LOCALS(&r300
->radeon
);
96 drm_r300_cmd_header_t cmd
;
100 addr
= (cmd
.vpu
.adrhi
<< 8) | cmd
.vpu
.adrlo
;
101 ndw
= atom
->check(ctx
, atom
);
103 BEGIN_BATCH_NO_AUTOSTATE(ndw
);
106 OUT_BATCH_REGVAL(R300_VAP_PVS_VECTOR_INDX_REG
, addr
);
107 OUT_BATCH(CP_PACKET0(R300_VAP_PVS_UPLOAD_DATA
, ndw
-1) | RADEON_ONE_REG_WR
);
108 OUT_BATCH_TABLE(&atom
->cmd
[1], ndw
);
109 OUT_BATCH_REGVAL(R300_VAP_PVS_STATE_FLUSH_REG
, 0);
113 void emit_r500fp(GLcontext
*ctx
, struct radeon_state_atom
* atom
)
115 r300ContextPtr r300
= R300_CONTEXT(ctx
);
116 BATCH_LOCALS(&r300
->radeon
);
117 drm_r300_cmd_header_t cmd
;
118 uint32_t addr
, ndw
, sz
;
121 ndw
= atom
->check(ctx
, atom
);
123 cmd
.u
= atom
->cmd
[0];
124 sz
= cmd
.r500fp
.count
;
125 addr
= ((cmd
.r500fp
.adrhi_flags
& 1) << 8) | cmd
.r500fp
.adrlo
;
126 type
= !!(cmd
.r500fp
.adrhi_flags
& R500FP_CONSTANT_TYPE
);
127 clamp
= !!(cmd
.r500fp
.adrhi_flags
& R500FP_CONSTANT_CLAMP
);
129 addr
|= (type
<< 16);
130 addr
|= (clamp
<< 17);
132 BEGIN_BATCH_NO_AUTOSTATE(ndw
);
133 OUT_BATCH(CP_PACKET0(R500_GA_US_VECTOR_INDEX
, 0));
136 OUT_BATCH(CP_PACKET0(R500_GA_US_VECTOR_DATA
, ndw
-1) | RADEON_ONE_REG_WR
);
137 OUT_BATCH_TABLE(&atom
->cmd
[1], ndw
);
141 static int check_tex_offsets(GLcontext
*ctx
, struct radeon_state_atom
* atom
)
143 r300ContextPtr r300
= R300_CONTEXT(ctx
);
144 int numtmus
= packet0_count(r300
, r300
->hw
.tex
.offset
.cmd
);
146 if (atom
->cmd
[0] == CP_PACKET2
) {
149 for(i
= 0; i
< numtmus
; ++i
) {
150 radeonTexObj
*t
= r300
->hw
.textures
[i
];
151 if (!t
&& !r300
->radeon
.radeonScreen
->kernel_mm
) {
153 } else if (t
&& t
->image_override
&& !t
->bo
) {
154 if (!r300
->radeon
.radeonScreen
->kernel_mm
)
162 static void emit_tex_offsets(GLcontext
*ctx
, struct radeon_state_atom
* atom
)
164 r300ContextPtr r300
= R300_CONTEXT(ctx
);
165 BATCH_LOCALS(&r300
->radeon
);
166 int numtmus
= packet0_count(r300
, r300
->hw
.tex
.offset
.cmd
);
169 for(i
= 0; i
< numtmus
; ++i
) {
170 radeonTexObj
*t
= r300
->hw
.textures
[i
];
171 if (t
&& !t
->image_override
) {
172 BEGIN_BATCH_NO_AUTOSTATE(4);
173 OUT_BATCH_REGSEQ(R300_TX_OFFSET_0
+ (i
* 4), 1);
174 OUT_BATCH_RELOC(t
->tile_bits
, t
->mt
->bo
, 0,
175 RADEON_GEM_DOMAIN_GTT
|RADEON_GEM_DOMAIN_VRAM
, 0, 0);
178 /* Texture unit hasn't a texture bound.
179 * We assign the current color buffer as a fakery to make
180 * KIL work on KMS (without it, the CS checker will complain).
182 if (r300
->radeon
.radeonScreen
->kernel_mm
) {
183 struct radeon_renderbuffer
*rrb
= radeon_get_colorbuffer(&r300
->radeon
);
184 if (rrb
&& rrb
->bo
) {
185 BEGIN_BATCH_NO_AUTOSTATE(4);
186 OUT_BATCH_REGSEQ(R300_TX_OFFSET_0
+ (i
* 4), 1);
187 OUT_BATCH_RELOC(0, rrb
->bo
, 0,
188 RADEON_GEM_DOMAIN_GTT
|RADEON_GEM_DOMAIN_VRAM
, 0, 0);
192 } else { /* override cases */
194 BEGIN_BATCH_NO_AUTOSTATE(4);
195 OUT_BATCH_REGSEQ(R300_TX_OFFSET_0
+ (i
* 4), 1);
196 OUT_BATCH_RELOC(t
->tile_bits
, t
->bo
, 0,
197 RADEON_GEM_DOMAIN_GTT
|RADEON_GEM_DOMAIN_VRAM
, 0, 0);
199 } else if (!r300
->radeon
.radeonScreen
->kernel_mm
) {
200 BEGIN_BATCH_NO_AUTOSTATE(2);
201 OUT_BATCH_REGSEQ(R300_TX_OFFSET_0
+ (i
* 4), 1);
202 OUT_BATCH(t
->override_offset
);
205 /* Texture unit hasn't a texture bound nothings to do */
211 void r300_emit_scissor(GLcontext
*ctx
)
213 r300ContextPtr r300
= R300_CONTEXT(ctx
);
214 BATCH_LOCALS(&r300
->radeon
);
215 unsigned x1
, y1
, x2
, y2
;
216 struct radeon_renderbuffer
*rrb
;
218 if (!r300
->radeon
.radeonScreen
->driScreen
->dri2
.enabled
) {
221 rrb
= radeon_get_colorbuffer(&r300
->radeon
);
222 if (!rrb
|| !rrb
->bo
) {
223 fprintf(stderr
, "no rrb\n");
226 if (r300
->radeon
.state
.scissor
.enabled
) {
227 x1
= r300
->radeon
.state
.scissor
.rect
.x1
;
228 y1
= r300
->radeon
.state
.scissor
.rect
.y1
;
229 x2
= r300
->radeon
.state
.scissor
.rect
.x2
;
230 y2
= r300
->radeon
.state
.scissor
.rect
.y2
;
234 x2
= rrb
->base
.Width
- 1;
235 y2
= rrb
->base
.Height
- 1;
237 if (r300
->radeon
.radeonScreen
->chip_family
< CHIP_FAMILY_RV515
) {
238 x1
+= R300_SCISSORS_OFFSET
;
239 y1
+= R300_SCISSORS_OFFSET
;
240 x2
+= R300_SCISSORS_OFFSET
;
241 y2
+= R300_SCISSORS_OFFSET
;
243 BEGIN_BATCH_NO_AUTOSTATE(3);
244 OUT_BATCH_REGSEQ(R300_SC_SCISSORS_TL
, 2);
245 OUT_BATCH((x1
<< R300_SCISSORS_X_SHIFT
)|(y1
<< R300_SCISSORS_Y_SHIFT
));
246 OUT_BATCH((x2
<< R300_SCISSORS_X_SHIFT
)|(y2
<< R300_SCISSORS_Y_SHIFT
));
249 static int check_cb_offset(GLcontext
*ctx
, struct radeon_state_atom
* atom
)
251 r300ContextPtr r300
= R300_CONTEXT(ctx
);
252 uint32_t dw
= 6 + 3 + 16;
253 if (r300
->radeon
.radeonScreen
->kernel_mm
)
255 if (!r300
->radeon
.radeonScreen
->driScreen
->dri2
.enabled
) {
261 static void emit_cb_offset(GLcontext
*ctx
, struct radeon_state_atom
* atom
)
263 r300ContextPtr r300
= R300_CONTEXT(ctx
);
264 BATCH_LOCALS(&r300
->radeon
);
265 struct radeon_renderbuffer
*rrb
;
267 uint32_t offset
= r300
->radeon
.state
.color
.draw_offset
;
271 rrb
= radeon_get_colorbuffer(&r300
->radeon
);
272 if (!rrb
|| !rrb
->bo
) {
273 fprintf(stderr
, "no rrb\n");
277 if (RADEON_DEBUG
& RADEON_STATE
)
278 fprintf(stderr
,"rrb is %p %d %dx%d\n", rrb
, offset
, rrb
->base
.Width
, rrb
->base
.Height
);
279 cbpitch
= (rrb
->pitch
/ rrb
->cpp
);
281 cbpitch
|= R300_COLOR_FORMAT_ARGB8888
;
282 else switch (rrb
->base
._ActualFormat
) {
284 cbpitch
|= R300_COLOR_FORMAT_RGB565
;
287 cbpitch
|= R300_COLOR_FORMAT_ARGB4444
;
290 cbpitch
|= R300_COLOR_FORMAT_ARGB1555
;
294 if (rrb
->bo
->flags
& RADEON_BO_FLAGS_MACRO_TILE
)
295 cbpitch
|= R300_COLOR_TILE_ENABLE
;
297 if (r300
->radeon
.radeonScreen
->kernel_mm
)
299 BEGIN_BATCH_NO_AUTOSTATE(dw
);
300 OUT_BATCH_REGSEQ(R300_RB3D_COLOROFFSET0
, 1);
301 OUT_BATCH_RELOC(offset
, rrb
->bo
, offset
, 0, RADEON_GEM_DOMAIN_VRAM
, 0);
302 OUT_BATCH_REGSEQ(R300_RB3D_COLORPITCH0
, 1);
303 if (!r300
->radeon
.radeonScreen
->kernel_mm
)
306 OUT_BATCH_RELOC(cbpitch
, rrb
->bo
, cbpitch
, 0, RADEON_GEM_DOMAIN_VRAM
, 0);
308 if (r300
->radeon
.radeonScreen
->driScreen
->dri2
.enabled
) {
309 if (r300
->radeon
.radeonScreen
->chip_family
>= CHIP_FAMILY_RV515
) {
310 BEGIN_BATCH_NO_AUTOSTATE(3);
311 OUT_BATCH_REGSEQ(R300_SC_SCISSORS_TL
, 2);
313 OUT_BATCH(((rrb
->base
.Width
- 1) << R300_SCISSORS_X_SHIFT
) |
314 ((rrb
->base
.Height
- 1) << R300_SCISSORS_Y_SHIFT
));
316 BEGIN_BATCH_NO_AUTOSTATE(16);
317 for (i
= 0; i
< 4; i
++) {
318 OUT_BATCH_REGSEQ(R300_SC_CLIPRECT_TL_0
+ (i
* 8), 2);
319 OUT_BATCH((0 << R300_CLIPRECT_X_SHIFT
) | (0 << R300_CLIPRECT_Y_SHIFT
));
320 OUT_BATCH(((rrb
->base
.Width
- 1) << R300_CLIPRECT_X_SHIFT
) | ((rrb
->base
.Height
- 1) << R300_CLIPRECT_Y_SHIFT
));
322 OUT_BATCH_REGSEQ(R300_SC_CLIP_RULE
, 1);
324 OUT_BATCH_REGSEQ(R300_SC_SCREENDOOR
, 1);
328 BEGIN_BATCH_NO_AUTOSTATE(3);
329 OUT_BATCH_REGSEQ(R300_SC_SCISSORS_TL
, 2);
330 OUT_BATCH((R300_SCISSORS_OFFSET
<< R300_SCISSORS_X_SHIFT
) |
331 (R300_SCISSORS_OFFSET
<< R300_SCISSORS_Y_SHIFT
));
332 OUT_BATCH(((rrb
->base
.Width
+ R300_SCISSORS_OFFSET
- 1) << R300_SCISSORS_X_SHIFT
) |
333 ((rrb
->base
.Height
+ R300_SCISSORS_OFFSET
- 1) << R300_SCISSORS_Y_SHIFT
));
335 BEGIN_BATCH_NO_AUTOSTATE(16);
336 for (i
= 0; i
< 4; i
++) {
337 OUT_BATCH_REGSEQ(R300_SC_CLIPRECT_TL_0
+ (i
* 8), 2);
338 OUT_BATCH((R300_SCISSORS_OFFSET
<< R300_CLIPRECT_X_SHIFT
) | (R300_SCISSORS_OFFSET
<< R300_CLIPRECT_Y_SHIFT
));
339 OUT_BATCH(((R300_SCISSORS_OFFSET
+ rrb
->base
.Width
- 1) << R300_CLIPRECT_X_SHIFT
) |
340 ((R300_SCISSORS_OFFSET
+ rrb
->base
.Height
- 1) << R300_CLIPRECT_Y_SHIFT
));
342 OUT_BATCH_REGSEQ(R300_SC_CLIP_RULE
, 1);
344 OUT_BATCH_REGSEQ(R300_SC_SCREENDOOR
, 1);
351 static int check_zb_offset(GLcontext
*ctx
, struct radeon_state_atom
* atom
)
353 r300ContextPtr r300
= R300_CONTEXT(ctx
);
356 if (r300
->radeon
.radeonScreen
->kernel_mm
)
361 static void emit_zb_offset(GLcontext
*ctx
, struct radeon_state_atom
* atom
)
363 r300ContextPtr r300
= R300_CONTEXT(ctx
);
364 BATCH_LOCALS(&r300
->radeon
);
365 struct radeon_renderbuffer
*rrb
;
367 uint32_t dw
= atom
->check(ctx
, atom
);
369 rrb
= radeon_get_depthbuffer(&r300
->radeon
);
373 zbpitch
= (rrb
->pitch
/ rrb
->cpp
);
374 if (!r300
->radeon
.radeonScreen
->kernel_mm
) {
375 if (rrb
->bo
->flags
& RADEON_BO_FLAGS_MACRO_TILE
) {
376 zbpitch
|= R300_DEPTHMACROTILE_ENABLE
;
378 if (rrb
->bo
->flags
& RADEON_BO_FLAGS_MICRO_TILE
){
379 zbpitch
|= R300_DEPTHMICROTILE_TILED
;
383 BEGIN_BATCH_NO_AUTOSTATE(dw
);
384 OUT_BATCH_REGSEQ(R300_ZB_DEPTHOFFSET
, 1);
385 OUT_BATCH_RELOC(0, rrb
->bo
, 0, 0, RADEON_GEM_DOMAIN_VRAM
, 0);
386 OUT_BATCH_REGSEQ(R300_ZB_DEPTHPITCH
, 1);
387 if (!r300
->radeon
.radeonScreen
->kernel_mm
)
390 OUT_BATCH_RELOC(cbpitch
, rrb
->bo
, zbpitch
, 0, RADEON_GEM_DOMAIN_VRAM
, 0);
394 static void emit_zstencil_format(GLcontext
*ctx
, struct radeon_state_atom
* atom
)
396 r300ContextPtr r300
= R300_CONTEXT(ctx
);
397 BATCH_LOCALS(&r300
->radeon
);
398 struct radeon_renderbuffer
*rrb
;
401 rrb
= radeon_get_depthbuffer(&r300
->radeon
);
406 format
= R300_DEPTHFORMAT_16BIT_INT_Z
;
407 else if (rrb
->cpp
== 4)
408 format
= R300_DEPTHFORMAT_24BIT_INT_Z_8BIT_STENCIL
;
411 BEGIN_BATCH_NO_AUTOSTATE(atom
->cmd_size
);
412 OUT_BATCH(atom
->cmd
[0]);
413 atom
->cmd
[1] &= ~0xf;
414 atom
->cmd
[1] |= format
;
415 OUT_BATCH(atom
->cmd
[1]);
416 OUT_BATCH(atom
->cmd
[2]);
417 OUT_BATCH(atom
->cmd
[3]);
418 OUT_BATCH(atom
->cmd
[4]);
422 static int check_never(GLcontext
*ctx
, struct radeon_state_atom
*atom
)
427 static int check_always(GLcontext
*ctx
, struct radeon_state_atom
*atom
)
429 return atom
->cmd_size
;
432 static int check_variable(GLcontext
*ctx
, struct radeon_state_atom
*atom
)
434 r300ContextPtr r300
= R300_CONTEXT(ctx
);
436 if (atom
->cmd
[0] == CP_PACKET2
) {
439 cnt
= packet0_count(r300
, atom
->cmd
);
440 return cnt
? cnt
+ 1 : 0;
443 int check_r500fp(GLcontext
*ctx
, struct radeon_state_atom
*atom
)
446 r300ContextPtr r300
= R300_CONTEXT(ctx
);
448 cnt
= r500fp_count(atom
->cmd
);
449 if (r300
->radeon
.radeonScreen
->kernel_mm
)
452 return cnt
? (cnt
* 6) + extra
: 0;
455 int check_r500fp_const(GLcontext
*ctx
, struct radeon_state_atom
*atom
)
458 r300ContextPtr r300
= R300_CONTEXT(ctx
);
460 cnt
= r500fp_count(atom
->cmd
);
461 if (r300
->radeon
.radeonScreen
->kernel_mm
)
464 cnt
= r500fp_count(atom
->cmd
);
465 return cnt
? (cnt
* 4) + extra
: 0;
468 #define ALLOC_STATE( ATOM, CHK, SZ, IDX ) \
470 r300->hw.ATOM.cmd_size = (SZ); \
471 r300->hw.ATOM.cmd = (uint32_t*)CALLOC((SZ) * sizeof(uint32_t)); \
472 r300->hw.ATOM.name = #ATOM; \
473 r300->hw.ATOM.idx = (IDX); \
474 r300->hw.ATOM.check = check_##CHK; \
475 r300->hw.ATOM.dirty = GL_FALSE; \
476 r300->radeon.hw.max_state_size += (SZ); \
477 insert_at_tail(&r300->radeon.hw.atomlist, &r300->hw.ATOM); \
480 * Allocate memory for the command buffer and initialize the state atom
481 * list. Note that the initial hardware state is set by r300InitState().
483 void r300InitCmdBuf(r300ContextPtr r300
)
489 has_tcl
= r300
->options
.hw_tcl_enabled
;
491 if (r300
->radeon
.radeonScreen
->chip_family
>= CHIP_FAMILY_RV515
)
494 r300
->radeon
.hw
.max_state_size
= 2 + 2; /* reserve extra space for WAIT_IDLE and tex cache flush */
496 mtu
= r300
->radeon
.glCtx
->Const
.MaxTextureUnits
;
497 if (RADEON_DEBUG
& RADEON_TEXTURE
) {
498 fprintf(stderr
, "Using %d maximum texture units..\n", mtu
);
501 /* Setup the atom linked list */
502 make_empty_list(&r300
->radeon
.hw
.atomlist
);
503 r300
->radeon
.hw
.atomlist
.name
= "atom-list";
505 /* Initialize state atoms */
506 ALLOC_STATE(vpt
, always
, R300_VPT_CMDSIZE
, 0);
507 r300
->hw
.vpt
.cmd
[R300_VPT_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_SE_VPORT_XSCALE
, 6);
508 ALLOC_STATE(vap_cntl
, always
, R300_VAP_CNTL_SIZE
, 0);
509 r300
->hw
.vap_cntl
.cmd
[R300_VAP_CNTL_FLUSH
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_VAP_PVS_STATE_FLUSH_REG
, 1);
510 r300
->hw
.vap_cntl
.cmd
[R300_VAP_CNTL_FLUSH_1
] = 0;
511 r300
->hw
.vap_cntl
.cmd
[R300_VAP_CNTL_CMD
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_VAP_CNTL
, 1);
512 if (is_r500
&& !r300
->radeon
.radeonScreen
->kernel_mm
) {
513 ALLOC_STATE(vap_index_offset
, always
, 2, 0);
514 r300
->hw
.vap_index_offset
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R500_VAP_INDEX_OFFSET
, 1);
515 r300
->hw
.vap_index_offset
.cmd
[1] = 0;
517 ALLOC_STATE(vte
, always
, 3, 0);
518 r300
->hw
.vte
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_SE_VTE_CNTL
, 2);
519 ALLOC_STATE(vap_vf_max_vtx_indx
, always
, 3, 0);
520 r300
->hw
.vap_vf_max_vtx_indx
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_VAP_VF_MAX_VTX_INDX
, 2);
521 ALLOC_STATE(vap_cntl_status
, always
, 2, 0);
522 r300
->hw
.vap_cntl_status
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_VAP_CNTL_STATUS
, 1);
523 ALLOC_STATE(vir
[0], variable
, R300_VIR_CMDSIZE
, 0);
524 r300
->hw
.vir
[0].cmd
[R300_VIR_CMD_0
] =
525 cmdpacket0(r300
->radeon
.radeonScreen
, R300_VAP_PROG_STREAM_CNTL_0
, 1);
526 ALLOC_STATE(vir
[1], variable
, R300_VIR_CMDSIZE
, 1);
527 r300
->hw
.vir
[1].cmd
[R300_VIR_CMD_0
] =
528 cmdpacket0(r300
->radeon
.radeonScreen
, R300_VAP_PROG_STREAM_CNTL_EXT_0
, 1);
529 ALLOC_STATE(vic
, always
, R300_VIC_CMDSIZE
, 0);
530 r300
->hw
.vic
.cmd
[R300_VIC_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_VAP_VTX_STATE_CNTL
, 2);
531 ALLOC_STATE(vap_psc_sgn_norm_cntl
, always
, 2, 0);
532 r300
->hw
.vap_psc_sgn_norm_cntl
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_VAP_PSC_SGN_NORM_CNTL
, SGN_NORM_ZERO_CLAMP_MINUS_ONE
);
535 ALLOC_STATE(vap_clip_cntl
, always
, 2, 0);
536 r300
->hw
.vap_clip_cntl
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_VAP_CLIP_CNTL
, 1);
537 ALLOC_STATE(vap_clip
, always
, 5, 0);
538 r300
->hw
.vap_clip
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_VAP_GB_VERT_CLIP_ADJ
, 4);
539 ALLOC_STATE(vap_pvs_vtx_timeout_reg
, always
, 2, 0);
540 r300
->hw
.vap_pvs_vtx_timeout_reg
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, VAP_PVS_VTX_TIMEOUT_REG
, 1);
543 ALLOC_STATE(vof
, always
, R300_VOF_CMDSIZE
, 0);
544 r300
->hw
.vof
.cmd
[R300_VOF_CMD_0
] =
545 cmdpacket0(r300
->radeon
.radeonScreen
, R300_VAP_OUTPUT_VTX_FMT_0
, 2);
548 ALLOC_STATE(pvs
, always
, R300_PVS_CMDSIZE
, 0);
549 r300
->hw
.pvs
.cmd
[R300_PVS_CMD_0
] =
550 cmdpacket0(r300
->radeon
.radeonScreen
, R300_VAP_PVS_CODE_CNTL_0
, 3);
553 ALLOC_STATE(gb_enable
, always
, 2, 0);
554 r300
->hw
.gb_enable
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_GB_ENABLE
, 1);
555 if (!r300
->radeon
.radeonScreen
->driScreen
->dri2
.enabled
) {
556 ALLOC_STATE(gb_misc
, always
, R300_GB_MISC_CMDSIZE
, 0);
558 ALLOC_STATE(gb_misc
, never
, R300_GB_MISC_CMDSIZE
, 0);
560 r300
->hw
.gb_misc
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_GB_MSPOS0
, 3);
561 ALLOC_STATE(gb_misc2
, always
, R300_GB_MISC2_CMDSIZE
, 0);
562 r300
->hw
.gb_misc2
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, 0x401C, 2);
563 ALLOC_STATE(txe
, always
, R300_TXE_CMDSIZE
, 0);
564 r300
->hw
.txe
.cmd
[R300_TXE_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_TX_ENABLE
, 1);
565 ALLOC_STATE(ga_point_s0
, always
, 5, 0);
566 r300
->hw
.ga_point_s0
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_GA_POINT_S0
, 4);
567 ALLOC_STATE(ga_triangle_stipple
, always
, 2, 0);
568 r300
->hw
.ga_triangle_stipple
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_GA_TRIANGLE_STIPPLE
, 1);
569 ALLOC_STATE(ps
, always
, R300_PS_CMDSIZE
, 0);
570 r300
->hw
.ps
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_GA_POINT_SIZE
, 1);
571 ALLOC_STATE(ga_point_minmax
, always
, 4, 0);
572 r300
->hw
.ga_point_minmax
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_GA_POINT_MINMAX
, 3);
573 ALLOC_STATE(lcntl
, always
, 2, 0);
574 r300
->hw
.lcntl
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_GA_LINE_CNTL
, 1);
575 ALLOC_STATE(ga_line_stipple
, always
, 4, 0);
576 r300
->hw
.ga_line_stipple
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_GA_LINE_STIPPLE_VALUE
, 3);
577 if (!r300
->radeon
.radeonScreen
->driScreen
->dri2
.enabled
) {
578 ALLOC_STATE(shade
, always
, 2, 0);
580 ALLOC_STATE(shade
, never
, 2, 0);
582 r300
->hw
.shade
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_GA_ENHANCE
, 1);
583 ALLOC_STATE(shade2
, always
, 4, 0);
584 r300
->hw
.shade2
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, 0x4278, 3);
585 ALLOC_STATE(polygon_mode
, always
, 4, 0);
586 r300
->hw
.polygon_mode
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_GA_POLY_MODE
, 3);
587 ALLOC_STATE(fogp
, always
, 3, 0);
588 r300
->hw
.fogp
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_GA_FOG_SCALE
, 2);
589 ALLOC_STATE(zbias_cntl
, always
, 2, 0);
590 r300
->hw
.zbias_cntl
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_SU_TEX_WRAP
, 1);
591 ALLOC_STATE(zbs
, always
, R300_ZBS_CMDSIZE
, 0);
592 r300
->hw
.zbs
.cmd
[R300_ZBS_CMD_0
] =
593 cmdpacket0(r300
->radeon
.radeonScreen
, R300_SU_POLY_OFFSET_FRONT_SCALE
, 4);
594 ALLOC_STATE(occlusion_cntl
, always
, 2, 0);
595 r300
->hw
.occlusion_cntl
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_SU_POLY_OFFSET_ENABLE
, 1);
596 ALLOC_STATE(cul
, always
, R300_CUL_CMDSIZE
, 0);
597 r300
->hw
.cul
.cmd
[R300_CUL_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_SU_CULL_MODE
, 1);
598 ALLOC_STATE(su_depth_scale
, always
, 3, 0);
599 r300
->hw
.su_depth_scale
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_SU_DEPTH_SCALE
, 2);
600 ALLOC_STATE(rc
, always
, R300_RC_CMDSIZE
, 0);
601 r300
->hw
.rc
.cmd
[R300_RC_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_RS_COUNT
, 2);
603 ALLOC_STATE(ri
, variable
, R500_RI_CMDSIZE
, 0);
604 r300
->hw
.ri
.cmd
[R300_RI_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R500_RS_IP_0
, 16);
605 ALLOC_STATE(rr
, variable
, R300_RR_CMDSIZE
, 0);
606 r300
->hw
.rr
.cmd
[R300_RR_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R500_RS_INST_0
, 1);
608 ALLOC_STATE(ri
, variable
, R300_RI_CMDSIZE
, 0);
609 r300
->hw
.ri
.cmd
[R300_RI_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_RS_IP_0
, 8);
610 ALLOC_STATE(rr
, variable
, R300_RR_CMDSIZE
, 0);
611 r300
->hw
.rr
.cmd
[R300_RR_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_RS_INST_0
, 1);
613 ALLOC_STATE(sc_hyperz
, always
, 3, 0);
614 r300
->hw
.sc_hyperz
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_SC_HYPERZ
, 2);
615 ALLOC_STATE(sc_screendoor
, always
, 2, 0);
616 r300
->hw
.sc_screendoor
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_SC_SCREENDOOR
, 1);
617 ALLOC_STATE(us_out_fmt
, always
, 6, 0);
618 r300
->hw
.us_out_fmt
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_US_OUT_FMT
, 5);
621 ALLOC_STATE(fp
, always
, R500_FP_CMDSIZE
, 0);
622 r300
->hw
.fp
.cmd
[R500_FP_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R500_US_CONFIG
, 2);
623 r300
->hw
.fp
.cmd
[R500_FP_CNTL
] = R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO
;
624 r300
->hw
.fp
.cmd
[R500_FP_CMD_1
] = cmdpacket0(r300
->radeon
.radeonScreen
, R500_US_CODE_ADDR
, 3);
625 r300
->hw
.fp
.cmd
[R500_FP_CMD_2
] = cmdpacket0(r300
->radeon
.radeonScreen
, R500_US_FC_CTRL
, 1);
626 r300
->hw
.fp
.cmd
[R500_FP_FC_CNTL
] = 0; /* FIXME when we add flow control */
628 ALLOC_STATE(r500fp
, r500fp
, R500_FPI_CMDSIZE
, 0);
629 r300
->hw
.r500fp
.cmd
[R300_FPI_CMD_0
] =
630 cmdr500fp(r300
->radeon
.radeonScreen
, 0, 0, 0, 0);
631 if (r300
->radeon
.radeonScreen
->kernel_mm
)
632 r300
->hw
.r500fp
.emit
= emit_r500fp
;
634 ALLOC_STATE(r500fp_const
, r500fp_const
, R500_FPP_CMDSIZE
, 0);
635 r300
->hw
.r500fp_const
.cmd
[R300_FPI_CMD_0
] =
636 cmdr500fp(r300
->radeon
.radeonScreen
, 0, 0, 1, 0);
637 if (r300
->radeon
.radeonScreen
->kernel_mm
)
638 r300
->hw
.r500fp_const
.emit
= emit_r500fp
;
640 ALLOC_STATE(fp
, always
, R300_FP_CMDSIZE
, 0);
641 r300
->hw
.fp
.cmd
[R300_FP_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_US_CONFIG
, 3);
642 r300
->hw
.fp
.cmd
[R300_FP_CMD_1
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_US_CODE_ADDR_0
, 4);
644 ALLOC_STATE(fpt
, variable
, R300_FPT_CMDSIZE
, 0);
645 r300
->hw
.fpt
.cmd
[R300_FPT_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_US_TEX_INST_0
, 0);
647 ALLOC_STATE(fpi
[0], variable
, R300_FPI_CMDSIZE
, 0);
648 r300
->hw
.fpi
[0].cmd
[R300_FPI_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_US_ALU_RGB_INST_0
, 1);
649 ALLOC_STATE(fpi
[1], variable
, R300_FPI_CMDSIZE
, 1);
650 r300
->hw
.fpi
[1].cmd
[R300_FPI_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_US_ALU_RGB_ADDR_0
, 1);
651 ALLOC_STATE(fpi
[2], variable
, R300_FPI_CMDSIZE
, 2);
652 r300
->hw
.fpi
[2].cmd
[R300_FPI_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_US_ALU_ALPHA_INST_0
, 1);
653 ALLOC_STATE(fpi
[3], variable
, R300_FPI_CMDSIZE
, 3);
654 r300
->hw
.fpi
[3].cmd
[R300_FPI_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_US_ALU_ALPHA_ADDR_0
, 1);
655 ALLOC_STATE(fpp
, variable
, R300_FPP_CMDSIZE
, 0);
656 r300
->hw
.fpp
.cmd
[R300_FPP_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_PFS_PARAM_0_X
, 0);
658 ALLOC_STATE(fogs
, always
, R300_FOGS_CMDSIZE
, 0);
659 r300
->hw
.fogs
.cmd
[R300_FOGS_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_FG_FOG_BLEND
, 1);
660 ALLOC_STATE(fogc
, always
, R300_FOGC_CMDSIZE
, 0);
661 r300
->hw
.fogc
.cmd
[R300_FOGC_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_FG_FOG_COLOR_R
, 3);
662 ALLOC_STATE(at
, always
, R300_AT_CMDSIZE
, 0);
663 r300
->hw
.at
.cmd
[R300_AT_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_FG_ALPHA_FUNC
, 2);
664 ALLOC_STATE(fg_depth_src
, always
, 2, 0);
665 r300
->hw
.fg_depth_src
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_FG_DEPTH_SRC
, 1);
666 ALLOC_STATE(rb3d_cctl
, always
, 2, 0);
667 r300
->hw
.rb3d_cctl
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_RB3D_CCTL
, 1);
668 ALLOC_STATE(bld
, always
, R300_BLD_CMDSIZE
, 0);
669 r300
->hw
.bld
.cmd
[R300_BLD_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_RB3D_CBLEND
, 2);
670 ALLOC_STATE(cmk
, always
, R300_CMK_CMDSIZE
, 0);
671 r300
->hw
.cmk
.cmd
[R300_CMK_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, RB3D_COLOR_CHANNEL_MASK
, 1);
673 ALLOC_STATE(blend_color
, always
, 3, 0);
674 r300
->hw
.blend_color
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R500_RB3D_CONSTANT_COLOR_AR
, 2);
676 ALLOC_STATE(blend_color
, always
, 2, 0);
677 r300
->hw
.blend_color
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_RB3D_BLEND_COLOR
, 1);
679 ALLOC_STATE(rop
, always
, 2, 0);
680 r300
->hw
.rop
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_RB3D_ROPCNTL
, 1);
681 ALLOC_STATE(cb
, cb_offset
, R300_CB_CMDSIZE
, 0);
682 r300
->hw
.cb
.emit
= &emit_cb_offset
;
683 ALLOC_STATE(rb3d_dither_ctl
, always
, 10, 0);
684 r300
->hw
.rb3d_dither_ctl
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_RB3D_DITHER_CTL
, 9);
685 ALLOC_STATE(rb3d_aaresolve_ctl
, always
, 2, 0);
686 r300
->hw
.rb3d_aaresolve_ctl
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_RB3D_AARESOLVE_CTL
, 1);
687 if ((r300
->radeon
.radeonScreen
->chip_family
>= CHIP_FAMILY_RV515
) ||
688 ( !r300
->radeon
.radeonScreen
->kernel_mm
&& (
689 (r300
->radeon
.radeonScreen
->chip_family
== CHIP_FAMILY_RS400
) ||
690 (r300
->radeon
.radeonScreen
->chip_family
== CHIP_FAMILY_RV410
) ||
691 (r300
->radeon
.radeonScreen
->chip_family
== CHIP_FAMILY_R420
) ) ) ) {
692 ALLOC_STATE(rb3d_discard_src_pixel_lte_threshold
, always
, 3, 0);
694 ALLOC_STATE(rb3d_discard_src_pixel_lte_threshold
, never
, 3, 0);
696 r300
->hw
.rb3d_discard_src_pixel_lte_threshold
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R500_RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD
, 2);
697 ALLOC_STATE(zs
, always
, R300_ZS_CMDSIZE
, 0);
698 r300
->hw
.zs
.cmd
[R300_ZS_CMD_0
] =
699 cmdpacket0(r300
->radeon
.radeonScreen
, R300_ZB_CNTL
, 3);
701 ALLOC_STATE(zstencil_format
, always
, 5, 0);
702 r300
->hw
.zstencil_format
.cmd
[0] =
703 cmdpacket0(r300
->radeon
.radeonScreen
, R300_ZB_FORMAT
, 4);
704 r300
->hw
.zstencil_format
.emit
= emit_zstencil_format
;
706 ALLOC_STATE(zb
, zb_offset
, R300_ZB_CMDSIZE
, 0);
707 r300
->hw
.zb
.emit
= emit_zb_offset
;
708 ALLOC_STATE(zb_depthclearvalue
, always
, 2, 0);
709 r300
->hw
.zb_depthclearvalue
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_ZB_DEPTHCLEARVALUE
, 1);
710 ALLOC_STATE(zb_zmask
, always
, 3, 0);
711 r300
->hw
.zb_zmask
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_ZB_ZMASK_OFFSET
, 2);
712 ALLOC_STATE(zb_hiz_offset
, always
, 2, 0);
713 r300
->hw
.zb_hiz_offset
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_ZB_HIZ_OFFSET
, 1);
714 ALLOC_STATE(zb_hiz_pitch
, always
, 2, 0);
715 r300
->hw
.zb_hiz_pitch
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_ZB_HIZ_PITCH
, 1);
717 /* VPU only on TCL */
720 if (r300
->radeon
.radeonScreen
->kernel_mm
) {
721 ALLOC_STATE(vap_flush
, always
, 10, 0);
722 /* flush processing vertices */
723 r300
->hw
.vap_flush
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_SC_SCREENDOOR
, 1);
724 r300
->hw
.vap_flush
.cmd
[1] = 0;
725 r300
->hw
.vap_flush
.cmd
[2] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_RB3D_DSTCACHE_CTLSTAT
, 1);
726 r300
->hw
.vap_flush
.cmd
[3] = R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D
;
727 r300
->hw
.vap_flush
.cmd
[4] = cmdpacket0(r300
->radeon
.radeonScreen
, RADEON_WAIT_UNTIL
, 1);
728 r300
->hw
.vap_flush
.cmd
[5] = RADEON_WAIT_3D_IDLECLEAN
;
729 r300
->hw
.vap_flush
.cmd
[6] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_SC_SCREENDOOR
, 1);
730 r300
->hw
.vap_flush
.cmd
[7] = 0xffffff;
731 r300
->hw
.vap_flush
.cmd
[8] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_VAP_PVS_STATE_FLUSH_REG
, 1);
732 r300
->hw
.vap_flush
.cmd
[9] = 0;
734 ALLOC_STATE(vap_flush
, never
, 10, 0);
738 ALLOC_STATE(vpi
, vpu
, R300_VPI_CMDSIZE
, 0);
739 r300
->hw
.vpi
.cmd
[0] =
740 cmdvpu(r300
->radeon
.radeonScreen
, R300_PVS_CODE_START
, 0);
741 if (r300
->radeon
.radeonScreen
->kernel_mm
)
742 r300
->hw
.vpi
.emit
= emit_vpu
;
745 ALLOC_STATE(vpp
, vpu
, R300_VPP_CMDSIZE
, 0);
746 r300
->hw
.vpp
.cmd
[0] =
747 cmdvpu(r300
->radeon
.radeonScreen
, R500_PVS_CONST_START
, 0);
748 if (r300
->radeon
.radeonScreen
->kernel_mm
)
749 r300
->hw
.vpp
.emit
= emit_vpu
;
751 ALLOC_STATE(vps
, vpu
, R300_VPS_CMDSIZE
, 0);
752 r300
->hw
.vps
.cmd
[0] =
753 cmdvpu(r300
->radeon
.radeonScreen
, R500_POINT_VPORT_SCALE_OFFSET
, 1);
754 if (r300
->radeon
.radeonScreen
->kernel_mm
)
755 r300
->hw
.vps
.emit
= emit_vpu
;
757 for (i
= 0; i
< 6; i
++) {
758 ALLOC_STATE(vpucp
[i
], vpu
, R300_VPUCP_CMDSIZE
, 0);
759 r300
->hw
.vpucp
[i
].cmd
[0] =
760 cmdvpu(r300
->radeon
.radeonScreen
,
761 R500_PVS_UCP_START
+ i
, 1);
762 if (r300
->radeon
.radeonScreen
->kernel_mm
)
763 r300
->hw
.vpucp
[i
].emit
= emit_vpu
;
766 ALLOC_STATE(vpp
, vpu
, R300_VPP_CMDSIZE
, 0);
767 r300
->hw
.vpp
.cmd
[0] =
768 cmdvpu(r300
->radeon
.radeonScreen
, R300_PVS_CONST_START
, 0);
769 if (r300
->radeon
.radeonScreen
->kernel_mm
)
770 r300
->hw
.vpp
.emit
= emit_vpu
;
772 ALLOC_STATE(vps
, vpu
, R300_VPS_CMDSIZE
, 0);
773 r300
->hw
.vps
.cmd
[0] =
774 cmdvpu(r300
->radeon
.radeonScreen
, R300_POINT_VPORT_SCALE_OFFSET
, 1);
775 if (r300
->radeon
.radeonScreen
->kernel_mm
)
776 r300
->hw
.vps
.emit
= emit_vpu
;
778 for (i
= 0; i
< 6; i
++) {
779 ALLOC_STATE(vpucp
[i
], vpu
, R300_VPUCP_CMDSIZE
, 0);
780 r300
->hw
.vpucp
[i
].cmd
[0] =
781 cmdvpu(r300
->radeon
.radeonScreen
,
782 R300_PVS_UCP_START
+ i
, 1);
783 if (r300
->radeon
.radeonScreen
->kernel_mm
)
784 r300
->hw
.vpucp
[i
].emit
= emit_vpu
;
790 ALLOC_STATE(tex
.filter
, variable
, mtu
+ 1, 0);
791 r300
->hw
.tex
.filter
.cmd
[R300_TEX_CMD_0
] =
792 cmdpacket0(r300
->radeon
.radeonScreen
, R300_TX_FILTER0_0
, 0);
794 ALLOC_STATE(tex
.filter_1
, variable
, mtu
+ 1, 0);
795 r300
->hw
.tex
.filter_1
.cmd
[R300_TEX_CMD_0
] =
796 cmdpacket0(r300
->radeon
.radeonScreen
, R300_TX_FILTER1_0
, 0);
798 ALLOC_STATE(tex
.size
, variable
, mtu
+ 1, 0);
799 r300
->hw
.tex
.size
.cmd
[R300_TEX_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_TX_SIZE_0
, 0);
801 ALLOC_STATE(tex
.format
, variable
, mtu
+ 1, 0);
802 r300
->hw
.tex
.format
.cmd
[R300_TEX_CMD_0
] =
803 cmdpacket0(r300
->radeon
.radeonScreen
, R300_TX_FORMAT_0
, 0);
805 ALLOC_STATE(tex
.pitch
, variable
, mtu
+ 1, 0);
806 r300
->hw
.tex
.pitch
.cmd
[R300_TEX_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_TX_FORMAT2_0
, 0);
808 ALLOC_STATE(tex
.offset
, tex_offsets
, 1, 0);
809 r300
->hw
.tex
.offset
.cmd
[R300_TEX_CMD_0
] =
810 cmdpacket0(r300
->radeon
.radeonScreen
, R300_TX_OFFSET_0
, 0);
811 r300
->hw
.tex
.offset
.emit
= &emit_tex_offsets
;
813 ALLOC_STATE(tex
.chroma_key
, variable
, mtu
+ 1, 0);
814 r300
->hw
.tex
.chroma_key
.cmd
[R300_TEX_CMD_0
] =
815 cmdpacket0(r300
->radeon
.radeonScreen
, R300_TX_CHROMA_KEY_0
, 0);
817 ALLOC_STATE(tex
.border_color
, variable
, mtu
+ 1, 0);
818 r300
->hw
.tex
.border_color
.cmd
[R300_TEX_CMD_0
] =
819 cmdpacket0(r300
->radeon
.radeonScreen
, R300_TX_BORDER_COLOR_0
, 0);
821 radeon_init_query_stateobj(&r300
->radeon
, R300_QUERYOBJ_CMDSIZE
);
822 if (r300
->radeon
.radeonScreen
->chip_family
== CHIP_FAMILY_RV530
) {
823 r300
->radeon
.query
.queryobj
.cmd
[R300_QUERYOBJ_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, RV530_FG_ZBREG_DEST
, 1);
824 r300
->radeon
.query
.queryobj
.cmd
[R300_QUERYOBJ_DATA_0
] = RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL
;
826 r300
->radeon
.query
.queryobj
.cmd
[R300_QUERYOBJ_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_SU_REG_DEST
, 1);
827 r300
->radeon
.query
.queryobj
.cmd
[R300_QUERYOBJ_DATA_0
] = R300_RASTER_PIPE_SELECT_ALL
;
829 r300
->radeon
.query
.queryobj
.cmd
[R300_QUERYOBJ_CMD_1
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_ZB_ZPASS_DATA
, 1);
830 r300
->radeon
.query
.queryobj
.cmd
[R300_QUERYOBJ_DATA_1
] = 0;
832 r300
->radeon
.hw
.is_dirty
= GL_TRUE
;
833 r300
->radeon
.hw
.all_dirty
= GL_TRUE
;
835 rcommonInitCmdBuf(&r300
->radeon
);