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[mesa.git] / src / mesa / drivers / dri / r300 / r300_cmdbuf.c
1 /*
2 Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
3
4 The Weather Channel (TM) funded Tungsten Graphics to develop the
5 initial release of the Radeon 8500 driver under the XFree86 license.
6 This notice must be preserved.
7
8 Permission is hereby granted, free of charge, to any person obtaining
9 a copy of this software and associated documentation files (the
10 "Software"), to deal in the Software without restriction, including
11 without limitation the rights to use, copy, modify, merge, publish,
12 distribute, sublicense, and/or sell copies of the Software, and to
13 permit persons to whom the Software is furnished to do so, subject to
14 the following conditions:
15
16 The above copyright notice and this permission notice (including the
17 next paragraph) shall be included in all copies or substantial
18 portions of the Software.
19
20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27
28 **************************************************************************/
29
30 /**
31 * \file
32 *
33 * \author Nicolai Haehnle <prefect_@gmx.net>
34 */
35
36 #include "main/glheader.h"
37 #include "main/state.h"
38 #include "main/imports.h"
39 #include "main/macros.h"
40 #include "main/context.h"
41 #include "main/simple_list.h"
42 #include "swrast/swrast.h"
43
44 #include "drm.h"
45 #include "radeon_drm.h"
46
47 #include "r300_context.h"
48 #include "r300_ioctl.h"
49 #include "radeon_reg.h"
50 #include "r300_reg.h"
51 #include "r300_cmdbuf.h"
52 #include "r300_emit.h"
53 #include "radeon_bocs_wrapper.h"
54 #include "radeon_mipmap_tree.h"
55 #include "r300_state.h"
56 #include "radeon_reg.h"
57
58 /** # of dwords reserved for additional instructions that may need to be written
59 * during flushing.
60 */
61 #define SPACE_FOR_FLUSHING 4
62
63 static unsigned packet0_count(r300ContextPtr r300, uint32_t *pkt)
64 {
65 if (r300->radeon.radeonScreen->kernel_mm) {
66 return ((((*pkt) >> 16) & 0x3FFF) + 1);
67 } else {
68 drm_r300_cmd_header_t *t = (drm_r300_cmd_header_t*)pkt;
69 return t->packet0.count;
70 }
71 }
72
73 #define vpu_count(ptr) (((drm_r300_cmd_header_t*)(ptr))->vpu.count)
74 #define r500fp_count(ptr) (((drm_r300_cmd_header_t*)(ptr))->r500fp.count)
75
76 void emit_vpu(GLcontext *ctx, struct radeon_state_atom * atom)
77 {
78 r300ContextPtr r300 = R300_CONTEXT(ctx);
79 BATCH_LOCALS(&r300->radeon);
80 drm_r300_cmd_header_t cmd;
81 uint32_t addr, ndw, i;
82
83 if (!r300->radeon.radeonScreen->kernel_mm) {
84 uint32_t dwords;
85 dwords = (*atom->check) (ctx, atom);
86 BEGIN_BATCH_NO_AUTOSTATE(dwords);
87 OUT_BATCH_TABLE(atom->cmd, dwords);
88 END_BATCH();
89 return;
90 }
91
92 cmd.u = atom->cmd[0];
93 addr = (cmd.vpu.adrhi << 8) | cmd.vpu.adrlo;
94 ndw = cmd.vpu.count * 4;
95 if (ndw) {
96
97 if (r300->vap_flush_needed) {
98 BEGIN_BATCH_NO_AUTOSTATE(15 + ndw);
99
100 /* flush processing vertices */
101 OUT_BATCH_REGVAL(R300_SC_SCREENDOOR, 0);
102 OUT_BATCH_REGVAL(R300_RB3D_DSTCACHE_CTLSTAT, R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D);
103 OUT_BATCH_REGVAL(RADEON_WAIT_UNTIL, RADEON_WAIT_3D_IDLECLEAN);
104 OUT_BATCH_REGVAL(R300_SC_SCREENDOOR, 0xffffff);
105 OUT_BATCH_REGVAL(R300_VAP_PVS_STATE_FLUSH_REG, 0);
106 r300->vap_flush_needed = GL_FALSE;
107 } else {
108 BEGIN_BATCH_NO_AUTOSTATE(5 + ndw);
109 }
110 OUT_BATCH_REGVAL(R300_VAP_PVS_VECTOR_INDX_REG, addr);
111 OUT_BATCH(CP_PACKET0(R300_VAP_PVS_UPLOAD_DATA, ndw-1) | RADEON_ONE_REG_WR);
112 for (i = 0; i < ndw; i++) {
113 OUT_BATCH(atom->cmd[i+1]);
114 }
115 OUT_BATCH_REGVAL(R300_VAP_PVS_STATE_FLUSH_REG, 0);
116 END_BATCH();
117 }
118 }
119
120 void emit_r500fp(GLcontext *ctx, struct radeon_state_atom * atom)
121 {
122 r300ContextPtr r300 = R300_CONTEXT(ctx);
123 BATCH_LOCALS(&r300->radeon);
124 drm_r300_cmd_header_t cmd;
125 uint32_t addr, ndw, i, sz;
126 int type, clamp, stride;
127
128 if (!r300->radeon.radeonScreen->kernel_mm) {
129 uint32_t dwords;
130 dwords = (*atom->check) (ctx, atom);
131 BEGIN_BATCH_NO_AUTOSTATE(dwords);
132 OUT_BATCH_TABLE(atom->cmd, dwords);
133 END_BATCH();
134 return;
135 }
136
137 cmd.u = atom->cmd[0];
138 sz = cmd.r500fp.count;
139 addr = ((cmd.r500fp.adrhi_flags & 1) << 8) | cmd.r500fp.adrlo;
140 type = !!(cmd.r500fp.adrhi_flags & R500FP_CONSTANT_TYPE);
141 clamp = !!(cmd.r500fp.adrhi_flags & R500FP_CONSTANT_CLAMP);
142
143 addr |= (type << 16);
144 addr |= (clamp << 17);
145
146 stride = type ? 4 : 6;
147
148 ndw = sz * stride;
149 if (ndw) {
150
151 BEGIN_BATCH_NO_AUTOSTATE(3 + ndw);
152 OUT_BATCH(CP_PACKET0(R500_GA_US_VECTOR_INDEX, 0));
153 OUT_BATCH(addr);
154 OUT_BATCH(CP_PACKET0(R500_GA_US_VECTOR_DATA, ndw-1) | RADEON_ONE_REG_WR);
155 for (i = 0; i < ndw; i++) {
156 OUT_BATCH(atom->cmd[i+1]);
157 }
158 END_BATCH();
159 }
160 }
161
162 static void emit_tex_offsets(GLcontext *ctx, struct radeon_state_atom * atom)
163 {
164 r300ContextPtr r300 = R300_CONTEXT(ctx);
165 BATCH_LOCALS(&r300->radeon);
166 int numtmus = packet0_count(r300, r300->hw.tex.offset.cmd);
167 int notexture = 0;
168
169 if (numtmus) {
170 int i;
171
172 for(i = 0; i < numtmus; ++i) {
173 radeonTexObj *t = r300->hw.textures[i];
174
175 if (!t)
176 notexture = 1;
177 }
178
179 if (r300->radeon.radeonScreen->kernel_mm && notexture) {
180 return;
181 }
182 BEGIN_BATCH_NO_AUTOSTATE(4 * numtmus);
183 for(i = 0; i < numtmus; ++i) {
184 radeonTexObj *t = r300->hw.textures[i];
185 OUT_BATCH_REGSEQ(R300_TX_OFFSET_0 + (i * 4), 1);
186 if (t && !t->image_override) {
187 OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, 0,
188 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
189 } else if (!t) {
190 OUT_BATCH(r300->radeon.radeonScreen->texOffset[0]);
191 } else { /* override cases */
192 if (t->bo) {
193 OUT_BATCH_RELOC(t->tile_bits, t->bo, 0,
194 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
195 } else if (!r300->radeon.radeonScreen->kernel_mm) {
196 OUT_BATCH(t->override_offset);
197 }
198 else
199 OUT_BATCH(r300->radeon.radeonScreen->texOffset[0]);
200 }
201 }
202 END_BATCH();
203 }
204 }
205
206 static void emit_cb_offset(GLcontext *ctx, struct radeon_state_atom * atom)
207 {
208 r300ContextPtr r300 = R300_CONTEXT(ctx);
209 BATCH_LOCALS(&r300->radeon);
210 struct radeon_renderbuffer *rrb;
211 uint32_t cbpitch;
212 uint32_t offset = r300->radeon.state.color.draw_offset;
213 uint32_t dw = 6;
214 int i;
215
216 rrb = radeon_get_colorbuffer(&r300->radeon);
217 if (!rrb || !rrb->bo) {
218 fprintf(stderr, "no rrb\n");
219 return;
220 }
221
222 cbpitch = (rrb->pitch / rrb->cpp);
223 if (rrb->cpp == 4)
224 cbpitch |= R300_COLOR_FORMAT_ARGB8888;
225 else
226 cbpitch |= R300_COLOR_FORMAT_RGB565;
227
228 if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE)
229 cbpitch |= R300_COLOR_TILE_ENABLE;
230
231 if (r300->radeon.radeonScreen->kernel_mm)
232 dw += 2;
233 BEGIN_BATCH_NO_AUTOSTATE(dw);
234 OUT_BATCH_REGSEQ(R300_RB3D_COLOROFFSET0, 1);
235 OUT_BATCH_RELOC(offset, rrb->bo, offset, 0, RADEON_GEM_DOMAIN_VRAM, 0);
236 OUT_BATCH_REGSEQ(R300_RB3D_COLORPITCH0, 1);
237 if (!r300->radeon.radeonScreen->kernel_mm)
238 OUT_BATCH(cbpitch);
239 else
240 OUT_BATCH_RELOC(cbpitch, rrb->bo, cbpitch, 0, RADEON_GEM_DOMAIN_VRAM, 0);
241 END_BATCH();
242 if (r300->radeon.radeonScreen->driScreen->dri2.enabled) {
243 if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) {
244 BEGIN_BATCH_NO_AUTOSTATE(3);
245 OUT_BATCH_REGSEQ(R300_SC_SCISSORS_TL, 2);
246 OUT_BATCH(0);
247 OUT_BATCH(((rrb->width - 1) << R300_SCISSORS_X_SHIFT) |
248 ((rrb->height - 1) << R300_SCISSORS_Y_SHIFT));
249 END_BATCH();
250 BEGIN_BATCH_NO_AUTOSTATE(16);
251 for (i = 0; i < 4; i++) {
252 OUT_BATCH_REGSEQ(R300_SC_CLIPRECT_TL_0 + (i * 8), 2);
253 OUT_BATCH((0 << R300_CLIPRECT_X_SHIFT) | (0 << R300_CLIPRECT_Y_SHIFT));
254 OUT_BATCH(((rrb->width - 1) << R300_CLIPRECT_X_SHIFT) | ((rrb->height - 1) << R300_CLIPRECT_Y_SHIFT));
255 }
256 OUT_BATCH_REGSEQ(R300_SC_CLIP_RULE, 1);
257 OUT_BATCH(0xAAAA);
258 OUT_BATCH_REGSEQ(R300_SC_SCREENDOOR, 1);
259 OUT_BATCH(0xffffff);
260 END_BATCH();
261 } else {
262 BEGIN_BATCH_NO_AUTOSTATE(3);
263 OUT_BATCH_REGSEQ(R300_SC_SCISSORS_TL, 2);
264 OUT_BATCH((R300_SCISSORS_OFFSET << R300_SCISSORS_X_SHIFT) |
265 (R300_SCISSORS_OFFSET << R300_SCISSORS_Y_SHIFT));
266 OUT_BATCH(((rrb->width + R300_SCISSORS_OFFSET - 1) << R300_SCISSORS_X_SHIFT) |
267 ((rrb->height + R300_SCISSORS_OFFSET - 1) << R300_SCISSORS_Y_SHIFT));
268 END_BATCH();
269 BEGIN_BATCH_NO_AUTOSTATE(16);
270 for (i = 0; i < 4; i++) {
271 OUT_BATCH_REGSEQ(R300_SC_CLIPRECT_TL_0 + (i * 8), 2);
272 OUT_BATCH((R300_SCISSORS_OFFSET << R300_CLIPRECT_X_SHIFT) | (R300_SCISSORS_OFFSET << R300_CLIPRECT_Y_SHIFT));
273 OUT_BATCH(((R300_SCISSORS_OFFSET + rrb->width - 1) << R300_CLIPRECT_X_SHIFT) |
274 ((R300_SCISSORS_OFFSET + rrb->height - 1) << R300_CLIPRECT_Y_SHIFT));
275 }
276 OUT_BATCH_REGSEQ(R300_SC_CLIP_RULE, 1);
277 OUT_BATCH(0xAAAA);
278 OUT_BATCH_REGSEQ(R300_SC_SCREENDOOR, 1);
279 OUT_BATCH(0xffffff);
280 END_BATCH();
281 }
282 }
283 }
284
285 static void emit_zb_offset(GLcontext *ctx, struct radeon_state_atom * atom)
286 {
287 r300ContextPtr r300 = R300_CONTEXT(ctx);
288 BATCH_LOCALS(&r300->radeon);
289 struct radeon_renderbuffer *rrb;
290 uint32_t zbpitch;
291
292 rrb = radeon_get_depthbuffer(&r300->radeon);
293 if (!rrb)
294 return;
295
296 zbpitch = (rrb->pitch / rrb->cpp);
297 if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE) {
298 zbpitch |= R300_DEPTHMACROTILE_ENABLE;
299 }
300 if (rrb->bo->flags & RADEON_BO_FLAGS_MICRO_TILE){
301 zbpitch |= R300_DEPTHMICROTILE_TILED;
302 }
303
304 BEGIN_BATCH_NO_AUTOSTATE(6);
305 OUT_BATCH_REGSEQ(R300_ZB_DEPTHOFFSET, 1);
306 OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
307 OUT_BATCH_REGVAL(R300_ZB_DEPTHPITCH, zbpitch);
308 END_BATCH();
309 }
310
311 static void emit_gb_misc(GLcontext *ctx, struct radeon_state_atom * atom)
312 {
313 r300ContextPtr r300 = R300_CONTEXT(ctx);
314 BATCH_LOCALS(&r300->radeon);
315
316 if (!r300->radeon.radeonScreen->driScreen->dri2.enabled) {
317 BEGIN_BATCH_NO_AUTOSTATE(4);
318 OUT_BATCH(atom->cmd[0]);
319 OUT_BATCH(atom->cmd[1]);
320 OUT_BATCH(atom->cmd[2]);
321 OUT_BATCH(atom->cmd[3]);
322 END_BATCH();
323 }
324 }
325
326 static void emit_shade_misc(GLcontext *ctx, struct radeon_state_atom * atom)
327 {
328 r300ContextPtr r300 = R300_CONTEXT(ctx);
329 BATCH_LOCALS(&r300->radeon);
330
331 if (!r300->radeon.radeonScreen->driScreen->dri2.enabled) {
332 BEGIN_BATCH_NO_AUTOSTATE(2);
333 OUT_BATCH(atom->cmd[0]);
334 OUT_BATCH(atom->cmd[1]);
335 END_BATCH();
336 }
337 }
338
339 static void emit_zstencil_format(GLcontext *ctx, struct radeon_state_atom * atom)
340 {
341 r300ContextPtr r300 = R300_CONTEXT(ctx);
342 BATCH_LOCALS(&r300->radeon);
343 struct radeon_renderbuffer *rrb;
344 uint32_t format = 0;
345
346 rrb = radeon_get_depthbuffer(&r300->radeon);
347 if (!rrb)
348 format = 0;
349 else {
350 if (rrb->cpp == 2)
351 format = R300_DEPTHFORMAT_16BIT_INT_Z;
352 else if (rrb->cpp == 4)
353 format = R300_DEPTHFORMAT_24BIT_INT_Z_8BIT_STENCIL;
354 }
355
356 OUT_BATCH(atom->cmd[0]);
357 atom->cmd[1] &= ~0xf;
358 atom->cmd[1] |= format;
359 OUT_BATCH(atom->cmd[1]);
360 OUT_BATCH(atom->cmd[2]);
361 OUT_BATCH(atom->cmd[3]);
362 OUT_BATCH(atom->cmd[4]);
363 }
364
365 static int check_always(GLcontext *ctx, struct radeon_state_atom *atom)
366 {
367 return atom->cmd_size;
368 }
369
370 static int check_variable(GLcontext *ctx, struct radeon_state_atom *atom)
371 {
372 r300ContextPtr r300 = R300_CONTEXT(ctx);
373 int cnt;
374 if (atom->cmd[0] == CP_PACKET2) {
375 return 0;
376 }
377 cnt = packet0_count(r300, atom->cmd);
378 return cnt ? cnt + 1 : 0;
379 }
380
381 int check_vpu(GLcontext *ctx, struct radeon_state_atom *atom)
382 {
383 int cnt;
384
385 cnt = vpu_count(atom->cmd);
386 return cnt ? (cnt * 4) + 1 : 0;
387 }
388
389 int check_r500fp(GLcontext *ctx, struct radeon_state_atom *atom)
390 {
391 int cnt;
392
393 cnt = r500fp_count(atom->cmd);
394 return cnt ? (cnt * 6) + 1 : 0;
395 }
396
397 int check_r500fp_const(GLcontext *ctx, struct radeon_state_atom *atom)
398 {
399 int cnt;
400
401 cnt = r500fp_count(atom->cmd);
402 return cnt ? (cnt * 4) + 1 : 0;
403 }
404
405 #define ALLOC_STATE( ATOM, CHK, SZ, IDX ) \
406 do { \
407 r300->hw.ATOM.cmd_size = (SZ); \
408 r300->hw.ATOM.cmd = (uint32_t*)CALLOC((SZ) * sizeof(uint32_t)); \
409 r300->hw.ATOM.name = #ATOM; \
410 r300->hw.ATOM.idx = (IDX); \
411 r300->hw.ATOM.check = check_##CHK; \
412 r300->hw.ATOM.dirty = GL_FALSE; \
413 r300->radeon.hw.max_state_size += (SZ); \
414 insert_at_tail(&r300->radeon.hw.atomlist, &r300->hw.ATOM); \
415 } while (0)
416 /**
417 * Allocate memory for the command buffer and initialize the state atom
418 * list. Note that the initial hardware state is set by r300InitState().
419 */
420 void r300InitCmdBuf(r300ContextPtr r300)
421 {
422 int mtu;
423 int has_tcl;
424 int is_r500 = 0;
425 int i;
426
427 has_tcl = r300->options.hw_tcl_enabled;
428
429 if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515)
430 is_r500 = 1;
431
432 r300->radeon.hw.max_state_size = 2 + 2; /* reserve extra space for WAIT_IDLE and tex cache flush */
433
434 mtu = r300->radeon.glCtx->Const.MaxTextureUnits;
435 if (RADEON_DEBUG & DEBUG_TEXTURE) {
436 fprintf(stderr, "Using %d maximum texture units..\n", mtu);
437 }
438
439 /* Setup the atom linked list */
440 make_empty_list(&r300->radeon.hw.atomlist);
441 r300->radeon.hw.atomlist.name = "atom-list";
442
443 /* Initialize state atoms */
444 ALLOC_STATE(vpt, always, R300_VPT_CMDSIZE, 0);
445 r300->hw.vpt.cmd[R300_VPT_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_SE_VPORT_XSCALE, 6);
446 ALLOC_STATE(vap_cntl, always, R300_VAP_CNTL_SIZE, 0);
447 r300->hw.vap_cntl.cmd[R300_VAP_CNTL_FLUSH] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PVS_STATE_FLUSH_REG, 1);
448 r300->hw.vap_cntl.cmd[R300_VAP_CNTL_FLUSH_1] = 0;
449 r300->hw.vap_cntl.cmd[R300_VAP_CNTL_CMD] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_CNTL, 1);
450 if (is_r500) {
451 ALLOC_STATE(vap_index_offset, always, 2, 0);
452 r300->hw.vap_index_offset.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R500_VAP_INDEX_OFFSET, 1);
453 r300->hw.vap_index_offset.cmd[1] = 0;
454 }
455 ALLOC_STATE(vte, always, 3, 0);
456 r300->hw.vte.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SE_VTE_CNTL, 2);
457 ALLOC_STATE(vap_vf_max_vtx_indx, always, 3, 0);
458 r300->hw.vap_vf_max_vtx_indx.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_VF_MAX_VTX_INDX, 2);
459 ALLOC_STATE(vap_cntl_status, always, 2, 0);
460 r300->hw.vap_cntl_status.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_CNTL_STATUS, 1);
461 ALLOC_STATE(vir[0], variable, R300_VIR_CMDSIZE, 0);
462 r300->hw.vir[0].cmd[R300_VIR_CMD_0] =
463 cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PROG_STREAM_CNTL_0, 1);
464 ALLOC_STATE(vir[1], variable, R300_VIR_CMDSIZE, 1);
465 r300->hw.vir[1].cmd[R300_VIR_CMD_0] =
466 cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PROG_STREAM_CNTL_EXT_0, 1);
467 ALLOC_STATE(vic, always, R300_VIC_CMDSIZE, 0);
468 r300->hw.vic.cmd[R300_VIC_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_VTX_STATE_CNTL, 2);
469 ALLOC_STATE(vap_psc_sgn_norm_cntl, always, 2, 0);
470 r300->hw.vap_psc_sgn_norm_cntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PSC_SGN_NORM_CNTL, SGN_NORM_ZERO_CLAMP_MINUS_ONE);
471
472 if (has_tcl) {
473 ALLOC_STATE(vap_clip_cntl, always, 2, 0);
474 r300->hw.vap_clip_cntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_CLIP_CNTL, 1);
475 ALLOC_STATE(vap_clip, always, 5, 0);
476 r300->hw.vap_clip.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_GB_VERT_CLIP_ADJ, 4);
477 ALLOC_STATE(vap_pvs_vtx_timeout_reg, always, 2, 0);
478 r300->hw.vap_pvs_vtx_timeout_reg.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, VAP_PVS_VTX_TIMEOUT_REG, 1);
479 }
480
481 ALLOC_STATE(vof, always, R300_VOF_CMDSIZE, 0);
482 r300->hw.vof.cmd[R300_VOF_CMD_0] =
483 cmdpacket0(r300->radeon.radeonScreen, R300_VAP_OUTPUT_VTX_FMT_0, 2);
484
485 if (has_tcl) {
486 ALLOC_STATE(pvs, always, R300_PVS_CMDSIZE, 0);
487 r300->hw.pvs.cmd[R300_PVS_CMD_0] =
488 cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PVS_CODE_CNTL_0, 3);
489 }
490
491 ALLOC_STATE(gb_enable, always, 2, 0);
492 r300->hw.gb_enable.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GB_ENABLE, 1);
493 ALLOC_STATE(gb_misc, always, R300_GB_MISC_CMDSIZE, 0);
494 r300->hw.gb_misc.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GB_MSPOS0, 3);
495 r300->hw.gb_misc.emit = emit_gb_misc;
496 ALLOC_STATE(gb_misc2, always, R300_GB_MISC2_CMDSIZE, 0);
497 r300->hw.gb_misc2.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, 0x401C, 2);
498 ALLOC_STATE(txe, always, R300_TXE_CMDSIZE, 0);
499 r300->hw.txe.cmd[R300_TXE_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_TX_ENABLE, 1);
500 ALLOC_STATE(ga_point_s0, always, 5, 0);
501 r300->hw.ga_point_s0.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_POINT_S0, 4);
502 ALLOC_STATE(ga_triangle_stipple, always, 2, 0);
503 r300->hw.ga_triangle_stipple.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_TRIANGLE_STIPPLE, 1);
504 ALLOC_STATE(ps, always, R300_PS_CMDSIZE, 0);
505 r300->hw.ps.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_POINT_SIZE, 1);
506 ALLOC_STATE(ga_point_minmax, always, 4, 0);
507 r300->hw.ga_point_minmax.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_POINT_MINMAX, 3);
508 ALLOC_STATE(lcntl, always, 2, 0);
509 r300->hw.lcntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_LINE_CNTL, 1);
510 ALLOC_STATE(ga_line_stipple, always, 4, 0);
511 r300->hw.ga_line_stipple.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_LINE_STIPPLE_VALUE, 3);
512 ALLOC_STATE(shade, always, 2, 0);
513 r300->hw.shade.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_ENHANCE, 1);
514 r300->hw.shade.emit = emit_shade_misc;
515 ALLOC_STATE(shade2, always, 4, 0);
516 r300->hw.shade2.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, 0x4278, 3);
517 ALLOC_STATE(polygon_mode, always, 4, 0);
518 r300->hw.polygon_mode.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_POLY_MODE, 3);
519 ALLOC_STATE(fogp, always, 3, 0);
520 r300->hw.fogp.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_FOG_SCALE, 2);
521 ALLOC_STATE(zbias_cntl, always, 2, 0);
522 r300->hw.zbias_cntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SU_TEX_WRAP, 1);
523 ALLOC_STATE(zbs, always, R300_ZBS_CMDSIZE, 0);
524 r300->hw.zbs.cmd[R300_ZBS_CMD_0] =
525 cmdpacket0(r300->radeon.radeonScreen, R300_SU_POLY_OFFSET_FRONT_SCALE, 4);
526 ALLOC_STATE(occlusion_cntl, always, 2, 0);
527 r300->hw.occlusion_cntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SU_POLY_OFFSET_ENABLE, 1);
528 ALLOC_STATE(cul, always, R300_CUL_CMDSIZE, 0);
529 r300->hw.cul.cmd[R300_CUL_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_SU_CULL_MODE, 1);
530 ALLOC_STATE(su_depth_scale, always, 3, 0);
531 r300->hw.su_depth_scale.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SU_DEPTH_SCALE, 2);
532 ALLOC_STATE(rc, always, R300_RC_CMDSIZE, 0);
533 r300->hw.rc.cmd[R300_RC_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RS_COUNT, 2);
534 if (is_r500) {
535 ALLOC_STATE(ri, always, R500_RI_CMDSIZE, 0);
536 r300->hw.ri.cmd[R300_RI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R500_RS_IP_0, 16);
537 for (i = 0; i < 8; i++) {
538 r300->hw.ri.cmd[R300_RI_CMD_0 + i +1] =
539 (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_S_SHIFT) |
540 (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_T_SHIFT) |
541 (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT) |
542 (R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT);
543 }
544 ALLOC_STATE(rr, variable, R300_RR_CMDSIZE, 0);
545 r300->hw.rr.cmd[R300_RR_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R500_RS_INST_0, 1);
546 } else {
547 ALLOC_STATE(ri, always, R300_RI_CMDSIZE, 0);
548 r300->hw.ri.cmd[R300_RI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RS_IP_0, 8);
549 ALLOC_STATE(rr, variable, R300_RR_CMDSIZE, 0);
550 r300->hw.rr.cmd[R300_RR_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RS_INST_0, 1);
551 }
552 ALLOC_STATE(sc_hyperz, always, 3, 0);
553 r300->hw.sc_hyperz.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SC_HYPERZ, 2);
554 ALLOC_STATE(sc_screendoor, always, 2, 0);
555 r300->hw.sc_screendoor.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SC_SCREENDOOR, 1);
556 ALLOC_STATE(us_out_fmt, always, 6, 0);
557 r300->hw.us_out_fmt.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_OUT_FMT, 5);
558
559 if (is_r500) {
560 ALLOC_STATE(fp, always, R500_FP_CMDSIZE, 0);
561 r300->hw.fp.cmd[R500_FP_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R500_US_CONFIG, 2);
562 r300->hw.fp.cmd[R500_FP_CNTL] = R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO;
563 r300->hw.fp.cmd[R500_FP_CMD_1] = cmdpacket0(r300->radeon.radeonScreen, R500_US_CODE_ADDR, 3);
564 r300->hw.fp.cmd[R500_FP_CMD_2] = cmdpacket0(r300->radeon.radeonScreen, R500_US_FC_CTRL, 1);
565 r300->hw.fp.cmd[R500_FP_FC_CNTL] = 0; /* FIXME when we add flow control */
566
567 ALLOC_STATE(r500fp, r500fp, R500_FPI_CMDSIZE, 0);
568 r300->hw.r500fp.cmd[R300_FPI_CMD_0] =
569 cmdr500fp(r300->radeon.radeonScreen, 0, 0, 0, 0);
570 r300->hw.r500fp.emit = emit_r500fp;
571 ALLOC_STATE(r500fp_const, r500fp_const, R500_FPP_CMDSIZE, 0);
572 r300->hw.r500fp_const.cmd[R300_FPI_CMD_0] =
573 cmdr500fp(r300->radeon.radeonScreen, 0, 0, 1, 0);
574 r300->hw.r500fp_const.emit = emit_r500fp;
575 } else {
576 ALLOC_STATE(fp, always, R300_FP_CMDSIZE, 0);
577 r300->hw.fp.cmd[R300_FP_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_CONFIG, 3);
578 r300->hw.fp.cmd[R300_FP_CMD_1] = cmdpacket0(r300->radeon.radeonScreen, R300_US_CODE_ADDR_0, 4);
579
580 ALLOC_STATE(fpt, variable, R300_FPT_CMDSIZE, 0);
581 r300->hw.fpt.cmd[R300_FPT_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_TEX_INST_0, 0);
582
583 ALLOC_STATE(fpi[0], variable, R300_FPI_CMDSIZE, 0);
584 r300->hw.fpi[0].cmd[R300_FPI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_ALU_RGB_INST_0, 1);
585 ALLOC_STATE(fpi[1], variable, R300_FPI_CMDSIZE, 1);
586 r300->hw.fpi[1].cmd[R300_FPI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_ALU_RGB_ADDR_0, 1);
587 ALLOC_STATE(fpi[2], variable, R300_FPI_CMDSIZE, 2);
588 r300->hw.fpi[2].cmd[R300_FPI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_ALU_ALPHA_INST_0, 1);
589 ALLOC_STATE(fpi[3], variable, R300_FPI_CMDSIZE, 3);
590 r300->hw.fpi[3].cmd[R300_FPI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_ALU_ALPHA_ADDR_0, 1);
591 ALLOC_STATE(fpp, variable, R300_FPP_CMDSIZE, 0);
592 r300->hw.fpp.cmd[R300_FPP_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_PFS_PARAM_0_X, 0);
593 }
594 ALLOC_STATE(fogs, always, R300_FOGS_CMDSIZE, 0);
595 r300->hw.fogs.cmd[R300_FOGS_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_FG_FOG_BLEND, 1);
596 ALLOC_STATE(fogc, always, R300_FOGC_CMDSIZE, 0);
597 r300->hw.fogc.cmd[R300_FOGC_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_FG_FOG_COLOR_R, 3);
598 ALLOC_STATE(at, always, R300_AT_CMDSIZE, 0);
599 r300->hw.at.cmd[R300_AT_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_FG_ALPHA_FUNC, 2);
600 ALLOC_STATE(fg_depth_src, always, 2, 0);
601 r300->hw.fg_depth_src.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_FG_DEPTH_SRC, 1);
602 ALLOC_STATE(rb3d_cctl, always, 2, 0);
603 r300->hw.rb3d_cctl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_CCTL, 1);
604 ALLOC_STATE(bld, always, R300_BLD_CMDSIZE, 0);
605 r300->hw.bld.cmd[R300_BLD_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_CBLEND, 2);
606 ALLOC_STATE(cmk, always, R300_CMK_CMDSIZE, 0);
607 r300->hw.cmk.cmd[R300_CMK_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, RB3D_COLOR_CHANNEL_MASK, 1);
608 if (is_r500) {
609 ALLOC_STATE(blend_color, always, 3, 0);
610 r300->hw.blend_color.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R500_RB3D_CONSTANT_COLOR_AR, 2);
611 } else {
612 ALLOC_STATE(blend_color, always, 2, 0);
613 r300->hw.blend_color.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_BLEND_COLOR, 1);
614 }
615 ALLOC_STATE(rop, always, 2, 0);
616 r300->hw.rop.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_ROPCNTL, 1);
617 ALLOC_STATE(cb, always, R300_CB_CMDSIZE, 0);
618 r300->hw.cb.emit = &emit_cb_offset;
619 ALLOC_STATE(rb3d_dither_ctl, always, 10, 0);
620 r300->hw.rb3d_dither_ctl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_DITHER_CTL, 9);
621 ALLOC_STATE(rb3d_aaresolve_ctl, always, 2, 0);
622 r300->hw.rb3d_aaresolve_ctl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_AARESOLVE_CTL, 1);
623 if (is_r500) {
624 ALLOC_STATE(rb3d_discard_src_pixel_lte_threshold, always, 3, 0);
625 r300->hw.rb3d_discard_src_pixel_lte_threshold.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R500_RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD, 2);
626 } else {
627 ALLOC_STATE(rb3d_discard_src_pixel_lte_threshold, always, 3, 0);
628 r300->hw.rb3d_discard_src_pixel_lte_threshold.cmd[0] = (2 << 30);
629 r300->hw.rb3d_discard_src_pixel_lte_threshold.cmd[1] = (2 << 30);
630 r300->hw.rb3d_discard_src_pixel_lte_threshold.cmd[2] = (2 << 30);
631 }
632 ALLOC_STATE(zs, always, R300_ZS_CMDSIZE, 0);
633 r300->hw.zs.cmd[R300_ZS_CMD_0] =
634 cmdpacket0(r300->radeon.radeonScreen, R300_ZB_CNTL, 3);
635
636 ALLOC_STATE(zstencil_format, always, 5, 0);
637 r300->hw.zstencil_format.cmd[0] =
638 cmdpacket0(r300->radeon.radeonScreen, R300_ZB_FORMAT, 4);
639 r300->hw.zstencil_format.emit = emit_zstencil_format;
640
641 ALLOC_STATE(zb, always, R300_ZB_CMDSIZE, 0);
642 r300->hw.zb.emit = emit_zb_offset;
643 ALLOC_STATE(zb_depthclearvalue, always, 2, 0);
644 r300->hw.zb_depthclearvalue.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_ZB_DEPTHCLEARVALUE, 1);
645 ALLOC_STATE(zb_zmask, always, 3, 0);
646 r300->hw.zb_zmask.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_ZB_ZMASK_OFFSET, 2);
647 ALLOC_STATE(zb_hiz_offset, always, 2, 0);
648 r300->hw.zb_hiz_offset.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_ZB_HIZ_OFFSET, 1);
649 ALLOC_STATE(zb_hiz_pitch, always, 2, 0);
650 r300->hw.zb_hiz_pitch.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_ZB_HIZ_PITCH, 1);
651
652 /* VPU only on TCL */
653 if (has_tcl) {
654 int i;
655 ALLOC_STATE(vpi, vpu, R300_VPI_CMDSIZE, 0);
656 r300->hw.vpi.cmd[0] =
657 cmdvpu(r300->radeon.radeonScreen, R300_PVS_CODE_START, 0);
658 r300->hw.vpi.emit = emit_vpu;
659
660 if (is_r500) {
661 ALLOC_STATE(vpp, vpu, R300_VPP_CMDSIZE, 0);
662 r300->hw.vpp.cmd[0] =
663 cmdvpu(r300->radeon.radeonScreen, R500_PVS_CONST_START, 0);
664 r300->hw.vpp.emit = emit_vpu;
665
666 ALLOC_STATE(vps, vpu, R300_VPS_CMDSIZE, 0);
667 r300->hw.vps.cmd[0] =
668 cmdvpu(r300->radeon.radeonScreen, R500_POINT_VPORT_SCALE_OFFSET, 1);
669 r300->hw.vps.emit = emit_vpu;
670
671 for (i = 0; i < 6; i++) {
672 ALLOC_STATE(vpucp[i], vpu, R300_VPUCP_CMDSIZE, 0);
673 r300->hw.vpucp[i].cmd[0] =
674 cmdvpu(r300->radeon.radeonScreen,
675 R500_PVS_UCP_START + i, 1);
676 r300->hw.vpucp[i].emit = emit_vpu;
677 }
678 } else {
679 ALLOC_STATE(vpp, vpu, R300_VPP_CMDSIZE, 0);
680 r300->hw.vpp.cmd[0] =
681 cmdvpu(r300->radeon.radeonScreen, R300_PVS_CONST_START, 0);
682 r300->hw.vpp.emit = emit_vpu;
683
684 ALLOC_STATE(vps, vpu, R300_VPS_CMDSIZE, 0);
685 r300->hw.vps.cmd[0] =
686 cmdvpu(r300->radeon.radeonScreen, R300_POINT_VPORT_SCALE_OFFSET, 1);
687 r300->hw.vps.emit = emit_vpu;
688
689 for (i = 0; i < 6; i++) {
690 ALLOC_STATE(vpucp[i], vpu, R300_VPUCP_CMDSIZE, 0);
691 r300->hw.vpucp[i].cmd[0] =
692 cmdvpu(r300->radeon.radeonScreen,
693 R300_PVS_UCP_START + i, 1);
694 r300->hw.vpucp[i].emit = emit_vpu;
695 }
696 }
697 }
698
699 /* Textures */
700 ALLOC_STATE(tex.filter, variable, mtu + 1, 0);
701 r300->hw.tex.filter.cmd[R300_TEX_CMD_0] =
702 cmdpacket0(r300->radeon.radeonScreen, R300_TX_FILTER0_0, 0);
703
704 ALLOC_STATE(tex.filter_1, variable, mtu + 1, 0);
705 r300->hw.tex.filter_1.cmd[R300_TEX_CMD_0] =
706 cmdpacket0(r300->radeon.radeonScreen, R300_TX_FILTER1_0, 0);
707
708 ALLOC_STATE(tex.size, variable, mtu + 1, 0);
709 r300->hw.tex.size.cmd[R300_TEX_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_TX_SIZE_0, 0);
710
711 ALLOC_STATE(tex.format, variable, mtu + 1, 0);
712 r300->hw.tex.format.cmd[R300_TEX_CMD_0] =
713 cmdpacket0(r300->radeon.radeonScreen, R300_TX_FORMAT_0, 0);
714
715 ALLOC_STATE(tex.pitch, variable, mtu + 1, 0);
716 r300->hw.tex.pitch.cmd[R300_TEX_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_TX_FORMAT2_0, 0);
717
718 ALLOC_STATE(tex.offset, variable, 1, 0);
719 r300->hw.tex.offset.cmd[R300_TEX_CMD_0] =
720 cmdpacket0(r300->radeon.radeonScreen, R300_TX_OFFSET_0, 0);
721 r300->hw.tex.offset.emit = &emit_tex_offsets;
722
723 ALLOC_STATE(tex.chroma_key, variable, mtu + 1, 0);
724 r300->hw.tex.chroma_key.cmd[R300_TEX_CMD_0] =
725 cmdpacket0(r300->radeon.radeonScreen, R300_TX_CHROMA_KEY_0, 0);
726
727 ALLOC_STATE(tex.border_color, variable, mtu + 1, 0);
728 r300->hw.tex.border_color.cmd[R300_TEX_CMD_0] =
729 cmdpacket0(r300->radeon.radeonScreen, R300_TX_BORDER_COLOR_0, 0);
730
731 r300->radeon.hw.is_dirty = GL_TRUE;
732 r300->radeon.hw.all_dirty = GL_TRUE;
733
734 rcommonInitCmdBuf(&r300->radeon);
735 }