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r300: Redirect constant TEX coordinates
[mesa.git] / src / mesa / drivers / dri / r300 / r300_cmdbuf.c
1 /*
2 Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
3
4 The Weather Channel (TM) funded Tungsten Graphics to develop the
5 initial release of the Radeon 8500 driver under the XFree86 license.
6 This notice must be preserved.
7
8 Permission is hereby granted, free of charge, to any person obtaining
9 a copy of this software and associated documentation files (the
10 "Software"), to deal in the Software without restriction, including
11 without limitation the rights to use, copy, modify, merge, publish,
12 distribute, sublicense, and/or sell copies of the Software, and to
13 permit persons to whom the Software is furnished to do so, subject to
14 the following conditions:
15
16 The above copyright notice and this permission notice (including the
17 next paragraph) shall be included in all copies or substantial
18 portions of the Software.
19
20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27
28 **************************************************************************/
29
30 /**
31 * \file
32 *
33 * \author Nicolai Haehnle <prefect_@gmx.net>
34 */
35
36 #include "main/glheader.h"
37 #include "main/state.h"
38 #include "main/imports.h"
39 #include "main/macros.h"
40 #include "main/context.h"
41 #include "main/simple_list.h"
42 #include "swrast/swrast.h"
43
44 #include "drm.h"
45 #include "radeon_drm.h"
46
47 #include "r300_context.h"
48 #include "r300_ioctl.h"
49 #include "radeon_reg.h"
50 #include "r300_reg.h"
51 #include "r300_cmdbuf.h"
52 #include "r300_emit.h"
53 #include "radeon_bocs_wrapper.h"
54 #include "radeon_mipmap_tree.h"
55 #include "r300_state.h"
56 #include "radeon_reg.h"
57
58 #define R300_VAP_PVS_UPLOAD_ADDRESS 0x2200
59 # define RADEON_ONE_REG_WR (1 << 15)
60
61 /** # of dwords reserved for additional instructions that may need to be written
62 * during flushing.
63 */
64 #define SPACE_FOR_FLUSHING 4
65
66 static unsigned packet0_count(r300ContextPtr r300, uint32_t *pkt)
67 {
68 if (r300->radeon.radeonScreen->kernel_mm) {
69 return ((((*pkt) >> 16) & 0x3FFF) + 1);
70 } else {
71 drm_r300_cmd_header_t *t = (drm_r300_cmd_header_t*)pkt;
72 return t->packet0.count;
73 }
74 return 0;
75 }
76
77 #define vpu_count(ptr) (((drm_r300_cmd_header_t*)(ptr))->vpu.count)
78 #define r500fp_count(ptr) (((drm_r300_cmd_header_t*)(ptr))->r500fp.count)
79
80 void emit_vpu(GLcontext *ctx, struct radeon_state_atom * atom)
81 {
82 r300ContextPtr r300 = R300_CONTEXT(ctx);
83 BATCH_LOCALS(&r300->radeon);
84 drm_r300_cmd_header_t cmd;
85 uint32_t addr, ndw, i;
86
87 if (!r300->radeon.radeonScreen->kernel_mm) {
88 uint32_t dwords;
89 dwords = (*atom->check) (ctx, atom);
90 BEGIN_BATCH_NO_AUTOSTATE(dwords);
91 OUT_BATCH_TABLE(atom->cmd, dwords);
92 END_BATCH();
93 return;
94 }
95
96 cmd.u = atom->cmd[0];
97 addr = (cmd.vpu.adrhi << 8) | cmd.vpu.adrlo;
98 ndw = cmd.vpu.count * 4;
99 if (ndw) {
100 BEGIN_BATCH_NO_AUTOSTATE(11 + ndw);
101
102 /* flush processing vertices */
103 OUT_BATCH(CP_PACKET0(R300_SC_SCREENDOOR, 0));
104 OUT_BATCH(0x0);
105 OUT_BATCH(CP_PACKET0(RADEON_WAIT_UNTIL, 0));
106 OUT_BATCH((1 << 15) | (1 << 28));
107 OUT_BATCH(CP_PACKET0(R300_SC_SCREENDOOR, 0));
108 OUT_BATCH(0x00FFFFFF);
109 OUT_BATCH(CP_PACKET0(R300_VAP_PVS_STATE_FLUSH_REG, 0));
110 OUT_BATCH(1);
111 /* write vpu */
112 OUT_BATCH(CP_PACKET0(R300_VAP_PVS_UPLOAD_ADDRESS, 0));
113 OUT_BATCH(addr);
114 OUT_BATCH(CP_PACKET0(R300_VAP_PVS_UPLOAD_DATA, ndw-1) | RADEON_ONE_REG_WR);
115 for (i = 0; i < ndw; i++) {
116 OUT_BATCH(atom->cmd[i+1]);
117 }
118 END_BATCH();
119 }
120 }
121
122 void emit_r500fp(GLcontext *ctx, struct radeon_state_atom * atom)
123 {
124 r300ContextPtr r300 = R300_CONTEXT(ctx);
125 BATCH_LOCALS(&r300->radeon);
126 drm_r300_cmd_header_t cmd;
127 uint32_t addr, ndw, i, sz;
128 int type, clamp, stride;
129
130 if (!r300->radeon.radeonScreen->kernel_mm) {
131 uint32_t dwords;
132 dwords = (*atom->check) (ctx, atom);
133 BEGIN_BATCH_NO_AUTOSTATE(dwords);
134 OUT_BATCH_TABLE(atom->cmd, dwords);
135 END_BATCH();
136 return;
137 }
138
139 cmd.u = atom->cmd[0];
140 sz = cmd.r500fp.count;
141 addr = ((cmd.r500fp.adrhi_flags & 1) << 8) | cmd.r500fp.adrlo;
142 type = !!(cmd.r500fp.adrhi_flags & R500FP_CONSTANT_TYPE);
143 clamp = !!(cmd.r500fp.adrhi_flags & R500FP_CONSTANT_CLAMP);
144
145 addr |= (type << 16);
146 addr |= (clamp << 17);
147
148 stride = type ? 4 : 6;
149
150 ndw = sz * stride;
151 if (ndw) {
152
153 BEGIN_BATCH_NO_AUTOSTATE(3 + ndw);
154 OUT_BATCH(CP_PACKET0(R500_GA_US_VECTOR_INDEX, 0));
155 OUT_BATCH(addr);
156 OUT_BATCH(CP_PACKET0(R500_GA_US_VECTOR_DATA, ndw-1) | RADEON_ONE_REG_WR);
157 for (i = 0; i < ndw; i++) {
158 OUT_BATCH(atom->cmd[i+1]);
159 }
160 END_BATCH();
161 }
162 }
163
164 static void emit_tex_offsets(GLcontext *ctx, struct radeon_state_atom * atom)
165 {
166 r300ContextPtr r300 = R300_CONTEXT(ctx);
167 BATCH_LOCALS(&r300->radeon);
168 int numtmus = packet0_count(r300, r300->hw.tex.offset.cmd);
169
170 if (numtmus) {
171 int i;
172
173 for(i = 0; i < numtmus; ++i) {
174 radeonTexObj *t = r300->hw.textures[i];
175 if (t && !t->image_override) {
176 BEGIN_BATCH_NO_AUTOSTATE(4);
177 OUT_BATCH_REGSEQ(R300_TX_OFFSET_0 + (i * 4), 1);
178 OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, 0,
179 RADEON_GEM_DOMAIN_VRAM, 0, 0);
180 END_BATCH();
181 } else if (!t) {
182 //assert(0);
183 } else {
184 if (t->bo) {
185 BEGIN_BATCH_NO_AUTOSTATE(4);
186 OUT_BATCH_REGSEQ(R300_TX_OFFSET_0 + (i * 4), 1);
187 OUT_BATCH_RELOC(t->tile_bits, t->bo, 0,
188 RADEON_GEM_DOMAIN_VRAM, 0, 0);
189 END_BATCH();
190 } else if (!r300->radeon.radeonScreen->kernel_mm) {
191 BEGIN_BATCH_NO_AUTOSTATE(2);
192 OUT_BATCH_REGSEQ(R300_TX_OFFSET_0 + (i * 4), 1);
193 OUT_BATCH(t->override_offset);
194 END_BATCH();
195 }
196 }
197 }
198 }
199 }
200
201 static void emit_cb_offset(GLcontext *ctx, struct radeon_state_atom * atom)
202 {
203 r300ContextPtr r300 = R300_CONTEXT(ctx);
204 BATCH_LOCALS(&r300->radeon);
205 struct radeon_renderbuffer *rrb;
206 uint32_t cbpitch;
207
208 rrb = radeon_get_colorbuffer(&r300->radeon);
209 if (!rrb || !rrb->bo) {
210 fprintf(stderr, "no rrb\n");
211 return;
212 }
213
214 cbpitch = (rrb->pitch / rrb->cpp);
215 if (rrb->cpp == 4)
216 cbpitch |= R300_COLOR_FORMAT_ARGB8888;
217 else
218 cbpitch |= R300_COLOR_FORMAT_RGB565;
219
220 if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE)
221 cbpitch |= R300_COLOR_TILE_ENABLE;
222
223 BEGIN_BATCH_NO_AUTOSTATE(6);
224 OUT_BATCH_REGSEQ(R300_RB3D_COLOROFFSET0, 1);
225 OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
226 OUT_BATCH_REGSEQ(R300_RB3D_COLORPITCH0, 1);
227 OUT_BATCH(cbpitch);
228 END_BATCH();
229 }
230
231 static void emit_zb_offset(GLcontext *ctx, struct radeon_state_atom * atom)
232 {
233 r300ContextPtr r300 = R300_CONTEXT(ctx);
234 BATCH_LOCALS(&r300->radeon);
235 struct radeon_renderbuffer *rrb;
236 uint32_t zbpitch;
237
238 rrb = radeon_get_depthbuffer(&r300->radeon);
239 if (!rrb)
240 return;
241
242 zbpitch = (rrb->pitch / rrb->cpp);
243 if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE) {
244 zbpitch |= R300_DEPTHMACROTILE_ENABLE;
245 }
246 if (rrb->bo->flags & RADEON_BO_FLAGS_MICRO_TILE){
247 zbpitch |= R300_DEPTHMICROTILE_TILED;
248 }
249
250 BEGIN_BATCH_NO_AUTOSTATE(6);
251 OUT_BATCH_REGSEQ(R300_ZB_DEPTHOFFSET, 1);
252 OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
253 OUT_BATCH_REGVAL(R300_ZB_DEPTHPITCH, zbpitch);
254 END_BATCH();
255 }
256
257 static int check_always(GLcontext *ctx, struct radeon_state_atom *atom)
258 {
259 return atom->cmd_size;
260 }
261
262 static int check_variable(GLcontext *ctx, struct radeon_state_atom *atom)
263 {
264 r300ContextPtr r300 = R300_CONTEXT(ctx);
265 int cnt;
266 if (atom->cmd[0] == CP_PACKET2) {
267 return 0;
268 }
269 cnt = packet0_count(r300, atom->cmd);
270 return cnt ? cnt + 1 : 0;
271 }
272
273 int check_vpu(GLcontext *ctx, struct radeon_state_atom *atom)
274 {
275 int cnt;
276
277 cnt = vpu_count(atom->cmd);
278 return cnt ? (cnt * 4) + 1 : 0;
279 }
280
281 int check_r500fp(GLcontext *ctx, struct radeon_state_atom *atom)
282 {
283 int cnt;
284
285 cnt = r500fp_count(atom->cmd);
286 return cnt ? (cnt * 6) + 1 : 0;
287 }
288
289 int check_r500fp_const(GLcontext *ctx, struct radeon_state_atom *atom)
290 {
291 int cnt;
292
293 cnt = r500fp_count(atom->cmd);
294 return cnt ? (cnt * 4) + 1 : 0;
295 }
296
297 #define ALLOC_STATE( ATOM, CHK, SZ, IDX ) \
298 do { \
299 r300->hw.ATOM.cmd_size = (SZ); \
300 r300->hw.ATOM.cmd = (uint32_t*)CALLOC((SZ) * sizeof(uint32_t)); \
301 r300->hw.ATOM.name = #ATOM; \
302 r300->hw.ATOM.idx = (IDX); \
303 r300->hw.ATOM.check = check_##CHK; \
304 r300->hw.ATOM.dirty = GL_FALSE; \
305 r300->radeon.hw.max_state_size += (SZ); \
306 insert_at_tail(&r300->radeon.hw.atomlist, &r300->hw.ATOM); \
307 } while (0)
308 /**
309 * Allocate memory for the command buffer and initialize the state atom
310 * list. Note that the initial hardware state is set by r300InitState().
311 */
312 void r300InitCmdBuf(r300ContextPtr r300)
313 {
314 int mtu;
315 int has_tcl = 1;
316 int is_r500 = 0;
317 int i;
318
319 if (!(r300->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL))
320 has_tcl = 0;
321
322 if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515)
323 is_r500 = 1;
324
325 r300->radeon.hw.max_state_size = 2 + 2; /* reserve extra space for WAIT_IDLE and tex cache flush */
326
327 mtu = r300->radeon.glCtx->Const.MaxTextureUnits;
328 if (RADEON_DEBUG & DEBUG_TEXTURE) {
329 fprintf(stderr, "Using %d maximum texture units..\n", mtu);
330 }
331
332 /* Setup the atom linked list */
333 make_empty_list(&r300->radeon.hw.atomlist);
334 r300->radeon.hw.atomlist.name = "atom-list";
335
336 /* Initialize state atoms */
337 ALLOC_STATE(vpt, always, R300_VPT_CMDSIZE, 0);
338 r300->hw.vpt.cmd[R300_VPT_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_SE_VPORT_XSCALE, 6);
339 ALLOC_STATE(vap_cntl, always, R300_VAP_CNTL_SIZE, 0);
340 r300->hw.vap_cntl.cmd[R300_VAP_CNTL_FLUSH] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PVS_STATE_FLUSH_REG, 1);
341 r300->hw.vap_cntl.cmd[R300_VAP_CNTL_FLUSH_1] = 0;
342 r300->hw.vap_cntl.cmd[R300_VAP_CNTL_CMD] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_CNTL, 1);
343 if (is_r500) {
344 ALLOC_STATE(vap_index_offset, always, 2, 0);
345 r300->hw.vap_index_offset.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R500_VAP_INDEX_OFFSET, 1);
346 r300->hw.vap_index_offset.cmd[1] = 0;
347 }
348 ALLOC_STATE(vte, always, 3, 0);
349 r300->hw.vte.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SE_VTE_CNTL, 2);
350 ALLOC_STATE(vap_vf_max_vtx_indx, always, 3, 0);
351 r300->hw.vap_vf_max_vtx_indx.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_VF_MAX_VTX_INDX, 2);
352 ALLOC_STATE(vap_cntl_status, always, 2, 0);
353 r300->hw.vap_cntl_status.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_CNTL_STATUS, 1);
354 ALLOC_STATE(vir[0], variable, R300_VIR_CMDSIZE, 0);
355 r300->hw.vir[0].cmd[R300_VIR_CMD_0] =
356 cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PROG_STREAM_CNTL_0, 1);
357 ALLOC_STATE(vir[1], variable, R300_VIR_CMDSIZE, 1);
358 r300->hw.vir[1].cmd[R300_VIR_CMD_0] =
359 cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PROG_STREAM_CNTL_EXT_0, 1);
360 ALLOC_STATE(vic, always, R300_VIC_CMDSIZE, 0);
361 r300->hw.vic.cmd[R300_VIC_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_VTX_STATE_CNTL, 2);
362 ALLOC_STATE(vap_psc_sgn_norm_cntl, always, 2, 0);
363 r300->hw.vap_psc_sgn_norm_cntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PSC_SGN_NORM_CNTL, SGN_NORM_ZERO_CLAMP_MINUS_ONE);
364
365 if (has_tcl) {
366 ALLOC_STATE(vap_clip_cntl, always, 2, 0);
367 r300->hw.vap_clip_cntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_CLIP_CNTL, 1);
368 ALLOC_STATE(vap_clip, always, 5, 0);
369 r300->hw.vap_clip.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_GB_VERT_CLIP_ADJ, 4);
370 ALLOC_STATE(vap_pvs_vtx_timeout_reg, always, 2, 0);
371 r300->hw.vap_pvs_vtx_timeout_reg.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, VAP_PVS_VTX_TIMEOUT_REG, 1);
372 }
373
374 ALLOC_STATE(vof, always, R300_VOF_CMDSIZE, 0);
375 r300->hw.vof.cmd[R300_VOF_CMD_0] =
376 cmdpacket0(r300->radeon.radeonScreen, R300_VAP_OUTPUT_VTX_FMT_0, 2);
377
378 if (has_tcl) {
379 ALLOC_STATE(pvs, always, R300_PVS_CMDSIZE, 0);
380 r300->hw.pvs.cmd[R300_PVS_CMD_0] =
381 cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PVS_CODE_CNTL_0, 3);
382 }
383
384 ALLOC_STATE(gb_enable, always, 2, 0);
385 r300->hw.gb_enable.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GB_ENABLE, 1);
386 ALLOC_STATE(gb_misc, always, R300_GB_MISC_CMDSIZE, 0);
387 r300->hw.gb_misc.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GB_MSPOS0, 5);
388 ALLOC_STATE(txe, always, R300_TXE_CMDSIZE, 0);
389 r300->hw.txe.cmd[R300_TXE_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_TX_ENABLE, 1);
390 ALLOC_STATE(ga_point_s0, always, 5, 0);
391 r300->hw.ga_point_s0.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_POINT_S0, 4);
392 ALLOC_STATE(ga_triangle_stipple, always, 2, 0);
393 r300->hw.ga_triangle_stipple.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_TRIANGLE_STIPPLE, 1);
394 ALLOC_STATE(ps, always, R300_PS_CMDSIZE, 0);
395 r300->hw.ps.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_POINT_SIZE, 1);
396 ALLOC_STATE(ga_point_minmax, always, 4, 0);
397 r300->hw.ga_point_minmax.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_POINT_MINMAX, 3);
398 ALLOC_STATE(lcntl, always, 2, 0);
399 r300->hw.lcntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_LINE_CNTL, 1);
400 ALLOC_STATE(ga_line_stipple, always, 4, 0);
401 r300->hw.ga_line_stipple.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_LINE_STIPPLE_VALUE, 3);
402 ALLOC_STATE(shade, always, 5, 0);
403 r300->hw.shade.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_ENHANCE, 4);
404 ALLOC_STATE(polygon_mode, always, 4, 0);
405 r300->hw.polygon_mode.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_POLY_MODE, 3);
406 ALLOC_STATE(fogp, always, 3, 0);
407 r300->hw.fogp.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_FOG_SCALE, 2);
408 ALLOC_STATE(zbias_cntl, always, 2, 0);
409 r300->hw.zbias_cntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SU_TEX_WRAP, 1);
410 ALLOC_STATE(zbs, always, R300_ZBS_CMDSIZE, 0);
411 r300->hw.zbs.cmd[R300_ZBS_CMD_0] =
412 cmdpacket0(r300->radeon.radeonScreen, R300_SU_POLY_OFFSET_FRONT_SCALE, 4);
413 ALLOC_STATE(occlusion_cntl, always, 2, 0);
414 r300->hw.occlusion_cntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SU_POLY_OFFSET_ENABLE, 1);
415 ALLOC_STATE(cul, always, R300_CUL_CMDSIZE, 0);
416 r300->hw.cul.cmd[R300_CUL_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_SU_CULL_MODE, 1);
417 ALLOC_STATE(su_depth_scale, always, 3, 0);
418 r300->hw.su_depth_scale.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SU_DEPTH_SCALE, 2);
419 ALLOC_STATE(rc, always, R300_RC_CMDSIZE, 0);
420 r300->hw.rc.cmd[R300_RC_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RS_COUNT, 2);
421 if (is_r500) {
422 ALLOC_STATE(ri, always, R500_RI_CMDSIZE, 0);
423 r300->hw.ri.cmd[R300_RI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R500_RS_IP_0, 16);
424 for (i = 0; i < 8; i++) {
425 r300->hw.ri.cmd[R300_RI_CMD_0 + i +1] =
426 (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_S_SHIFT) |
427 (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_T_SHIFT) |
428 (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT) |
429 (R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT);
430 }
431 ALLOC_STATE(rr, variable, R300_RR_CMDSIZE, 0);
432 r300->hw.rr.cmd[R300_RR_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R500_RS_INST_0, 1);
433 } else {
434 ALLOC_STATE(ri, always, R300_RI_CMDSIZE, 0);
435 r300->hw.ri.cmd[R300_RI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RS_IP_0, 8);
436 ALLOC_STATE(rr, variable, R300_RR_CMDSIZE, 0);
437 r300->hw.rr.cmd[R300_RR_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RS_INST_0, 1);
438 }
439 ALLOC_STATE(sc_hyperz, always, 3, 0);
440 r300->hw.sc_hyperz.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SC_HYPERZ, 2);
441 ALLOC_STATE(sc_screendoor, always, 2, 0);
442 r300->hw.sc_screendoor.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SC_SCREENDOOR, 1);
443 ALLOC_STATE(us_out_fmt, always, 6, 0);
444 r300->hw.us_out_fmt.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_OUT_FMT, 5);
445
446 if (is_r500) {
447 ALLOC_STATE(fp, always, R500_FP_CMDSIZE, 0);
448 r300->hw.fp.cmd[R500_FP_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R500_US_CONFIG, 2);
449 r300->hw.fp.cmd[R500_FP_CNTL] = R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO;
450 r300->hw.fp.cmd[R500_FP_CMD_1] = cmdpacket0(r300->radeon.radeonScreen, R500_US_CODE_ADDR, 3);
451 r300->hw.fp.cmd[R500_FP_CMD_2] = cmdpacket0(r300->radeon.radeonScreen, R500_US_FC_CTRL, 1);
452 r300->hw.fp.cmd[R500_FP_FC_CNTL] = 0; /* FIXME when we add flow control */
453
454 ALLOC_STATE(r500fp, r500fp, R500_FPI_CMDSIZE, 0);
455 r300->hw.r500fp.cmd[R300_FPI_CMD_0] =
456 cmdr500fp(r300->radeon.radeonScreen, 0, 0, 0, 0);
457 r300->hw.r500fp.emit = emit_r500fp;
458 ALLOC_STATE(r500fp_const, r500fp_const, R500_FPP_CMDSIZE, 0);
459 r300->hw.r500fp_const.cmd[R300_FPI_CMD_0] =
460 cmdr500fp(r300->radeon.radeonScreen, 0, 0, 1, 0);
461 r300->hw.r500fp_const.emit = emit_r500fp;
462 } else {
463 ALLOC_STATE(fp, always, R300_FP_CMDSIZE, 0);
464 r300->hw.fp.cmd[R300_FP_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_CONFIG, 3);
465 r300->hw.fp.cmd[R300_FP_CMD_1] = cmdpacket0(r300->radeon.radeonScreen, R300_US_CODE_ADDR_0, 4);
466
467 ALLOC_STATE(fpt, variable, R300_FPT_CMDSIZE, 0);
468 r300->hw.fpt.cmd[R300_FPT_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_TEX_INST_0, 0);
469
470 ALLOC_STATE(fpi[0], variable, R300_FPI_CMDSIZE, 0);
471 r300->hw.fpi[0].cmd[R300_FPI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_ALU_RGB_INST_0, 1);
472 ALLOC_STATE(fpi[1], variable, R300_FPI_CMDSIZE, 1);
473 r300->hw.fpi[1].cmd[R300_FPI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_ALU_RGB_ADDR_0, 1);
474 ALLOC_STATE(fpi[2], variable, R300_FPI_CMDSIZE, 2);
475 r300->hw.fpi[2].cmd[R300_FPI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_ALU_ALPHA_INST_0, 1);
476 ALLOC_STATE(fpi[3], variable, R300_FPI_CMDSIZE, 3);
477 r300->hw.fpi[3].cmd[R300_FPI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_ALU_ALPHA_ADDR_0, 1);
478 ALLOC_STATE(fpp, variable, R300_FPP_CMDSIZE, 0);
479 r300->hw.fpp.cmd[R300_FPP_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_PFS_PARAM_0_X, 0);
480 }
481 ALLOC_STATE(fogs, always, R300_FOGS_CMDSIZE, 0);
482 r300->hw.fogs.cmd[R300_FOGS_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_FG_FOG_BLEND, 1);
483 ALLOC_STATE(fogc, always, R300_FOGC_CMDSIZE, 0);
484 r300->hw.fogc.cmd[R300_FOGC_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_FG_FOG_COLOR_R, 3);
485 ALLOC_STATE(at, always, R300_AT_CMDSIZE, 0);
486 r300->hw.at.cmd[R300_AT_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_FG_ALPHA_FUNC, 2);
487 ALLOC_STATE(fg_depth_src, always, 2, 0);
488 r300->hw.fg_depth_src.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_FG_DEPTH_SRC, 1);
489 ALLOC_STATE(rb3d_cctl, always, 2, 0);
490 r300->hw.rb3d_cctl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_CCTL, 1);
491 ALLOC_STATE(bld, always, R300_BLD_CMDSIZE, 0);
492 r300->hw.bld.cmd[R300_BLD_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_CBLEND, 2);
493 ALLOC_STATE(cmk, always, R300_CMK_CMDSIZE, 0);
494 r300->hw.cmk.cmd[R300_CMK_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, RB3D_COLOR_CHANNEL_MASK, 1);
495 if (is_r500) {
496 ALLOC_STATE(blend_color, always, 3, 0);
497 r300->hw.blend_color.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R500_RB3D_CONSTANT_COLOR_AR, 2);
498 } else {
499 ALLOC_STATE(blend_color, always, 2, 0);
500 r300->hw.blend_color.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_BLEND_COLOR, 1);
501 }
502 ALLOC_STATE(rop, always, 2, 0);
503 r300->hw.rop.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_ROPCNTL, 1);
504 ALLOC_STATE(cb, always, R300_CB_CMDSIZE, 0);
505 r300->hw.cb.emit = &emit_cb_offset;
506 ALLOC_STATE(rb3d_dither_ctl, always, 10, 0);
507 r300->hw.rb3d_dither_ctl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_DITHER_CTL, 9);
508 ALLOC_STATE(rb3d_aaresolve_ctl, always, 2, 0);
509 r300->hw.rb3d_aaresolve_ctl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_AARESOLVE_CTL, 1);
510 ALLOC_STATE(rb3d_discard_src_pixel_lte_threshold, always, 3, 0);
511 r300->hw.rb3d_discard_src_pixel_lte_threshold.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R500_RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD, 2);
512 ALLOC_STATE(zs, always, R300_ZS_CMDSIZE, 0);
513 r300->hw.zs.cmd[R300_ZS_CMD_0] =
514 cmdpacket0(r300->radeon.radeonScreen, R300_ZB_CNTL, 3);
515 ALLOC_STATE(zstencil_format, always, 5, 0);
516 r300->hw.zstencil_format.cmd[0] =
517 cmdpacket0(r300->radeon.radeonScreen, R300_ZB_FORMAT, 4);
518 ALLOC_STATE(zb, always, R300_ZB_CMDSIZE, 0);
519 r300->hw.zb.emit = emit_zb_offset;
520 ALLOC_STATE(zb_depthclearvalue, always, 2, 0);
521 r300->hw.zb_depthclearvalue.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_ZB_DEPTHCLEARVALUE, 1);
522 ALLOC_STATE(unk4F30, always, 3, 0);
523 r300->hw.unk4F30.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, 0x4F30, 2);
524 ALLOC_STATE(zb_hiz_offset, always, 2, 0);
525 r300->hw.zb_hiz_offset.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_ZB_HIZ_OFFSET, 1);
526 ALLOC_STATE(zb_hiz_pitch, always, 2, 0);
527 r300->hw.zb_hiz_pitch.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_ZB_HIZ_PITCH, 1);
528
529 /* VPU only on TCL */
530 if (has_tcl) {
531 int i;
532 ALLOC_STATE(vpi, vpu, R300_VPI_CMDSIZE, 0);
533 r300->hw.vpi.cmd[0] =
534 cmdvpu(r300->radeon.radeonScreen, R300_PVS_CODE_START, 0);
535 r300->hw.vpi.emit = emit_vpu;
536
537 if (is_r500) {
538 ALLOC_STATE(vpp, vpu, R300_VPP_CMDSIZE, 0);
539 r300->hw.vpp.cmd[0] =
540 cmdvpu(r300->radeon.radeonScreen, R500_PVS_CONST_START, 0);
541 r300->hw.vpp.emit = emit_vpu;
542
543 ALLOC_STATE(vps, vpu, R300_VPS_CMDSIZE, 0);
544 r300->hw.vps.cmd[0] =
545 cmdvpu(r300->radeon.radeonScreen, R500_POINT_VPORT_SCALE_OFFSET, 1);
546 r300->hw.vps.emit = emit_vpu;
547
548 for (i = 0; i < 6; i++) {
549 ALLOC_STATE(vpucp[i], vpu, R300_VPUCP_CMDSIZE, 0);
550 r300->hw.vpucp[i].cmd[0] =
551 cmdvpu(r300->radeon.radeonScreen,
552 R500_PVS_UCP_START + i, 1);
553 r300->hw.vpucp[i].emit = emit_vpu;
554 }
555 } else {
556 ALLOC_STATE(vpp, vpu, R300_VPP_CMDSIZE, 0);
557 r300->hw.vpp.cmd[0] =
558 cmdvpu(r300->radeon.radeonScreen, R300_PVS_CONST_START, 0);
559 r300->hw.vpp.emit = emit_vpu;
560
561 ALLOC_STATE(vps, vpu, R300_VPS_CMDSIZE, 0);
562 r300->hw.vps.cmd[0] =
563 cmdvpu(r300->radeon.radeonScreen, R300_POINT_VPORT_SCALE_OFFSET, 1);
564 r300->hw.vps.emit = emit_vpu;
565
566 for (i = 0; i < 6; i++) {
567 ALLOC_STATE(vpucp[i], vpu, R300_VPUCP_CMDSIZE, 0);
568 r300->hw.vpucp[i].cmd[0] =
569 cmdvpu(r300->radeon.radeonScreen,
570 R300_PVS_UCP_START + i, 1);
571 r300->hw.vpucp[i].emit = emit_vpu;
572 }
573 }
574 }
575
576 /* Textures */
577 ALLOC_STATE(tex.filter, variable, mtu + 1, 0);
578 r300->hw.tex.filter.cmd[R300_TEX_CMD_0] =
579 cmdpacket0(r300->radeon.radeonScreen, R300_TX_FILTER0_0, 0);
580
581 ALLOC_STATE(tex.filter_1, variable, mtu + 1, 0);
582 r300->hw.tex.filter_1.cmd[R300_TEX_CMD_0] =
583 cmdpacket0(r300->radeon.radeonScreen, R300_TX_FILTER1_0, 0);
584
585 ALLOC_STATE(tex.size, variable, mtu + 1, 0);
586 r300->hw.tex.size.cmd[R300_TEX_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_TX_SIZE_0, 0);
587
588 ALLOC_STATE(tex.format, variable, mtu + 1, 0);
589 r300->hw.tex.format.cmd[R300_TEX_CMD_0] =
590 cmdpacket0(r300->radeon.radeonScreen, R300_TX_FORMAT_0, 0);
591
592 ALLOC_STATE(tex.pitch, variable, mtu + 1, 0);
593 r300->hw.tex.pitch.cmd[R300_TEX_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_TX_FORMAT2_0, 0);
594
595 ALLOC_STATE(tex.offset, variable, 1, 0);
596 r300->hw.tex.offset.cmd[R300_TEX_CMD_0] =
597 cmdpacket0(r300->radeon.radeonScreen, R300_TX_OFFSET_0, 0);
598 r300->hw.tex.offset.emit = &emit_tex_offsets;
599
600 ALLOC_STATE(tex.chroma_key, variable, mtu + 1, 0);
601 r300->hw.tex.chroma_key.cmd[R300_TEX_CMD_0] =
602 cmdpacket0(r300->radeon.radeonScreen, R300_TX_CHROMA_KEY_0, 0);
603
604 ALLOC_STATE(tex.border_color, variable, mtu + 1, 0);
605 r300->hw.tex.border_color.cmd[R300_TEX_CMD_0] =
606 cmdpacket0(r300->radeon.radeonScreen, R300_TX_BORDER_COLOR_0, 0);
607
608 r300->radeon.hw.is_dirty = GL_TRUE;
609 r300->radeon.hw.all_dirty = GL_TRUE;
610
611 rcommonInitCmdBuf(&r300->radeon);
612 }
613
614 /**
615 * Destroy the command buffer and state atoms.
616 */
617 void r300DestroyCmdBuf(r300ContextPtr r300)
618 {
619 struct radeon_state_atom *atom;
620
621 foreach(atom, &r300->radeon.hw.atomlist) {
622 FREE(atom->cmd);
623 }
624
625 }