src/mesa/drivers/dri/r300/r300_cmdbuf.c

   1 /*
   2 Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
   3
   4 The Weather Channel (TM) funded Tungsten Graphics to develop the
   5 initial release of the Radeon 8500 driver under the XFree86 license.
   6 This notice must be preserved.
   7
   8 Permission is hereby granted, free of charge, to any person obtaining
   9 a copy of this software and associated documentation files (the
  10 "Software"), to deal in the Software without restriction, including
  11 without limitation the rights to use, copy, modify, merge, publish,
  12 distribute, sublicense, and/or sell copies of the Software, and to
  13 permit persons to whom the Software is furnished to do so, subject to
  14 the following conditions:
  15
  16 The above copyright notice and this permission notice (including the
  17 next paragraph) shall be included in all copies or substantial
  18 portions of the Software.
  19
  20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27
  28 **************************************************************************/
  29
  30 /**
  31  * \file
  32  *
  33  * \author Nicolai Haehnle <prefect_@gmx.net>
  34  */
  35
  36 #include "main/glheader.h"
  37 #include "main/state.h"
  38 #include "main/imports.h"
  39 #include "main/macros.h"
  40 #include "main/context.h"
  41 #include "main/simple_list.h"
  42 #include "swrast/swrast.h"
  43
  44 #include "drm.h"
  45 #include "radeon_drm.h"
  46
  47 #include "radeon_buffer.h"
  48 #include "radeon_ioctl.h"
  49 #include "r300_context.h"
  50 #include "r300_ioctl.h"
  51 #include "radeon_reg.h"
  52 #include "r300_reg.h"
  53 #include "r300_cmdbuf.h"
  54 #include "r300_emit.h"
  55 #include "r300_mipmap_tree.h"
  56 #include "r300_state.h"
  57 #include "radeon_cs_legacy.h"
  58 #include "radeon_cs_gem.h"
  59 #include "radeon_reg.h"
  60
  61 #define R300_VAP_PVS_UPLOAD_ADDRESS 0x2200
  62 #   define RADEON_ONE_REG_WR        (1 << 15)
  63
  64 // Set this to 1 for extremely verbose debugging of command buffers
  65 #define DEBUG_CMDBUF            0
  66
  67 /** # of dwords reserved for additional instructions that may need to be written
  68  * during flushing.
  69  */
  70 #define SPACE_FOR_FLUSHING      4
  71
  72 /**
  73  * Send the current command buffer via ioctl to the hardware.
  74  */
  75 int r300FlushCmdBufLocked(r300ContextPtr r300, const char *caller)
  76 {
  77         int ret = 0;
  78
  79         if (r300->cmdbuf.flushing) {
  80                 fprintf(stderr, "Recursive call into r300FlushCmdBufLocked!\n");
  81                 exit(-1);
  82         }
  83         r300->cmdbuf.flushing = 1;
  84     if (r300->cmdbuf.cs->cdw) {
  85         ret = radeon_cs_emit(r300->cmdbuf.cs);
  86         r300->hw.all_dirty = 1;
  87     }
  88     radeon_cs_erase(r300->cmdbuf.cs);
  89         r300->cmdbuf.flushing = 0;
  90         return ret;
  91 }
  92
  93 int r300FlushCmdBuf(r300ContextPtr r300, const char *caller)
  94 {
  95         int ret;
  96
  97         LOCK_HARDWARE(&r300->radeon);
  98         ret = r300FlushCmdBufLocked(r300, caller);
  99         UNLOCK_HARDWARE(&r300->radeon);
 100
 101         if (ret) {
 102                 fprintf(stderr, "drmRadeonCmdBuffer: %d\n", ret);
 103                 _mesa_exit(ret);
 104         }
 105
 106         return ret;
 107 }
 108
 109 /**
 110  * Make sure that enough space is available in the command buffer
 111  * by flushing if necessary.
 112  *
 113  * \param dwords The number of dwords we need to be free on the command buffer
 114  */
 115 void r300EnsureCmdBufSpace(r300ContextPtr r300, int dwords, const char *caller)
 116 {
 117         if ((r300->cmdbuf.cs->cdw + dwords + 128) > r300->cmdbuf.size ||
 118         radeon_cs_need_flush(r300->cmdbuf.cs)) {
 119                 r300FlushCmdBuf(r300, caller);
 120     }
 121 }
 122
 123 void r300BeginBatch(r300ContextPtr r300, int n,
 124                     int dostate,
 125                     const char *file,
 126                     const char *function,
 127                     int line)
 128 {
 129         r300EnsureCmdBufSpace(r300, n, function);
 130         if (!r300->cmdbuf.cs->cdw && dostate) {
 131                 if (RADEON_DEBUG & DEBUG_IOCTL)
 132                         fprintf(stderr, "Reemit state after flush (from %s)\n", function);
 133                 r300EmitState(r300);
 134         }
 135     radeon_cs_begin(r300->cmdbuf.cs, n, file, function, line);
 136 }
 137
 138 static void r300PrintStateAtom(r300ContextPtr r300,
 139                                struct radeon_state_atom *state)
 140 {
 141         int i;
 142         int dwords = (*state->check) (r300->radeon.glCtx, state);
 143
 144         fprintf(stderr, "  emit %s %d/%d\n", state->name, dwords, state->cmd_size);
 145
 146         if (RADEON_DEBUG & DEBUG_VERBOSE) {
 147                 for (i = 0; i < dwords; i++) {
 148                         fprintf(stderr, "      %s[%d]: %08x\n",
 149                                 state->name, i, state->cmd[i]);
 150                 }
 151         }
 152 }
 153
 154 /**
 155  * Emit all atoms with a dirty field equal to dirty.
 156  *
 157  * The caller must have ensured that there is enough space in the command
 158  * buffer.
 159  */
 160 static INLINE void r300EmitAtoms(r300ContextPtr r300, GLboolean dirty)
 161 {
 162         BATCH_LOCALS(r300);
 163         struct radeon_state_atom *atom;
 164         int dwords;
 165
 166     cp_wait(r300, R300_WAIT_3D | R300_WAIT_3D_CLEAN);
 167         BEGIN_BATCH_NO_AUTOSTATE(2);
 168         OUT_BATCH(cmdpacket0(r300->radeon.radeonScreen, R300_TX_INVALTAGS, 1));
 169         OUT_BATCH(R300_TX_FLUSH);
 170         END_BATCH();
 171     end_3d(r300);
 172
 173         /* Emit actual atoms */
 174         foreach(atom, &r300->hw.atomlist) {
 175                 if ((atom->dirty || r300->hw.all_dirty) == dirty) {
 176                         dwords = (*atom->check) (r300->radeon.glCtx, atom);
 177                         if (dwords) {
 178                                 if (DEBUG_CMDBUF && RADEON_DEBUG & DEBUG_STATE) {
 179                                         r300PrintStateAtom(r300, atom);
 180                                 }
 181                                 if (atom->emit) {
 182                                         (*atom->emit)(r300->radeon.glCtx, atom);
 183                                 } else {
 184                                         BEGIN_BATCH_NO_AUTOSTATE(dwords);
 185                                         OUT_BATCH_TABLE(atom->cmd, dwords);
 186                                         END_BATCH();
 187                                 }
 188                                 atom->dirty = GL_FALSE;
 189                         } else {
 190                                 if (DEBUG_CMDBUF && RADEON_DEBUG & DEBUG_STATE) {
 191                                         fprintf(stderr, "  skip state %s\n",
 192                                                 atom->name);
 193                                 }
 194                         }
 195                 }
 196         }
 197
 198         COMMIT_BATCH();
 199 }
 200
 201 /**
 202  * Copy dirty hardware state atoms into the command buffer.
 203  *
 204  * We also copy out clean state if we're at the start of a buffer. That makes
 205  * it easy to recover from lost contexts.
 206  */
 207 void r300EmitState(r300ContextPtr r300)
 208 {
 209         if (RADEON_DEBUG & (DEBUG_STATE | DEBUG_PRIMS))
 210                 fprintf(stderr, "%s\n", __FUNCTION__);
 211
 212         if (r300->cmdbuf.cs->cdw && !r300->hw.is_dirty && !r300->hw.all_dirty)
 213                 return;
 214
 215         /* To avoid going across the entire set of states multiple times, just check
 216          * for enough space for the case of emitting all state.
 217          */
 218         r300EnsureCmdBufSpace(r300, r300->hw.max_state_size, __FUNCTION__);
 219
 220         if (!r300->cmdbuf.cs->cdw) {
 221                 if (RADEON_DEBUG & DEBUG_STATE)
 222                         fprintf(stderr, "Begin reemit state\n");
 223
 224                 r300EmitAtoms(r300, GL_FALSE);
 225         }
 226
 227         if (RADEON_DEBUG & DEBUG_STATE)
 228                 fprintf(stderr, "Begin dirty state\n");
 229
 230         r300EmitAtoms(r300, GL_TRUE);
 231         r300->hw.is_dirty = GL_FALSE;
 232         r300->hw.all_dirty = GL_FALSE;
 233 }
 234
 235 static unsigned packet0_count(r300ContextPtr r300, uint32_t *pkt)
 236 {
 237     if (r300->radeon.radeonScreen->kernel_mm) {
 238         return ((((*pkt) >> 16) & 0x3FFF) + 1);
 239     } else {
 240         drm_r300_cmd_header_t *t = (drm_r300_cmd_header_t*)pkt;
 241         return t->packet0.count;
 242     }
 243     return 0;
 244 }
 245
 246 #define vpu_count(ptr) (((drm_r300_cmd_header_t*)(ptr))->vpu.count)
 247 #define r500fp_count(ptr) (((drm_r300_cmd_header_t*)(ptr))->r500fp.count)
 248
 249 void emit_vpu(GLcontext *ctx, struct radeon_state_atom * atom)
 250 {
 251         r300ContextPtr r300 = R300_CONTEXT(ctx);
 252         BATCH_LOCALS(r300);
 253         drm_r300_cmd_header_t cmd;
 254     uint32_t addr, ndw, i;
 255
 256     if (!r300->radeon.radeonScreen->kernel_mm) {
 257         uint32_t dwords;
 258         dwords = (*atom->check) (ctx, atom);
 259         BEGIN_BATCH_NO_AUTOSTATE(dwords);
 260         OUT_BATCH_TABLE(atom->cmd, dwords);
 261         END_BATCH();
 262         return;
 263     }
 264
 265     cmd.u = atom->cmd[0];
 266     addr = (cmd.vpu.adrhi << 8) | cmd.vpu.adrlo;
 267         ndw = cmd.vpu.count * 4;
 268     if (ndw) {
 269         /* flush processing vertices */
 270         OUT_BATCH(CP_PACKET0(R300_SC_SCREENDOOR, 0));
 271         OUT_BATCH(0x0);
 272         OUT_BATCH(CP_PACKET0(RADEON_WAIT_UNTIL, 0));
 273         OUT_BATCH((1 << 15) | (1 << 28));
 274         OUT_BATCH(CP_PACKET0(R300_SC_SCREENDOOR, 0));
 275         OUT_BATCH(0x00FFFFFF);
 276         OUT_BATCH(CP_PACKET0(R300_VAP_PVS_STATE_FLUSH_REG, 0));
 277         OUT_BATCH(1);
 278         /* write vpu */
 279         OUT_BATCH(CP_PACKET0(R300_VAP_PVS_UPLOAD_ADDRESS, 0));
 280         OUT_BATCH(addr);
 281         OUT_BATCH(CP_PACKET0(R300_VAP_PVS_UPLOAD_DATA, ndw-1) | RADEON_ONE_REG_WR);
 282         for (i = 0; i < ndw; i++) {
 283             OUT_BATCH(atom->cmd[i+1]);
 284         }
 285     }
 286 }
 287
 288 void emit_r500fp(GLcontext *ctx, struct radeon_state_atom * atom)
 289 {
 290         r300ContextPtr r300 = R300_CONTEXT(ctx);
 291         BATCH_LOCALS(r300);
 292         drm_r300_cmd_header_t cmd;
 293         uint32_t addr, ndw, i, sz;
 294         int type, clamp, stride;
 295
 296         if (!r300->radeon.radeonScreen->kernel_mm) {
 297                 uint32_t dwords;
 298                 dwords = (*atom->check) (ctx, atom);
 299                 BEGIN_BATCH_NO_AUTOSTATE(dwords);
 300                 OUT_BATCH_TABLE(atom->cmd, dwords);
 301                 END_BATCH();
 302                 return;
 303         }
 304
 305         cmd.u = atom->cmd[0];
 306         sz = cmd.r500fp.count;
 307         addr = ((cmd.r500fp.adrhi_flags & 1) << 8) | cmd.r500fp.adrlo;
 308         type = !!(cmd.r500fp.adrhi_flags & R500FP_CONSTANT_TYPE);
 309         clamp = !!(cmd.r500fp.adrhi_flags & R500FP_CONSTANT_CLAMP);
 310
 311         addr |= (type << 16);
 312         addr |= (clamp << 17);
 313
 314         stride = type ? 4 : 6;
 315
 316         ndw = sz * stride;
 317         if (ndw) {
 318
 319                 OUT_BATCH(CP_PACKET0(R500_GA_US_VECTOR_INDEX, 0));
 320                 OUT_BATCH(addr);
 321                 OUT_BATCH(CP_PACKET0(R500_GA_US_VECTOR_DATA, ndw-1) | RADEON_ONE_REG_WR);
 322                 for (i = 0; i < ndw; i++) {
 323                         OUT_BATCH(atom->cmd[i+1]);
 324                 }
 325         }
 326 }
 327
 328 static void emit_tex_offsets(GLcontext *ctx, struct radeon_state_atom * atom)
 329 {
 330         r300ContextPtr r300 = R300_CONTEXT(ctx);
 331         BATCH_LOCALS(r300);
 332         int numtmus = packet0_count(r300, r300->hw.tex.offset.cmd);
 333
 334         if (numtmus) {
 335                 int i;
 336
 337                 for(i = 0; i < numtmus; ++i) {
 338                     BEGIN_BATCH(2);
 339                 OUT_BATCH_REGSEQ(R300_TX_OFFSET_0 + (i * 4), 1);
 340                         r300TexObj *t = r300->hw.textures[i];
 341                         if (t && !t->image_override) {
 342                                 OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, 0,
 343                                 RADEON_GEM_DOMAIN_VRAM, 0, 0);
 344                         } else if (!t) {
 345                                 OUT_BATCH(r300->radeon.radeonScreen->texOffset[0]);
 346                         } else {
 347                                 if (t->bo) {
 348                                         OUT_BATCH_RELOC(t->tile_bits, t->bo, 0,
 349                                                         RADEON_GEM_DOMAIN_VRAM, 0, 0);
 350                                 } else {
 351                                         OUT_BATCH(t->override_offset);
 352                                 }
 353                         }
 354                         END_BATCH();
 355                 }
 356         }
 357 }
 358
 359 static void emit_cb_offset(GLcontext *ctx, struct radeon_state_atom * atom)
 360 {
 361         r300ContextPtr r300 = R300_CONTEXT(ctx);
 362         BATCH_LOCALS(r300);
 363         struct radeon_renderbuffer *rrb;
 364         uint32_t cbpitch;
 365         GLframebuffer *fb = r300->radeon.dri.drawable->driverPrivate;
 366
 367         rrb = r300->radeon.state.color.rrb;
 368         if (r300->radeon.radeonScreen->driScreen->dri2.enabled) {
 369                 rrb = (struct radeon_renderbuffer *)fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer;
 370         }
 371         if (!rrb || !rrb->bo) {
 372                 fprintf(stderr, "no rrb\n");
 373                 return;
 374         }
 375
 376         cbpitch = (rrb->pitch / rrb->cpp);
 377         if (rrb->cpp == 4)
 378                 cbpitch |= R300_COLOR_FORMAT_ARGB8888;
 379         else
 380                 cbpitch |= R300_COLOR_FORMAT_RGB565;
 381
 382         if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE)
 383                 cbpitch |= R300_COLOR_TILE_ENABLE;
 384
 385         BEGIN_BATCH(4);
 386         OUT_BATCH_REGSEQ(R300_RB3D_COLOROFFSET0, 1);
 387         OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
 388         OUT_BATCH_REGSEQ(R300_RB3D_COLORPITCH0, 1);
 389         OUT_BATCH(cbpitch);
 390         END_BATCH();
 391 }
 392
 393 static void emit_zb_offset(GLcontext *ctx, struct radeon_state_atom * atom)
 394 {
 395         r300ContextPtr r300 = R300_CONTEXT(ctx);
 396         BATCH_LOCALS(r300);
 397         struct radeon_renderbuffer *rrb;
 398         uint32_t zbpitch;
 399
 400         rrb = r300->radeon.state.depth.rrb;
 401         if (!rrb)
 402                 return;
 403
 404         zbpitch = (rrb->pitch / rrb->cpp);
 405         if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE) {
 406                 zbpitch |= R300_DEPTHMACROTILE_ENABLE;
 407         }
 408         if (rrb->bo->flags & RADEON_BO_FLAGS_MICRO_TILE){
 409                 zbpitch |= R300_DEPTHMICROTILE_TILED;
 410         }
 411
 412         BEGIN_BATCH(4);
 413         OUT_BATCH_REGSEQ(R300_ZB_DEPTHOFFSET, 1);
 414         OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
 415         OUT_BATCH_REGVAL(R300_ZB_DEPTHPITCH, zbpitch);
 416         END_BATCH();
 417 }
 418
 419 static int check_always(GLcontext *ctx, struct radeon_state_atom *atom)
 420 {
 421         return atom->cmd_size;
 422 }
 423
 424 static int check_variable(GLcontext *ctx, struct radeon_state_atom *atom)
 425 {
 426         r300ContextPtr r300 = R300_CONTEXT(ctx);
 427         int cnt;
 428         if (atom->cmd[0] == CP_PACKET2) {
 429                 return 0;
 430         }
 431         cnt = packet0_count(r300, atom->cmd);
 432         return cnt ? cnt + 1 : 0;
 433 }
 434
 435 int check_vpu(GLcontext *ctx, struct radeon_state_atom *atom)
 436 {
 437         int cnt;
 438
 439         cnt = vpu_count(atom->cmd);
 440         return cnt ? (cnt * 4) + 1 : 0;
 441 }
 442
 443 int check_r500fp(GLcontext *ctx, struct radeon_state_atom *atom)
 444 {
 445         int cnt;
 446
 447         cnt = r500fp_count(atom->cmd);
 448         return cnt ? (cnt * 6) + 1 : 0;
 449 }
 450
 451 int check_r500fp_const(GLcontext *ctx, struct radeon_state_atom *atom)
 452 {
 453         int cnt;
 454
 455         cnt = r500fp_count(atom->cmd);
 456         return cnt ? (cnt * 4) + 1 : 0;
 457 }
 458
 459 #define ALLOC_STATE( ATOM, CHK, SZ, IDX )                               \
 460    do {                                                                 \
 461       r300->hw.ATOM.cmd_size = (SZ);                                    \
 462       r300->hw.ATOM.cmd = (uint32_t*)CALLOC((SZ) * sizeof(uint32_t));   \
 463       r300->hw.ATOM.name = #ATOM;                                       \
 464       r300->hw.ATOM.idx = (IDX);                                        \
 465       r300->hw.ATOM.check = check_##CHK;                                \
 466       r300->hw.ATOM.dirty = GL_FALSE;                                   \
 467       r300->hw.max_state_size += (SZ);                                  \
 468       insert_at_tail(&r300->hw.atomlist, &r300->hw.ATOM);               \
 469    } while (0)
 470 /**
 471  * Allocate memory for the command buffer and initialize the state atom
 472  * list. Note that the initial hardware state is set by r300InitState().
 473  */
 474 void r300InitCmdBuf(r300ContextPtr r300)
 475 {
 476         int size, mtu;
 477         int has_tcl = 1;
 478         int is_r500 = 0;
 479         int i;
 480
 481         if (!(r300->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL))
 482                 has_tcl = 0;
 483
 484         if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515)
 485                 is_r500 = 1;
 486
 487         r300->hw.max_state_size = 2 + 2;        /* reserve extra space for WAIT_IDLE and tex cache flush */
 488
 489         mtu = r300->radeon.glCtx->Const.MaxTextureUnits;
 490         if (RADEON_DEBUG & DEBUG_TEXTURE) {
 491                 fprintf(stderr, "Using %d maximum texture units..\n", mtu);
 492         }
 493
 494         /* Setup the atom linked list */
 495         make_empty_list(&r300->hw.atomlist);
 496         r300->hw.atomlist.name = "atom-list";
 497
 498         /* Initialize state atoms */
 499         ALLOC_STATE(vpt, always, R300_VPT_CMDSIZE, 0);
 500         r300->hw.vpt.cmd[R300_VPT_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_SE_VPORT_XSCALE, 6);
 501         ALLOC_STATE(vap_cntl, always, R300_VAP_CNTL_SIZE, 0);
 502         r300->hw.vap_cntl.cmd[R300_VAP_CNTL_FLUSH] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PVS_STATE_FLUSH_REG, 1);
 503         r300->hw.vap_cntl.cmd[R300_VAP_CNTL_FLUSH_1] = 0;
 504         r300->hw.vap_cntl.cmd[R300_VAP_CNTL_CMD] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_CNTL, 1);
 505         if (is_r500) {
 506             ALLOC_STATE(vap_index_offset, always, 2, 0);
 507             r300->hw.vap_index_offset.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R500_VAP_INDEX_OFFSET, 1);
 508             r300->hw.vap_index_offset.cmd[1] = 0;
 509         }
 510         ALLOC_STATE(vte, always, 3, 0);
 511         r300->hw.vte.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SE_VTE_CNTL, 2);
 512         ALLOC_STATE(vap_vf_max_vtx_indx, always, 3, 0);
 513         r300->hw.vap_vf_max_vtx_indx.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_VF_MAX_VTX_INDX, 2);
 514         ALLOC_STATE(vap_cntl_status, always, 2, 0);
 515         r300->hw.vap_cntl_status.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_CNTL_STATUS, 1);
 516         ALLOC_STATE(vir[0], variable, R300_VIR_CMDSIZE, 0);
 517         r300->hw.vir[0].cmd[R300_VIR_CMD_0] =
 518             cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PROG_STREAM_CNTL_0, 1);
 519         ALLOC_STATE(vir[1], variable, R300_VIR_CMDSIZE, 1);
 520         r300->hw.vir[1].cmd[R300_VIR_CMD_0] =
 521             cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PROG_STREAM_CNTL_EXT_0, 1);
 522         ALLOC_STATE(vic, always, R300_VIC_CMDSIZE, 0);
 523         r300->hw.vic.cmd[R300_VIC_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_VTX_STATE_CNTL, 2);
 524         ALLOC_STATE(vap_psc_sgn_norm_cntl, always, 2, 0);
 525         r300->hw.vap_psc_sgn_norm_cntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PSC_SGN_NORM_CNTL, SGN_NORM_ZERO_CLAMP_MINUS_ONE);
 526
 527         if (has_tcl) {
 528                 ALLOC_STATE(vap_clip_cntl, always, 2, 0);
 529                 r300->hw.vap_clip_cntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_CLIP_CNTL, 1);
 530                 ALLOC_STATE(vap_clip, always, 5, 0);
 531                 r300->hw.vap_clip.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_GB_VERT_CLIP_ADJ, 4);
 532                 ALLOC_STATE(vap_pvs_vtx_timeout_reg, always, 2, 0);
 533                 r300->hw.vap_pvs_vtx_timeout_reg.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, VAP_PVS_VTX_TIMEOUT_REG, 1);
 534         }
 535
 536         ALLOC_STATE(vof, always, R300_VOF_CMDSIZE, 0);
 537         r300->hw.vof.cmd[R300_VOF_CMD_0] =
 538             cmdpacket0(r300->radeon.radeonScreen, R300_VAP_OUTPUT_VTX_FMT_0, 2);
 539
 540         if (has_tcl) {
 541                 ALLOC_STATE(pvs, always, R300_PVS_CMDSIZE, 0);
 542                 r300->hw.pvs.cmd[R300_PVS_CMD_0] =
 543                     cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PVS_CODE_CNTL_0, 3);
 544         }
 545
 546         ALLOC_STATE(gb_enable, always, 2, 0);
 547         r300->hw.gb_enable.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GB_ENABLE, 1);
 548         ALLOC_STATE(gb_misc, always, R300_GB_MISC_CMDSIZE, 0);
 549         r300->hw.gb_misc.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GB_MSPOS0, 5);
 550         ALLOC_STATE(txe, always, R300_TXE_CMDSIZE, 0);
 551         r300->hw.txe.cmd[R300_TXE_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_TX_ENABLE, 1);
 552         ALLOC_STATE(ga_point_s0, always, 5, 0);
 553         r300->hw.ga_point_s0.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_POINT_S0, 4);
 554         ALLOC_STATE(ga_triangle_stipple, always, 2, 0);
 555         r300->hw.ga_triangle_stipple.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_TRIANGLE_STIPPLE, 1);
 556         ALLOC_STATE(ps, always, R300_PS_CMDSIZE, 0);
 557         r300->hw.ps.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_POINT_SIZE, 1);
 558         ALLOC_STATE(ga_point_minmax, always, 4, 0);
 559         r300->hw.ga_point_minmax.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_POINT_MINMAX, 3);
 560         ALLOC_STATE(lcntl, always, 2, 0);
 561         r300->hw.lcntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_LINE_CNTL, 1);
 562         ALLOC_STATE(ga_line_stipple, always, 4, 0);
 563         r300->hw.ga_line_stipple.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_LINE_STIPPLE_VALUE, 3);
 564         ALLOC_STATE(shade, always, 5, 0);
 565         r300->hw.shade.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_ENHANCE, 4);
 566         ALLOC_STATE(polygon_mode, always, 4, 0);
 567         r300->hw.polygon_mode.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_POLY_MODE, 3);
 568         ALLOC_STATE(fogp, always, 3, 0);
 569         r300->hw.fogp.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_FOG_SCALE, 2);
 570         ALLOC_STATE(zbias_cntl, always, 2, 0);
 571         r300->hw.zbias_cntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SU_TEX_WRAP, 1);
 572         ALLOC_STATE(zbs, always, R300_ZBS_CMDSIZE, 0);
 573         r300->hw.zbs.cmd[R300_ZBS_CMD_0] =
 574             cmdpacket0(r300->radeon.radeonScreen, R300_SU_POLY_OFFSET_FRONT_SCALE, 4);
 575         ALLOC_STATE(occlusion_cntl, always, 2, 0);
 576         r300->hw.occlusion_cntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SU_POLY_OFFSET_ENABLE, 1);
 577         ALLOC_STATE(cul, always, R300_CUL_CMDSIZE, 0);
 578         r300->hw.cul.cmd[R300_CUL_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_SU_CULL_MODE, 1);
 579         ALLOC_STATE(su_depth_scale, always, 3, 0);
 580         r300->hw.su_depth_scale.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SU_DEPTH_SCALE, 2);
 581         ALLOC_STATE(rc, always, R300_RC_CMDSIZE, 0);
 582         r300->hw.rc.cmd[R300_RC_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RS_COUNT, 2);
 583         if (is_r500) {
 584                 ALLOC_STATE(ri, always, R500_RI_CMDSIZE, 0);
 585                 r300->hw.ri.cmd[R300_RI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R500_RS_IP_0, 16);
 586                 for (i = 0; i < 8; i++) {
 587                         r300->hw.ri.cmd[R300_RI_CMD_0 + i +1] =
 588                           (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_S_SHIFT) |
 589                           (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_T_SHIFT) |
 590                           (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT) |
 591                           (R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT);
 592                 }
 593                 ALLOC_STATE(rr, variable, R300_RR_CMDSIZE, 0);
 594                 r300->hw.rr.cmd[R300_RR_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R500_RS_INST_0, 1);
 595         } else {
 596                 ALLOC_STATE(ri, always, R300_RI_CMDSIZE, 0);
 597                 r300->hw.ri.cmd[R300_RI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RS_IP_0, 8);
 598                 ALLOC_STATE(rr, variable, R300_RR_CMDSIZE, 0);
 599                 r300->hw.rr.cmd[R300_RR_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RS_INST_0, 1);
 600         }
 601         ALLOC_STATE(sc_hyperz, always, 3, 0);
 602         r300->hw.sc_hyperz.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SC_HYPERZ, 2);
 603         ALLOC_STATE(sc_screendoor, always, 2, 0);
 604         r300->hw.sc_screendoor.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SC_SCREENDOOR, 1);
 605         ALLOC_STATE(us_out_fmt, always, 6, 0);
 606         r300->hw.us_out_fmt.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_OUT_FMT, 5);
 607
 608         if (is_r500) {
 609                 ALLOC_STATE(fp, always, R500_FP_CMDSIZE, 0);
 610                 r300->hw.fp.cmd[R500_FP_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R500_US_CONFIG, 2);
 611                 r300->hw.fp.cmd[R500_FP_CNTL] = R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO;
 612                 r300->hw.fp.cmd[R500_FP_CMD_1] = cmdpacket0(r300->radeon.radeonScreen, R500_US_CODE_ADDR, 3);
 613                 r300->hw.fp.cmd[R500_FP_CMD_2] = cmdpacket0(r300->radeon.radeonScreen, R500_US_FC_CTRL, 1);
 614                 r300->hw.fp.cmd[R500_FP_FC_CNTL] = 0; /* FIXME when we add flow control */
 615
 616                 ALLOC_STATE(r500fp, r500fp, R500_FPI_CMDSIZE, 0);
 617                 r300->hw.r500fp.cmd[R300_FPI_CMD_0] =
 618                         cmdr500fp(r300->radeon.radeonScreen, 0, 0, 0, 0);
 619                 r300->hw.r500fp.emit = emit_r500fp;
 620                 ALLOC_STATE(r500fp_const, r500fp_const, R500_FPP_CMDSIZE, 0);
 621                 r300->hw.r500fp_const.cmd[R300_FPI_CMD_0] =
 622                         cmdr500fp(r300->radeon.radeonScreen, 0, 0, 1, 0);
 623                 r300->hw.r500fp_const.emit = emit_r500fp;
 624         } else {
 625                 ALLOC_STATE(fp, always, R300_FP_CMDSIZE, 0);
 626                 r300->hw.fp.cmd[R300_FP_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_CONFIG, 3);
 627                 r300->hw.fp.cmd[R300_FP_CMD_1] = cmdpacket0(r300->radeon.radeonScreen, R300_US_CODE_ADDR_0, 4);
 628
 629                 ALLOC_STATE(fpt, variable, R300_FPT_CMDSIZE, 0);
 630                 r300->hw.fpt.cmd[R300_FPT_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_TEX_INST_0, 0);
 631
 632                 ALLOC_STATE(fpi[0], variable, R300_FPI_CMDSIZE, 0);
 633                 r300->hw.fpi[0].cmd[R300_FPI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_ALU_RGB_INST_0, 1);
 634                 ALLOC_STATE(fpi[1], variable, R300_FPI_CMDSIZE, 1);
 635                 r300->hw.fpi[1].cmd[R300_FPI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_ALU_RGB_ADDR_0, 1);
 636                 ALLOC_STATE(fpi[2], variable, R300_FPI_CMDSIZE, 2);
 637                 r300->hw.fpi[2].cmd[R300_FPI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_ALU_ALPHA_INST_0, 1);
 638                 ALLOC_STATE(fpi[3], variable, R300_FPI_CMDSIZE, 3);
 639                 r300->hw.fpi[3].cmd[R300_FPI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_ALU_ALPHA_ADDR_0, 1);
 640                 ALLOC_STATE(fpp, variable, R300_FPP_CMDSIZE, 0);
 641                 r300->hw.fpp.cmd[R300_FPP_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_PFS_PARAM_0_X, 0);
 642         }
 643         ALLOC_STATE(fogs, always, R300_FOGS_CMDSIZE, 0);
 644         r300->hw.fogs.cmd[R300_FOGS_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_FG_FOG_BLEND, 1);
 645         ALLOC_STATE(fogc, always, R300_FOGC_CMDSIZE, 0);
 646         r300->hw.fogc.cmd[R300_FOGC_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_FG_FOG_COLOR_R, 3);
 647         ALLOC_STATE(at, always, R300_AT_CMDSIZE, 0);
 648         r300->hw.at.cmd[R300_AT_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_FG_ALPHA_FUNC, 2);
 649         ALLOC_STATE(fg_depth_src, always, 2, 0);
 650         r300->hw.fg_depth_src.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_FG_DEPTH_SRC, 1);
 651         ALLOC_STATE(rb3d_cctl, always, 2, 0);
 652         r300->hw.rb3d_cctl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_CCTL, 1);
 653         ALLOC_STATE(bld, always, R300_BLD_CMDSIZE, 0);
 654         r300->hw.bld.cmd[R300_BLD_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_CBLEND, 2);
 655         ALLOC_STATE(cmk, always, R300_CMK_CMDSIZE, 0);
 656         r300->hw.cmk.cmd[R300_CMK_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, RB3D_COLOR_CHANNEL_MASK, 1);
 657         if (is_r500) {
 658                 ALLOC_STATE(blend_color, always, 3, 0);
 659                 r300->hw.blend_color.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R500_RB3D_CONSTANT_COLOR_AR, 2);
 660         } else {
 661                 ALLOC_STATE(blend_color, always, 2, 0);
 662                 r300->hw.blend_color.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_BLEND_COLOR, 1);
 663         }
 664         ALLOC_STATE(rop, always, 2, 0);
 665         r300->hw.rop.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_ROPCNTL, 1);
 666         ALLOC_STATE(cb, always, R300_CB_CMDSIZE, 0);
 667         r300->hw.cb.emit = &emit_cb_offset;
 668         ALLOC_STATE(rb3d_dither_ctl, always, 10, 0);
 669         r300->hw.rb3d_dither_ctl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_DITHER_CTL, 9);
 670         ALLOC_STATE(rb3d_aaresolve_ctl, always, 2, 0);
 671         r300->hw.rb3d_aaresolve_ctl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_AARESOLVE_CTL, 1);
 672         ALLOC_STATE(rb3d_discard_src_pixel_lte_threshold, always, 3, 0);
 673         r300->hw.rb3d_discard_src_pixel_lte_threshold.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R500_RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD, 2);
 674         ALLOC_STATE(zs, always, R300_ZS_CMDSIZE, 0);
 675         r300->hw.zs.cmd[R300_ZS_CMD_0] =
 676             cmdpacket0(r300->radeon.radeonScreen, R300_ZB_CNTL, 3);
 677         ALLOC_STATE(zstencil_format, always, 5, 0);
 678         r300->hw.zstencil_format.cmd[0] =
 679             cmdpacket0(r300->radeon.radeonScreen, R300_ZB_FORMAT, 4);
 680         ALLOC_STATE(zb, always, R300_ZB_CMDSIZE, 0);
 681         r300->hw.zb.emit = emit_zb_offset;
 682         ALLOC_STATE(zb_depthclearvalue, always, 2, 0);
 683         r300->hw.zb_depthclearvalue.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_ZB_DEPTHCLEARVALUE, 1);
 684         ALLOC_STATE(unk4F30, always, 3, 0);
 685         r300->hw.unk4F30.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, 0x4F30, 2);
 686         ALLOC_STATE(zb_hiz_offset, always, 2, 0);
 687         r300->hw.zb_hiz_offset.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_ZB_HIZ_OFFSET, 1);
 688         ALLOC_STATE(zb_hiz_pitch, always, 2, 0);
 689         r300->hw.zb_hiz_pitch.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_ZB_HIZ_PITCH, 1);
 690
 691         /* VPU only on TCL */
 692         if (has_tcl) {
 693                 int i;
 694                 ALLOC_STATE(vpi, vpu, R300_VPI_CMDSIZE, 0);
 695                 r300->hw.vpi.cmd[0] =
 696                     cmdvpu(r300->radeon.radeonScreen, R300_PVS_CODE_START, 0);
 697                 r300->hw.vpi.emit = emit_vpu;
 698
 699                 if (is_r500) {
 700                     ALLOC_STATE(vpp, vpu, R300_VPP_CMDSIZE, 0);
 701                     r300->hw.vpp.cmd[0] =
 702                         cmdvpu(r300->radeon.radeonScreen, R500_PVS_CONST_START, 0);
 703                     r300->hw.vpp.emit = emit_vpu;
 704
 705                     ALLOC_STATE(vps, vpu, R300_VPS_CMDSIZE, 0);
 706                     r300->hw.vps.cmd[0] =
 707                         cmdvpu(r300->radeon.radeonScreen, R500_POINT_VPORT_SCALE_OFFSET, 1);
 708                     r300->hw.vps.emit = emit_vpu;
 709
 710                         for (i = 0; i < 6; i++) {
 711                           ALLOC_STATE(vpucp[i], vpu, R300_VPUCP_CMDSIZE, 0);
 712                           r300->hw.vpucp[i].cmd[0] =
 713                                   cmdvpu(r300->radeon.radeonScreen,
 714                            R500_PVS_UCP_START + i, 1);
 715                                 r300->hw.vpucp[i].emit = emit_vpu;
 716                         }
 717                 } else {
 718                     ALLOC_STATE(vpp, vpu, R300_VPP_CMDSIZE, 0);
 719                     r300->hw.vpp.cmd[0] =
 720                         cmdvpu(r300->radeon.radeonScreen, R300_PVS_CONST_START, 0);
 721                     r300->hw.vpp.emit = emit_vpu;
 722
 723                     ALLOC_STATE(vps, vpu, R300_VPS_CMDSIZE, 0);
 724                     r300->hw.vps.cmd[0] =
 725                         cmdvpu(r300->radeon.radeonScreen, R300_POINT_VPORT_SCALE_OFFSET, 1);
 726                     r300->hw.vps.emit = emit_vpu;
 727
 728                         for (i = 0; i < 6; i++) {
 729                                 ALLOC_STATE(vpucp[i], vpu, R300_VPUCP_CMDSIZE, 0);
 730                                 r300->hw.vpucp[i].cmd[0] =
 731                                         cmdvpu(r300->radeon.radeonScreen,
 732                                                R300_PVS_UCP_START + i, 1);
 733                                 r300->hw.vpucp[i].emit = emit_vpu;
 734                         }
 735                 }
 736         }
 737
 738         /* Textures */
 739         ALLOC_STATE(tex.filter, variable, mtu + 1, 0);
 740         r300->hw.tex.filter.cmd[R300_TEX_CMD_0] =
 741             cmdpacket0(r300->radeon.radeonScreen, R300_TX_FILTER0_0, 0);
 742
 743         ALLOC_STATE(tex.filter_1, variable, mtu + 1, 0);
 744         r300->hw.tex.filter_1.cmd[R300_TEX_CMD_0] =
 745             cmdpacket0(r300->radeon.radeonScreen, R300_TX_FILTER1_0, 0);
 746
 747         ALLOC_STATE(tex.size, variable, mtu + 1, 0);
 748         r300->hw.tex.size.cmd[R300_TEX_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_TX_SIZE_0, 0);
 749
 750         ALLOC_STATE(tex.format, variable, mtu + 1, 0);
 751         r300->hw.tex.format.cmd[R300_TEX_CMD_0] =
 752             cmdpacket0(r300->radeon.radeonScreen, R300_TX_FORMAT_0, 0);
 753
 754         ALLOC_STATE(tex.pitch, variable, mtu + 1, 0);
 755         r300->hw.tex.pitch.cmd[R300_TEX_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_TX_FORMAT2_0, 0);
 756
 757         ALLOC_STATE(tex.offset, variable, 1, 0);
 758         r300->hw.tex.offset.cmd[R300_TEX_CMD_0] =
 759             cmdpacket0(r300->radeon.radeonScreen, R300_TX_OFFSET_0, 0);
 760         r300->hw.tex.offset.emit = &emit_tex_offsets;
 761
 762         ALLOC_STATE(tex.chroma_key, variable, mtu + 1, 0);
 763         r300->hw.tex.chroma_key.cmd[R300_TEX_CMD_0] =
 764             cmdpacket0(r300->radeon.radeonScreen, R300_TX_CHROMA_KEY_0, 0);
 765
 766         ALLOC_STATE(tex.border_color, variable, mtu + 1, 0);
 767         r300->hw.tex.border_color.cmd[R300_TEX_CMD_0] =
 768             cmdpacket0(r300->radeon.radeonScreen, R300_TX_BORDER_COLOR_0, 0);
 769
 770         r300->hw.is_dirty = GL_TRUE;
 771         r300->hw.all_dirty = GL_TRUE;
 772
 773         /* Initialize command buffer */
 774         size =
 775             256 * driQueryOptioni(&r300->radeon.optionCache,
 776                                   "command_buffer_size");
 777         if (size < 2 * r300->hw.max_state_size) {
 778                 size = 2 * r300->hw.max_state_size + 65535;
 779         }
 780         if (size > 64 * 256)
 781                 size = 64 * 256;
 782
 783         size = 64 * 1024 / 4;
 784         if (RADEON_DEBUG & (DEBUG_IOCTL | DEBUG_DMA)) {
 785                 fprintf(stderr, "sizeof(drm_r300_cmd_header_t)=%zd\n",
 786                         sizeof(drm_r300_cmd_header_t));
 787                 fprintf(stderr, "sizeof(drm_radeon_cmd_buffer_t)=%zd\n",
 788                         sizeof(drm_radeon_cmd_buffer_t));
 789                 fprintf(stderr,
 790                         "Allocating %d bytes command buffer (max state is %d bytes)\n",
 791                         size * 4, r300->hw.max_state_size * 4);
 792         }
 793
 794     if (r300->radeon.radeonScreen->kernel_mm) {
 795         int fd = r300->radeon.radeonScreen->driScreen->fd;
 796         r300->cmdbuf.csm = radeon_cs_manager_gem_ctor(fd);
 797     } else {
 798         r300->cmdbuf.csm = radeon_cs_manager_legacy_ctor(&r300->radeon);
 799     }
 800     if (r300->cmdbuf.csm == NULL) {
 801         /* FIXME: fatal error */
 802         return;
 803     }
 804     r300->cmdbuf.cs = radeon_cs_create(r300->cmdbuf.csm, size);
 805     assert(r300->cmdbuf.cs != NULL);
 806         r300->cmdbuf.size = size;
 807 }
 808
 809 /**
 810  * Destroy the command buffer and state atoms.
 811  */
 812 void r300DestroyCmdBuf(r300ContextPtr r300)
 813 {
 814         struct radeon_state_atom *atom;
 815
 816     radeon_cs_destroy(r300->cmdbuf.cs);
 817         foreach(atom, &r300->hw.atomlist) {
 818                 FREE(atom->cmd);
 819         }
 820     if (r300->radeon.radeonScreen->driScreen->dri2.enabled || r300->radeon.radeonScreen->kernel_mm) {
 821         radeon_cs_manager_gem_dtor(r300->cmdbuf.csm);
 822     } else {
 823         radeon_cs_manager_legacy_dtor(r300->cmdbuf.csm);
 824     }
 825 }