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r300: Clean emit code.
[mesa.git] / src / mesa / drivers / dri / r300 / r300_cmdbuf.c
1 /*
2 Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
3
4 The Weather Channel (TM) funded Tungsten Graphics to develop the
5 initial release of the Radeon 8500 driver under the XFree86 license.
6 This notice must be preserved.
7
8 Permission is hereby granted, free of charge, to any person obtaining
9 a copy of this software and associated documentation files (the
10 "Software"), to deal in the Software without restriction, including
11 without limitation the rights to use, copy, modify, merge, publish,
12 distribute, sublicense, and/or sell copies of the Software, and to
13 permit persons to whom the Software is furnished to do so, subject to
14 the following conditions:
15
16 The above copyright notice and this permission notice (including the
17 next paragraph) shall be included in all copies or substantial
18 portions of the Software.
19
20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27
28 **************************************************************************/
29
30 /**
31 * \file
32 *
33 * \author Nicolai Haehnle <prefect_@gmx.net>
34 */
35
36 #include "main/glheader.h"
37 #include "main/state.h"
38 #include "main/imports.h"
39 #include "main/macros.h"
40 #include "main/context.h"
41 #include "main/simple_list.h"
42 #include "swrast/swrast.h"
43
44 #include "drm.h"
45 #include "radeon_drm.h"
46
47 #include "r300_context.h"
48 #include "r300_ioctl.h"
49 #include "radeon_reg.h"
50 #include "r300_reg.h"
51 #include "r300_cmdbuf.h"
52 #include "r300_emit.h"
53 #include "radeon_bocs_wrapper.h"
54 #include "radeon_mipmap_tree.h"
55 #include "r300_state.h"
56 #include "radeon_reg.h"
57 #include "radeon_queryobj.h"
58
59 /** # of dwords reserved for additional instructions that may need to be written
60 * during flushing.
61 */
62 #define SPACE_FOR_FLUSHING 4
63
64 static unsigned packet0_count(r300ContextPtr r300, uint32_t *pkt)
65 {
66 if (r300->radeon.radeonScreen->kernel_mm) {
67 return ((((*pkt) >> 16) & 0x3FFF) + 1);
68 } else {
69 drm_r300_cmd_header_t *t = (drm_r300_cmd_header_t*)pkt;
70 return t->packet0.count;
71 }
72 }
73
74 #define vpu_count(ptr) (((drm_r300_cmd_header_t*)(ptr))->vpu.count)
75 #define r500fp_count(ptr) (((drm_r300_cmd_header_t*)(ptr))->r500fp.count)
76
77 int check_vpu(GLcontext *ctx, struct radeon_state_atom *atom)
78 {
79 r300ContextPtr r300 = R300_CONTEXT(ctx);
80 int cnt;
81 int extra = 1;
82 cnt = vpu_count(atom->cmd);
83
84 if (r300->radeon.radeonScreen->kernel_mm) {
85 extra = 5;
86 }
87
88 return cnt ? (cnt * 4) + extra : 0;
89 }
90
91
92 void emit_vpu(GLcontext *ctx, struct radeon_state_atom * atom)
93 {
94 r300ContextPtr r300 = R300_CONTEXT(ctx);
95 BATCH_LOCALS(&r300->radeon);
96 drm_r300_cmd_header_t cmd;
97 uint32_t addr, ndw;
98
99 cmd.u = atom->cmd[0];
100 addr = (cmd.vpu.adrhi << 8) | cmd.vpu.adrlo;
101 ndw = atom->check(ctx, atom);
102
103 BEGIN_BATCH_NO_AUTOSTATE(ndw);
104
105 ndw -= 5;
106 OUT_BATCH_REGVAL(R300_VAP_PVS_VECTOR_INDX_REG, addr);
107 OUT_BATCH(CP_PACKET0(R300_VAP_PVS_UPLOAD_DATA, ndw-1) | RADEON_ONE_REG_WR);
108 OUT_BATCH_TABLE(atom->cmd + 1, ndw);
109 OUT_BATCH_REGVAL(R300_VAP_PVS_STATE_FLUSH_REG, 0);
110 END_BATCH();
111 }
112
113 void emit_r500fp(GLcontext *ctx, struct radeon_state_atom * atom)
114 {
115 r300ContextPtr r300 = R300_CONTEXT(ctx);
116 BATCH_LOCALS(&r300->radeon);
117 drm_r300_cmd_header_t cmd;
118 uint32_t addr, ndw, sz;
119 int type, clamp;
120
121 ndw = atom->check(ctx, atom);
122
123 cmd.u = atom->cmd[0];
124 sz = cmd.r500fp.count;
125 addr = ((cmd.r500fp.adrhi_flags & 1) << 8) | cmd.r500fp.adrlo;
126 type = !!(cmd.r500fp.adrhi_flags & R500FP_CONSTANT_TYPE);
127 clamp = !!(cmd.r500fp.adrhi_flags & R500FP_CONSTANT_CLAMP);
128
129 addr |= (type << 16);
130 addr |= (clamp << 17);
131
132 BEGIN_BATCH_NO_AUTOSTATE(ndw);
133 OUT_BATCH(CP_PACKET0(R500_GA_US_VECTOR_INDEX, 0));
134 OUT_BATCH(addr);
135 ndw-=3;
136 OUT_BATCH(CP_PACKET0(R500_GA_US_VECTOR_DATA, ndw-1) | RADEON_ONE_REG_WR);
137 OUT_BATCH_TABLE(atom->cmd + 1, ndw);
138 END_BATCH();
139 }
140
141 static int check_tex_offsets(GLcontext *ctx, struct radeon_state_atom * atom)
142 {
143 r300ContextPtr r300 = R300_CONTEXT(ctx);
144 int numtmus = packet0_count(r300, r300->hw.tex.offset.cmd);
145 int dw = 0, i;
146 if (atom->cmd[0] == CP_PACKET2) {
147 return dw;
148 }
149 for(i = 0; i < numtmus; ++i) {
150 radeonTexObj *t = r300->hw.textures[i];
151 if (!t && !r300->radeon.radeonScreen->kernel_mm) {
152 dw += 0;
153 } else if (t && t->image_override && !t->bo) {
154 if (!r300->radeon.radeonScreen->kernel_mm)
155 dw += 2;
156 } else
157 dw += 4;
158 }
159 return dw;
160 }
161
162 static void emit_tex_offsets(GLcontext *ctx, struct radeon_state_atom * atom)
163 {
164 r300ContextPtr r300 = R300_CONTEXT(ctx);
165 BATCH_LOCALS(&r300->radeon);
166 int numtmus = packet0_count(r300, r300->hw.tex.offset.cmd);
167 int i;
168
169 for(i = 0; i < numtmus; ++i) {
170 radeonTexObj *t = r300->hw.textures[i];
171 if (t && !t->image_override) {
172 BEGIN_BATCH_NO_AUTOSTATE(4);
173 OUT_BATCH_REGSEQ(R300_TX_OFFSET_0 + (i * 4), 1);
174 OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, 0,
175 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
176 END_BATCH();
177 } else if (!t) {
178 /* Texture unit hasn't a texture bound.
179 * We assign the current color buffer as a fakery to make
180 * KIL work on KMS (without it, the CS checker will complain).
181 */
182 if (r300->radeon.radeonScreen->kernel_mm) {
183 struct radeon_renderbuffer *rrb = radeon_get_colorbuffer(&r300->radeon);
184 if (rrb && rrb->bo) {
185 BEGIN_BATCH_NO_AUTOSTATE(4);
186 OUT_BATCH_REGSEQ(R300_TX_OFFSET_0 + (i * 4), 1);
187 OUT_BATCH_RELOC(0, rrb->bo, 0,
188 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
189 END_BATCH();
190 }
191 }
192 } else { /* override cases */
193 if (t->bo) {
194 BEGIN_BATCH_NO_AUTOSTATE(4);
195 OUT_BATCH_REGSEQ(R300_TX_OFFSET_0 + (i * 4), 1);
196 OUT_BATCH_RELOC(t->tile_bits, t->bo, 0,
197 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
198 END_BATCH();
199 } else if (!r300->radeon.radeonScreen->kernel_mm) {
200 BEGIN_BATCH_NO_AUTOSTATE(2);
201 OUT_BATCH_REGSEQ(R300_TX_OFFSET_0 + (i * 4), 1);
202 OUT_BATCH(t->override_offset);
203 END_BATCH();
204 } else {
205 /* Texture unit hasn't a texture bound nothings to do */
206 }
207 }
208 }
209 }
210
211 void r300_emit_scissor(GLcontext *ctx)
212 {
213 r300ContextPtr r300 = R300_CONTEXT(ctx);
214 BATCH_LOCALS(&r300->radeon);
215 unsigned x1, y1, x2, y2;
216 struct radeon_renderbuffer *rrb;
217
218 if (!r300->radeon.radeonScreen->driScreen->dri2.enabled) {
219 return;
220 }
221 rrb = radeon_get_colorbuffer(&r300->radeon);
222 if (!rrb || !rrb->bo) {
223 fprintf(stderr, "no rrb\n");
224 return;
225 }
226 if (r300->radeon.state.scissor.enabled) {
227 x1 = r300->radeon.state.scissor.rect.x1;
228 y1 = r300->radeon.state.scissor.rect.y1;
229 x2 = r300->radeon.state.scissor.rect.x2 - 1;
230 y2 = r300->radeon.state.scissor.rect.y2 - 1;
231 } else {
232 x1 = 0;
233 y1 = 0;
234 x2 = rrb->base.Width - 1;
235 y2 = rrb->base.Height - 1;
236 }
237 if (r300->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV515) {
238 x1 += R300_SCISSORS_OFFSET;
239 y1 += R300_SCISSORS_OFFSET;
240 x2 += R300_SCISSORS_OFFSET;
241 y2 += R300_SCISSORS_OFFSET;
242 }
243 BEGIN_BATCH_NO_AUTOSTATE(3);
244 OUT_BATCH_REGSEQ(R300_SC_SCISSORS_TL, 2);
245 OUT_BATCH((x1 << R300_SCISSORS_X_SHIFT)|(y1 << R300_SCISSORS_Y_SHIFT));
246 OUT_BATCH((x2 << R300_SCISSORS_X_SHIFT)|(y2 << R300_SCISSORS_Y_SHIFT));
247 END_BATCH();
248 }
249 static int check_cb_offset(GLcontext *ctx, struct radeon_state_atom * atom)
250 {
251 r300ContextPtr r300 = R300_CONTEXT(ctx);
252 uint32_t dw = 6 + 3 + 16;
253 if (r300->radeon.radeonScreen->kernel_mm)
254 dw += 2;
255 return dw;
256 }
257
258 static void emit_cb_offset(GLcontext *ctx, struct radeon_state_atom * atom)
259 {
260 r300ContextPtr r300 = R300_CONTEXT(ctx);
261 BATCH_LOCALS(&r300->radeon);
262 struct radeon_renderbuffer *rrb;
263 uint32_t cbpitch;
264 uint32_t offset = r300->radeon.state.color.draw_offset;
265 uint32_t dw = 6;
266 int i;
267
268 rrb = radeon_get_colorbuffer(&r300->radeon);
269 if (!rrb || !rrb->bo) {
270 fprintf(stderr, "no rrb\n");
271 return;
272 }
273
274 if (RADEON_DEBUG & DEBUG_STATE)
275 fprintf(stderr,"rrb is %p %d %dx%d\n", rrb, offset, rrb->base.Width, rrb->base.Height);
276 cbpitch = (rrb->pitch / rrb->cpp);
277 if (rrb->cpp == 4)
278 cbpitch |= R300_COLOR_FORMAT_ARGB8888;
279 else switch (rrb->base._ActualFormat) {
280 case GL_RGB5:
281 cbpitch |= R300_COLOR_FORMAT_RGB565;
282 break;
283 case GL_RGBA4:
284 cbpitch |= R300_COLOR_FORMAT_ARGB4444;
285 break;
286 case GL_RGB5_A1:
287 cbpitch |= R300_COLOR_FORMAT_ARGB1555;
288 break;
289 }
290
291 if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE)
292 cbpitch |= R300_COLOR_TILE_ENABLE;
293
294 if (r300->radeon.radeonScreen->kernel_mm)
295 dw += 2;
296 BEGIN_BATCH_NO_AUTOSTATE(dw);
297 OUT_BATCH_REGSEQ(R300_RB3D_COLOROFFSET0, 1);
298 OUT_BATCH_RELOC(offset, rrb->bo, offset, 0, RADEON_GEM_DOMAIN_VRAM, 0);
299 OUT_BATCH_REGSEQ(R300_RB3D_COLORPITCH0, 1);
300 if (!r300->radeon.radeonScreen->kernel_mm)
301 OUT_BATCH(cbpitch);
302 else
303 OUT_BATCH_RELOC(cbpitch, rrb->bo, cbpitch, 0, RADEON_GEM_DOMAIN_VRAM, 0);
304 END_BATCH();
305 if (r300->radeon.radeonScreen->driScreen->dri2.enabled) {
306 if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) {
307 BEGIN_BATCH_NO_AUTOSTATE(3);
308 OUT_BATCH_REGSEQ(R300_SC_SCISSORS_TL, 2);
309 OUT_BATCH(0);
310 OUT_BATCH(((rrb->base.Width - 1) << R300_SCISSORS_X_SHIFT) |
311 ((rrb->base.Height - 1) << R300_SCISSORS_Y_SHIFT));
312 END_BATCH();
313 BEGIN_BATCH_NO_AUTOSTATE(16);
314 for (i = 0; i < 4; i++) {
315 OUT_BATCH_REGSEQ(R300_SC_CLIPRECT_TL_0 + (i * 8), 2);
316 OUT_BATCH((0 << R300_CLIPRECT_X_SHIFT) | (0 << R300_CLIPRECT_Y_SHIFT));
317 OUT_BATCH(((rrb->base.Width - 1) << R300_CLIPRECT_X_SHIFT) | ((rrb->base.Height - 1) << R300_CLIPRECT_Y_SHIFT));
318 }
319 OUT_BATCH_REGSEQ(R300_SC_CLIP_RULE, 1);
320 OUT_BATCH(0xAAAA);
321 OUT_BATCH_REGSEQ(R300_SC_SCREENDOOR, 1);
322 OUT_BATCH(0xffffff);
323 END_BATCH();
324 } else {
325 BEGIN_BATCH_NO_AUTOSTATE(3);
326 OUT_BATCH_REGSEQ(R300_SC_SCISSORS_TL, 2);
327 OUT_BATCH((R300_SCISSORS_OFFSET << R300_SCISSORS_X_SHIFT) |
328 (R300_SCISSORS_OFFSET << R300_SCISSORS_Y_SHIFT));
329 OUT_BATCH(((rrb->base.Width + R300_SCISSORS_OFFSET - 1) << R300_SCISSORS_X_SHIFT) |
330 ((rrb->base.Height + R300_SCISSORS_OFFSET - 1) << R300_SCISSORS_Y_SHIFT));
331 END_BATCH();
332 BEGIN_BATCH_NO_AUTOSTATE(16);
333 for (i = 0; i < 4; i++) {
334 OUT_BATCH_REGSEQ(R300_SC_CLIPRECT_TL_0 + (i * 8), 2);
335 OUT_BATCH((R300_SCISSORS_OFFSET << R300_CLIPRECT_X_SHIFT) | (R300_SCISSORS_OFFSET << R300_CLIPRECT_Y_SHIFT));
336 OUT_BATCH(((R300_SCISSORS_OFFSET + rrb->base.Width - 1) << R300_CLIPRECT_X_SHIFT) |
337 ((R300_SCISSORS_OFFSET + rrb->base.Height - 1) << R300_CLIPRECT_Y_SHIFT));
338 }
339 OUT_BATCH_REGSEQ(R300_SC_CLIP_RULE, 1);
340 OUT_BATCH(0xAAAA);
341 OUT_BATCH_REGSEQ(R300_SC_SCREENDOOR, 1);
342 OUT_BATCH(0xffffff);
343 END_BATCH();
344 }
345 }
346 }
347
348 static int check_zb_offset(GLcontext *ctx, struct radeon_state_atom * atom)
349 {
350 r300ContextPtr r300 = R300_CONTEXT(ctx);
351 uint32_t dw;
352 dw = 6;
353 if (r300->radeon.radeonScreen->kernel_mm)
354 dw += 2;
355 return dw;
356 }
357
358 static void emit_zb_offset(GLcontext *ctx, struct radeon_state_atom * atom)
359 {
360 r300ContextPtr r300 = R300_CONTEXT(ctx);
361 BATCH_LOCALS(&r300->radeon);
362 struct radeon_renderbuffer *rrb;
363 uint32_t zbpitch;
364 uint32_t dw = atom->check(ctx, atom);
365
366 rrb = radeon_get_depthbuffer(&r300->radeon);
367 if (!rrb)
368 return;
369
370 zbpitch = (rrb->pitch / rrb->cpp);
371 if (!r300->radeon.radeonScreen->kernel_mm) {
372 if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE) {
373 zbpitch |= R300_DEPTHMACROTILE_ENABLE;
374 }
375 if (rrb->bo->flags & RADEON_BO_FLAGS_MICRO_TILE){
376 zbpitch |= R300_DEPTHMICROTILE_TILED;
377 }
378 }
379
380 BEGIN_BATCH_NO_AUTOSTATE(dw);
381 OUT_BATCH_REGSEQ(R300_ZB_DEPTHOFFSET, 1);
382 OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
383 OUT_BATCH_REGSEQ(R300_ZB_DEPTHPITCH, 1);
384 if (!r300->radeon.radeonScreen->kernel_mm)
385 OUT_BATCH(zbpitch);
386 else
387 OUT_BATCH_RELOC(cbpitch, rrb->bo, zbpitch, 0, RADEON_GEM_DOMAIN_VRAM, 0);
388 END_BATCH();
389 }
390
391 static void emit_zstencil_format(GLcontext *ctx, struct radeon_state_atom * atom)
392 {
393 r300ContextPtr r300 = R300_CONTEXT(ctx);
394 BATCH_LOCALS(&r300->radeon);
395 struct radeon_renderbuffer *rrb;
396 uint32_t format = 0;
397
398 rrb = radeon_get_depthbuffer(&r300->radeon);
399 if (!rrb)
400 format = 0;
401 else {
402 if (rrb->cpp == 2)
403 format = R300_DEPTHFORMAT_16BIT_INT_Z;
404 else if (rrb->cpp == 4)
405 format = R300_DEPTHFORMAT_24BIT_INT_Z_8BIT_STENCIL;
406 }
407
408 BEGIN_BATCH_NO_AUTOSTATE(atom->cmd_size);
409 OUT_BATCH(atom->cmd[0]);
410 atom->cmd[1] &= ~0xf;
411 atom->cmd[1] |= format;
412 OUT_BATCH(atom->cmd[1]);
413 OUT_BATCH(atom->cmd[2]);
414 OUT_BATCH(atom->cmd[3]);
415 OUT_BATCH(atom->cmd[4]);
416 END_BATCH();
417 }
418
419 static int check_never(GLcontext *ctx, struct radeon_state_atom *atom)
420 {
421 return 0;
422 }
423
424 static int check_always(GLcontext *ctx, struct radeon_state_atom *atom)
425 {
426 return atom->cmd_size;
427 }
428
429 static int check_variable(GLcontext *ctx, struct radeon_state_atom *atom)
430 {
431 r300ContextPtr r300 = R300_CONTEXT(ctx);
432 int cnt;
433 if (atom->cmd[0] == CP_PACKET2) {
434 return 0;
435 }
436 cnt = packet0_count(r300, atom->cmd);
437 return cnt ? cnt + 1 : 0;
438 }
439
440 int check_r500fp(GLcontext *ctx, struct radeon_state_atom *atom)
441 {
442 int cnt;
443 r300ContextPtr r300 = R300_CONTEXT(ctx);
444 int extra = 1;
445 cnt = r500fp_count(atom->cmd);
446 if (r300->radeon.radeonScreen->kernel_mm)
447 extra = 3;
448
449 return cnt ? (cnt * 6) + extra : 0;
450 }
451
452 int check_r500fp_const(GLcontext *ctx, struct radeon_state_atom *atom)
453 {
454 int cnt;
455 r300ContextPtr r300 = R300_CONTEXT(ctx);
456 int extra = 1;
457 cnt = r500fp_count(atom->cmd);
458 if (r300->radeon.radeonScreen->kernel_mm)
459 extra = 3;
460
461 cnt = r500fp_count(atom->cmd);
462 return cnt ? (cnt * 4) + extra : 0;
463 }
464
465 #define ALLOC_STATE( ATOM, CHK, SZ, IDX ) \
466 do { \
467 r300->hw.ATOM.cmd_size = (SZ); \
468 r300->hw.ATOM.cmd = (uint32_t*)CALLOC((SZ) * sizeof(uint32_t)); \
469 r300->hw.ATOM.name = #ATOM; \
470 r300->hw.ATOM.idx = (IDX); \
471 r300->hw.ATOM.check = check_##CHK; \
472 r300->hw.ATOM.dirty = GL_FALSE; \
473 r300->radeon.hw.max_state_size += (SZ); \
474 insert_at_tail(&r300->radeon.hw.atomlist, &r300->hw.ATOM); \
475 } while (0)
476 /**
477 * Allocate memory for the command buffer and initialize the state atom
478 * list. Note that the initial hardware state is set by r300InitState().
479 */
480 void r300InitCmdBuf(r300ContextPtr r300)
481 {
482 int mtu;
483 int has_tcl;
484 int is_r500 = 0;
485
486 has_tcl = r300->options.hw_tcl_enabled;
487
488 if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515)
489 is_r500 = 1;
490
491 r300->radeon.hw.max_state_size = 2 + 2; /* reserve extra space for WAIT_IDLE and tex cache flush */
492
493 mtu = r300->radeon.glCtx->Const.MaxTextureUnits;
494 if (RADEON_DEBUG & DEBUG_TEXTURE) {
495 fprintf(stderr, "Using %d maximum texture units..\n", mtu);
496 }
497
498 /* Setup the atom linked list */
499 make_empty_list(&r300->radeon.hw.atomlist);
500 r300->radeon.hw.atomlist.name = "atom-list";
501
502 /* Initialize state atoms */
503 ALLOC_STATE(vpt, always, R300_VPT_CMDSIZE, 0);
504 r300->hw.vpt.cmd[R300_VPT_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_SE_VPORT_XSCALE, 6);
505 ALLOC_STATE(vap_cntl, always, R300_VAP_CNTL_SIZE, 0);
506 r300->hw.vap_cntl.cmd[R300_VAP_CNTL_FLUSH] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PVS_STATE_FLUSH_REG, 1);
507 r300->hw.vap_cntl.cmd[R300_VAP_CNTL_FLUSH_1] = 0;
508 r300->hw.vap_cntl.cmd[R300_VAP_CNTL_CMD] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_CNTL, 1);
509 if (is_r500 && !r300->radeon.radeonScreen->kernel_mm) {
510 ALLOC_STATE(vap_index_offset, always, 2, 0);
511 r300->hw.vap_index_offset.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R500_VAP_INDEX_OFFSET, 1);
512 r300->hw.vap_index_offset.cmd[1] = 0;
513 }
514 ALLOC_STATE(vte, always, 3, 0);
515 r300->hw.vte.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SE_VTE_CNTL, 2);
516 ALLOC_STATE(vap_vf_max_vtx_indx, always, 3, 0);
517 r300->hw.vap_vf_max_vtx_indx.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_VF_MAX_VTX_INDX, 2);
518 ALLOC_STATE(vap_cntl_status, always, 2, 0);
519 r300->hw.vap_cntl_status.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_CNTL_STATUS, 1);
520 ALLOC_STATE(vir[0], variable, R300_VIR_CMDSIZE, 0);
521 r300->hw.vir[0].cmd[R300_VIR_CMD_0] =
522 cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PROG_STREAM_CNTL_0, 1);
523 ALLOC_STATE(vir[1], variable, R300_VIR_CMDSIZE, 1);
524 r300->hw.vir[1].cmd[R300_VIR_CMD_0] =
525 cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PROG_STREAM_CNTL_EXT_0, 1);
526 ALLOC_STATE(vic, always, R300_VIC_CMDSIZE, 0);
527 r300->hw.vic.cmd[R300_VIC_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_VTX_STATE_CNTL, 2);
528 ALLOC_STATE(vap_psc_sgn_norm_cntl, always, 2, 0);
529 r300->hw.vap_psc_sgn_norm_cntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PSC_SGN_NORM_CNTL, SGN_NORM_ZERO_CLAMP_MINUS_ONE);
530
531 if (has_tcl) {
532 ALLOC_STATE(vap_clip_cntl, always, 2, 0);
533 r300->hw.vap_clip_cntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_CLIP_CNTL, 1);
534 ALLOC_STATE(vap_clip, always, 5, 0);
535 r300->hw.vap_clip.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_GB_VERT_CLIP_ADJ, 4);
536 ALLOC_STATE(vap_pvs_vtx_timeout_reg, always, 2, 0);
537 r300->hw.vap_pvs_vtx_timeout_reg.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, VAP_PVS_VTX_TIMEOUT_REG, 1);
538 }
539
540 ALLOC_STATE(vof, always, R300_VOF_CMDSIZE, 0);
541 r300->hw.vof.cmd[R300_VOF_CMD_0] =
542 cmdpacket0(r300->radeon.radeonScreen, R300_VAP_OUTPUT_VTX_FMT_0, 2);
543
544 if (has_tcl) {
545 ALLOC_STATE(pvs, always, R300_PVS_CMDSIZE, 0);
546 r300->hw.pvs.cmd[R300_PVS_CMD_0] =
547 cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PVS_CODE_CNTL_0, 3);
548 }
549
550 ALLOC_STATE(gb_enable, always, 2, 0);
551 r300->hw.gb_enable.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GB_ENABLE, 1);
552 if (!r300->radeon.radeonScreen->driScreen->dri2.enabled) {
553 ALLOC_STATE(gb_misc, always, R300_GB_MISC_CMDSIZE, 0);
554 } else {
555 ALLOC_STATE(gb_misc, never, R300_GB_MISC_CMDSIZE, 0);
556 }
557 r300->hw.gb_misc.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GB_MSPOS0, 3);
558 ALLOC_STATE(gb_misc2, always, R300_GB_MISC2_CMDSIZE, 0);
559 r300->hw.gb_misc2.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, 0x401C, 2);
560 ALLOC_STATE(txe, always, R300_TXE_CMDSIZE, 0);
561 r300->hw.txe.cmd[R300_TXE_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_TX_ENABLE, 1);
562 ALLOC_STATE(ga_point_s0, always, 5, 0);
563 r300->hw.ga_point_s0.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_POINT_S0, 4);
564 ALLOC_STATE(ga_triangle_stipple, always, 2, 0);
565 r300->hw.ga_triangle_stipple.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_TRIANGLE_STIPPLE, 1);
566 ALLOC_STATE(ps, always, R300_PS_CMDSIZE, 0);
567 r300->hw.ps.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_POINT_SIZE, 1);
568 ALLOC_STATE(ga_point_minmax, always, 4, 0);
569 r300->hw.ga_point_minmax.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_POINT_MINMAX, 3);
570 ALLOC_STATE(lcntl, always, 2, 0);
571 r300->hw.lcntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_LINE_CNTL, 1);
572 ALLOC_STATE(ga_line_stipple, always, 4, 0);
573 r300->hw.ga_line_stipple.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_LINE_STIPPLE_VALUE, 3);
574 if (!r300->radeon.radeonScreen->driScreen->dri2.enabled) {
575 ALLOC_STATE(shade, always, 2, 0);
576 } else {
577 ALLOC_STATE(shade, never, 2, 0);
578 }
579 r300->hw.shade.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_ENHANCE, 1);
580 ALLOC_STATE(shade2, always, 4, 0);
581 r300->hw.shade2.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, 0x4278, 3);
582 ALLOC_STATE(polygon_mode, always, 4, 0);
583 r300->hw.polygon_mode.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_POLY_MODE, 3);
584 ALLOC_STATE(fogp, always, 3, 0);
585 r300->hw.fogp.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_FOG_SCALE, 2);
586 ALLOC_STATE(zbias_cntl, always, 2, 0);
587 r300->hw.zbias_cntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SU_TEX_WRAP, 1);
588 ALLOC_STATE(zbs, always, R300_ZBS_CMDSIZE, 0);
589 r300->hw.zbs.cmd[R300_ZBS_CMD_0] =
590 cmdpacket0(r300->radeon.radeonScreen, R300_SU_POLY_OFFSET_FRONT_SCALE, 4);
591 ALLOC_STATE(occlusion_cntl, always, 2, 0);
592 r300->hw.occlusion_cntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SU_POLY_OFFSET_ENABLE, 1);
593 ALLOC_STATE(cul, always, R300_CUL_CMDSIZE, 0);
594 r300->hw.cul.cmd[R300_CUL_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_SU_CULL_MODE, 1);
595 ALLOC_STATE(su_depth_scale, always, 3, 0);
596 r300->hw.su_depth_scale.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SU_DEPTH_SCALE, 2);
597 ALLOC_STATE(rc, always, R300_RC_CMDSIZE, 0);
598 r300->hw.rc.cmd[R300_RC_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RS_COUNT, 2);
599 if (is_r500) {
600 ALLOC_STATE(ri, variable, R500_RI_CMDSIZE, 0);
601 r300->hw.ri.cmd[R300_RI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R500_RS_IP_0, 16);
602 ALLOC_STATE(rr, variable, R300_RR_CMDSIZE, 0);
603 r300->hw.rr.cmd[R300_RR_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R500_RS_INST_0, 1);
604 } else {
605 ALLOC_STATE(ri, variable, R300_RI_CMDSIZE, 0);
606 r300->hw.ri.cmd[R300_RI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RS_IP_0, 8);
607 ALLOC_STATE(rr, variable, R300_RR_CMDSIZE, 0);
608 r300->hw.rr.cmd[R300_RR_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RS_INST_0, 1);
609 }
610 ALLOC_STATE(sc_hyperz, always, 3, 0);
611 r300->hw.sc_hyperz.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SC_HYPERZ, 2);
612 ALLOC_STATE(sc_screendoor, always, 2, 0);
613 r300->hw.sc_screendoor.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SC_SCREENDOOR, 1);
614 ALLOC_STATE(us_out_fmt, always, 6, 0);
615 r300->hw.us_out_fmt.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_OUT_FMT, 5);
616
617 if (is_r500) {
618 ALLOC_STATE(fp, always, R500_FP_CMDSIZE, 0);
619 r300->hw.fp.cmd[R500_FP_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R500_US_CONFIG, 2);
620 r300->hw.fp.cmd[R500_FP_CNTL] = R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO;
621 r300->hw.fp.cmd[R500_FP_CMD_1] = cmdpacket0(r300->radeon.radeonScreen, R500_US_CODE_ADDR, 3);
622 r300->hw.fp.cmd[R500_FP_CMD_2] = cmdpacket0(r300->radeon.radeonScreen, R500_US_FC_CTRL, 1);
623 r300->hw.fp.cmd[R500_FP_FC_CNTL] = 0; /* FIXME when we add flow control */
624
625 ALLOC_STATE(r500fp, r500fp, R500_FPI_CMDSIZE, 0);
626 r300->hw.r500fp.cmd[R300_FPI_CMD_0] =
627 cmdr500fp(r300->radeon.radeonScreen, 0, 0, 0, 0);
628 if (r300->radeon.radeonScreen->kernel_mm)
629 r300->hw.r500fp.emit = emit_r500fp;
630
631 ALLOC_STATE(r500fp_const, r500fp_const, R500_FPP_CMDSIZE, 0);
632 r300->hw.r500fp_const.cmd[R300_FPI_CMD_0] =
633 cmdr500fp(r300->radeon.radeonScreen, 0, 0, 1, 0);
634 if (r300->radeon.radeonScreen->kernel_mm)
635 r300->hw.r500fp_const.emit = emit_r500fp;
636 } else {
637 ALLOC_STATE(fp, always, R300_FP_CMDSIZE, 0);
638 r300->hw.fp.cmd[R300_FP_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_CONFIG, 3);
639 r300->hw.fp.cmd[R300_FP_CMD_1] = cmdpacket0(r300->radeon.radeonScreen, R300_US_CODE_ADDR_0, 4);
640
641 ALLOC_STATE(fpt, variable, R300_FPT_CMDSIZE, 0);
642 r300->hw.fpt.cmd[R300_FPT_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_TEX_INST_0, 0);
643
644 ALLOC_STATE(fpi[0], variable, R300_FPI_CMDSIZE, 0);
645 r300->hw.fpi[0].cmd[R300_FPI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_ALU_RGB_INST_0, 1);
646 ALLOC_STATE(fpi[1], variable, R300_FPI_CMDSIZE, 1);
647 r300->hw.fpi[1].cmd[R300_FPI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_ALU_RGB_ADDR_0, 1);
648 ALLOC_STATE(fpi[2], variable, R300_FPI_CMDSIZE, 2);
649 r300->hw.fpi[2].cmd[R300_FPI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_ALU_ALPHA_INST_0, 1);
650 ALLOC_STATE(fpi[3], variable, R300_FPI_CMDSIZE, 3);
651 r300->hw.fpi[3].cmd[R300_FPI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_ALU_ALPHA_ADDR_0, 1);
652 ALLOC_STATE(fpp, variable, R300_FPP_CMDSIZE, 0);
653 r300->hw.fpp.cmd[R300_FPP_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_PFS_PARAM_0_X, 0);
654 }
655 ALLOC_STATE(fogs, always, R300_FOGS_CMDSIZE, 0);
656 r300->hw.fogs.cmd[R300_FOGS_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_FG_FOG_BLEND, 1);
657 ALLOC_STATE(fogc, always, R300_FOGC_CMDSIZE, 0);
658 r300->hw.fogc.cmd[R300_FOGC_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_FG_FOG_COLOR_R, 3);
659 ALLOC_STATE(at, always, R300_AT_CMDSIZE, 0);
660 r300->hw.at.cmd[R300_AT_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_FG_ALPHA_FUNC, 2);
661 ALLOC_STATE(fg_depth_src, always, 2, 0);
662 r300->hw.fg_depth_src.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_FG_DEPTH_SRC, 1);
663 ALLOC_STATE(rb3d_cctl, always, 2, 0);
664 r300->hw.rb3d_cctl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_CCTL, 1);
665 ALLOC_STATE(bld, always, R300_BLD_CMDSIZE, 0);
666 r300->hw.bld.cmd[R300_BLD_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_CBLEND, 2);
667 ALLOC_STATE(cmk, always, R300_CMK_CMDSIZE, 0);
668 r300->hw.cmk.cmd[R300_CMK_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, RB3D_COLOR_CHANNEL_MASK, 1);
669 if (is_r500) {
670 ALLOC_STATE(blend_color, always, 3, 0);
671 r300->hw.blend_color.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R500_RB3D_CONSTANT_COLOR_AR, 2);
672 } else {
673 ALLOC_STATE(blend_color, always, 2, 0);
674 r300->hw.blend_color.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_BLEND_COLOR, 1);
675 }
676 ALLOC_STATE(rop, always, 2, 0);
677 r300->hw.rop.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_ROPCNTL, 1);
678 ALLOC_STATE(cb, cb_offset, R300_CB_CMDSIZE, 0);
679 r300->hw.cb.emit = &emit_cb_offset;
680 ALLOC_STATE(rb3d_dither_ctl, always, 10, 0);
681 r300->hw.rb3d_dither_ctl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_DITHER_CTL, 9);
682 ALLOC_STATE(rb3d_aaresolve_ctl, always, 2, 0);
683 r300->hw.rb3d_aaresolve_ctl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_AARESOLVE_CTL, 1);
684 if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) {
685 ALLOC_STATE(rb3d_discard_src_pixel_lte_threshold, always, 3, 0);
686 } else {
687 ALLOC_STATE(rb3d_discard_src_pixel_lte_threshold, never, 3, 0);
688 }
689 r300->hw.rb3d_discard_src_pixel_lte_threshold.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R500_RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD, 2);
690 ALLOC_STATE(zs, always, R300_ZS_CMDSIZE, 0);
691 r300->hw.zs.cmd[R300_ZS_CMD_0] =
692 cmdpacket0(r300->radeon.radeonScreen, R300_ZB_CNTL, 3);
693
694 ALLOC_STATE(zstencil_format, always, 5, 0);
695 r300->hw.zstencil_format.cmd[0] =
696 cmdpacket0(r300->radeon.radeonScreen, R300_ZB_FORMAT, 4);
697 r300->hw.zstencil_format.emit = emit_zstencil_format;
698
699 ALLOC_STATE(zb, zb_offset, R300_ZB_CMDSIZE, 0);
700 r300->hw.zb.emit = emit_zb_offset;
701 ALLOC_STATE(zb_depthclearvalue, always, 2, 0);
702 r300->hw.zb_depthclearvalue.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_ZB_DEPTHCLEARVALUE, 1);
703 ALLOC_STATE(zb_zmask, always, 3, 0);
704 r300->hw.zb_zmask.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_ZB_ZMASK_OFFSET, 2);
705 ALLOC_STATE(zb_hiz_offset, always, 2, 0);
706 r300->hw.zb_hiz_offset.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_ZB_HIZ_OFFSET, 1);
707 ALLOC_STATE(zb_hiz_pitch, always, 2, 0);
708 r300->hw.zb_hiz_pitch.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_ZB_HIZ_PITCH, 1);
709
710 /* VPU only on TCL */
711 if (has_tcl) {
712 int i;
713 ALLOC_STATE(vap_flush, always, 10, 0);
714 /* flush processing vertices */
715 r300->hw.vap_flush.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SC_SCREENDOOR, 1);
716 r300->hw.vap_flush.cmd[1] = 0;
717 r300->hw.vap_flush.cmd[2] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_DSTCACHE_CTLSTAT, 1);
718 r300->hw.vap_flush.cmd[3] = R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D;
719 r300->hw.vap_flush.cmd[4] = cmdpacket0(r300->radeon.radeonScreen, RADEON_WAIT_UNTIL, 1);
720 r300->hw.vap_flush.cmd[5] = RADEON_WAIT_3D_IDLECLEAN;
721 r300->hw.vap_flush.cmd[6] = cmdpacket0(r300->radeon.radeonScreen, R300_SC_SCREENDOOR, 1);
722 r300->hw.vap_flush.cmd[7] = 0xffffff;
723 r300->hw.vap_flush.cmd[8] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PVS_STATE_FLUSH_REG, 1);
724 r300->hw.vap_flush.cmd[9] = 0;
725
726
727 ALLOC_STATE(vpi, vpu, R300_VPI_CMDSIZE, 0);
728 r300->hw.vpi.cmd[0] =
729 cmdvpu(r300->radeon.radeonScreen, R300_PVS_CODE_START, 0);
730 if (r300->radeon.radeonScreen->kernel_mm)
731 r300->hw.vpi.emit = emit_vpu;
732
733 if (is_r500) {
734 ALLOC_STATE(vpp, vpu, R300_VPP_CMDSIZE, 0);
735 r300->hw.vpp.cmd[0] =
736 cmdvpu(r300->radeon.radeonScreen, R500_PVS_CONST_START, 0);
737 if (r300->radeon.radeonScreen->kernel_mm)
738 r300->hw.vpp.emit = emit_vpu;
739
740 ALLOC_STATE(vps, vpu, R300_VPS_CMDSIZE, 0);
741 r300->hw.vps.cmd[0] =
742 cmdvpu(r300->radeon.radeonScreen, R500_POINT_VPORT_SCALE_OFFSET, 1);
743 if (r300->radeon.radeonScreen->kernel_mm)
744 r300->hw.vps.emit = emit_vpu;
745
746 for (i = 0; i < 6; i++) {
747 ALLOC_STATE(vpucp[i], vpu, R300_VPUCP_CMDSIZE, 0);
748 r300->hw.vpucp[i].cmd[0] =
749 cmdvpu(r300->radeon.radeonScreen,
750 R500_PVS_UCP_START + i, 1);
751 if (r300->radeon.radeonScreen->kernel_mm)
752 r300->hw.vpucp[i].emit = emit_vpu;
753 }
754 } else {
755 ALLOC_STATE(vpp, vpu, R300_VPP_CMDSIZE, 0);
756 r300->hw.vpp.cmd[0] =
757 cmdvpu(r300->radeon.radeonScreen, R300_PVS_CONST_START, 0);
758 if (r300->radeon.radeonScreen->kernel_mm)
759 r300->hw.vpp.emit = emit_vpu;
760
761 ALLOC_STATE(vps, vpu, R300_VPS_CMDSIZE, 0);
762 r300->hw.vps.cmd[0] =
763 cmdvpu(r300->radeon.radeonScreen, R300_POINT_VPORT_SCALE_OFFSET, 1);
764 if (r300->radeon.radeonScreen->kernel_mm)
765 r300->hw.vps.emit = emit_vpu;
766
767 for (i = 0; i < 6; i++) {
768 ALLOC_STATE(vpucp[i], vpu, R300_VPUCP_CMDSIZE, 0);
769 r300->hw.vpucp[i].cmd[0] =
770 cmdvpu(r300->radeon.radeonScreen,
771 R300_PVS_UCP_START + i, 1);
772 if (r300->radeon.radeonScreen->kernel_mm)
773 r300->hw.vpucp[i].emit = emit_vpu;
774 }
775 }
776 }
777
778 /* Textures */
779 ALLOC_STATE(tex.filter, variable, mtu + 1, 0);
780 r300->hw.tex.filter.cmd[R300_TEX_CMD_0] =
781 cmdpacket0(r300->radeon.radeonScreen, R300_TX_FILTER0_0, 0);
782
783 ALLOC_STATE(tex.filter_1, variable, mtu + 1, 0);
784 r300->hw.tex.filter_1.cmd[R300_TEX_CMD_0] =
785 cmdpacket0(r300->radeon.radeonScreen, R300_TX_FILTER1_0, 0);
786
787 ALLOC_STATE(tex.size, variable, mtu + 1, 0);
788 r300->hw.tex.size.cmd[R300_TEX_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_TX_SIZE_0, 0);
789
790 ALLOC_STATE(tex.format, variable, mtu + 1, 0);
791 r300->hw.tex.format.cmd[R300_TEX_CMD_0] =
792 cmdpacket0(r300->radeon.radeonScreen, R300_TX_FORMAT_0, 0);
793
794 ALLOC_STATE(tex.pitch, variable, mtu + 1, 0);
795 r300->hw.tex.pitch.cmd[R300_TEX_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_TX_FORMAT2_0, 0);
796
797 ALLOC_STATE(tex.offset, tex_offsets, 1, 0);
798 r300->hw.tex.offset.cmd[R300_TEX_CMD_0] =
799 cmdpacket0(r300->radeon.radeonScreen, R300_TX_OFFSET_0, 0);
800 r300->hw.tex.offset.emit = &emit_tex_offsets;
801
802 ALLOC_STATE(tex.chroma_key, variable, mtu + 1, 0);
803 r300->hw.tex.chroma_key.cmd[R300_TEX_CMD_0] =
804 cmdpacket0(r300->radeon.radeonScreen, R300_TX_CHROMA_KEY_0, 0);
805
806 ALLOC_STATE(tex.border_color, variable, mtu + 1, 0);
807 r300->hw.tex.border_color.cmd[R300_TEX_CMD_0] =
808 cmdpacket0(r300->radeon.radeonScreen, R300_TX_BORDER_COLOR_0, 0);
809
810 radeon_init_query_stateobj(&r300->radeon, R300_QUERYOBJ_CMDSIZE);
811 if (r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV530) {
812 r300->radeon.query.queryobj.cmd[R300_QUERYOBJ_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, RV530_FG_ZBREG_DEST, 1);
813 r300->radeon.query.queryobj.cmd[R300_QUERYOBJ_DATA_0] = RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL;
814 } else {
815 r300->radeon.query.queryobj.cmd[R300_QUERYOBJ_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_SU_REG_DEST, 1);
816 r300->radeon.query.queryobj.cmd[R300_QUERYOBJ_DATA_0] = R300_RASTER_PIPE_SELECT_ALL;
817 }
818 r300->radeon.query.queryobj.cmd[R300_QUERYOBJ_CMD_1] = cmdpacket0(r300->radeon.radeonScreen, R300_ZB_ZPASS_DATA, 1);
819 r300->radeon.query.queryobj.cmd[R300_QUERYOBJ_DATA_1] = 0;
820
821 r300->radeon.hw.is_dirty = GL_TRUE;
822 r300->radeon.hw.all_dirty = GL_TRUE;
823
824 rcommonInitCmdBuf(&r300->radeon);
825 }