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[mesa.git] / src / mesa / drivers / dri / r300 / r300_cmdbuf.c
1 /*
2 Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
3
4 The Weather Channel (TM) funded Tungsten Graphics to develop the
5 initial release of the Radeon 8500 driver under the XFree86 license.
6 This notice must be preserved.
7
8 Permission is hereby granted, free of charge, to any person obtaining
9 a copy of this software and associated documentation files (the
10 "Software"), to deal in the Software without restriction, including
11 without limitation the rights to use, copy, modify, merge, publish,
12 distribute, sublicense, and/or sell copies of the Software, and to
13 permit persons to whom the Software is furnished to do so, subject to
14 the following conditions:
15
16 The above copyright notice and this permission notice (including the
17 next paragraph) shall be included in all copies or substantial
18 portions of the Software.
19
20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27
28 **************************************************************************/
29
30 /**
31 * \file
32 *
33 * \author Nicolai Haehnle <prefect_@gmx.net>
34 */
35
36 #include "main/glheader.h"
37 #include "main/state.h"
38 #include "main/imports.h"
39 #include "main/macros.h"
40 #include "main/context.h"
41 #include "main/simple_list.h"
42 #include "swrast/swrast.h"
43
44 #include "drm.h"
45 #include "radeon_drm.h"
46
47 #include "r300_context.h"
48 #include "r300_ioctl.h"
49 #include "radeon_reg.h"
50 #include "r300_reg.h"
51 #include "r300_cmdbuf.h"
52 #include "r300_emit.h"
53 #include "radeon_bocs_wrapper.h"
54 #include "radeon_mipmap_tree.h"
55 #include "r300_state.h"
56 #include "radeon_reg.h"
57
58 /** # of dwords reserved for additional instructions that may need to be written
59 * during flushing.
60 */
61 #define SPACE_FOR_FLUSHING 4
62
63 static unsigned packet0_count(r300ContextPtr r300, uint32_t *pkt)
64 {
65 if (r300->radeon.radeonScreen->kernel_mm) {
66 return ((((*pkt) >> 16) & 0x3FFF) + 1);
67 } else {
68 drm_r300_cmd_header_t *t = (drm_r300_cmd_header_t*)pkt;
69 return t->packet0.count;
70 }
71 }
72
73 #define vpu_count(ptr) (((drm_r300_cmd_header_t*)(ptr))->vpu.count)
74 #define r500fp_count(ptr) (((drm_r300_cmd_header_t*)(ptr))->r500fp.count)
75
76 void emit_vpu(GLcontext *ctx, struct radeon_state_atom * atom)
77 {
78 r300ContextPtr r300 = R300_CONTEXT(ctx);
79 BATCH_LOCALS(&r300->radeon);
80 drm_r300_cmd_header_t cmd;
81 uint32_t addr, ndw, i;
82
83 if (!r300->radeon.radeonScreen->kernel_mm) {
84 uint32_t dwords;
85 dwords = (*atom->check) (ctx, atom);
86 BEGIN_BATCH_NO_AUTOSTATE(dwords);
87 OUT_BATCH_TABLE(atom->cmd, dwords);
88 END_BATCH();
89 return;
90 }
91
92 cmd.u = atom->cmd[0];
93 addr = (cmd.vpu.adrhi << 8) | cmd.vpu.adrlo;
94 ndw = cmd.vpu.count * 4;
95 if (ndw) {
96
97 if (r300->vap_flush_needed) {
98 BEGIN_BATCH_NO_AUTOSTATE(15 + ndw);
99
100 /* flush processing vertices */
101 OUT_BATCH_REGVAL(R300_SC_SCREENDOOR, 0);
102 OUT_BATCH_REGVAL(R300_RB3D_DSTCACHE_CTLSTAT, R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D);
103 OUT_BATCH_REGVAL(RADEON_WAIT_UNTIL, RADEON_WAIT_3D_IDLECLEAN);
104 OUT_BATCH_REGVAL(R300_SC_SCREENDOOR, 0xffffff);
105 OUT_BATCH_REGVAL(R300_VAP_PVS_STATE_FLUSH_REG, 0);
106 r300->vap_flush_needed = GL_FALSE;
107 } else {
108 BEGIN_BATCH_NO_AUTOSTATE(5 + ndw);
109 }
110 OUT_BATCH_REGVAL(R300_VAP_PVS_VECTOR_INDX_REG, addr);
111 OUT_BATCH(CP_PACKET0(R300_VAP_PVS_UPLOAD_DATA, ndw-1) | RADEON_ONE_REG_WR);
112 for (i = 0; i < ndw; i++) {
113 OUT_BATCH(atom->cmd[i+1]);
114 }
115 OUT_BATCH_REGVAL(R300_VAP_PVS_STATE_FLUSH_REG, 0);
116 END_BATCH();
117 }
118 }
119
120 void emit_r500fp(GLcontext *ctx, struct radeon_state_atom * atom)
121 {
122 r300ContextPtr r300 = R300_CONTEXT(ctx);
123 BATCH_LOCALS(&r300->radeon);
124 drm_r300_cmd_header_t cmd;
125 uint32_t addr, ndw, i, sz;
126 int type, clamp, stride;
127
128 if (!r300->radeon.radeonScreen->kernel_mm) {
129 uint32_t dwords;
130 dwords = (*atom->check) (ctx, atom);
131 BEGIN_BATCH_NO_AUTOSTATE(dwords);
132 OUT_BATCH_TABLE(atom->cmd, dwords);
133 END_BATCH();
134 return;
135 }
136
137 cmd.u = atom->cmd[0];
138 sz = cmd.r500fp.count;
139 addr = ((cmd.r500fp.adrhi_flags & 1) << 8) | cmd.r500fp.adrlo;
140 type = !!(cmd.r500fp.adrhi_flags & R500FP_CONSTANT_TYPE);
141 clamp = !!(cmd.r500fp.adrhi_flags & R500FP_CONSTANT_CLAMP);
142
143 addr |= (type << 16);
144 addr |= (clamp << 17);
145
146 stride = type ? 4 : 6;
147
148 ndw = sz * stride;
149 if (ndw) {
150
151 BEGIN_BATCH_NO_AUTOSTATE(3 + ndw);
152 OUT_BATCH(CP_PACKET0(R500_GA_US_VECTOR_INDEX, 0));
153 OUT_BATCH(addr);
154 OUT_BATCH(CP_PACKET0(R500_GA_US_VECTOR_DATA, ndw-1) | RADEON_ONE_REG_WR);
155 for (i = 0; i < ndw; i++) {
156 OUT_BATCH(atom->cmd[i+1]);
157 }
158 END_BATCH();
159 }
160 }
161
162 static void emit_tex_offsets(GLcontext *ctx, struct radeon_state_atom * atom)
163 {
164 r300ContextPtr r300 = R300_CONTEXT(ctx);
165 BATCH_LOCALS(&r300->radeon);
166 int numtmus = packet0_count(r300, r300->hw.tex.offset.cmd);
167 int notexture = 0;
168
169 if (numtmus) {
170 int i;
171
172 for(i = 0; i < numtmus; ++i) {
173 radeonTexObj *t = r300->hw.textures[i];
174
175 if (!t)
176 notexture = 1;
177 }
178
179 if (r300->radeon.radeonScreen->kernel_mm && notexture) {
180 return;
181 }
182 BEGIN_BATCH_NO_AUTOSTATE(4 * numtmus);
183 for(i = 0; i < numtmus; ++i) {
184 radeonTexObj *t = r300->hw.textures[i];
185 OUT_BATCH_REGSEQ(R300_TX_OFFSET_0 + (i * 4), 1);
186 if (t && !t->image_override) {
187 OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, 0,
188 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
189 } else if (!t) {
190 OUT_BATCH(r300->radeon.radeonScreen->texOffset[0]);
191 } else { /* override cases */
192 if (t->bo) {
193 OUT_BATCH_RELOC(t->tile_bits, t->bo, 0,
194 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
195 } else if (!r300->radeon.radeonScreen->kernel_mm) {
196 OUT_BATCH(t->override_offset);
197 }
198 else
199 OUT_BATCH(r300->radeon.radeonScreen->texOffset[0]);
200 }
201 }
202 END_BATCH();
203 }
204 }
205
206 static void emit_cb_offset(GLcontext *ctx, struct radeon_state_atom * atom)
207 {
208 r300ContextPtr r300 = R300_CONTEXT(ctx);
209 BATCH_LOCALS(&r300->radeon);
210 struct radeon_renderbuffer *rrb;
211 uint32_t cbpitch;
212 uint32_t offset = r300->radeon.state.color.draw_offset;
213 uint32_t dw = 6;
214 int i;
215
216 rrb = radeon_get_colorbuffer(&r300->radeon);
217 if (!rrb || !rrb->bo) {
218 fprintf(stderr, "no rrb\n");
219 return;
220 }
221
222 cbpitch = (rrb->pitch / rrb->cpp);
223 if (rrb->cpp == 4)
224 cbpitch |= R300_COLOR_FORMAT_ARGB8888;
225 else
226 cbpitch |= R300_COLOR_FORMAT_RGB565;
227
228 if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE)
229 cbpitch |= R300_COLOR_TILE_ENABLE;
230
231 if (r300->radeon.radeonScreen->kernel_mm)
232 dw += 2;
233 BEGIN_BATCH_NO_AUTOSTATE(dw);
234 OUT_BATCH_REGSEQ(R300_RB3D_COLOROFFSET0, 1);
235 OUT_BATCH_RELOC(offset, rrb->bo, offset, 0, RADEON_GEM_DOMAIN_VRAM, 0);
236 OUT_BATCH_REGSEQ(R300_RB3D_COLORPITCH0, 1);
237 if (!r300->radeon.radeonScreen->kernel_mm)
238 OUT_BATCH(cbpitch);
239 else
240 OUT_BATCH_RELOC(cbpitch, rrb->bo, cbpitch, 0, RADEON_GEM_DOMAIN_VRAM, 0);
241 END_BATCH();
242 if (r300->radeon.radeonScreen->driScreen->dri2.enabled) {
243 if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) {
244 BEGIN_BATCH_NO_AUTOSTATE(3);
245 OUT_BATCH_REGSEQ(R300_SC_SCISSORS_TL, 2);
246 OUT_BATCH(0);
247 OUT_BATCH(((rrb->width - 1) << R300_SCISSORS_X_SHIFT) |
248 ((rrb->height - 1) << R300_SCISSORS_Y_SHIFT));
249 END_BATCH();
250 BEGIN_BATCH_NO_AUTOSTATE(16);
251 for (i = 0; i < 4; i++) {
252 OUT_BATCH_REGSEQ(R300_SC_CLIPRECT_TL_0 + (i * 8), 2);
253 OUT_BATCH((0 << R300_CLIPRECT_X_SHIFT) | (0 << R300_CLIPRECT_Y_SHIFT));
254 OUT_BATCH(((rrb->width - 1) << R300_CLIPRECT_X_SHIFT) | ((rrb->height - 1) << R300_CLIPRECT_Y_SHIFT));
255 }
256 OUT_BATCH_REGSEQ(R300_SC_CLIP_RULE, 1);
257 OUT_BATCH(0xAAAA);
258 OUT_BATCH_REGSEQ(R300_SC_SCREENDOOR, 1);
259 OUT_BATCH(0xffffff);
260 END_BATCH();
261 } else {
262 BEGIN_BATCH_NO_AUTOSTATE(3);
263 OUT_BATCH_REGSEQ(R300_SC_SCISSORS_TL, 2);
264 OUT_BATCH((R300_SCISSORS_OFFSET << R300_SCISSORS_X_SHIFT) |
265 (R300_SCISSORS_OFFSET << R300_SCISSORS_Y_SHIFT));
266 OUT_BATCH(((rrb->width + R300_SCISSORS_OFFSET - 1) << R300_SCISSORS_X_SHIFT) |
267 ((rrb->height + R300_SCISSORS_OFFSET - 1) << R300_SCISSORS_Y_SHIFT));
268 END_BATCH();
269 BEGIN_BATCH_NO_AUTOSTATE(16);
270 for (i = 0; i < 4; i++) {
271 OUT_BATCH_REGSEQ(R300_SC_CLIPRECT_TL_0 + (i * 8), 2);
272 OUT_BATCH((R300_SCISSORS_OFFSET << R300_CLIPRECT_X_SHIFT) | (R300_SCISSORS_OFFSET << R300_CLIPRECT_Y_SHIFT));
273 OUT_BATCH(((R300_SCISSORS_OFFSET + rrb->width - 1) << R300_CLIPRECT_X_SHIFT) |
274 ((R300_SCISSORS_OFFSET + rrb->height - 1) << R300_CLIPRECT_Y_SHIFT));
275 }
276 OUT_BATCH_REGSEQ(R300_SC_CLIP_RULE, 1);
277 OUT_BATCH(0xAAAA);
278 OUT_BATCH_REGSEQ(R300_SC_SCREENDOOR, 1);
279 OUT_BATCH(0xffffff);
280 END_BATCH();
281 }
282 }
283 }
284
285 static void emit_zb_offset(GLcontext *ctx, struct radeon_state_atom * atom)
286 {
287 r300ContextPtr r300 = R300_CONTEXT(ctx);
288 BATCH_LOCALS(&r300->radeon);
289 struct radeon_renderbuffer *rrb;
290 uint32_t zbpitch;
291
292 rrb = radeon_get_depthbuffer(&r300->radeon);
293 if (!rrb)
294 return;
295
296 zbpitch = (rrb->pitch / rrb->cpp);
297 if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE) {
298 zbpitch |= R300_DEPTHMACROTILE_ENABLE;
299 }
300 if (rrb->bo->flags & RADEON_BO_FLAGS_MICRO_TILE){
301 zbpitch |= R300_DEPTHMICROTILE_TILED;
302 }
303
304 BEGIN_BATCH_NO_AUTOSTATE(6);
305 OUT_BATCH_REGSEQ(R300_ZB_DEPTHOFFSET, 1);
306 OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
307 OUT_BATCH_REGVAL(R300_ZB_DEPTHPITCH, zbpitch);
308 END_BATCH();
309 }
310
311 static void emit_zstencil_format(GLcontext *ctx, struct radeon_state_atom * atom)
312 {
313 r300ContextPtr r300 = R300_CONTEXT(ctx);
314 BATCH_LOCALS(&r300->radeon);
315 struct radeon_renderbuffer *rrb;
316 uint32_t format = 0;
317
318 rrb = radeon_get_depthbuffer(&r300->radeon);
319 if (!rrb)
320 format = 0;
321 else {
322 if (rrb->cpp == 2)
323 format = R300_DEPTHFORMAT_16BIT_INT_Z;
324 else if (rrb->cpp == 4)
325 format = R300_DEPTHFORMAT_24BIT_INT_Z_8BIT_STENCIL;
326 }
327
328 OUT_BATCH(atom->cmd[0]);
329 atom->cmd[1] &= ~0xf;
330 atom->cmd[1] |= format;
331 OUT_BATCH(atom->cmd[1]);
332 OUT_BATCH(atom->cmd[2]);
333 OUT_BATCH(atom->cmd[3]);
334 OUT_BATCH(atom->cmd[4]);
335 }
336
337 static int check_always(GLcontext *ctx, struct radeon_state_atom *atom)
338 {
339 return atom->cmd_size;
340 }
341
342 static int check_variable(GLcontext *ctx, struct radeon_state_atom *atom)
343 {
344 r300ContextPtr r300 = R300_CONTEXT(ctx);
345 int cnt;
346 if (atom->cmd[0] == CP_PACKET2) {
347 return 0;
348 }
349 cnt = packet0_count(r300, atom->cmd);
350 return cnt ? cnt + 1 : 0;
351 }
352
353 int check_vpu(GLcontext *ctx, struct radeon_state_atom *atom)
354 {
355 int cnt;
356
357 cnt = vpu_count(atom->cmd);
358 return cnt ? (cnt * 4) + 1 : 0;
359 }
360
361 int check_r500fp(GLcontext *ctx, struct radeon_state_atom *atom)
362 {
363 int cnt;
364
365 cnt = r500fp_count(atom->cmd);
366 return cnt ? (cnt * 6) + 1 : 0;
367 }
368
369 int check_r500fp_const(GLcontext *ctx, struct radeon_state_atom *atom)
370 {
371 int cnt;
372
373 cnt = r500fp_count(atom->cmd);
374 return cnt ? (cnt * 4) + 1 : 0;
375 }
376
377 #define ALLOC_STATE( ATOM, CHK, SZ, IDX ) \
378 do { \
379 r300->hw.ATOM.cmd_size = (SZ); \
380 r300->hw.ATOM.cmd = (uint32_t*)CALLOC((SZ) * sizeof(uint32_t)); \
381 r300->hw.ATOM.name = #ATOM; \
382 r300->hw.ATOM.idx = (IDX); \
383 r300->hw.ATOM.check = check_##CHK; \
384 r300->hw.ATOM.dirty = GL_FALSE; \
385 r300->radeon.hw.max_state_size += (SZ); \
386 insert_at_tail(&r300->radeon.hw.atomlist, &r300->hw.ATOM); \
387 } while (0)
388 /**
389 * Allocate memory for the command buffer and initialize the state atom
390 * list. Note that the initial hardware state is set by r300InitState().
391 */
392 void r300InitCmdBuf(r300ContextPtr r300)
393 {
394 int mtu;
395 int has_tcl = 1;
396 int is_r500 = 0;
397 int i;
398
399 if (!(r300->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL))
400 has_tcl = 0;
401
402 if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515)
403 is_r500 = 1;
404
405 r300->radeon.hw.max_state_size = 2 + 2; /* reserve extra space for WAIT_IDLE and tex cache flush */
406
407 mtu = r300->radeon.glCtx->Const.MaxTextureUnits;
408 if (RADEON_DEBUG & DEBUG_TEXTURE) {
409 fprintf(stderr, "Using %d maximum texture units..\n", mtu);
410 }
411
412 /* Setup the atom linked list */
413 make_empty_list(&r300->radeon.hw.atomlist);
414 r300->radeon.hw.atomlist.name = "atom-list";
415
416 /* Initialize state atoms */
417 ALLOC_STATE(vpt, always, R300_VPT_CMDSIZE, 0);
418 r300->hw.vpt.cmd[R300_VPT_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_SE_VPORT_XSCALE, 6);
419 ALLOC_STATE(vap_cntl, always, R300_VAP_CNTL_SIZE, 0);
420 r300->hw.vap_cntl.cmd[R300_VAP_CNTL_FLUSH] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PVS_STATE_FLUSH_REG, 1);
421 r300->hw.vap_cntl.cmd[R300_VAP_CNTL_FLUSH_1] = 0;
422 r300->hw.vap_cntl.cmd[R300_VAP_CNTL_CMD] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_CNTL, 1);
423 if (is_r500) {
424 ALLOC_STATE(vap_index_offset, always, 2, 0);
425 r300->hw.vap_index_offset.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R500_VAP_INDEX_OFFSET, 1);
426 r300->hw.vap_index_offset.cmd[1] = 0;
427 }
428 ALLOC_STATE(vte, always, 3, 0);
429 r300->hw.vte.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SE_VTE_CNTL, 2);
430 ALLOC_STATE(vap_vf_max_vtx_indx, always, 3, 0);
431 r300->hw.vap_vf_max_vtx_indx.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_VF_MAX_VTX_INDX, 2);
432 ALLOC_STATE(vap_cntl_status, always, 2, 0);
433 r300->hw.vap_cntl_status.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_CNTL_STATUS, 1);
434 ALLOC_STATE(vir[0], variable, R300_VIR_CMDSIZE, 0);
435 r300->hw.vir[0].cmd[R300_VIR_CMD_0] =
436 cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PROG_STREAM_CNTL_0, 1);
437 ALLOC_STATE(vir[1], variable, R300_VIR_CMDSIZE, 1);
438 r300->hw.vir[1].cmd[R300_VIR_CMD_0] =
439 cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PROG_STREAM_CNTL_EXT_0, 1);
440 ALLOC_STATE(vic, always, R300_VIC_CMDSIZE, 0);
441 r300->hw.vic.cmd[R300_VIC_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_VTX_STATE_CNTL, 2);
442 ALLOC_STATE(vap_psc_sgn_norm_cntl, always, 2, 0);
443 r300->hw.vap_psc_sgn_norm_cntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PSC_SGN_NORM_CNTL, SGN_NORM_ZERO_CLAMP_MINUS_ONE);
444
445 if (has_tcl) {
446 ALLOC_STATE(vap_clip_cntl, always, 2, 0);
447 r300->hw.vap_clip_cntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_CLIP_CNTL, 1);
448 ALLOC_STATE(vap_clip, always, 5, 0);
449 r300->hw.vap_clip.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_GB_VERT_CLIP_ADJ, 4);
450 ALLOC_STATE(vap_pvs_vtx_timeout_reg, always, 2, 0);
451 r300->hw.vap_pvs_vtx_timeout_reg.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, VAP_PVS_VTX_TIMEOUT_REG, 1);
452 }
453
454 ALLOC_STATE(vof, always, R300_VOF_CMDSIZE, 0);
455 r300->hw.vof.cmd[R300_VOF_CMD_0] =
456 cmdpacket0(r300->radeon.radeonScreen, R300_VAP_OUTPUT_VTX_FMT_0, 2);
457
458 if (has_tcl) {
459 ALLOC_STATE(pvs, always, R300_PVS_CMDSIZE, 0);
460 r300->hw.pvs.cmd[R300_PVS_CMD_0] =
461 cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PVS_CODE_CNTL_0, 3);
462 }
463
464 ALLOC_STATE(gb_enable, always, 2, 0);
465 r300->hw.gb_enable.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GB_ENABLE, 1);
466 ALLOC_STATE(gb_misc, always, R300_GB_MISC_CMDSIZE, 0);
467 r300->hw.gb_misc.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GB_MSPOS0, 5);
468 ALLOC_STATE(txe, always, R300_TXE_CMDSIZE, 0);
469 r300->hw.txe.cmd[R300_TXE_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_TX_ENABLE, 1);
470 ALLOC_STATE(ga_point_s0, always, 5, 0);
471 r300->hw.ga_point_s0.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_POINT_S0, 4);
472 ALLOC_STATE(ga_triangle_stipple, always, 2, 0);
473 r300->hw.ga_triangle_stipple.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_TRIANGLE_STIPPLE, 1);
474 ALLOC_STATE(ps, always, R300_PS_CMDSIZE, 0);
475 r300->hw.ps.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_POINT_SIZE, 1);
476 ALLOC_STATE(ga_point_minmax, always, 4, 0);
477 r300->hw.ga_point_minmax.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_POINT_MINMAX, 3);
478 ALLOC_STATE(lcntl, always, 2, 0);
479 r300->hw.lcntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_LINE_CNTL, 1);
480 ALLOC_STATE(ga_line_stipple, always, 4, 0);
481 r300->hw.ga_line_stipple.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_LINE_STIPPLE_VALUE, 3);
482 ALLOC_STATE(shade, always, 5, 0);
483 r300->hw.shade.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_ENHANCE, 4);
484 ALLOC_STATE(polygon_mode, always, 4, 0);
485 r300->hw.polygon_mode.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_POLY_MODE, 3);
486 ALLOC_STATE(fogp, always, 3, 0);
487 r300->hw.fogp.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_FOG_SCALE, 2);
488 ALLOC_STATE(zbias_cntl, always, 2, 0);
489 r300->hw.zbias_cntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SU_TEX_WRAP, 1);
490 ALLOC_STATE(zbs, always, R300_ZBS_CMDSIZE, 0);
491 r300->hw.zbs.cmd[R300_ZBS_CMD_0] =
492 cmdpacket0(r300->radeon.radeonScreen, R300_SU_POLY_OFFSET_FRONT_SCALE, 4);
493 ALLOC_STATE(occlusion_cntl, always, 2, 0);
494 r300->hw.occlusion_cntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SU_POLY_OFFSET_ENABLE, 1);
495 ALLOC_STATE(cul, always, R300_CUL_CMDSIZE, 0);
496 r300->hw.cul.cmd[R300_CUL_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_SU_CULL_MODE, 1);
497 ALLOC_STATE(su_depth_scale, always, 3, 0);
498 r300->hw.su_depth_scale.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SU_DEPTH_SCALE, 2);
499 ALLOC_STATE(rc, always, R300_RC_CMDSIZE, 0);
500 r300->hw.rc.cmd[R300_RC_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RS_COUNT, 2);
501 if (is_r500) {
502 ALLOC_STATE(ri, always, R500_RI_CMDSIZE, 0);
503 r300->hw.ri.cmd[R300_RI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R500_RS_IP_0, 16);
504 for (i = 0; i < 8; i++) {
505 r300->hw.ri.cmd[R300_RI_CMD_0 + i +1] =
506 (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_S_SHIFT) |
507 (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_T_SHIFT) |
508 (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT) |
509 (R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT);
510 }
511 ALLOC_STATE(rr, variable, R300_RR_CMDSIZE, 0);
512 r300->hw.rr.cmd[R300_RR_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R500_RS_INST_0, 1);
513 } else {
514 ALLOC_STATE(ri, always, R300_RI_CMDSIZE, 0);
515 r300->hw.ri.cmd[R300_RI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RS_IP_0, 8);
516 ALLOC_STATE(rr, variable, R300_RR_CMDSIZE, 0);
517 r300->hw.rr.cmd[R300_RR_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RS_INST_0, 1);
518 }
519 ALLOC_STATE(sc_hyperz, always, 3, 0);
520 r300->hw.sc_hyperz.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SC_HYPERZ, 2);
521 ALLOC_STATE(sc_screendoor, always, 2, 0);
522 r300->hw.sc_screendoor.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SC_SCREENDOOR, 1);
523 ALLOC_STATE(us_out_fmt, always, 6, 0);
524 r300->hw.us_out_fmt.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_OUT_FMT, 5);
525
526 if (is_r500) {
527 ALLOC_STATE(fp, always, R500_FP_CMDSIZE, 0);
528 r300->hw.fp.cmd[R500_FP_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R500_US_CONFIG, 2);
529 r300->hw.fp.cmd[R500_FP_CNTL] = R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO;
530 r300->hw.fp.cmd[R500_FP_CMD_1] = cmdpacket0(r300->radeon.radeonScreen, R500_US_CODE_ADDR, 3);
531 r300->hw.fp.cmd[R500_FP_CMD_2] = cmdpacket0(r300->radeon.radeonScreen, R500_US_FC_CTRL, 1);
532 r300->hw.fp.cmd[R500_FP_FC_CNTL] = 0; /* FIXME when we add flow control */
533
534 ALLOC_STATE(r500fp, r500fp, R500_FPI_CMDSIZE, 0);
535 r300->hw.r500fp.cmd[R300_FPI_CMD_0] =
536 cmdr500fp(r300->radeon.radeonScreen, 0, 0, 0, 0);
537 r300->hw.r500fp.emit = emit_r500fp;
538 ALLOC_STATE(r500fp_const, r500fp_const, R500_FPP_CMDSIZE, 0);
539 r300->hw.r500fp_const.cmd[R300_FPI_CMD_0] =
540 cmdr500fp(r300->radeon.radeonScreen, 0, 0, 1, 0);
541 r300->hw.r500fp_const.emit = emit_r500fp;
542 } else {
543 ALLOC_STATE(fp, always, R300_FP_CMDSIZE, 0);
544 r300->hw.fp.cmd[R300_FP_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_CONFIG, 3);
545 r300->hw.fp.cmd[R300_FP_CMD_1] = cmdpacket0(r300->radeon.radeonScreen, R300_US_CODE_ADDR_0, 4);
546
547 ALLOC_STATE(fpt, variable, R300_FPT_CMDSIZE, 0);
548 r300->hw.fpt.cmd[R300_FPT_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_TEX_INST_0, 0);
549
550 ALLOC_STATE(fpi[0], variable, R300_FPI_CMDSIZE, 0);
551 r300->hw.fpi[0].cmd[R300_FPI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_ALU_RGB_INST_0, 1);
552 ALLOC_STATE(fpi[1], variable, R300_FPI_CMDSIZE, 1);
553 r300->hw.fpi[1].cmd[R300_FPI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_ALU_RGB_ADDR_0, 1);
554 ALLOC_STATE(fpi[2], variable, R300_FPI_CMDSIZE, 2);
555 r300->hw.fpi[2].cmd[R300_FPI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_ALU_ALPHA_INST_0, 1);
556 ALLOC_STATE(fpi[3], variable, R300_FPI_CMDSIZE, 3);
557 r300->hw.fpi[3].cmd[R300_FPI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_ALU_ALPHA_ADDR_0, 1);
558 ALLOC_STATE(fpp, variable, R300_FPP_CMDSIZE, 0);
559 r300->hw.fpp.cmd[R300_FPP_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_PFS_PARAM_0_X, 0);
560 }
561 ALLOC_STATE(fogs, always, R300_FOGS_CMDSIZE, 0);
562 r300->hw.fogs.cmd[R300_FOGS_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_FG_FOG_BLEND, 1);
563 ALLOC_STATE(fogc, always, R300_FOGC_CMDSIZE, 0);
564 r300->hw.fogc.cmd[R300_FOGC_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_FG_FOG_COLOR_R, 3);
565 ALLOC_STATE(at, always, R300_AT_CMDSIZE, 0);
566 r300->hw.at.cmd[R300_AT_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_FG_ALPHA_FUNC, 2);
567 ALLOC_STATE(fg_depth_src, always, 2, 0);
568 r300->hw.fg_depth_src.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_FG_DEPTH_SRC, 1);
569 ALLOC_STATE(rb3d_cctl, always, 2, 0);
570 r300->hw.rb3d_cctl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_CCTL, 1);
571 ALLOC_STATE(bld, always, R300_BLD_CMDSIZE, 0);
572 r300->hw.bld.cmd[R300_BLD_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_CBLEND, 2);
573 ALLOC_STATE(cmk, always, R300_CMK_CMDSIZE, 0);
574 r300->hw.cmk.cmd[R300_CMK_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, RB3D_COLOR_CHANNEL_MASK, 1);
575 if (is_r500) {
576 ALLOC_STATE(blend_color, always, 3, 0);
577 r300->hw.blend_color.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R500_RB3D_CONSTANT_COLOR_AR, 2);
578 } else {
579 ALLOC_STATE(blend_color, always, 2, 0);
580 r300->hw.blend_color.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_BLEND_COLOR, 1);
581 }
582 ALLOC_STATE(rop, always, 2, 0);
583 r300->hw.rop.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_ROPCNTL, 1);
584 ALLOC_STATE(cb, always, R300_CB_CMDSIZE, 0);
585 r300->hw.cb.emit = &emit_cb_offset;
586 ALLOC_STATE(rb3d_dither_ctl, always, 10, 0);
587 r300->hw.rb3d_dither_ctl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_DITHER_CTL, 9);
588 ALLOC_STATE(rb3d_aaresolve_ctl, always, 2, 0);
589 r300->hw.rb3d_aaresolve_ctl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_AARESOLVE_CTL, 1);
590 ALLOC_STATE(rb3d_discard_src_pixel_lte_threshold, always, 3, 0);
591 r300->hw.rb3d_discard_src_pixel_lte_threshold.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R500_RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD, 2);
592 ALLOC_STATE(zs, always, R300_ZS_CMDSIZE, 0);
593 r300->hw.zs.cmd[R300_ZS_CMD_0] =
594 cmdpacket0(r300->radeon.radeonScreen, R300_ZB_CNTL, 3);
595
596 ALLOC_STATE(zstencil_format, always, 5, 0);
597 r300->hw.zstencil_format.cmd[0] =
598 cmdpacket0(r300->radeon.radeonScreen, R300_ZB_FORMAT, 4);
599 r300->hw.zstencil_format.emit = emit_zstencil_format;
600
601 ALLOC_STATE(zb, always, R300_ZB_CMDSIZE, 0);
602 r300->hw.zb.emit = emit_zb_offset;
603 ALLOC_STATE(zb_depthclearvalue, always, 2, 0);
604 r300->hw.zb_depthclearvalue.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_ZB_DEPTHCLEARVALUE, 1);
605 ALLOC_STATE(zb_zmask, always, 3, 0);
606 r300->hw.zb_zmask.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_ZB_ZMASK_OFFSET, 2);
607 ALLOC_STATE(zb_hiz_offset, always, 2, 0);
608 r300->hw.zb_hiz_offset.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_ZB_HIZ_OFFSET, 1);
609 ALLOC_STATE(zb_hiz_pitch, always, 2, 0);
610 r300->hw.zb_hiz_pitch.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_ZB_HIZ_PITCH, 1);
611
612 /* VPU only on TCL */
613 if (has_tcl) {
614 int i;
615 ALLOC_STATE(vpi, vpu, R300_VPI_CMDSIZE, 0);
616 r300->hw.vpi.cmd[0] =
617 cmdvpu(r300->radeon.radeonScreen, R300_PVS_CODE_START, 0);
618 r300->hw.vpi.emit = emit_vpu;
619
620 if (is_r500) {
621 ALLOC_STATE(vpp, vpu, R300_VPP_CMDSIZE, 0);
622 r300->hw.vpp.cmd[0] =
623 cmdvpu(r300->radeon.radeonScreen, R500_PVS_CONST_START, 0);
624 r300->hw.vpp.emit = emit_vpu;
625
626 ALLOC_STATE(vps, vpu, R300_VPS_CMDSIZE, 0);
627 r300->hw.vps.cmd[0] =
628 cmdvpu(r300->radeon.radeonScreen, R500_POINT_VPORT_SCALE_OFFSET, 1);
629 r300->hw.vps.emit = emit_vpu;
630
631 for (i = 0; i < 6; i++) {
632 ALLOC_STATE(vpucp[i], vpu, R300_VPUCP_CMDSIZE, 0);
633 r300->hw.vpucp[i].cmd[0] =
634 cmdvpu(r300->radeon.radeonScreen,
635 R500_PVS_UCP_START + i, 1);
636 r300->hw.vpucp[i].emit = emit_vpu;
637 }
638 } else {
639 ALLOC_STATE(vpp, vpu, R300_VPP_CMDSIZE, 0);
640 r300->hw.vpp.cmd[0] =
641 cmdvpu(r300->radeon.radeonScreen, R300_PVS_CONST_START, 0);
642 r300->hw.vpp.emit = emit_vpu;
643
644 ALLOC_STATE(vps, vpu, R300_VPS_CMDSIZE, 0);
645 r300->hw.vps.cmd[0] =
646 cmdvpu(r300->radeon.radeonScreen, R300_POINT_VPORT_SCALE_OFFSET, 1);
647 r300->hw.vps.emit = emit_vpu;
648
649 for (i = 0; i < 6; i++) {
650 ALLOC_STATE(vpucp[i], vpu, R300_VPUCP_CMDSIZE, 0);
651 r300->hw.vpucp[i].cmd[0] =
652 cmdvpu(r300->radeon.radeonScreen,
653 R300_PVS_UCP_START + i, 1);
654 r300->hw.vpucp[i].emit = emit_vpu;
655 }
656 }
657 }
658
659 /* Textures */
660 ALLOC_STATE(tex.filter, variable, mtu + 1, 0);
661 r300->hw.tex.filter.cmd[R300_TEX_CMD_0] =
662 cmdpacket0(r300->radeon.radeonScreen, R300_TX_FILTER0_0, 0);
663
664 ALLOC_STATE(tex.filter_1, variable, mtu + 1, 0);
665 r300->hw.tex.filter_1.cmd[R300_TEX_CMD_0] =
666 cmdpacket0(r300->radeon.radeonScreen, R300_TX_FILTER1_0, 0);
667
668 ALLOC_STATE(tex.size, variable, mtu + 1, 0);
669 r300->hw.tex.size.cmd[R300_TEX_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_TX_SIZE_0, 0);
670
671 ALLOC_STATE(tex.format, variable, mtu + 1, 0);
672 r300->hw.tex.format.cmd[R300_TEX_CMD_0] =
673 cmdpacket0(r300->radeon.radeonScreen, R300_TX_FORMAT_0, 0);
674
675 ALLOC_STATE(tex.pitch, variable, mtu + 1, 0);
676 r300->hw.tex.pitch.cmd[R300_TEX_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_TX_FORMAT2_0, 0);
677
678 ALLOC_STATE(tex.offset, variable, 1, 0);
679 r300->hw.tex.offset.cmd[R300_TEX_CMD_0] =
680 cmdpacket0(r300->radeon.radeonScreen, R300_TX_OFFSET_0, 0);
681 r300->hw.tex.offset.emit = &emit_tex_offsets;
682
683 ALLOC_STATE(tex.chroma_key, variable, mtu + 1, 0);
684 r300->hw.tex.chroma_key.cmd[R300_TEX_CMD_0] =
685 cmdpacket0(r300->radeon.radeonScreen, R300_TX_CHROMA_KEY_0, 0);
686
687 ALLOC_STATE(tex.border_color, variable, mtu + 1, 0);
688 r300->hw.tex.border_color.cmd[R300_TEX_CMD_0] =
689 cmdpacket0(r300->radeon.radeonScreen, R300_TX_BORDER_COLOR_0, 0);
690
691 r300->radeon.hw.is_dirty = GL_TRUE;
692 r300->radeon.hw.all_dirty = GL_TRUE;
693
694 rcommonInitCmdBuf(&r300->radeon);
695 }