src/mesa/drivers/dri/r300/r300_cmdbuf.c

   1 /*
   2 Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
   3
   4 The Weather Channel (TM) funded Tungsten Graphics to develop the
   5 initial release of the Radeon 8500 driver under the XFree86 license.
   6 This notice must be preserved.
   7
   8 Permission is hereby granted, free of charge, to any person obtaining
   9 a copy of this software and associated documentation files (the
  10 "Software"), to deal in the Software without restriction, including
  11 without limitation the rights to use, copy, modify, merge, publish,
  12 distribute, sublicense, and/or sell copies of the Software, and to
  13 permit persons to whom the Software is furnished to do so, subject to
  14 the following conditions:
  15
  16 The above copyright notice and this permission notice (including the
  17 next paragraph) shall be included in all copies or substantial
  18 portions of the Software.
  19
  20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27
  28 **************************************************************************/
  29
  30 /**
  31  * \file
  32  *
  33  * \author Nicolai Haehnle <prefect_@gmx.net>
  34  */
  35
  36 #include "main/glheader.h"
  37 #include "main/state.h"
  38 #include "main/imports.h"
  39 #include "main/macros.h"
  40 #include "main/context.h"
  41 #include "main/simple_list.h"
  42 #include "swrast/swrast.h"
  43
  44 #include "drm.h"
  45 #include "radeon_drm.h"
  46
  47 #include "r300_context.h"
  48 #include "r300_ioctl.h"
  49 #include "radeon_reg.h"
  50 #include "r300_reg.h"
  51 #include "r300_cmdbuf.h"
  52 #include "r300_emit.h"
  53 #include "radeon_bocs_wrapper.h"
  54 #include "radeon_mipmap_tree.h"
  55 #include "r300_state.h"
  56 #include "radeon_reg.h"
  57
  58 /** # of dwords reserved for additional instructions that may need to be written
  59  * during flushing.
  60  */
  61 #define SPACE_FOR_FLUSHING      4
  62
  63 static unsigned packet0_count(r300ContextPtr r300, uint32_t *pkt)
  64 {
  65     if (r300->radeon.radeonScreen->kernel_mm) {
  66         return ((((*pkt) >> 16) & 0x3FFF) + 1);
  67     } else {
  68         drm_r300_cmd_header_t *t = (drm_r300_cmd_header_t*)pkt;
  69         return t->packet0.count;
  70     }
  71 }
  72
  73 #define vpu_count(ptr) (((drm_r300_cmd_header_t*)(ptr))->vpu.count)
  74 #define r500fp_count(ptr) (((drm_r300_cmd_header_t*)(ptr))->r500fp.count)
  75
  76 void emit_vpu(GLcontext *ctx, struct radeon_state_atom * atom)
  77 {
  78         r300ContextPtr r300 = R300_CONTEXT(ctx);
  79         BATCH_LOCALS(&r300->radeon);
  80         drm_r300_cmd_header_t cmd;
  81         uint32_t addr, ndw, i;
  82
  83         if (!r300->radeon.radeonScreen->kernel_mm) {
  84                 uint32_t dwords;
  85                 dwords = (*atom->check) (ctx, atom);
  86                 BEGIN_BATCH_NO_AUTOSTATE(dwords);
  87                 OUT_BATCH_TABLE(atom->cmd, dwords);
  88                 END_BATCH();
  89                 return;
  90         }
  91
  92         cmd.u = atom->cmd[0];
  93         addr = (cmd.vpu.adrhi << 8) | cmd.vpu.adrlo;
  94         ndw = cmd.vpu.count * 4;
  95         if (ndw) {
  96
  97                 if (r300->vap_flush_needed) {
  98                         BEGIN_BATCH_NO_AUTOSTATE(15 + ndw);
  99
 100                         /* flush processing vertices */
 101                         OUT_BATCH_REGVAL(R300_SC_SCREENDOOR, 0);
 102                         OUT_BATCH_REGVAL(R300_RB3D_DSTCACHE_CTLSTAT, R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D);
 103                         OUT_BATCH_REGVAL(RADEON_WAIT_UNTIL, RADEON_WAIT_3D_IDLECLEAN);
 104                         OUT_BATCH_REGVAL(R300_SC_SCREENDOOR, 0xffffff);
 105                         OUT_BATCH_REGVAL(R300_VAP_PVS_STATE_FLUSH_REG, 0);
 106                         r300->vap_flush_needed = GL_FALSE;
 107                 } else {
 108                         BEGIN_BATCH_NO_AUTOSTATE(5 + ndw);
 109                 }
 110                 OUT_BATCH_REGVAL(R300_VAP_PVS_VECTOR_INDX_REG, addr);
 111                 OUT_BATCH(CP_PACKET0(R300_VAP_PVS_UPLOAD_DATA, ndw-1) | RADEON_ONE_REG_WR);
 112                 for (i = 0; i < ndw; i++) {
 113                         OUT_BATCH(atom->cmd[i+1]);
 114                 }
 115                 OUT_BATCH_REGVAL(R300_VAP_PVS_STATE_FLUSH_REG, 0);
 116                 END_BATCH();
 117         }
 118 }
 119
 120 void emit_r500fp(GLcontext *ctx, struct radeon_state_atom * atom)
 121 {
 122         r300ContextPtr r300 = R300_CONTEXT(ctx);
 123         BATCH_LOCALS(&r300->radeon);
 124         drm_r300_cmd_header_t cmd;
 125         uint32_t addr, ndw, i, sz;
 126         int type, clamp, stride;
 127
 128         if (!r300->radeon.radeonScreen->kernel_mm) {
 129                 uint32_t dwords;
 130                 dwords = (*atom->check) (ctx, atom);
 131                 BEGIN_BATCH_NO_AUTOSTATE(dwords);
 132                 OUT_BATCH_TABLE(atom->cmd, dwords);
 133                 END_BATCH();
 134                 return;
 135         }
 136
 137         cmd.u = atom->cmd[0];
 138         sz = cmd.r500fp.count;
 139         addr = ((cmd.r500fp.adrhi_flags & 1) << 8) | cmd.r500fp.adrlo;
 140         type = !!(cmd.r500fp.adrhi_flags & R500FP_CONSTANT_TYPE);
 141         clamp = !!(cmd.r500fp.adrhi_flags & R500FP_CONSTANT_CLAMP);
 142
 143         addr |= (type << 16);
 144         addr |= (clamp << 17);
 145
 146         stride = type ? 4 : 6;
 147
 148         ndw = sz * stride;
 149         if (ndw) {
 150
 151                 BEGIN_BATCH_NO_AUTOSTATE(3 + ndw);
 152                 OUT_BATCH(CP_PACKET0(R500_GA_US_VECTOR_INDEX, 0));
 153                 OUT_BATCH(addr);
 154                 OUT_BATCH(CP_PACKET0(R500_GA_US_VECTOR_DATA, ndw-1) | RADEON_ONE_REG_WR);
 155                 for (i = 0; i < ndw; i++) {
 156                         OUT_BATCH(atom->cmd[i+1]);
 157                 }
 158                 END_BATCH();
 159         }
 160 }
 161
 162 static void emit_tex_offsets(GLcontext *ctx, struct radeon_state_atom * atom)
 163 {
 164         r300ContextPtr r300 = R300_CONTEXT(ctx);
 165         BATCH_LOCALS(&r300->radeon);
 166         int numtmus = packet0_count(r300, r300->hw.tex.offset.cmd);
 167         int i;
 168
 169         for(i = 0; i < numtmus; ++i) {
 170                 radeonTexObj *t = r300->hw.textures[i];
 171                 if (t && !t->image_override) {
 172                         BEGIN_BATCH_NO_AUTOSTATE(4);
 173                         OUT_BATCH_REGSEQ(R300_TX_OFFSET_0 + (i * 4), 1);
 174                         OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, 0,
 175                                         RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
 176                         END_BATCH();
 177                 } else if (!t) {
 178                         /* Texture unit hasn't a texture bound.
 179                          * We assign the current color buffer as a fakery to make
 180                          * KIL work. */
 181                         struct radeon_renderbuffer *rrb = radeon_get_colorbuffer(&r300->radeon);
 182                         if (rrb && rrb->bo) {
 183                                 BEGIN_BATCH_NO_AUTOSTATE(4);
 184                                 OUT_BATCH_REGSEQ(R300_TX_OFFSET_0 + (i * 4), 1);
 185                                 OUT_BATCH_RELOC(0, rrb->bo, 0,
 186                                                 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
 187                                 END_BATCH();
 188                         }
 189                 } else { /* override cases */
 190                         if (t->bo) {
 191                                 BEGIN_BATCH_NO_AUTOSTATE(4);
 192                                 OUT_BATCH_REGSEQ(R300_TX_OFFSET_0 + (i * 4), 1);
 193                                 OUT_BATCH_RELOC(t->tile_bits, t->bo, 0,
 194                                                 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
 195                                 END_BATCH();
 196                         } else if (!r300->radeon.radeonScreen->kernel_mm) {
 197                                 BEGIN_BATCH_NO_AUTOSTATE(2);
 198                                 OUT_BATCH_REGSEQ(R300_TX_OFFSET_0 + (i * 4), 1);
 199                                 OUT_BATCH(t->override_offset);
 200                                 END_BATCH();
 201                         } else {
 202                                 /* Texture unit hasn't a texture bound nothings to do */
 203                         }
 204                 }
 205         }
 206 }
 207
 208 void r300_emit_scissor(GLcontext *ctx)
 209 {
 210         r300ContextPtr r300 = R300_CONTEXT(ctx);
 211         BATCH_LOCALS(&r300->radeon);
 212     unsigned x1, y1, x2, y2;
 213         struct radeon_renderbuffer *rrb;
 214
 215     if (!r300->radeon.radeonScreen->driScreen->dri2.enabled) {
 216         return;
 217     }
 218         rrb = radeon_get_colorbuffer(&r300->radeon);
 219         if (!rrb || !rrb->bo) {
 220                 fprintf(stderr, "no rrb\n");
 221                 return;
 222         }
 223     if (r300->radeon.state.scissor.enabled) {
 224         x1 = r300->radeon.state.scissor.rect.x1;
 225         y1 = r300->radeon.state.scissor.rect.y1;
 226         x2 = r300->radeon.state.scissor.rect.x2 - 1;
 227         y2 = r300->radeon.state.scissor.rect.y2 - 1;
 228     } else {
 229         x1 = 0;
 230         y1 = 0;
 231         x2 = rrb->base.Width - 1;
 232         y2 = rrb->base.Height - 1;
 233     }
 234     if (r300->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV515) {
 235         x1 += R300_SCISSORS_OFFSET;
 236         y1 += R300_SCISSORS_OFFSET;
 237         x2 += R300_SCISSORS_OFFSET;
 238         y2 += R300_SCISSORS_OFFSET;
 239     }
 240     BEGIN_BATCH_NO_AUTOSTATE(3);
 241     OUT_BATCH_REGSEQ(R300_SC_SCISSORS_TL, 2);
 242     OUT_BATCH((x1 << R300_SCISSORS_X_SHIFT)|(y1 << R300_SCISSORS_Y_SHIFT));
 243     OUT_BATCH((x2 << R300_SCISSORS_X_SHIFT)|(y2 << R300_SCISSORS_Y_SHIFT));
 244     END_BATCH();
 245 }
 246
 247 static void emit_cb_offset(GLcontext *ctx, struct radeon_state_atom * atom)
 248 {
 249         r300ContextPtr r300 = R300_CONTEXT(ctx);
 250         BATCH_LOCALS(&r300->radeon);
 251         struct radeon_renderbuffer *rrb;
 252         uint32_t cbpitch;
 253         uint32_t offset = r300->radeon.state.color.draw_offset;
 254         uint32_t dw = 6;
 255     int i;
 256
 257         rrb = radeon_get_colorbuffer(&r300->radeon);
 258         if (!rrb || !rrb->bo) {
 259                 fprintf(stderr, "no rrb\n");
 260                 return;
 261         }
 262
 263         if (RADEON_DEBUG & DEBUG_STATE)
 264            fprintf(stderr,"rrb is %p %d %dx%d\n", rrb, offset, rrb->base.Width, rrb->base.Height);
 265         cbpitch = (rrb->pitch / rrb->cpp);
 266         if (rrb->cpp == 4)
 267                 cbpitch |= R300_COLOR_FORMAT_ARGB8888;
 268         else switch (rrb->base._ActualFormat) {
 269         case GL_RGB5:
 270                 cbpitch |= R300_COLOR_FORMAT_RGB565;
 271                 break;
 272         case GL_RGBA4:
 273                 cbpitch |= R300_COLOR_FORMAT_ARGB4444;
 274                 break;
 275         case GL_RGB5_A1:
 276                 cbpitch |= R300_COLOR_FORMAT_ARGB1555;
 277                 break;
 278         }
 279
 280         if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE)
 281                 cbpitch |= R300_COLOR_TILE_ENABLE;
 282
 283         if (r300->radeon.radeonScreen->kernel_mm)
 284                 dw += 2;
 285         BEGIN_BATCH_NO_AUTOSTATE(dw);
 286         OUT_BATCH_REGSEQ(R300_RB3D_COLOROFFSET0, 1);
 287         OUT_BATCH_RELOC(offset, rrb->bo, offset, 0, RADEON_GEM_DOMAIN_VRAM, 0);
 288         OUT_BATCH_REGSEQ(R300_RB3D_COLORPITCH0, 1);
 289         if (!r300->radeon.radeonScreen->kernel_mm)
 290                 OUT_BATCH(cbpitch);
 291         else
 292                 OUT_BATCH_RELOC(cbpitch, rrb->bo, cbpitch, 0, RADEON_GEM_DOMAIN_VRAM, 0);
 293         END_BATCH();
 294     if (r300->radeon.radeonScreen->driScreen->dri2.enabled) {
 295         if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) {
 296             BEGIN_BATCH_NO_AUTOSTATE(3);
 297             OUT_BATCH_REGSEQ(R300_SC_SCISSORS_TL, 2);
 298             OUT_BATCH(0);
 299             OUT_BATCH(((rrb->base.Width - 1) << R300_SCISSORS_X_SHIFT) |
 300                     ((rrb->base.Height - 1) << R300_SCISSORS_Y_SHIFT));
 301             END_BATCH();
 302             BEGIN_BATCH_NO_AUTOSTATE(16);
 303             for (i = 0; i < 4; i++) {
 304                 OUT_BATCH_REGSEQ(R300_SC_CLIPRECT_TL_0 + (i * 8), 2);
 305                 OUT_BATCH((0 << R300_CLIPRECT_X_SHIFT) | (0 << R300_CLIPRECT_Y_SHIFT));
 306                 OUT_BATCH(((rrb->base.Width - 1) << R300_CLIPRECT_X_SHIFT) | ((rrb->base.Height - 1) << R300_CLIPRECT_Y_SHIFT));
 307             }
 308             OUT_BATCH_REGSEQ(R300_SC_CLIP_RULE, 1);
 309             OUT_BATCH(0xAAAA);
 310             OUT_BATCH_REGSEQ(R300_SC_SCREENDOOR, 1);
 311             OUT_BATCH(0xffffff);
 312             END_BATCH();
 313         } else {
 314             BEGIN_BATCH_NO_AUTOSTATE(3);
 315             OUT_BATCH_REGSEQ(R300_SC_SCISSORS_TL, 2);
 316             OUT_BATCH((R300_SCISSORS_OFFSET << R300_SCISSORS_X_SHIFT) |
 317                     (R300_SCISSORS_OFFSET << R300_SCISSORS_Y_SHIFT));
 318             OUT_BATCH(((rrb->base.Width + R300_SCISSORS_OFFSET - 1) << R300_SCISSORS_X_SHIFT) |
 319                     ((rrb->base.Height + R300_SCISSORS_OFFSET - 1) << R300_SCISSORS_Y_SHIFT));
 320             END_BATCH();
 321             BEGIN_BATCH_NO_AUTOSTATE(16);
 322             for (i = 0; i < 4; i++) {
 323                 OUT_BATCH_REGSEQ(R300_SC_CLIPRECT_TL_0 + (i * 8), 2);
 324                 OUT_BATCH((R300_SCISSORS_OFFSET << R300_CLIPRECT_X_SHIFT) | (R300_SCISSORS_OFFSET << R300_CLIPRECT_Y_SHIFT));
 325                 OUT_BATCH(((R300_SCISSORS_OFFSET + rrb->base.Width - 1) << R300_CLIPRECT_X_SHIFT) |
 326                           ((R300_SCISSORS_OFFSET + rrb->base.Height - 1) << R300_CLIPRECT_Y_SHIFT));
 327             }
 328             OUT_BATCH_REGSEQ(R300_SC_CLIP_RULE, 1);
 329             OUT_BATCH(0xAAAA);
 330             OUT_BATCH_REGSEQ(R300_SC_SCREENDOOR, 1);
 331             OUT_BATCH(0xffffff);
 332             END_BATCH();
 333         }
 334     }
 335 }
 336
 337 static void emit_zb_offset(GLcontext *ctx, struct radeon_state_atom * atom)
 338 {
 339         r300ContextPtr r300 = R300_CONTEXT(ctx);
 340         BATCH_LOCALS(&r300->radeon);
 341         struct radeon_renderbuffer *rrb;
 342         uint32_t zbpitch;
 343         uint32_t dw;
 344
 345         rrb = radeon_get_depthbuffer(&r300->radeon);
 346         if (!rrb)
 347                 return;
 348
 349         zbpitch = (rrb->pitch / rrb->cpp);
 350         if (!r300->radeon.radeonScreen->kernel_mm) {
 351             if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE) {
 352                 zbpitch |= R300_DEPTHMACROTILE_ENABLE;
 353            }
 354             if (rrb->bo->flags & RADEON_BO_FLAGS_MICRO_TILE){
 355                 zbpitch |= R300_DEPTHMICROTILE_TILED;
 356             }
 357         }
 358
 359         dw = 6;
 360         if (r300->radeon.radeonScreen->kernel_mm)
 361                 dw += 2;
 362         BEGIN_BATCH_NO_AUTOSTATE(dw);
 363         OUT_BATCH_REGSEQ(R300_ZB_DEPTHOFFSET, 1);
 364         OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
 365         OUT_BATCH_REGSEQ(R300_ZB_DEPTHPITCH, 1);
 366         if (!r300->radeon.radeonScreen->kernel_mm)
 367             OUT_BATCH(zbpitch);
 368         else
 369             OUT_BATCH_RELOC(cbpitch, rrb->bo, zbpitch, 0, RADEON_GEM_DOMAIN_VRAM, 0);
 370         END_BATCH();
 371 }
 372
 373 static void emit_gb_misc(GLcontext *ctx, struct radeon_state_atom * atom)
 374 {
 375         r300ContextPtr r300 = R300_CONTEXT(ctx);
 376         BATCH_LOCALS(&r300->radeon);
 377     if (!r300->radeon.radeonScreen->driScreen->dri2.enabled) {
 378         BEGIN_BATCH_NO_AUTOSTATE(4);
 379         OUT_BATCH(atom->cmd[0]);
 380         OUT_BATCH(atom->cmd[1]);
 381         OUT_BATCH(atom->cmd[2]);
 382         OUT_BATCH(atom->cmd[3]);
 383         END_BATCH();
 384     }
 385 }
 386
 387 static void emit_threshold_misc(GLcontext *ctx, struct radeon_state_atom * atom)
 388 {
 389         r300ContextPtr r300 = R300_CONTEXT(ctx);
 390         BATCH_LOCALS(&r300->radeon);
 391     if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) {
 392         BEGIN_BATCH_NO_AUTOSTATE(3);
 393         OUT_BATCH(atom->cmd[0]);
 394         OUT_BATCH(atom->cmd[1]);
 395         OUT_BATCH(atom->cmd[2]);
 396         END_BATCH();
 397     }
 398 }
 399
 400 static void emit_shade_misc(GLcontext *ctx, struct radeon_state_atom * atom)
 401 {
 402         r300ContextPtr r300 = R300_CONTEXT(ctx);
 403         BATCH_LOCALS(&r300->radeon);
 404
 405     if (!r300->radeon.radeonScreen->driScreen->dri2.enabled) {
 406         BEGIN_BATCH_NO_AUTOSTATE(2);
 407         OUT_BATCH(atom->cmd[0]);
 408         OUT_BATCH(atom->cmd[1]);
 409         END_BATCH();
 410     }
 411 }
 412
 413 static void emit_zstencil_format(GLcontext *ctx, struct radeon_state_atom * atom)
 414 {
 415         r300ContextPtr r300 = R300_CONTEXT(ctx);
 416         BATCH_LOCALS(&r300->radeon);
 417         struct radeon_renderbuffer *rrb;
 418         uint32_t format = 0;
 419
 420         rrb = radeon_get_depthbuffer(&r300->radeon);
 421         if (!rrb)
 422           format = 0;
 423         else {
 424           if (rrb->cpp == 2)
 425             format = R300_DEPTHFORMAT_16BIT_INT_Z;
 426           else if (rrb->cpp == 4)
 427             format = R300_DEPTHFORMAT_24BIT_INT_Z_8BIT_STENCIL;
 428         }
 429
 430         OUT_BATCH(atom->cmd[0]);
 431         atom->cmd[1] &= ~0xf;
 432         atom->cmd[1] |= format;
 433         OUT_BATCH(atom->cmd[1]);
 434         OUT_BATCH(atom->cmd[2]);
 435         OUT_BATCH(atom->cmd[3]);
 436         OUT_BATCH(atom->cmd[4]);
 437 }
 438
 439 static int check_always(GLcontext *ctx, struct radeon_state_atom *atom)
 440 {
 441         return atom->cmd_size;
 442 }
 443
 444 static int check_variable(GLcontext *ctx, struct radeon_state_atom *atom)
 445 {
 446         r300ContextPtr r300 = R300_CONTEXT(ctx);
 447         int cnt;
 448         if (atom->cmd[0] == CP_PACKET2) {
 449                 return 0;
 450         }
 451         cnt = packet0_count(r300, atom->cmd);
 452         return cnt ? cnt + 1 : 0;
 453 }
 454
 455 int check_vpu(GLcontext *ctx, struct radeon_state_atom *atom)
 456 {
 457         int cnt;
 458
 459         cnt = vpu_count(atom->cmd);
 460         return cnt ? (cnt * 4) + 1 : 0;
 461 }
 462
 463 int check_r500fp(GLcontext *ctx, struct radeon_state_atom *atom)
 464 {
 465         int cnt;
 466
 467         cnt = r500fp_count(atom->cmd);
 468         return cnt ? (cnt * 6) + 1 : 0;
 469 }
 470
 471 int check_r500fp_const(GLcontext *ctx, struct radeon_state_atom *atom)
 472 {
 473         int cnt;
 474
 475         cnt = r500fp_count(atom->cmd);
 476         return cnt ? (cnt * 4) + 1 : 0;
 477 }
 478
 479 #define ALLOC_STATE( ATOM, CHK, SZ, IDX )                               \
 480    do {                                                                 \
 481       r300->hw.ATOM.cmd_size = (SZ);                                    \
 482       r300->hw.ATOM.cmd = (uint32_t*)CALLOC((SZ) * sizeof(uint32_t));   \
 483       r300->hw.ATOM.name = #ATOM;                                       \
 484       r300->hw.ATOM.idx = (IDX);                                        \
 485       r300->hw.ATOM.check = check_##CHK;                                \
 486       r300->hw.ATOM.dirty = GL_FALSE;                                   \
 487       r300->radeon.hw.max_state_size += (SZ);                                   \
 488       insert_at_tail(&r300->radeon.hw.atomlist, &r300->hw.ATOM);                \
 489    } while (0)
 490 /**
 491  * Allocate memory for the command buffer and initialize the state atom
 492  * list. Note that the initial hardware state is set by r300InitState().
 493  */
 494 void r300InitCmdBuf(r300ContextPtr r300)
 495 {
 496         int mtu;
 497         int has_tcl;
 498         int is_r500 = 0;
 499
 500         has_tcl = r300->options.hw_tcl_enabled;
 501
 502         if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515)
 503                 is_r500 = 1;
 504
 505         r300->radeon.hw.max_state_size = 2 + 2; /* reserve extra space for WAIT_IDLE and tex cache flush */
 506
 507         mtu = r300->radeon.glCtx->Const.MaxTextureUnits;
 508         if (RADEON_DEBUG & DEBUG_TEXTURE) {
 509                 fprintf(stderr, "Using %d maximum texture units..\n", mtu);
 510         }
 511
 512         /* Setup the atom linked list */
 513         make_empty_list(&r300->radeon.hw.atomlist);
 514         r300->radeon.hw.atomlist.name = "atom-list";
 515
 516         /* Initialize state atoms */
 517         ALLOC_STATE(vpt, always, R300_VPT_CMDSIZE, 0);
 518         r300->hw.vpt.cmd[R300_VPT_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_SE_VPORT_XSCALE, 6);
 519         ALLOC_STATE(vap_cntl, always, R300_VAP_CNTL_SIZE, 0);
 520         r300->hw.vap_cntl.cmd[R300_VAP_CNTL_FLUSH] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PVS_STATE_FLUSH_REG, 1);
 521         r300->hw.vap_cntl.cmd[R300_VAP_CNTL_FLUSH_1] = 0;
 522         r300->hw.vap_cntl.cmd[R300_VAP_CNTL_CMD] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_CNTL, 1);
 523         if (is_r500 && !r300->radeon.radeonScreen->kernel_mm) {
 524             ALLOC_STATE(vap_index_offset, always, 2, 0);
 525             r300->hw.vap_index_offset.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R500_VAP_INDEX_OFFSET, 1);
 526             r300->hw.vap_index_offset.cmd[1] = 0;
 527         }
 528         ALLOC_STATE(vte, always, 3, 0);
 529         r300->hw.vte.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SE_VTE_CNTL, 2);
 530         ALLOC_STATE(vap_vf_max_vtx_indx, always, 3, 0);
 531         r300->hw.vap_vf_max_vtx_indx.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_VF_MAX_VTX_INDX, 2);
 532         ALLOC_STATE(vap_cntl_status, always, 2, 0);
 533         r300->hw.vap_cntl_status.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_CNTL_STATUS, 1);
 534         ALLOC_STATE(vir[0], variable, R300_VIR_CMDSIZE, 0);
 535         r300->hw.vir[0].cmd[R300_VIR_CMD_0] =
 536             cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PROG_STREAM_CNTL_0, 1);
 537         ALLOC_STATE(vir[1], variable, R300_VIR_CMDSIZE, 1);
 538         r300->hw.vir[1].cmd[R300_VIR_CMD_0] =
 539             cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PROG_STREAM_CNTL_EXT_0, 1);
 540         ALLOC_STATE(vic, always, R300_VIC_CMDSIZE, 0);
 541         r300->hw.vic.cmd[R300_VIC_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_VTX_STATE_CNTL, 2);
 542         ALLOC_STATE(vap_psc_sgn_norm_cntl, always, 2, 0);
 543         r300->hw.vap_psc_sgn_norm_cntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PSC_SGN_NORM_CNTL, SGN_NORM_ZERO_CLAMP_MINUS_ONE);
 544
 545         if (has_tcl) {
 546                 ALLOC_STATE(vap_clip_cntl, always, 2, 0);
 547                 r300->hw.vap_clip_cntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_CLIP_CNTL, 1);
 548                 ALLOC_STATE(vap_clip, always, 5, 0);
 549                 r300->hw.vap_clip.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_GB_VERT_CLIP_ADJ, 4);
 550                 ALLOC_STATE(vap_pvs_vtx_timeout_reg, always, 2, 0);
 551                 r300->hw.vap_pvs_vtx_timeout_reg.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, VAP_PVS_VTX_TIMEOUT_REG, 1);
 552         }
 553
 554         ALLOC_STATE(vof, always, R300_VOF_CMDSIZE, 0);
 555         r300->hw.vof.cmd[R300_VOF_CMD_0] =
 556             cmdpacket0(r300->radeon.radeonScreen, R300_VAP_OUTPUT_VTX_FMT_0, 2);
 557
 558         if (has_tcl) {
 559                 ALLOC_STATE(pvs, always, R300_PVS_CMDSIZE, 0);
 560                 r300->hw.pvs.cmd[R300_PVS_CMD_0] =
 561                     cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PVS_CODE_CNTL_0, 3);
 562         }
 563
 564         ALLOC_STATE(gb_enable, always, 2, 0);
 565         r300->hw.gb_enable.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GB_ENABLE, 1);
 566         ALLOC_STATE(gb_misc, always, R300_GB_MISC_CMDSIZE, 0);
 567         r300->hw.gb_misc.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GB_MSPOS0, 3);
 568         r300->hw.gb_misc.emit = emit_gb_misc;
 569         ALLOC_STATE(gb_misc2, always, R300_GB_MISC2_CMDSIZE, 0);
 570     r300->hw.gb_misc2.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, 0x401C, 2);
 571         ALLOC_STATE(txe, always, R300_TXE_CMDSIZE, 0);
 572         r300->hw.txe.cmd[R300_TXE_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_TX_ENABLE, 1);
 573         ALLOC_STATE(ga_point_s0, always, 5, 0);
 574         r300->hw.ga_point_s0.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_POINT_S0, 4);
 575         ALLOC_STATE(ga_triangle_stipple, always, 2, 0);
 576         r300->hw.ga_triangle_stipple.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_TRIANGLE_STIPPLE, 1);
 577         ALLOC_STATE(ps, always, R300_PS_CMDSIZE, 0);
 578         r300->hw.ps.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_POINT_SIZE, 1);
 579         ALLOC_STATE(ga_point_minmax, always, 4, 0);
 580         r300->hw.ga_point_minmax.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_POINT_MINMAX, 3);
 581         ALLOC_STATE(lcntl, always, 2, 0);
 582         r300->hw.lcntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_LINE_CNTL, 1);
 583         ALLOC_STATE(ga_line_stipple, always, 4, 0);
 584         r300->hw.ga_line_stipple.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_LINE_STIPPLE_VALUE, 3);
 585         ALLOC_STATE(shade, always, 2, 0);
 586         r300->hw.shade.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_ENHANCE, 1);
 587         r300->hw.shade.emit = emit_shade_misc;
 588         ALLOC_STATE(shade2, always, 4, 0);
 589         r300->hw.shade2.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, 0x4278, 3);
 590         ALLOC_STATE(polygon_mode, always, 4, 0);
 591         r300->hw.polygon_mode.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_POLY_MODE, 3);
 592         ALLOC_STATE(fogp, always, 3, 0);
 593         r300->hw.fogp.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_FOG_SCALE, 2);
 594         ALLOC_STATE(zbias_cntl, always, 2, 0);
 595         r300->hw.zbias_cntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SU_TEX_WRAP, 1);
 596         ALLOC_STATE(zbs, always, R300_ZBS_CMDSIZE, 0);
 597         r300->hw.zbs.cmd[R300_ZBS_CMD_0] =
 598             cmdpacket0(r300->radeon.radeonScreen, R300_SU_POLY_OFFSET_FRONT_SCALE, 4);
 599         ALLOC_STATE(occlusion_cntl, always, 2, 0);
 600         r300->hw.occlusion_cntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SU_POLY_OFFSET_ENABLE, 1);
 601         ALLOC_STATE(cul, always, R300_CUL_CMDSIZE, 0);
 602         r300->hw.cul.cmd[R300_CUL_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_SU_CULL_MODE, 1);
 603         ALLOC_STATE(su_depth_scale, always, 3, 0);
 604         r300->hw.su_depth_scale.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SU_DEPTH_SCALE, 2);
 605         ALLOC_STATE(rc, always, R300_RC_CMDSIZE, 0);
 606         r300->hw.rc.cmd[R300_RC_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RS_COUNT, 2);
 607         if (is_r500) {
 608                 ALLOC_STATE(ri, variable, R500_RI_CMDSIZE, 0);
 609                 r300->hw.ri.cmd[R300_RI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R500_RS_IP_0, 16);
 610                 ALLOC_STATE(rr, variable, R300_RR_CMDSIZE, 0);
 611                 r300->hw.rr.cmd[R300_RR_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R500_RS_INST_0, 1);
 612         } else {
 613                 ALLOC_STATE(ri, variable, R300_RI_CMDSIZE, 0);
 614                 r300->hw.ri.cmd[R300_RI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RS_IP_0, 8);
 615                 ALLOC_STATE(rr, variable, R300_RR_CMDSIZE, 0);
 616                 r300->hw.rr.cmd[R300_RR_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RS_INST_0, 1);
 617         }
 618         ALLOC_STATE(sc_hyperz, always, 3, 0);
 619         r300->hw.sc_hyperz.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SC_HYPERZ, 2);
 620         ALLOC_STATE(sc_screendoor, always, 2, 0);
 621         r300->hw.sc_screendoor.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SC_SCREENDOOR, 1);
 622         ALLOC_STATE(us_out_fmt, always, 6, 0);
 623         r300->hw.us_out_fmt.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_OUT_FMT, 5);
 624
 625         if (is_r500) {
 626                 ALLOC_STATE(fp, always, R500_FP_CMDSIZE, 0);
 627                 r300->hw.fp.cmd[R500_FP_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R500_US_CONFIG, 2);
 628                 r300->hw.fp.cmd[R500_FP_CNTL] = R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO;
 629                 r300->hw.fp.cmd[R500_FP_CMD_1] = cmdpacket0(r300->radeon.radeonScreen, R500_US_CODE_ADDR, 3);
 630                 r300->hw.fp.cmd[R500_FP_CMD_2] = cmdpacket0(r300->radeon.radeonScreen, R500_US_FC_CTRL, 1);
 631                 r300->hw.fp.cmd[R500_FP_FC_CNTL] = 0; /* FIXME when we add flow control */
 632
 633                 ALLOC_STATE(r500fp, r500fp, R500_FPI_CMDSIZE, 0);
 634                 r300->hw.r500fp.cmd[R300_FPI_CMD_0] =
 635                         cmdr500fp(r300->radeon.radeonScreen, 0, 0, 0, 0);
 636                 r300->hw.r500fp.emit = emit_r500fp;
 637                 ALLOC_STATE(r500fp_const, r500fp_const, R500_FPP_CMDSIZE, 0);
 638                 r300->hw.r500fp_const.cmd[R300_FPI_CMD_0] =
 639                         cmdr500fp(r300->radeon.radeonScreen, 0, 0, 1, 0);
 640                 r300->hw.r500fp_const.emit = emit_r500fp;
 641         } else {
 642                 ALLOC_STATE(fp, always, R300_FP_CMDSIZE, 0);
 643                 r300->hw.fp.cmd[R300_FP_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_CONFIG, 3);
 644                 r300->hw.fp.cmd[R300_FP_CMD_1] = cmdpacket0(r300->radeon.radeonScreen, R300_US_CODE_ADDR_0, 4);
 645
 646                 ALLOC_STATE(fpt, variable, R300_FPT_CMDSIZE, 0);
 647                 r300->hw.fpt.cmd[R300_FPT_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_TEX_INST_0, 0);
 648
 649                 ALLOC_STATE(fpi[0], variable, R300_FPI_CMDSIZE, 0);
 650                 r300->hw.fpi[0].cmd[R300_FPI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_ALU_RGB_INST_0, 1);
 651                 ALLOC_STATE(fpi[1], variable, R300_FPI_CMDSIZE, 1);
 652                 r300->hw.fpi[1].cmd[R300_FPI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_ALU_RGB_ADDR_0, 1);
 653                 ALLOC_STATE(fpi[2], variable, R300_FPI_CMDSIZE, 2);
 654                 r300->hw.fpi[2].cmd[R300_FPI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_ALU_ALPHA_INST_0, 1);
 655                 ALLOC_STATE(fpi[3], variable, R300_FPI_CMDSIZE, 3);
 656                 r300->hw.fpi[3].cmd[R300_FPI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_ALU_ALPHA_ADDR_0, 1);
 657                 ALLOC_STATE(fpp, variable, R300_FPP_CMDSIZE, 0);
 658                 r300->hw.fpp.cmd[R300_FPP_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_PFS_PARAM_0_X, 0);
 659         }
 660         ALLOC_STATE(fogs, always, R300_FOGS_CMDSIZE, 0);
 661         r300->hw.fogs.cmd[R300_FOGS_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_FG_FOG_BLEND, 1);
 662         ALLOC_STATE(fogc, always, R300_FOGC_CMDSIZE, 0);
 663         r300->hw.fogc.cmd[R300_FOGC_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_FG_FOG_COLOR_R, 3);
 664         ALLOC_STATE(at, always, R300_AT_CMDSIZE, 0);
 665         r300->hw.at.cmd[R300_AT_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_FG_ALPHA_FUNC, 2);
 666         ALLOC_STATE(fg_depth_src, always, 2, 0);
 667         r300->hw.fg_depth_src.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_FG_DEPTH_SRC, 1);
 668         ALLOC_STATE(rb3d_cctl, always, 2, 0);
 669         r300->hw.rb3d_cctl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_CCTL, 1);
 670         ALLOC_STATE(bld, always, R300_BLD_CMDSIZE, 0);
 671         r300->hw.bld.cmd[R300_BLD_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_CBLEND, 2);
 672         ALLOC_STATE(cmk, always, R300_CMK_CMDSIZE, 0);
 673         r300->hw.cmk.cmd[R300_CMK_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, RB3D_COLOR_CHANNEL_MASK, 1);
 674         if (is_r500) {
 675                 ALLOC_STATE(blend_color, always, 3, 0);
 676                 r300->hw.blend_color.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R500_RB3D_CONSTANT_COLOR_AR, 2);
 677         } else {
 678                 ALLOC_STATE(blend_color, always, 2, 0);
 679                 r300->hw.blend_color.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_BLEND_COLOR, 1);
 680         }
 681         ALLOC_STATE(rop, always, 2, 0);
 682         r300->hw.rop.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_ROPCNTL, 1);
 683         ALLOC_STATE(cb, always, R300_CB_CMDSIZE, 0);
 684         r300->hw.cb.emit = &emit_cb_offset;
 685         ALLOC_STATE(rb3d_dither_ctl, always, 10, 0);
 686         r300->hw.rb3d_dither_ctl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_DITHER_CTL, 9);
 687         ALLOC_STATE(rb3d_aaresolve_ctl, always, 2, 0);
 688         r300->hw.rb3d_aaresolve_ctl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_AARESOLVE_CTL, 1);
 689     ALLOC_STATE(rb3d_discard_src_pixel_lte_threshold, always, 3, 0);
 690     r300->hw.rb3d_discard_src_pixel_lte_threshold.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R500_RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD, 2);
 691         r300->hw.rb3d_discard_src_pixel_lte_threshold.emit = emit_threshold_misc;
 692         ALLOC_STATE(zs, always, R300_ZS_CMDSIZE, 0);
 693         r300->hw.zs.cmd[R300_ZS_CMD_0] =
 694             cmdpacket0(r300->radeon.radeonScreen, R300_ZB_CNTL, 3);
 695
 696         ALLOC_STATE(zstencil_format, always, 5, 0);
 697         r300->hw.zstencil_format.cmd[0] =
 698             cmdpacket0(r300->radeon.radeonScreen, R300_ZB_FORMAT, 4);
 699         r300->hw.zstencil_format.emit = emit_zstencil_format;
 700
 701         ALLOC_STATE(zb, always, R300_ZB_CMDSIZE, 0);
 702         r300->hw.zb.emit = emit_zb_offset;
 703         ALLOC_STATE(zb_depthclearvalue, always, 2, 0);
 704         r300->hw.zb_depthclearvalue.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_ZB_DEPTHCLEARVALUE, 1);
 705         ALLOC_STATE(zb_zmask, always, 3, 0);
 706         r300->hw.zb_zmask.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_ZB_ZMASK_OFFSET, 2);
 707         ALLOC_STATE(zb_hiz_offset, always, 2, 0);
 708         r300->hw.zb_hiz_offset.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_ZB_HIZ_OFFSET, 1);
 709         ALLOC_STATE(zb_hiz_pitch, always, 2, 0);
 710         r300->hw.zb_hiz_pitch.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_ZB_HIZ_PITCH, 1);
 711
 712         /* VPU only on TCL */
 713         if (has_tcl) {
 714                 int i;
 715                 ALLOC_STATE(vpi, vpu, R300_VPI_CMDSIZE, 0);
 716                 r300->hw.vpi.cmd[0] =
 717                     cmdvpu(r300->radeon.radeonScreen, R300_PVS_CODE_START, 0);
 718                 r300->hw.vpi.emit = emit_vpu;
 719
 720                 if (is_r500) {
 721                     ALLOC_STATE(vpp, vpu, R300_VPP_CMDSIZE, 0);
 722                     r300->hw.vpp.cmd[0] =
 723                         cmdvpu(r300->radeon.radeonScreen, R500_PVS_CONST_START, 0);
 724                     r300->hw.vpp.emit = emit_vpu;
 725
 726                     ALLOC_STATE(vps, vpu, R300_VPS_CMDSIZE, 0);
 727                     r300->hw.vps.cmd[0] =
 728                         cmdvpu(r300->radeon.radeonScreen, R500_POINT_VPORT_SCALE_OFFSET, 1);
 729                     r300->hw.vps.emit = emit_vpu;
 730
 731                         for (i = 0; i < 6; i++) {
 732                           ALLOC_STATE(vpucp[i], vpu, R300_VPUCP_CMDSIZE, 0);
 733                           r300->hw.vpucp[i].cmd[0] =
 734                                   cmdvpu(r300->radeon.radeonScreen,
 735                            R500_PVS_UCP_START + i, 1);
 736                                 r300->hw.vpucp[i].emit = emit_vpu;
 737                         }
 738                 } else {
 739                     ALLOC_STATE(vpp, vpu, R300_VPP_CMDSIZE, 0);
 740                     r300->hw.vpp.cmd[0] =
 741                         cmdvpu(r300->radeon.radeonScreen, R300_PVS_CONST_START, 0);
 742                     r300->hw.vpp.emit = emit_vpu;
 743
 744                     ALLOC_STATE(vps, vpu, R300_VPS_CMDSIZE, 0);
 745                     r300->hw.vps.cmd[0] =
 746                         cmdvpu(r300->radeon.radeonScreen, R300_POINT_VPORT_SCALE_OFFSET, 1);
 747                     r300->hw.vps.emit = emit_vpu;
 748
 749                         for (i = 0; i < 6; i++) {
 750                                 ALLOC_STATE(vpucp[i], vpu, R300_VPUCP_CMDSIZE, 0);
 751                                 r300->hw.vpucp[i].cmd[0] =
 752                                         cmdvpu(r300->radeon.radeonScreen,
 753                                                R300_PVS_UCP_START + i, 1);
 754                                 r300->hw.vpucp[i].emit = emit_vpu;
 755                         }
 756                 }
 757         }
 758
 759         /* Textures */
 760         ALLOC_STATE(tex.filter, variable, mtu + 1, 0);
 761         r300->hw.tex.filter.cmd[R300_TEX_CMD_0] =
 762             cmdpacket0(r300->radeon.radeonScreen, R300_TX_FILTER0_0, 0);
 763
 764         ALLOC_STATE(tex.filter_1, variable, mtu + 1, 0);
 765         r300->hw.tex.filter_1.cmd[R300_TEX_CMD_0] =
 766             cmdpacket0(r300->radeon.radeonScreen, R300_TX_FILTER1_0, 0);
 767
 768         ALLOC_STATE(tex.size, variable, mtu + 1, 0);
 769         r300->hw.tex.size.cmd[R300_TEX_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_TX_SIZE_0, 0);
 770
 771         ALLOC_STATE(tex.format, variable, mtu + 1, 0);
 772         r300->hw.tex.format.cmd[R300_TEX_CMD_0] =
 773             cmdpacket0(r300->radeon.radeonScreen, R300_TX_FORMAT_0, 0);
 774
 775         ALLOC_STATE(tex.pitch, variable, mtu + 1, 0);
 776         r300->hw.tex.pitch.cmd[R300_TEX_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_TX_FORMAT2_0, 0);
 777
 778         ALLOC_STATE(tex.offset, variable, 1, 0);
 779         r300->hw.tex.offset.cmd[R300_TEX_CMD_0] =
 780             cmdpacket0(r300->radeon.radeonScreen, R300_TX_OFFSET_0, 0);
 781         r300->hw.tex.offset.emit = &emit_tex_offsets;
 782
 783         ALLOC_STATE(tex.chroma_key, variable, mtu + 1, 0);
 784         r300->hw.tex.chroma_key.cmd[R300_TEX_CMD_0] =
 785             cmdpacket0(r300->radeon.radeonScreen, R300_TX_CHROMA_KEY_0, 0);
 786
 787         ALLOC_STATE(tex.border_color, variable, mtu + 1, 0);
 788         r300->hw.tex.border_color.cmd[R300_TEX_CMD_0] =
 789             cmdpacket0(r300->radeon.radeonScreen, R300_TX_BORDER_COLOR_0, 0);
 790
 791         r300->radeon.hw.is_dirty = GL_TRUE;
 792         r300->radeon.hw.all_dirty = GL_TRUE;
 793
 794         rcommonInitCmdBuf(&r300->radeon);
 795 }