src/mesa/drivers/dri/r300/r300_cmdbuf.c

   1 /*
   2 Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
   3
   4 The Weather Channel (TM) funded Tungsten Graphics to develop the
   5 initial release of the Radeon 8500 driver under the XFree86 license.
   6 This notice must be preserved.
   7
   8 Permission is hereby granted, free of charge, to any person obtaining
   9 a copy of this software and associated documentation files (the
  10 "Software"), to deal in the Software without restriction, including
  11 without limitation the rights to use, copy, modify, merge, publish,
  12 distribute, sublicense, and/or sell copies of the Software, and to
  13 permit persons to whom the Software is furnished to do so, subject to
  14 the following conditions:
  15
  16 The above copyright notice and this permission notice (including the
  17 next paragraph) shall be included in all copies or substantial
  18 portions of the Software.
  19
  20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27
  28 **************************************************************************/
  29
  30 /**
  31  * \file
  32  *
  33  * \author Nicolai Haehnle <prefect_@gmx.net>
  34  */
  35
  36 #include "main/glheader.h"
  37 #include "main/state.h"
  38 #include "main/imports.h"
  39 #include "main/macros.h"
  40 #include "main/context.h"
  41 #include "main/simple_list.h"
  42 #include "swrast/swrast.h"
  43
  44 #include "drm.h"
  45 #include "radeon_drm.h"
  46
  47 #include "radeon_buffer.h"
  48 #include "radeon_ioctl.h"
  49 #include "r300_context.h"
  50 #include "r300_ioctl.h"
  51 #include "radeon_reg.h"
  52 #include "r300_reg.h"
  53 #include "r300_cmdbuf.h"
  54 #include "r300_emit.h"
  55 #include "radeon_mipmap_tree.h"
  56 #include "r300_state.h"
  57 #include "radeon_cs_legacy.h"
  58 #include "radeon_cs_gem.h"
  59 #include "radeon_reg.h"
  60
  61 #define R300_VAP_PVS_UPLOAD_ADDRESS 0x2200
  62 #   define RADEON_ONE_REG_WR        (1 << 15)
  63
  64 // Set this to 1 for extremely verbose debugging of command buffers
  65 #define DEBUG_CMDBUF            0
  66
  67 /** # of dwords reserved for additional instructions that may need to be written
  68  * during flushing.
  69  */
  70 #define SPACE_FOR_FLUSHING      4
  71
  72 static void r300PrintStateAtom(r300ContextPtr r300,
  73                                struct radeon_state_atom *state)
  74 {
  75         int i;
  76         int dwords = (*state->check) (r300->radeon.glCtx, state);
  77
  78         fprintf(stderr, "  emit %s %d/%d\n", state->name, dwords, state->cmd_size);
  79
  80         if (RADEON_DEBUG & DEBUG_VERBOSE) {
  81                 for (i = 0; i < dwords; i++) {
  82                         fprintf(stderr, "      %s[%d]: %08x\n",
  83                                 state->name, i, state->cmd[i]);
  84                 }
  85         }
  86 }
  87
  88 /**
  89  * Emit all atoms with a dirty field equal to dirty.
  90  *
  91  * The caller must have ensured that there is enough space in the command
  92  * buffer.
  93  */
  94 static INLINE void r300EmitAtoms(r300ContextPtr r300, GLboolean dirty)
  95 {
  96         BATCH_LOCALS(&r300->radeon);
  97         struct radeon_state_atom *atom;
  98         int dwords;
  99
 100     cp_wait(r300, R300_WAIT_3D | R300_WAIT_3D_CLEAN);
 101         BEGIN_BATCH_NO_AUTOSTATE(2);
 102         OUT_BATCH(cmdpacket0(r300->radeon.radeonScreen, R300_TX_INVALTAGS, 1));
 103         OUT_BATCH(R300_TX_FLUSH);
 104         END_BATCH();
 105     end_3d(r300);
 106
 107         /* Emit actual atoms */
 108         foreach(atom, &r300->hw.atomlist) {
 109                 if ((atom->dirty || r300->hw.all_dirty) == dirty) {
 110                         dwords = (*atom->check) (r300->radeon.glCtx, atom);
 111                         if (dwords) {
 112                                 if (DEBUG_CMDBUF && RADEON_DEBUG & DEBUG_STATE) {
 113                                         r300PrintStateAtom(r300, atom);
 114                                 }
 115                                 if (atom->emit) {
 116                                         (*atom->emit)(r300->radeon.glCtx, atom);
 117                                 } else {
 118                                         BEGIN_BATCH_NO_AUTOSTATE(dwords);
 119                                         OUT_BATCH_TABLE(atom->cmd, dwords);
 120                                         END_BATCH();
 121                                 }
 122                                 atom->dirty = GL_FALSE;
 123                         } else {
 124                                 if (DEBUG_CMDBUF && RADEON_DEBUG & DEBUG_STATE) {
 125                                         fprintf(stderr, "  skip state %s\n",
 126                                                 atom->name);
 127                                 }
 128                         }
 129                 }
 130         }
 131
 132         COMMIT_BATCH();
 133 }
 134
 135 /**
 136  * Copy dirty hardware state atoms into the command buffer.
 137  *
 138  * We also copy out clean state if we're at the start of a buffer. That makes
 139  * it easy to recover from lost contexts.
 140  */
 141 void r300EmitState(r300ContextPtr r300)
 142 {
 143         if (RADEON_DEBUG & (DEBUG_STATE | DEBUG_PRIMS))
 144                 fprintf(stderr, "%s\n", __FUNCTION__);
 145
 146         if (r300->radeon.cmdbuf.cs->cdw && !r300->hw.is_dirty && !r300->hw.all_dirty)
 147                 return;
 148
 149         /* To avoid going across the entire set of states multiple times, just check
 150          * for enough space for the case of emitting all state.
 151          */
 152         rcommonEnsureCmdBufSpace(&r300->radeon, r300->hw.max_state_size, __FUNCTION__);
 153
 154         if (!r300->radeon.cmdbuf.cs->cdw) {
 155                 if (RADEON_DEBUG & DEBUG_STATE)
 156                         fprintf(stderr, "Begin reemit state\n");
 157
 158                 r300EmitAtoms(r300, GL_FALSE);
 159         }
 160
 161         if (RADEON_DEBUG & DEBUG_STATE)
 162                 fprintf(stderr, "Begin dirty state\n");
 163
 164         r300EmitAtoms(r300, GL_TRUE);
 165         r300->hw.is_dirty = GL_FALSE;
 166         r300->hw.all_dirty = GL_FALSE;
 167 }
 168
 169 static unsigned packet0_count(r300ContextPtr r300, uint32_t *pkt)
 170 {
 171     if (r300->radeon.radeonScreen->kernel_mm) {
 172         return ((((*pkt) >> 16) & 0x3FFF) + 1);
 173     } else {
 174         drm_r300_cmd_header_t *t = (drm_r300_cmd_header_t*)pkt;
 175         return t->packet0.count;
 176     }
 177     return 0;
 178 }
 179
 180 #define vpu_count(ptr) (((drm_r300_cmd_header_t*)(ptr))->vpu.count)
 181 #define r500fp_count(ptr) (((drm_r300_cmd_header_t*)(ptr))->r500fp.count)
 182
 183 void emit_vpu(GLcontext *ctx, struct radeon_state_atom * atom)
 184 {
 185         r300ContextPtr r300 = R300_CONTEXT(ctx);
 186         BATCH_LOCALS(&r300->radeon);
 187         drm_r300_cmd_header_t cmd;
 188     uint32_t addr, ndw, i;
 189
 190     if (!r300->radeon.radeonScreen->kernel_mm) {
 191         uint32_t dwords;
 192         dwords = (*atom->check) (ctx, atom);
 193         BEGIN_BATCH_NO_AUTOSTATE(dwords);
 194         OUT_BATCH_TABLE(atom->cmd, dwords);
 195         END_BATCH();
 196         return;
 197     }
 198
 199     cmd.u = atom->cmd[0];
 200     addr = (cmd.vpu.adrhi << 8) | cmd.vpu.adrlo;
 201         ndw = cmd.vpu.count * 4;
 202     if (ndw) {
 203         /* flush processing vertices */
 204         OUT_BATCH(CP_PACKET0(R300_SC_SCREENDOOR, 0));
 205         OUT_BATCH(0x0);
 206         OUT_BATCH(CP_PACKET0(RADEON_WAIT_UNTIL, 0));
 207         OUT_BATCH((1 << 15) | (1 << 28));
 208         OUT_BATCH(CP_PACKET0(R300_SC_SCREENDOOR, 0));
 209         OUT_BATCH(0x00FFFFFF);
 210         OUT_BATCH(CP_PACKET0(R300_VAP_PVS_STATE_FLUSH_REG, 0));
 211         OUT_BATCH(1);
 212         /* write vpu */
 213         OUT_BATCH(CP_PACKET0(R300_VAP_PVS_UPLOAD_ADDRESS, 0));
 214         OUT_BATCH(addr);
 215         OUT_BATCH(CP_PACKET0(R300_VAP_PVS_UPLOAD_DATA, ndw-1) | RADEON_ONE_REG_WR);
 216         for (i = 0; i < ndw; i++) {
 217             OUT_BATCH(atom->cmd[i+1]);
 218         }
 219     }
 220 }
 221
 222 void emit_r500fp(GLcontext *ctx, struct radeon_state_atom * atom)
 223 {
 224         r300ContextPtr r300 = R300_CONTEXT(ctx);
 225         BATCH_LOCALS(&r300->radeon);
 226         drm_r300_cmd_header_t cmd;
 227         uint32_t addr, ndw, i, sz;
 228         int type, clamp, stride;
 229
 230         if (!r300->radeon.radeonScreen->kernel_mm) {
 231                 uint32_t dwords;
 232                 dwords = (*atom->check) (ctx, atom);
 233                 BEGIN_BATCH_NO_AUTOSTATE(dwords);
 234                 OUT_BATCH_TABLE(atom->cmd, dwords);
 235                 END_BATCH();
 236                 return;
 237         }
 238
 239         cmd.u = atom->cmd[0];
 240         sz = cmd.r500fp.count;
 241         addr = ((cmd.r500fp.adrhi_flags & 1) << 8) | cmd.r500fp.adrlo;
 242         type = !!(cmd.r500fp.adrhi_flags & R500FP_CONSTANT_TYPE);
 243         clamp = !!(cmd.r500fp.adrhi_flags & R500FP_CONSTANT_CLAMP);
 244
 245         addr |= (type << 16);
 246         addr |= (clamp << 17);
 247
 248         stride = type ? 4 : 6;
 249
 250         ndw = sz * stride;
 251         if (ndw) {
 252
 253                 OUT_BATCH(CP_PACKET0(R500_GA_US_VECTOR_INDEX, 0));
 254                 OUT_BATCH(addr);
 255                 OUT_BATCH(CP_PACKET0(R500_GA_US_VECTOR_DATA, ndw-1) | RADEON_ONE_REG_WR);
 256                 for (i = 0; i < ndw; i++) {
 257                         OUT_BATCH(atom->cmd[i+1]);
 258                 }
 259         }
 260 }
 261
 262 static void emit_tex_offsets(GLcontext *ctx, struct radeon_state_atom * atom)
 263 {
 264         r300ContextPtr r300 = R300_CONTEXT(ctx);
 265         BATCH_LOCALS(&r300->radeon);
 266         int numtmus = packet0_count(r300, r300->hw.tex.offset.cmd);
 267
 268         if (numtmus) {
 269                 int i;
 270
 271                 for(i = 0; i < numtmus; ++i) {
 272                     BEGIN_BATCH(2);
 273                 OUT_BATCH_REGSEQ(R300_TX_OFFSET_0 + (i * 4), 1);
 274                         radeonTexObj *t = r300->hw.textures[i];
 275                         if (t && !t->image_override) {
 276                                 OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, 0,
 277                                 RADEON_GEM_DOMAIN_VRAM, 0, 0);
 278                         } else if (!t) {
 279                                 OUT_BATCH(r300->radeon.radeonScreen->texOffset[0]);
 280                         } else {
 281                                 if (t->bo) {
 282                                         OUT_BATCH_RELOC(t->tile_bits, t->bo, 0,
 283                                                         RADEON_GEM_DOMAIN_VRAM, 0, 0);
 284                                 } else {
 285                                         OUT_BATCH(t->override_offset);
 286                                 }
 287                         }
 288                         END_BATCH();
 289                 }
 290         }
 291 }
 292
 293 static void emit_cb_offset(GLcontext *ctx, struct radeon_state_atom * atom)
 294 {
 295         r300ContextPtr r300 = R300_CONTEXT(ctx);
 296         BATCH_LOCALS(&r300->radeon);
 297         struct radeon_renderbuffer *rrb;
 298         uint32_t cbpitch;
 299
 300         rrb = radeon_get_colorbuffer(&r300->radeon);
 301         if (!rrb || !rrb->bo) {
 302                 fprintf(stderr, "no rrb\n");
 303                 return;
 304         }
 305
 306         cbpitch = (rrb->pitch / rrb->cpp);
 307         if (rrb->cpp == 4)
 308                 cbpitch |= R300_COLOR_FORMAT_ARGB8888;
 309         else
 310                 cbpitch |= R300_COLOR_FORMAT_RGB565;
 311
 312         if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE)
 313                 cbpitch |= R300_COLOR_TILE_ENABLE;
 314
 315         BEGIN_BATCH(4);
 316         OUT_BATCH_REGSEQ(R300_RB3D_COLOROFFSET0, 1);
 317         OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
 318         OUT_BATCH_REGSEQ(R300_RB3D_COLORPITCH0, 1);
 319         OUT_BATCH(cbpitch);
 320         END_BATCH();
 321 }
 322
 323 static void emit_zb_offset(GLcontext *ctx, struct radeon_state_atom * atom)
 324 {
 325         r300ContextPtr r300 = R300_CONTEXT(ctx);
 326         BATCH_LOCALS(&r300->radeon);
 327         struct radeon_renderbuffer *rrb;
 328         uint32_t zbpitch;
 329
 330         rrb = radeon_get_depthbuffer(&r300->radeon);
 331         if (!rrb)
 332                 return;
 333
 334         zbpitch = (rrb->pitch / rrb->cpp);
 335         if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE) {
 336                 zbpitch |= R300_DEPTHMACROTILE_ENABLE;
 337         }
 338         if (rrb->bo->flags & RADEON_BO_FLAGS_MICRO_TILE){
 339                 zbpitch |= R300_DEPTHMICROTILE_TILED;
 340         }
 341
 342         BEGIN_BATCH(4);
 343         OUT_BATCH_REGSEQ(R300_ZB_DEPTHOFFSET, 1);
 344         OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
 345         OUT_BATCH_REGVAL(R300_ZB_DEPTHPITCH, zbpitch);
 346         END_BATCH();
 347 }
 348
 349 static int check_always(GLcontext *ctx, struct radeon_state_atom *atom)
 350 {
 351         return atom->cmd_size;
 352 }
 353
 354 static int check_variable(GLcontext *ctx, struct radeon_state_atom *atom)
 355 {
 356         r300ContextPtr r300 = R300_CONTEXT(ctx);
 357         int cnt;
 358         if (atom->cmd[0] == CP_PACKET2) {
 359                 return 0;
 360         }
 361         cnt = packet0_count(r300, atom->cmd);
 362         return cnt ? cnt + 1 : 0;
 363 }
 364
 365 int check_vpu(GLcontext *ctx, struct radeon_state_atom *atom)
 366 {
 367         int cnt;
 368
 369         cnt = vpu_count(atom->cmd);
 370         return cnt ? (cnt * 4) + 1 : 0;
 371 }
 372
 373 int check_r500fp(GLcontext *ctx, struct radeon_state_atom *atom)
 374 {
 375         int cnt;
 376
 377         cnt = r500fp_count(atom->cmd);
 378         return cnt ? (cnt * 6) + 1 : 0;
 379 }
 380
 381 int check_r500fp_const(GLcontext *ctx, struct radeon_state_atom *atom)
 382 {
 383         int cnt;
 384
 385         cnt = r500fp_count(atom->cmd);
 386         return cnt ? (cnt * 4) + 1 : 0;
 387 }
 388
 389 #define ALLOC_STATE( ATOM, CHK, SZ, IDX )                               \
 390    do {                                                                 \
 391       r300->hw.ATOM.cmd_size = (SZ);                                    \
 392       r300->hw.ATOM.cmd = (uint32_t*)CALLOC((SZ) * sizeof(uint32_t));   \
 393       r300->hw.ATOM.name = #ATOM;                                       \
 394       r300->hw.ATOM.idx = (IDX);                                        \
 395       r300->hw.ATOM.check = check_##CHK;                                \
 396       r300->hw.ATOM.dirty = GL_FALSE;                                   \
 397       r300->hw.max_state_size += (SZ);                                  \
 398       insert_at_tail(&r300->hw.atomlist, &r300->hw.ATOM);               \
 399    } while (0)
 400 /**
 401  * Allocate memory for the command buffer and initialize the state atom
 402  * list. Note that the initial hardware state is set by r300InitState().
 403  */
 404 void r300InitCmdBuf(r300ContextPtr r300)
 405 {
 406         int mtu;
 407         int has_tcl = 1;
 408         int is_r500 = 0;
 409         int i;
 410
 411         if (!(r300->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL))
 412                 has_tcl = 0;
 413
 414         if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515)
 415                 is_r500 = 1;
 416
 417         r300->hw.max_state_size = 2 + 2;        /* reserve extra space for WAIT_IDLE and tex cache flush */
 418
 419         mtu = r300->radeon.glCtx->Const.MaxTextureUnits;
 420         if (RADEON_DEBUG & DEBUG_TEXTURE) {
 421                 fprintf(stderr, "Using %d maximum texture units..\n", mtu);
 422         }
 423
 424         /* Setup the atom linked list */
 425         make_empty_list(&r300->hw.atomlist);
 426         r300->hw.atomlist.name = "atom-list";
 427
 428         /* Initialize state atoms */
 429         ALLOC_STATE(vpt, always, R300_VPT_CMDSIZE, 0);
 430         r300->hw.vpt.cmd[R300_VPT_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_SE_VPORT_XSCALE, 6);
 431         ALLOC_STATE(vap_cntl, always, R300_VAP_CNTL_SIZE, 0);
 432         r300->hw.vap_cntl.cmd[R300_VAP_CNTL_FLUSH] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PVS_STATE_FLUSH_REG, 1);
 433         r300->hw.vap_cntl.cmd[R300_VAP_CNTL_FLUSH_1] = 0;
 434         r300->hw.vap_cntl.cmd[R300_VAP_CNTL_CMD] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_CNTL, 1);
 435         if (is_r500) {
 436             ALLOC_STATE(vap_index_offset, always, 2, 0);
 437             r300->hw.vap_index_offset.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R500_VAP_INDEX_OFFSET, 1);
 438             r300->hw.vap_index_offset.cmd[1] = 0;
 439         }
 440         ALLOC_STATE(vte, always, 3, 0);
 441         r300->hw.vte.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SE_VTE_CNTL, 2);
 442         ALLOC_STATE(vap_vf_max_vtx_indx, always, 3, 0);
 443         r300->hw.vap_vf_max_vtx_indx.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_VF_MAX_VTX_INDX, 2);
 444         ALLOC_STATE(vap_cntl_status, always, 2, 0);
 445         r300->hw.vap_cntl_status.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_CNTL_STATUS, 1);
 446         ALLOC_STATE(vir[0], variable, R300_VIR_CMDSIZE, 0);
 447         r300->hw.vir[0].cmd[R300_VIR_CMD_0] =
 448             cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PROG_STREAM_CNTL_0, 1);
 449         ALLOC_STATE(vir[1], variable, R300_VIR_CMDSIZE, 1);
 450         r300->hw.vir[1].cmd[R300_VIR_CMD_0] =
 451             cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PROG_STREAM_CNTL_EXT_0, 1);
 452         ALLOC_STATE(vic, always, R300_VIC_CMDSIZE, 0);
 453         r300->hw.vic.cmd[R300_VIC_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_VTX_STATE_CNTL, 2);
 454         ALLOC_STATE(vap_psc_sgn_norm_cntl, always, 2, 0);
 455         r300->hw.vap_psc_sgn_norm_cntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PSC_SGN_NORM_CNTL, SGN_NORM_ZERO_CLAMP_MINUS_ONE);
 456
 457         if (has_tcl) {
 458                 ALLOC_STATE(vap_clip_cntl, always, 2, 0);
 459                 r300->hw.vap_clip_cntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_CLIP_CNTL, 1);
 460                 ALLOC_STATE(vap_clip, always, 5, 0);
 461                 r300->hw.vap_clip.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_GB_VERT_CLIP_ADJ, 4);
 462                 ALLOC_STATE(vap_pvs_vtx_timeout_reg, always, 2, 0);
 463                 r300->hw.vap_pvs_vtx_timeout_reg.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, VAP_PVS_VTX_TIMEOUT_REG, 1);
 464         }
 465
 466         ALLOC_STATE(vof, always, R300_VOF_CMDSIZE, 0);
 467         r300->hw.vof.cmd[R300_VOF_CMD_0] =
 468             cmdpacket0(r300->radeon.radeonScreen, R300_VAP_OUTPUT_VTX_FMT_0, 2);
 469
 470         if (has_tcl) {
 471                 ALLOC_STATE(pvs, always, R300_PVS_CMDSIZE, 0);
 472                 r300->hw.pvs.cmd[R300_PVS_CMD_0] =
 473                     cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PVS_CODE_CNTL_0, 3);
 474         }
 475
 476         ALLOC_STATE(gb_enable, always, 2, 0);
 477         r300->hw.gb_enable.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GB_ENABLE, 1);
 478         ALLOC_STATE(gb_misc, always, R300_GB_MISC_CMDSIZE, 0);
 479         r300->hw.gb_misc.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GB_MSPOS0, 5);
 480         ALLOC_STATE(txe, always, R300_TXE_CMDSIZE, 0);
 481         r300->hw.txe.cmd[R300_TXE_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_TX_ENABLE, 1);
 482         ALLOC_STATE(ga_point_s0, always, 5, 0);
 483         r300->hw.ga_point_s0.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_POINT_S0, 4);
 484         ALLOC_STATE(ga_triangle_stipple, always, 2, 0);
 485         r300->hw.ga_triangle_stipple.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_TRIANGLE_STIPPLE, 1);
 486         ALLOC_STATE(ps, always, R300_PS_CMDSIZE, 0);
 487         r300->hw.ps.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_POINT_SIZE, 1);
 488         ALLOC_STATE(ga_point_minmax, always, 4, 0);
 489         r300->hw.ga_point_minmax.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_POINT_MINMAX, 3);
 490         ALLOC_STATE(lcntl, always, 2, 0);
 491         r300->hw.lcntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_LINE_CNTL, 1);
 492         ALLOC_STATE(ga_line_stipple, always, 4, 0);
 493         r300->hw.ga_line_stipple.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_LINE_STIPPLE_VALUE, 3);
 494         ALLOC_STATE(shade, always, 5, 0);
 495         r300->hw.shade.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_ENHANCE, 4);
 496         ALLOC_STATE(polygon_mode, always, 4, 0);
 497         r300->hw.polygon_mode.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_POLY_MODE, 3);
 498         ALLOC_STATE(fogp, always, 3, 0);
 499         r300->hw.fogp.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_FOG_SCALE, 2);
 500         ALLOC_STATE(zbias_cntl, always, 2, 0);
 501         r300->hw.zbias_cntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SU_TEX_WRAP, 1);
 502         ALLOC_STATE(zbs, always, R300_ZBS_CMDSIZE, 0);
 503         r300->hw.zbs.cmd[R300_ZBS_CMD_0] =
 504             cmdpacket0(r300->radeon.radeonScreen, R300_SU_POLY_OFFSET_FRONT_SCALE, 4);
 505         ALLOC_STATE(occlusion_cntl, always, 2, 0);
 506         r300->hw.occlusion_cntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SU_POLY_OFFSET_ENABLE, 1);
 507         ALLOC_STATE(cul, always, R300_CUL_CMDSIZE, 0);
 508         r300->hw.cul.cmd[R300_CUL_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_SU_CULL_MODE, 1);
 509         ALLOC_STATE(su_depth_scale, always, 3, 0);
 510         r300->hw.su_depth_scale.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SU_DEPTH_SCALE, 2);
 511         ALLOC_STATE(rc, always, R300_RC_CMDSIZE, 0);
 512         r300->hw.rc.cmd[R300_RC_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RS_COUNT, 2);
 513         if (is_r500) {
 514                 ALLOC_STATE(ri, always, R500_RI_CMDSIZE, 0);
 515                 r300->hw.ri.cmd[R300_RI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R500_RS_IP_0, 16);
 516                 for (i = 0; i < 8; i++) {
 517                         r300->hw.ri.cmd[R300_RI_CMD_0 + i +1] =
 518                           (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_S_SHIFT) |
 519                           (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_T_SHIFT) |
 520                           (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT) |
 521                           (R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT);
 522                 }
 523                 ALLOC_STATE(rr, variable, R300_RR_CMDSIZE, 0);
 524                 r300->hw.rr.cmd[R300_RR_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R500_RS_INST_0, 1);
 525         } else {
 526                 ALLOC_STATE(ri, always, R300_RI_CMDSIZE, 0);
 527                 r300->hw.ri.cmd[R300_RI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RS_IP_0, 8);
 528                 ALLOC_STATE(rr, variable, R300_RR_CMDSIZE, 0);
 529                 r300->hw.rr.cmd[R300_RR_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RS_INST_0, 1);
 530         }
 531         ALLOC_STATE(sc_hyperz, always, 3, 0);
 532         r300->hw.sc_hyperz.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SC_HYPERZ, 2);
 533         ALLOC_STATE(sc_screendoor, always, 2, 0);
 534         r300->hw.sc_screendoor.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SC_SCREENDOOR, 1);
 535         ALLOC_STATE(us_out_fmt, always, 6, 0);
 536         r300->hw.us_out_fmt.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_OUT_FMT, 5);
 537
 538         if (is_r500) {
 539                 ALLOC_STATE(fp, always, R500_FP_CMDSIZE, 0);
 540                 r300->hw.fp.cmd[R500_FP_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R500_US_CONFIG, 2);
 541                 r300->hw.fp.cmd[R500_FP_CNTL] = R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO;
 542                 r300->hw.fp.cmd[R500_FP_CMD_1] = cmdpacket0(r300->radeon.radeonScreen, R500_US_CODE_ADDR, 3);
 543                 r300->hw.fp.cmd[R500_FP_CMD_2] = cmdpacket0(r300->radeon.radeonScreen, R500_US_FC_CTRL, 1);
 544                 r300->hw.fp.cmd[R500_FP_FC_CNTL] = 0; /* FIXME when we add flow control */
 545
 546                 ALLOC_STATE(r500fp, r500fp, R500_FPI_CMDSIZE, 0);
 547                 r300->hw.r500fp.cmd[R300_FPI_CMD_0] =
 548                         cmdr500fp(r300->radeon.radeonScreen, 0, 0, 0, 0);
 549                 r300->hw.r500fp.emit = emit_r500fp;
 550                 ALLOC_STATE(r500fp_const, r500fp_const, R500_FPP_CMDSIZE, 0);
 551                 r300->hw.r500fp_const.cmd[R300_FPI_CMD_0] =
 552                         cmdr500fp(r300->radeon.radeonScreen, 0, 0, 1, 0);
 553                 r300->hw.r500fp_const.emit = emit_r500fp;
 554         } else {
 555                 ALLOC_STATE(fp, always, R300_FP_CMDSIZE, 0);
 556                 r300->hw.fp.cmd[R300_FP_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_CONFIG, 3);
 557                 r300->hw.fp.cmd[R300_FP_CMD_1] = cmdpacket0(r300->radeon.radeonScreen, R300_US_CODE_ADDR_0, 4);
 558
 559                 ALLOC_STATE(fpt, variable, R300_FPT_CMDSIZE, 0);
 560                 r300->hw.fpt.cmd[R300_FPT_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_TEX_INST_0, 0);
 561
 562                 ALLOC_STATE(fpi[0], variable, R300_FPI_CMDSIZE, 0);
 563                 r300->hw.fpi[0].cmd[R300_FPI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_ALU_RGB_INST_0, 1);
 564                 ALLOC_STATE(fpi[1], variable, R300_FPI_CMDSIZE, 1);
 565                 r300->hw.fpi[1].cmd[R300_FPI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_ALU_RGB_ADDR_0, 1);
 566                 ALLOC_STATE(fpi[2], variable, R300_FPI_CMDSIZE, 2);
 567                 r300->hw.fpi[2].cmd[R300_FPI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_ALU_ALPHA_INST_0, 1);
 568                 ALLOC_STATE(fpi[3], variable, R300_FPI_CMDSIZE, 3);
 569                 r300->hw.fpi[3].cmd[R300_FPI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_ALU_ALPHA_ADDR_0, 1);
 570                 ALLOC_STATE(fpp, variable, R300_FPP_CMDSIZE, 0);
 571                 r300->hw.fpp.cmd[R300_FPP_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_PFS_PARAM_0_X, 0);
 572         }
 573         ALLOC_STATE(fogs, always, R300_FOGS_CMDSIZE, 0);
 574         r300->hw.fogs.cmd[R300_FOGS_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_FG_FOG_BLEND, 1);
 575         ALLOC_STATE(fogc, always, R300_FOGC_CMDSIZE, 0);
 576         r300->hw.fogc.cmd[R300_FOGC_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_FG_FOG_COLOR_R, 3);
 577         ALLOC_STATE(at, always, R300_AT_CMDSIZE, 0);
 578         r300->hw.at.cmd[R300_AT_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_FG_ALPHA_FUNC, 2);
 579         ALLOC_STATE(fg_depth_src, always, 2, 0);
 580         r300->hw.fg_depth_src.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_FG_DEPTH_SRC, 1);
 581         ALLOC_STATE(rb3d_cctl, always, 2, 0);
 582         r300->hw.rb3d_cctl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_CCTL, 1);
 583         ALLOC_STATE(bld, always, R300_BLD_CMDSIZE, 0);
 584         r300->hw.bld.cmd[R300_BLD_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_CBLEND, 2);
 585         ALLOC_STATE(cmk, always, R300_CMK_CMDSIZE, 0);
 586         r300->hw.cmk.cmd[R300_CMK_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, RB3D_COLOR_CHANNEL_MASK, 1);
 587         if (is_r500) {
 588                 ALLOC_STATE(blend_color, always, 3, 0);
 589                 r300->hw.blend_color.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R500_RB3D_CONSTANT_COLOR_AR, 2);
 590         } else {
 591                 ALLOC_STATE(blend_color, always, 2, 0);
 592                 r300->hw.blend_color.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_BLEND_COLOR, 1);
 593         }
 594         ALLOC_STATE(rop, always, 2, 0);
 595         r300->hw.rop.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_ROPCNTL, 1);
 596         ALLOC_STATE(cb, always, R300_CB_CMDSIZE, 0);
 597         r300->hw.cb.emit = &emit_cb_offset;
 598         ALLOC_STATE(rb3d_dither_ctl, always, 10, 0);
 599         r300->hw.rb3d_dither_ctl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_DITHER_CTL, 9);
 600         ALLOC_STATE(rb3d_aaresolve_ctl, always, 2, 0);
 601         r300->hw.rb3d_aaresolve_ctl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_AARESOLVE_CTL, 1);
 602         ALLOC_STATE(rb3d_discard_src_pixel_lte_threshold, always, 3, 0);
 603         r300->hw.rb3d_discard_src_pixel_lte_threshold.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R500_RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD, 2);
 604         ALLOC_STATE(zs, always, R300_ZS_CMDSIZE, 0);
 605         r300->hw.zs.cmd[R300_ZS_CMD_0] =
 606             cmdpacket0(r300->radeon.radeonScreen, R300_ZB_CNTL, 3);
 607         ALLOC_STATE(zstencil_format, always, 5, 0);
 608         r300->hw.zstencil_format.cmd[0] =
 609             cmdpacket0(r300->radeon.radeonScreen, R300_ZB_FORMAT, 4);
 610         ALLOC_STATE(zb, always, R300_ZB_CMDSIZE, 0);
 611         r300->hw.zb.emit = emit_zb_offset;
 612         ALLOC_STATE(zb_depthclearvalue, always, 2, 0);
 613         r300->hw.zb_depthclearvalue.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_ZB_DEPTHCLEARVALUE, 1);
 614         ALLOC_STATE(unk4F30, always, 3, 0);
 615         r300->hw.unk4F30.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, 0x4F30, 2);
 616         ALLOC_STATE(zb_hiz_offset, always, 2, 0);
 617         r300->hw.zb_hiz_offset.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_ZB_HIZ_OFFSET, 1);
 618         ALLOC_STATE(zb_hiz_pitch, always, 2, 0);
 619         r300->hw.zb_hiz_pitch.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_ZB_HIZ_PITCH, 1);
 620
 621         /* VPU only on TCL */
 622         if (has_tcl) {
 623                 int i;
 624                 ALLOC_STATE(vpi, vpu, R300_VPI_CMDSIZE, 0);
 625                 r300->hw.vpi.cmd[0] =
 626                     cmdvpu(r300->radeon.radeonScreen, R300_PVS_CODE_START, 0);
 627                 r300->hw.vpi.emit = emit_vpu;
 628
 629                 if (is_r500) {
 630                     ALLOC_STATE(vpp, vpu, R300_VPP_CMDSIZE, 0);
 631                     r300->hw.vpp.cmd[0] =
 632                         cmdvpu(r300->radeon.radeonScreen, R500_PVS_CONST_START, 0);
 633                     r300->hw.vpp.emit = emit_vpu;
 634
 635                     ALLOC_STATE(vps, vpu, R300_VPS_CMDSIZE, 0);
 636                     r300->hw.vps.cmd[0] =
 637                         cmdvpu(r300->radeon.radeonScreen, R500_POINT_VPORT_SCALE_OFFSET, 1);
 638                     r300->hw.vps.emit = emit_vpu;
 639
 640                         for (i = 0; i < 6; i++) {
 641                           ALLOC_STATE(vpucp[i], vpu, R300_VPUCP_CMDSIZE, 0);
 642                           r300->hw.vpucp[i].cmd[0] =
 643                                   cmdvpu(r300->radeon.radeonScreen,
 644                            R500_PVS_UCP_START + i, 1);
 645                                 r300->hw.vpucp[i].emit = emit_vpu;
 646                         }
 647                 } else {
 648                     ALLOC_STATE(vpp, vpu, R300_VPP_CMDSIZE, 0);
 649                     r300->hw.vpp.cmd[0] =
 650                         cmdvpu(r300->radeon.radeonScreen, R300_PVS_CONST_START, 0);
 651                     r300->hw.vpp.emit = emit_vpu;
 652
 653                     ALLOC_STATE(vps, vpu, R300_VPS_CMDSIZE, 0);
 654                     r300->hw.vps.cmd[0] =
 655                         cmdvpu(r300->radeon.radeonScreen, R300_POINT_VPORT_SCALE_OFFSET, 1);
 656                     r300->hw.vps.emit = emit_vpu;
 657
 658                         for (i = 0; i < 6; i++) {
 659                                 ALLOC_STATE(vpucp[i], vpu, R300_VPUCP_CMDSIZE, 0);
 660                                 r300->hw.vpucp[i].cmd[0] =
 661                                         cmdvpu(r300->radeon.radeonScreen,
 662                                                R300_PVS_UCP_START + i, 1);
 663                                 r300->hw.vpucp[i].emit = emit_vpu;
 664                         }
 665                 }
 666         }
 667
 668         /* Textures */
 669         ALLOC_STATE(tex.filter, variable, mtu + 1, 0);
 670         r300->hw.tex.filter.cmd[R300_TEX_CMD_0] =
 671             cmdpacket0(r300->radeon.radeonScreen, R300_TX_FILTER0_0, 0);
 672
 673         ALLOC_STATE(tex.filter_1, variable, mtu + 1, 0);
 674         r300->hw.tex.filter_1.cmd[R300_TEX_CMD_0] =
 675             cmdpacket0(r300->radeon.radeonScreen, R300_TX_FILTER1_0, 0);
 676
 677         ALLOC_STATE(tex.size, variable, mtu + 1, 0);
 678         r300->hw.tex.size.cmd[R300_TEX_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_TX_SIZE_0, 0);
 679
 680         ALLOC_STATE(tex.format, variable, mtu + 1, 0);
 681         r300->hw.tex.format.cmd[R300_TEX_CMD_0] =
 682             cmdpacket0(r300->radeon.radeonScreen, R300_TX_FORMAT_0, 0);
 683
 684         ALLOC_STATE(tex.pitch, variable, mtu + 1, 0);
 685         r300->hw.tex.pitch.cmd[R300_TEX_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_TX_FORMAT2_0, 0);
 686
 687         ALLOC_STATE(tex.offset, variable, 1, 0);
 688         r300->hw.tex.offset.cmd[R300_TEX_CMD_0] =
 689             cmdpacket0(r300->radeon.radeonScreen, R300_TX_OFFSET_0, 0);
 690         r300->hw.tex.offset.emit = &emit_tex_offsets;
 691
 692         ALLOC_STATE(tex.chroma_key, variable, mtu + 1, 0);
 693         r300->hw.tex.chroma_key.cmd[R300_TEX_CMD_0] =
 694             cmdpacket0(r300->radeon.radeonScreen, R300_TX_CHROMA_KEY_0, 0);
 695
 696         ALLOC_STATE(tex.border_color, variable, mtu + 1, 0);
 697         r300->hw.tex.border_color.cmd[R300_TEX_CMD_0] =
 698             cmdpacket0(r300->radeon.radeonScreen, R300_TX_BORDER_COLOR_0, 0);
 699
 700         r300->hw.is_dirty = GL_TRUE;
 701         r300->hw.all_dirty = GL_TRUE;
 702
 703         rcommonInitCmdBuf(&r300->radeon, r300->hw.max_state_size);
 704 }
 705
 706 /**
 707  * Destroy the command buffer and state atoms.
 708  */
 709 void r300DestroyCmdBuf(r300ContextPtr r300)
 710 {
 711         struct radeon_state_atom *atom;
 712
 713         foreach(atom, &r300->hw.atomlist) {
 714                 FREE(atom->cmd);
 715         }
 716         rcommonDestroyCmdBuf(&r300->radeon);
 717
 718 }