2 Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
4 The Weather Channel (TM) funded Tungsten Graphics to develop the
5 initial release of the Radeon 8500 driver under the XFree86 license.
6 This notice must be preserved.
8 Permission is hereby granted, free of charge, to any person obtaining
9 a copy of this software and associated documentation files (the
10 "Software"), to deal in the Software without restriction, including
11 without limitation the rights to use, copy, modify, merge, publish,
12 distribute, sublicense, and/or sell copies of the Software, and to
13 permit persons to whom the Software is furnished to do so, subject to
14 the following conditions:
16 The above copyright notice and this permission notice (including the
17 next paragraph) shall be included in all copies or substantial
18 portions of the Software.
20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
28 **************************************************************************/
33 * \author Nicolai Haehnle <prefect_@gmx.net>
36 #include "main/glheader.h"
37 #include "main/state.h"
38 #include "main/imports.h"
39 #include "main/macros.h"
40 #include "main/context.h"
41 #include "main/simple_list.h"
42 #include "swrast/swrast.h"
45 #include "radeon_drm.h"
47 #include "r300_context.h"
48 #include "r300_ioctl.h"
50 #include "r300_cmdbuf.h"
51 #include "r300_emit.h"
52 #include "radeon_bocs_wrapper.h"
53 #include "radeon_mipmap_tree.h"
54 #include "r300_state.h"
55 #include "radeon_queryobj.h"
57 /** # of dwords reserved for additional instructions that may need to be written
60 #define SPACE_FOR_FLUSHING 4
62 static unsigned packet0_count(r300ContextPtr r300
, uint32_t *pkt
)
64 if (r300
->radeon
.radeonScreen
->kernel_mm
) {
65 return ((((*pkt
) >> 16) & 0x3FFF) + 1);
67 drm_r300_cmd_header_t
*t
= (drm_r300_cmd_header_t
*)pkt
;
68 return t
->packet0
.count
;
72 #define vpu_count(ptr) (((drm_r300_cmd_header_t*)(ptr))->vpu.count)
73 #define r500fp_count(ptr) (((drm_r300_cmd_header_t*)(ptr))->r500fp.count)
75 int check_vpu(GLcontext
*ctx
, struct radeon_state_atom
*atom
)
77 r300ContextPtr r300
= R300_CONTEXT(ctx
);
80 cnt
= vpu_count(atom
->cmd
);
82 if (r300
->radeon
.radeonScreen
->kernel_mm
) {
86 return cnt
? (cnt
* 4) + extra
: 0;
90 void emit_vpu(GLcontext
*ctx
, struct radeon_state_atom
* atom
)
92 r300ContextPtr r300
= R300_CONTEXT(ctx
);
93 BATCH_LOCALS(&r300
->radeon
);
94 drm_r300_cmd_header_t cmd
;
98 addr
= (cmd
.vpu
.adrhi
<< 8) | cmd
.vpu
.adrlo
;
99 ndw
= atom
->check(ctx
, atom
);
101 BEGIN_BATCH_NO_AUTOSTATE(ndw
);
104 OUT_BATCH_REGVAL(R300_VAP_PVS_VECTOR_INDX_REG
, addr
);
105 OUT_BATCH(CP_PACKET0(R300_VAP_PVS_UPLOAD_DATA
, ndw
-1) | RADEON_ONE_REG_WR
);
106 OUT_BATCH_TABLE(&atom
->cmd
[1], ndw
);
107 OUT_BATCH_REGVAL(R300_VAP_PVS_STATE_FLUSH_REG
, 0);
111 void emit_r500fp(GLcontext
*ctx
, struct radeon_state_atom
* atom
)
113 r300ContextPtr r300
= R300_CONTEXT(ctx
);
114 BATCH_LOCALS(&r300
->radeon
);
115 drm_r300_cmd_header_t cmd
;
116 uint32_t addr
, ndw
, sz
;
119 ndw
= atom
->check(ctx
, atom
);
121 cmd
.u
= atom
->cmd
[0];
122 sz
= cmd
.r500fp
.count
;
123 addr
= ((cmd
.r500fp
.adrhi_flags
& 1) << 8) | cmd
.r500fp
.adrlo
;
124 type
= !!(cmd
.r500fp
.adrhi_flags
& R500FP_CONSTANT_TYPE
);
125 clamp
= !!(cmd
.r500fp
.adrhi_flags
& R500FP_CONSTANT_CLAMP
);
127 addr
|= (type
<< 16);
128 addr
|= (clamp
<< 17);
130 BEGIN_BATCH_NO_AUTOSTATE(ndw
);
131 OUT_BATCH(CP_PACKET0(R500_GA_US_VECTOR_INDEX
, 0));
134 OUT_BATCH(CP_PACKET0(R500_GA_US_VECTOR_DATA
, ndw
-1) | RADEON_ONE_REG_WR
);
135 OUT_BATCH_TABLE(&atom
->cmd
[1], ndw
);
139 static int check_tex_offsets(GLcontext
*ctx
, struct radeon_state_atom
* atom
)
141 r300ContextPtr r300
= R300_CONTEXT(ctx
);
142 int numtmus
= packet0_count(r300
, r300
->hw
.tex
.offset
.cmd
);
144 if (atom
->cmd
[0] == CP_PACKET2
) {
147 for(i
= 0; i
< numtmus
; ++i
) {
148 radeonTexObj
*t
= r300
->hw
.textures
[i
];
149 if (!t
&& !r300
->radeon
.radeonScreen
->kernel_mm
) {
151 } else if (t
&& t
->image_override
&& !t
->bo
) {
152 if (!r300
->radeon
.radeonScreen
->kernel_mm
)
160 static void emit_tex_offsets(GLcontext
*ctx
, struct radeon_state_atom
* atom
)
162 r300ContextPtr r300
= R300_CONTEXT(ctx
);
163 BATCH_LOCALS(&r300
->radeon
);
164 int numtmus
= packet0_count(r300
, r300
->hw
.tex
.offset
.cmd
);
167 for(i
= 0; i
< numtmus
; ++i
) {
168 radeonTexObj
*t
= r300
->hw
.textures
[i
];
169 if (t
&& !t
->image_override
) {
170 BEGIN_BATCH_NO_AUTOSTATE(4);
171 OUT_BATCH_REGSEQ(R300_TX_OFFSET_0
+ (i
* 4), 1);
172 OUT_BATCH_RELOC(t
->tile_bits
, t
->mt
->bo
, get_base_teximage_offset(t
),
173 RADEON_GEM_DOMAIN_GTT
|RADEON_GEM_DOMAIN_VRAM
, 0, 0);
176 /* Texture unit hasn't a texture bound.
177 * We assign the current color buffer as a fakery to make
178 * KIL work on KMS (without it, the CS checker will complain).
180 if (r300
->radeon
.radeonScreen
->kernel_mm
) {
181 struct radeon_renderbuffer
*rrb
= radeon_get_colorbuffer(&r300
->radeon
);
182 if (rrb
&& rrb
->bo
) {
183 BEGIN_BATCH_NO_AUTOSTATE(4);
184 OUT_BATCH_REGSEQ(R300_TX_OFFSET_0
+ (i
* 4), 1);
185 OUT_BATCH_RELOC(0, rrb
->bo
, 0,
186 RADEON_GEM_DOMAIN_GTT
|RADEON_GEM_DOMAIN_VRAM
, 0, 0);
190 } else { /* override cases */
192 BEGIN_BATCH_NO_AUTOSTATE(4);
193 OUT_BATCH_REGSEQ(R300_TX_OFFSET_0
+ (i
* 4), 1);
194 OUT_BATCH_RELOC(t
->tile_bits
, t
->bo
, 0,
195 RADEON_GEM_DOMAIN_GTT
|RADEON_GEM_DOMAIN_VRAM
, 0, 0);
197 } else if (!r300
->radeon
.radeonScreen
->kernel_mm
) {
198 BEGIN_BATCH_NO_AUTOSTATE(2);
199 OUT_BATCH_REGSEQ(R300_TX_OFFSET_0
+ (i
* 4), 1);
200 OUT_BATCH(t
->override_offset
);
203 /* Texture unit hasn't a texture bound nothings to do */
209 void r300_emit_scissor(GLcontext
*ctx
)
211 r300ContextPtr r300
= R300_CONTEXT(ctx
);
212 BATCH_LOCALS(&r300
->radeon
);
213 unsigned x1
, y1
, x2
, y2
;
214 struct radeon_renderbuffer
*rrb
;
216 if (!r300
->radeon
.radeonScreen
->driScreen
->dri2
.enabled
) {
219 rrb
= radeon_get_colorbuffer(&r300
->radeon
);
220 if (!rrb
|| !rrb
->bo
) {
221 fprintf(stderr
, "no rrb\n");
224 if (r300
->radeon
.state
.scissor
.enabled
) {
225 x1
= r300
->radeon
.state
.scissor
.rect
.x1
;
226 y1
= r300
->radeon
.state
.scissor
.rect
.y1
;
227 x2
= r300
->radeon
.state
.scissor
.rect
.x2
;
228 y2
= r300
->radeon
.state
.scissor
.rect
.y2
;
232 x2
= rrb
->base
.Width
- 1;
233 y2
= rrb
->base
.Height
- 1;
235 if (r300
->radeon
.radeonScreen
->chip_family
< CHIP_FAMILY_RV515
) {
236 x1
+= R300_SCISSORS_OFFSET
;
237 y1
+= R300_SCISSORS_OFFSET
;
238 x2
+= R300_SCISSORS_OFFSET
;
239 y2
+= R300_SCISSORS_OFFSET
;
241 BEGIN_BATCH_NO_AUTOSTATE(3);
242 OUT_BATCH_REGSEQ(R300_SC_SCISSORS_TL
, 2);
243 OUT_BATCH((x1
<< R300_SCISSORS_X_SHIFT
)|(y1
<< R300_SCISSORS_Y_SHIFT
));
244 OUT_BATCH((x2
<< R300_SCISSORS_X_SHIFT
)|(y2
<< R300_SCISSORS_Y_SHIFT
));
247 static int check_cb_offset(GLcontext
*ctx
, struct radeon_state_atom
* atom
)
249 r300ContextPtr r300
= R300_CONTEXT(ctx
);
250 uint32_t dw
= 6 + 3 + 16;
251 if (r300
->radeon
.radeonScreen
->kernel_mm
)
253 if (!r300
->radeon
.radeonScreen
->driScreen
->dri2
.enabled
) {
259 static void emit_cb_offset(GLcontext
*ctx
, struct radeon_state_atom
* atom
)
261 r300ContextPtr r300
= R300_CONTEXT(ctx
);
262 BATCH_LOCALS(&r300
->radeon
);
263 struct radeon_renderbuffer
*rrb
;
265 uint32_t offset
= r300
->radeon
.state
.color
.draw_offset
;
269 rrb
= radeon_get_colorbuffer(&r300
->radeon
);
270 if (!rrb
|| !rrb
->bo
) {
271 fprintf(stderr
, "no rrb\n");
275 if (RADEON_DEBUG
& RADEON_STATE
)
276 fprintf(stderr
,"rrb is %p %d %dx%d\n", rrb
, offset
, rrb
->base
.Width
, rrb
->base
.Height
);
277 cbpitch
= (rrb
->pitch
/ rrb
->cpp
);
279 cbpitch
|= R300_COLOR_FORMAT_ARGB8888
;
280 else switch (rrb
->base
.Format
) {
281 case MESA_FORMAT_RGB565
:
282 assert(_mesa_little_endian());
283 cbpitch
|= R300_COLOR_FORMAT_RGB565
;
285 case MESA_FORMAT_RGB565_REV
:
286 assert(!_mesa_little_endian());
287 cbpitch
|= R300_COLOR_FORMAT_RGB565
;
289 case MESA_FORMAT_ARGB4444
:
290 assert(_mesa_little_endian());
291 cbpitch
|= R300_COLOR_FORMAT_ARGB4444
;
293 case MESA_FORMAT_ARGB4444_REV
:
294 assert(!_mesa_little_endian());
295 cbpitch
|= R300_COLOR_FORMAT_ARGB4444
;
297 case MESA_FORMAT_ARGB1555
:
298 assert(_mesa_little_endian());
299 cbpitch
|= R300_COLOR_FORMAT_ARGB1555
;
301 case MESA_FORMAT_ARGB1555_REV
:
302 assert(!_mesa_little_endian());
303 cbpitch
|= R300_COLOR_FORMAT_ARGB1555
;
306 _mesa_problem(ctx
, "unexpected format in emit_cb_offset()");
309 if (rrb
->bo
->flags
& RADEON_BO_FLAGS_MACRO_TILE
)
310 cbpitch
|= R300_COLOR_TILE_ENABLE
;
312 if (r300
->radeon
.radeonScreen
->kernel_mm
)
314 BEGIN_BATCH_NO_AUTOSTATE(dw
);
315 OUT_BATCH_REGSEQ(R300_RB3D_COLOROFFSET0
, 1);
316 OUT_BATCH_RELOC(offset
, rrb
->bo
, offset
, 0, RADEON_GEM_DOMAIN_VRAM
, 0);
317 OUT_BATCH_REGSEQ(R300_RB3D_COLORPITCH0
, 1);
318 if (!r300
->radeon
.radeonScreen
->kernel_mm
)
321 OUT_BATCH_RELOC(cbpitch
, rrb
->bo
, cbpitch
, 0, RADEON_GEM_DOMAIN_VRAM
, 0);
323 if (r300
->radeon
.radeonScreen
->driScreen
->dri2
.enabled
) {
324 if (r300
->radeon
.radeonScreen
->chip_family
>= CHIP_FAMILY_RV515
) {
325 BEGIN_BATCH_NO_AUTOSTATE(3);
326 OUT_BATCH_REGSEQ(R300_SC_SCISSORS_TL
, 2);
328 OUT_BATCH(((rrb
->base
.Width
- 1) << R300_SCISSORS_X_SHIFT
) |
329 ((rrb
->base
.Height
- 1) << R300_SCISSORS_Y_SHIFT
));
331 BEGIN_BATCH_NO_AUTOSTATE(16);
332 for (i
= 0; i
< 4; i
++) {
333 OUT_BATCH_REGSEQ(R300_SC_CLIPRECT_TL_0
+ (i
* 8), 2);
334 OUT_BATCH((0 << R300_CLIPRECT_X_SHIFT
) | (0 << R300_CLIPRECT_Y_SHIFT
));
335 OUT_BATCH(((rrb
->base
.Width
- 1) << R300_CLIPRECT_X_SHIFT
) | ((rrb
->base
.Height
- 1) << R300_CLIPRECT_Y_SHIFT
));
337 OUT_BATCH_REGSEQ(R300_SC_CLIP_RULE
, 1);
339 OUT_BATCH_REGSEQ(R300_SC_SCREENDOOR
, 1);
343 BEGIN_BATCH_NO_AUTOSTATE(3);
344 OUT_BATCH_REGSEQ(R300_SC_SCISSORS_TL
, 2);
345 OUT_BATCH((R300_SCISSORS_OFFSET
<< R300_SCISSORS_X_SHIFT
) |
346 (R300_SCISSORS_OFFSET
<< R300_SCISSORS_Y_SHIFT
));
347 OUT_BATCH(((rrb
->base
.Width
+ R300_SCISSORS_OFFSET
- 1) << R300_SCISSORS_X_SHIFT
) |
348 ((rrb
->base
.Height
+ R300_SCISSORS_OFFSET
- 1) << R300_SCISSORS_Y_SHIFT
));
350 BEGIN_BATCH_NO_AUTOSTATE(16);
351 for (i
= 0; i
< 4; i
++) {
352 OUT_BATCH_REGSEQ(R300_SC_CLIPRECT_TL_0
+ (i
* 8), 2);
353 OUT_BATCH((R300_SCISSORS_OFFSET
<< R300_CLIPRECT_X_SHIFT
) | (R300_SCISSORS_OFFSET
<< R300_CLIPRECT_Y_SHIFT
));
354 OUT_BATCH(((R300_SCISSORS_OFFSET
+ rrb
->base
.Width
- 1) << R300_CLIPRECT_X_SHIFT
) |
355 ((R300_SCISSORS_OFFSET
+ rrb
->base
.Height
- 1) << R300_CLIPRECT_Y_SHIFT
));
357 OUT_BATCH_REGSEQ(R300_SC_CLIP_RULE
, 1);
359 OUT_BATCH_REGSEQ(R300_SC_SCREENDOOR
, 1);
366 static int check_zb_offset(GLcontext
*ctx
, struct radeon_state_atom
* atom
)
368 r300ContextPtr r300
= R300_CONTEXT(ctx
);
371 if (r300
->radeon
.radeonScreen
->kernel_mm
)
376 static void emit_zb_offset(GLcontext
*ctx
, struct radeon_state_atom
* atom
)
378 r300ContextPtr r300
= R300_CONTEXT(ctx
);
379 BATCH_LOCALS(&r300
->radeon
);
380 struct radeon_renderbuffer
*rrb
;
382 uint32_t dw
= atom
->check(ctx
, atom
);
384 rrb
= radeon_get_depthbuffer(&r300
->radeon
);
388 zbpitch
= (rrb
->pitch
/ rrb
->cpp
);
389 if (!r300
->radeon
.radeonScreen
->kernel_mm
) {
390 if (rrb
->bo
->flags
& RADEON_BO_FLAGS_MACRO_TILE
) {
391 zbpitch
|= R300_DEPTHMACROTILE_ENABLE
;
393 if (rrb
->bo
->flags
& RADEON_BO_FLAGS_MICRO_TILE
){
394 zbpitch
|= R300_DEPTHMICROTILE_TILED
;
398 BEGIN_BATCH_NO_AUTOSTATE(dw
);
399 OUT_BATCH_REGSEQ(R300_ZB_DEPTHOFFSET
, 1);
400 OUT_BATCH_RELOC(0, rrb
->bo
, 0, 0, RADEON_GEM_DOMAIN_VRAM
, 0);
401 OUT_BATCH_REGSEQ(R300_ZB_DEPTHPITCH
, 1);
402 if (!r300
->radeon
.radeonScreen
->kernel_mm
)
405 OUT_BATCH_RELOC(cbpitch
, rrb
->bo
, zbpitch
, 0, RADEON_GEM_DOMAIN_VRAM
, 0);
409 static void emit_zstencil_format(GLcontext
*ctx
, struct radeon_state_atom
* atom
)
411 r300ContextPtr r300
= R300_CONTEXT(ctx
);
412 BATCH_LOCALS(&r300
->radeon
);
413 struct radeon_renderbuffer
*rrb
;
416 rrb
= radeon_get_depthbuffer(&r300
->radeon
);
421 format
= R300_DEPTHFORMAT_16BIT_INT_Z
;
422 else if (rrb
->cpp
== 4)
423 format
= R300_DEPTHFORMAT_24BIT_INT_Z_8BIT_STENCIL
;
426 BEGIN_BATCH_NO_AUTOSTATE(atom
->cmd_size
);
427 OUT_BATCH(atom
->cmd
[0]);
428 atom
->cmd
[1] &= ~0xf;
429 atom
->cmd
[1] |= format
;
430 OUT_BATCH(atom
->cmd
[1]);
431 OUT_BATCH(atom
->cmd
[2]);
432 OUT_BATCH(atom
->cmd
[3]);
433 OUT_BATCH(atom
->cmd
[4]);
437 static int check_never(GLcontext
*ctx
, struct radeon_state_atom
*atom
)
442 static int check_always(GLcontext
*ctx
, struct radeon_state_atom
*atom
)
444 return atom
->cmd_size
;
447 static int check_variable(GLcontext
*ctx
, struct radeon_state_atom
*atom
)
449 r300ContextPtr r300
= R300_CONTEXT(ctx
);
451 if (atom
->cmd
[0] == CP_PACKET2
) {
454 cnt
= packet0_count(r300
, atom
->cmd
);
455 return cnt
? cnt
+ 1 : 0;
458 int check_r500fp(GLcontext
*ctx
, struct radeon_state_atom
*atom
)
461 r300ContextPtr r300
= R300_CONTEXT(ctx
);
463 cnt
= r500fp_count(atom
->cmd
);
464 if (r300
->radeon
.radeonScreen
->kernel_mm
)
467 return cnt
? (cnt
* 6) + extra
: 0;
470 int check_r500fp_const(GLcontext
*ctx
, struct radeon_state_atom
*atom
)
473 r300ContextPtr r300
= R300_CONTEXT(ctx
);
475 cnt
= r500fp_count(atom
->cmd
);
476 if (r300
->radeon
.radeonScreen
->kernel_mm
)
479 cnt
= r500fp_count(atom
->cmd
);
480 return cnt
? (cnt
* 4) + extra
: 0;
483 #define ALLOC_STATE( ATOM, CHK, SZ, IDX ) \
485 r300->hw.ATOM.cmd_size = (SZ); \
486 r300->hw.ATOM.cmd = (uint32_t*)CALLOC((SZ) * sizeof(uint32_t)); \
487 r300->hw.ATOM.name = #ATOM; \
488 r300->hw.ATOM.idx = (IDX); \
489 r300->hw.ATOM.check = check_##CHK; \
490 r300->hw.ATOM.dirty = GL_FALSE; \
491 r300->radeon.hw.max_state_size += (SZ); \
492 insert_at_tail(&r300->radeon.hw.atomlist, &r300->hw.ATOM); \
495 * Allocate memory for the command buffer and initialize the state atom
496 * list. Note that the initial hardware state is set by r300InitState().
498 void r300InitCmdBuf(r300ContextPtr r300
)
504 has_tcl
= r300
->options
.hw_tcl_enabled
;
506 if (r300
->radeon
.radeonScreen
->chip_family
>= CHIP_FAMILY_RV515
)
509 r300
->radeon
.hw
.max_state_size
= 2 + 2; /* reserve extra space for WAIT_IDLE and tex cache flush */
511 mtu
= r300
->radeon
.glCtx
->Const
.MaxTextureUnits
;
512 if (RADEON_DEBUG
& RADEON_TEXTURE
) {
513 fprintf(stderr
, "Using %d maximum texture units..\n", mtu
);
516 /* Setup the atom linked list */
517 make_empty_list(&r300
->radeon
.hw
.atomlist
);
518 r300
->radeon
.hw
.atomlist
.name
= "atom-list";
520 /* Initialize state atoms */
521 ALLOC_STATE(vpt
, always
, R300_VPT_CMDSIZE
, 0);
522 r300
->hw
.vpt
.cmd
[R300_VPT_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_SE_VPORT_XSCALE
, 6);
523 ALLOC_STATE(vap_cntl
, always
, R300_VAP_CNTL_SIZE
, 0);
524 r300
->hw
.vap_cntl
.cmd
[R300_VAP_CNTL_FLUSH
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_VAP_PVS_STATE_FLUSH_REG
, 1);
525 r300
->hw
.vap_cntl
.cmd
[R300_VAP_CNTL_FLUSH_1
] = 0;
526 r300
->hw
.vap_cntl
.cmd
[R300_VAP_CNTL_CMD
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_VAP_CNTL
, 1);
527 if (is_r500
&& !r300
->radeon
.radeonScreen
->kernel_mm
) {
528 ALLOC_STATE(vap_index_offset
, always
, 2, 0);
529 r300
->hw
.vap_index_offset
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R500_VAP_INDEX_OFFSET
, 1);
530 r300
->hw
.vap_index_offset
.cmd
[1] = 0;
532 ALLOC_STATE(vte
, always
, 3, 0);
533 r300
->hw
.vte
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_SE_VTE_CNTL
, 2);
534 ALLOC_STATE(vap_vf_max_vtx_indx
, always
, 3, 0);
535 r300
->hw
.vap_vf_max_vtx_indx
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_VAP_VF_MAX_VTX_INDX
, 2);
536 ALLOC_STATE(vap_cntl_status
, always
, 2, 0);
537 r300
->hw
.vap_cntl_status
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_VAP_CNTL_STATUS
, 1);
538 ALLOC_STATE(vir
[0], variable
, R300_VIR_CMDSIZE
, 0);
539 r300
->hw
.vir
[0].cmd
[R300_VIR_CMD_0
] =
540 cmdpacket0(r300
->radeon
.radeonScreen
, R300_VAP_PROG_STREAM_CNTL_0
, 1);
541 ALLOC_STATE(vir
[1], variable
, R300_VIR_CMDSIZE
, 1);
542 r300
->hw
.vir
[1].cmd
[R300_VIR_CMD_0
] =
543 cmdpacket0(r300
->radeon
.radeonScreen
, R300_VAP_PROG_STREAM_CNTL_EXT_0
, 1);
544 ALLOC_STATE(vic
, always
, R300_VIC_CMDSIZE
, 0);
545 r300
->hw
.vic
.cmd
[R300_VIC_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_VAP_VTX_STATE_CNTL
, 2);
546 ALLOC_STATE(vap_psc_sgn_norm_cntl
, always
, 2, 0);
547 r300
->hw
.vap_psc_sgn_norm_cntl
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_VAP_PSC_SGN_NORM_CNTL
, SGN_NORM_ZERO_CLAMP_MINUS_ONE
);
550 ALLOC_STATE(vap_clip_cntl
, always
, 2, 0);
551 r300
->hw
.vap_clip_cntl
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_VAP_CLIP_CNTL
, 1);
552 ALLOC_STATE(vap_clip
, always
, 5, 0);
553 r300
->hw
.vap_clip
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_VAP_GB_VERT_CLIP_ADJ
, 4);
554 ALLOC_STATE(vap_pvs_vtx_timeout_reg
, always
, 2, 0);
555 r300
->hw
.vap_pvs_vtx_timeout_reg
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, VAP_PVS_VTX_TIMEOUT_REG
, 1);
558 ALLOC_STATE(vof
, always
, R300_VOF_CMDSIZE
, 0);
559 r300
->hw
.vof
.cmd
[R300_VOF_CMD_0
] =
560 cmdpacket0(r300
->radeon
.radeonScreen
, R300_VAP_OUTPUT_VTX_FMT_0
, 2);
563 ALLOC_STATE(pvs
, always
, R300_PVS_CMDSIZE
, 0);
564 r300
->hw
.pvs
.cmd
[R300_PVS_CMD_0
] =
565 cmdpacket0(r300
->radeon
.radeonScreen
, R300_VAP_PVS_CODE_CNTL_0
, 3);
568 ALLOC_STATE(gb_enable
, always
, 2, 0);
569 r300
->hw
.gb_enable
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_GB_ENABLE
, 1);
570 if (!r300
->radeon
.radeonScreen
->driScreen
->dri2
.enabled
) {
571 ALLOC_STATE(gb_misc
, always
, R300_GB_MISC_CMDSIZE
, 0);
573 ALLOC_STATE(gb_misc
, never
, R300_GB_MISC_CMDSIZE
, 0);
575 r300
->hw
.gb_misc
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_GB_MSPOS0
, 3);
576 ALLOC_STATE(gb_misc2
, always
, R300_GB_MISC2_CMDSIZE
, 0);
577 r300
->hw
.gb_misc2
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, 0x401C, 2);
578 ALLOC_STATE(txe
, always
, R300_TXE_CMDSIZE
, 0);
579 r300
->hw
.txe
.cmd
[R300_TXE_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_TX_ENABLE
, 1);
580 ALLOC_STATE(ga_point_s0
, always
, 5, 0);
581 r300
->hw
.ga_point_s0
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_GA_POINT_S0
, 4);
582 ALLOC_STATE(ga_triangle_stipple
, always
, 2, 0);
583 r300
->hw
.ga_triangle_stipple
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_GA_TRIANGLE_STIPPLE
, 1);
584 ALLOC_STATE(ps
, always
, R300_PS_CMDSIZE
, 0);
585 r300
->hw
.ps
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_GA_POINT_SIZE
, 1);
586 ALLOC_STATE(ga_point_minmax
, always
, 4, 0);
587 r300
->hw
.ga_point_minmax
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_GA_POINT_MINMAX
, 3);
588 ALLOC_STATE(lcntl
, always
, 2, 0);
589 r300
->hw
.lcntl
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_GA_LINE_CNTL
, 1);
590 ALLOC_STATE(ga_line_stipple
, always
, 4, 0);
591 r300
->hw
.ga_line_stipple
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_GA_LINE_STIPPLE_VALUE
, 3);
592 if (!r300
->radeon
.radeonScreen
->driScreen
->dri2
.enabled
) {
593 ALLOC_STATE(shade
, always
, 2, 0);
595 ALLOC_STATE(shade
, never
, 2, 0);
597 r300
->hw
.shade
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_GA_ENHANCE
, 1);
598 ALLOC_STATE(shade2
, always
, 4, 0);
599 r300
->hw
.shade2
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, 0x4278, 3);
600 ALLOC_STATE(polygon_mode
, always
, 4, 0);
601 r300
->hw
.polygon_mode
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_GA_POLY_MODE
, 3);
602 ALLOC_STATE(fogp
, always
, 3, 0);
603 r300
->hw
.fogp
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_GA_FOG_SCALE
, 2);
604 ALLOC_STATE(zbias_cntl
, always
, 2, 0);
605 r300
->hw
.zbias_cntl
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_SU_TEX_WRAP
, 1);
606 ALLOC_STATE(zbs
, always
, R300_ZBS_CMDSIZE
, 0);
607 r300
->hw
.zbs
.cmd
[R300_ZBS_CMD_0
] =
608 cmdpacket0(r300
->radeon
.radeonScreen
, R300_SU_POLY_OFFSET_FRONT_SCALE
, 4);
609 ALLOC_STATE(occlusion_cntl
, always
, 2, 0);
610 r300
->hw
.occlusion_cntl
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_SU_POLY_OFFSET_ENABLE
, 1);
611 ALLOC_STATE(cul
, always
, R300_CUL_CMDSIZE
, 0);
612 r300
->hw
.cul
.cmd
[R300_CUL_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_SU_CULL_MODE
, 1);
613 ALLOC_STATE(su_depth_scale
, always
, 3, 0);
614 r300
->hw
.su_depth_scale
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_SU_DEPTH_SCALE
, 2);
615 ALLOC_STATE(rc
, always
, R300_RC_CMDSIZE
, 0);
616 r300
->hw
.rc
.cmd
[R300_RC_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_RS_COUNT
, 2);
618 ALLOC_STATE(ri
, variable
, R500_RI_CMDSIZE
, 0);
619 r300
->hw
.ri
.cmd
[R300_RI_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R500_RS_IP_0
, 16);
620 ALLOC_STATE(rr
, variable
, R300_RR_CMDSIZE
, 0);
621 r300
->hw
.rr
.cmd
[R300_RR_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R500_RS_INST_0
, 1);
623 ALLOC_STATE(ri
, variable
, R300_RI_CMDSIZE
, 0);
624 r300
->hw
.ri
.cmd
[R300_RI_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_RS_IP_0
, 8);
625 ALLOC_STATE(rr
, variable
, R300_RR_CMDSIZE
, 0);
626 r300
->hw
.rr
.cmd
[R300_RR_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_RS_INST_0
, 1);
628 ALLOC_STATE(sc_hyperz
, always
, 3, 0);
629 r300
->hw
.sc_hyperz
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_SC_HYPERZ
, 2);
630 ALLOC_STATE(sc_screendoor
, always
, 2, 0);
631 r300
->hw
.sc_screendoor
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_SC_SCREENDOOR
, 1);
632 ALLOC_STATE(us_out_fmt
, always
, 6, 0);
633 r300
->hw
.us_out_fmt
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_US_OUT_FMT
, 5);
636 ALLOC_STATE(fp
, always
, R500_FP_CMDSIZE
, 0);
637 r300
->hw
.fp
.cmd
[R500_FP_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R500_US_CONFIG
, 2);
638 r300
->hw
.fp
.cmd
[R500_FP_CNTL
] = R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO
;
639 r300
->hw
.fp
.cmd
[R500_FP_CMD_1
] = cmdpacket0(r300
->radeon
.radeonScreen
, R500_US_CODE_ADDR
, 3);
640 r300
->hw
.fp
.cmd
[R500_FP_CMD_2
] = cmdpacket0(r300
->radeon
.radeonScreen
, R500_US_FC_CTRL
, 1);
641 r300
->hw
.fp
.cmd
[R500_FP_FC_CNTL
] = 0; /* FIXME when we add flow control */
643 ALLOC_STATE(r500fp
, r500fp
, R500_FPI_CMDSIZE
, 0);
644 r300
->hw
.r500fp
.cmd
[R300_FPI_CMD_0
] =
645 cmdr500fp(r300
->radeon
.radeonScreen
, 0, 0, 0, 0);
646 if (r300
->radeon
.radeonScreen
->kernel_mm
)
647 r300
->hw
.r500fp
.emit
= emit_r500fp
;
649 ALLOC_STATE(r500fp_const
, r500fp_const
, R500_FPP_CMDSIZE
, 0);
650 r300
->hw
.r500fp_const
.cmd
[R300_FPI_CMD_0
] =
651 cmdr500fp(r300
->radeon
.radeonScreen
, 0, 0, 1, 0);
652 if (r300
->radeon
.radeonScreen
->kernel_mm
)
653 r300
->hw
.r500fp_const
.emit
= emit_r500fp
;
655 ALLOC_STATE(fp
, always
, R300_FP_CMDSIZE
, 0);
656 r300
->hw
.fp
.cmd
[R300_FP_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_US_CONFIG
, 3);
657 r300
->hw
.fp
.cmd
[R300_FP_CMD_1
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_US_CODE_ADDR_0
, 4);
659 ALLOC_STATE(fpt
, variable
, R300_FPT_CMDSIZE
, 0);
660 r300
->hw
.fpt
.cmd
[R300_FPT_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_US_TEX_INST_0
, 0);
662 ALLOC_STATE(fpi
[0], variable
, R300_FPI_CMDSIZE
, 0);
663 r300
->hw
.fpi
[0].cmd
[R300_FPI_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_US_ALU_RGB_INST_0
, 1);
664 ALLOC_STATE(fpi
[1], variable
, R300_FPI_CMDSIZE
, 1);
665 r300
->hw
.fpi
[1].cmd
[R300_FPI_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_US_ALU_RGB_ADDR_0
, 1);
666 ALLOC_STATE(fpi
[2], variable
, R300_FPI_CMDSIZE
, 2);
667 r300
->hw
.fpi
[2].cmd
[R300_FPI_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_US_ALU_ALPHA_INST_0
, 1);
668 ALLOC_STATE(fpi
[3], variable
, R300_FPI_CMDSIZE
, 3);
669 r300
->hw
.fpi
[3].cmd
[R300_FPI_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_US_ALU_ALPHA_ADDR_0
, 1);
670 ALLOC_STATE(fpp
, variable
, R300_FPP_CMDSIZE
, 0);
671 r300
->hw
.fpp
.cmd
[R300_FPP_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_PFS_PARAM_0_X
, 0);
673 ALLOC_STATE(fogs
, always
, R300_FOGS_CMDSIZE
, 0);
674 r300
->hw
.fogs
.cmd
[R300_FOGS_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_FG_FOG_BLEND
, 1);
675 ALLOC_STATE(fogc
, always
, R300_FOGC_CMDSIZE
, 0);
676 r300
->hw
.fogc
.cmd
[R300_FOGC_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_FG_FOG_COLOR_R
, 3);
677 ALLOC_STATE(at
, always
, R300_AT_CMDSIZE
, 0);
678 r300
->hw
.at
.cmd
[R300_AT_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_FG_ALPHA_FUNC
, 2);
679 ALLOC_STATE(fg_depth_src
, always
, 2, 0);
680 r300
->hw
.fg_depth_src
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_FG_DEPTH_SRC
, 1);
681 ALLOC_STATE(rb3d_cctl
, always
, 2, 0);
682 r300
->hw
.rb3d_cctl
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_RB3D_CCTL
, 1);
683 ALLOC_STATE(bld
, always
, R300_BLD_CMDSIZE
, 0);
684 r300
->hw
.bld
.cmd
[R300_BLD_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_RB3D_CBLEND
, 2);
685 ALLOC_STATE(cmk
, always
, R300_CMK_CMDSIZE
, 0);
686 r300
->hw
.cmk
.cmd
[R300_CMK_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, RB3D_COLOR_CHANNEL_MASK
, 1);
688 ALLOC_STATE(blend_color
, always
, 3, 0);
689 r300
->hw
.blend_color
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R500_RB3D_CONSTANT_COLOR_AR
, 2);
691 ALLOC_STATE(blend_color
, always
, 2, 0);
692 r300
->hw
.blend_color
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_RB3D_BLEND_COLOR
, 1);
694 ALLOC_STATE(rop
, always
, 2, 0);
695 r300
->hw
.rop
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_RB3D_ROPCNTL
, 1);
696 ALLOC_STATE(cb
, cb_offset
, R300_CB_CMDSIZE
, 0);
697 r300
->hw
.cb
.emit
= &emit_cb_offset
;
698 ALLOC_STATE(rb3d_dither_ctl
, always
, 10, 0);
699 r300
->hw
.rb3d_dither_ctl
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_RB3D_DITHER_CTL
, 9);
700 ALLOC_STATE(rb3d_aaresolve_ctl
, always
, 2, 0);
701 r300
->hw
.rb3d_aaresolve_ctl
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_RB3D_AARESOLVE_CTL
, 1);
702 if (r300
->radeon
.radeonScreen
->chip_family
>= CHIP_FAMILY_RV350
) {
703 ALLOC_STATE(rb3d_discard_src_pixel_lte_threshold
, always
, 3, 0);
705 ALLOC_STATE(rb3d_discard_src_pixel_lte_threshold
, never
, 3, 0);
707 r300
->hw
.rb3d_discard_src_pixel_lte_threshold
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R500_RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD
, 2);
708 ALLOC_STATE(zs
, always
, R300_ZS_CMDSIZE
, 0);
709 r300
->hw
.zs
.cmd
[R300_ZS_CMD_0
] =
710 cmdpacket0(r300
->radeon
.radeonScreen
, R300_ZB_CNTL
, 3);
712 if (r300
->radeon
.radeonScreen
->kernel_mm
)
713 ALLOC_STATE(zsb
, always
, R300_ZSB_CMDSIZE
, 0);
715 ALLOC_STATE(zsb
, never
, R300_ZSB_CMDSIZE
, 0);
716 r300
->hw
.zsb
.cmd
[R300_ZSB_CMD_0
] =
717 cmdpacket0(r300
->radeon
.radeonScreen
, R500_ZB_STENCILREFMASK_BF
, 1);
720 ALLOC_STATE(zstencil_format
, always
, 5, 0);
721 r300
->hw
.zstencil_format
.cmd
[0] =
722 cmdpacket0(r300
->radeon
.radeonScreen
, R300_ZB_FORMAT
, 4);
723 r300
->hw
.zstencil_format
.emit
= emit_zstencil_format
;
725 ALLOC_STATE(zb
, zb_offset
, R300_ZB_CMDSIZE
, 0);
726 r300
->hw
.zb
.emit
= emit_zb_offset
;
727 ALLOC_STATE(zb_depthclearvalue
, always
, 2, 0);
728 r300
->hw
.zb_depthclearvalue
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_ZB_DEPTHCLEARVALUE
, 1);
729 ALLOC_STATE(zb_zmask
, always
, 3, 0);
730 r300
->hw
.zb_zmask
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_ZB_ZMASK_OFFSET
, 2);
731 ALLOC_STATE(zb_hiz_offset
, always
, 2, 0);
732 r300
->hw
.zb_hiz_offset
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_ZB_HIZ_OFFSET
, 1);
733 ALLOC_STATE(zb_hiz_pitch
, always
, 2, 0);
734 r300
->hw
.zb_hiz_pitch
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_ZB_HIZ_PITCH
, 1);
736 /* VPU only on TCL */
739 if (r300
->radeon
.radeonScreen
->kernel_mm
) {
740 ALLOC_STATE(vap_flush
, always
, 10, 0);
741 /* flush processing vertices */
742 r300
->hw
.vap_flush
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_SC_SCREENDOOR
, 1);
743 r300
->hw
.vap_flush
.cmd
[1] = 0;
744 r300
->hw
.vap_flush
.cmd
[2] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_RB3D_DSTCACHE_CTLSTAT
, 1);
745 r300
->hw
.vap_flush
.cmd
[3] = R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D
;
746 r300
->hw
.vap_flush
.cmd
[4] = cmdpacket0(r300
->radeon
.radeonScreen
, RADEON_WAIT_UNTIL
, 1);
747 r300
->hw
.vap_flush
.cmd
[5] = RADEON_WAIT_3D_IDLECLEAN
;
748 r300
->hw
.vap_flush
.cmd
[6] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_SC_SCREENDOOR
, 1);
749 r300
->hw
.vap_flush
.cmd
[7] = 0xffffff;
750 r300
->hw
.vap_flush
.cmd
[8] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_VAP_PVS_STATE_FLUSH_REG
, 1);
751 r300
->hw
.vap_flush
.cmd
[9] = 0;
753 ALLOC_STATE(vap_flush
, never
, 10, 0);
757 ALLOC_STATE(vpi
, vpu
, R300_VPI_CMDSIZE
, 0);
758 r300
->hw
.vpi
.cmd
[0] =
759 cmdvpu(r300
->radeon
.radeonScreen
, R300_PVS_CODE_START
, 0);
760 if (r300
->radeon
.radeonScreen
->kernel_mm
)
761 r300
->hw
.vpi
.emit
= emit_vpu
;
764 ALLOC_STATE(vpp
, vpu
, R300_VPP_CMDSIZE
, 0);
765 r300
->hw
.vpp
.cmd
[0] =
766 cmdvpu(r300
->radeon
.radeonScreen
, R500_PVS_CONST_START
, 0);
767 if (r300
->radeon
.radeonScreen
->kernel_mm
)
768 r300
->hw
.vpp
.emit
= emit_vpu
;
770 ALLOC_STATE(vps
, vpu
, R300_VPS_CMDSIZE
, 0);
771 r300
->hw
.vps
.cmd
[0] =
772 cmdvpu(r300
->radeon
.radeonScreen
, R500_POINT_VPORT_SCALE_OFFSET
, 1);
773 if (r300
->radeon
.radeonScreen
->kernel_mm
)
774 r300
->hw
.vps
.emit
= emit_vpu
;
776 for (i
= 0; i
< 6; i
++) {
777 ALLOC_STATE(vpucp
[i
], vpu
, R300_VPUCP_CMDSIZE
, 0);
778 r300
->hw
.vpucp
[i
].cmd
[0] =
779 cmdvpu(r300
->radeon
.radeonScreen
,
780 R500_PVS_UCP_START
+ i
, 1);
781 if (r300
->radeon
.radeonScreen
->kernel_mm
)
782 r300
->hw
.vpucp
[i
].emit
= emit_vpu
;
785 ALLOC_STATE(vpp
, vpu
, R300_VPP_CMDSIZE
, 0);
786 r300
->hw
.vpp
.cmd
[0] =
787 cmdvpu(r300
->radeon
.radeonScreen
, R300_PVS_CONST_START
, 0);
788 if (r300
->radeon
.radeonScreen
->kernel_mm
)
789 r300
->hw
.vpp
.emit
= emit_vpu
;
791 ALLOC_STATE(vps
, vpu
, R300_VPS_CMDSIZE
, 0);
792 r300
->hw
.vps
.cmd
[0] =
793 cmdvpu(r300
->radeon
.radeonScreen
, R300_POINT_VPORT_SCALE_OFFSET
, 1);
794 if (r300
->radeon
.radeonScreen
->kernel_mm
)
795 r300
->hw
.vps
.emit
= emit_vpu
;
797 for (i
= 0; i
< 6; i
++) {
798 ALLOC_STATE(vpucp
[i
], vpu
, R300_VPUCP_CMDSIZE
, 0);
799 r300
->hw
.vpucp
[i
].cmd
[0] =
800 cmdvpu(r300
->radeon
.radeonScreen
,
801 R300_PVS_UCP_START
+ i
, 1);
802 if (r300
->radeon
.radeonScreen
->kernel_mm
)
803 r300
->hw
.vpucp
[i
].emit
= emit_vpu
;
809 ALLOC_STATE(tex
.filter
, variable
, mtu
+ 1, 0);
810 r300
->hw
.tex
.filter
.cmd
[R300_TEX_CMD_0
] =
811 cmdpacket0(r300
->radeon
.radeonScreen
, R300_TX_FILTER0_0
, 0);
813 ALLOC_STATE(tex
.filter_1
, variable
, mtu
+ 1, 0);
814 r300
->hw
.tex
.filter_1
.cmd
[R300_TEX_CMD_0
] =
815 cmdpacket0(r300
->radeon
.radeonScreen
, R300_TX_FILTER1_0
, 0);
817 ALLOC_STATE(tex
.size
, variable
, mtu
+ 1, 0);
818 r300
->hw
.tex
.size
.cmd
[R300_TEX_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_TX_SIZE_0
, 0);
820 ALLOC_STATE(tex
.format
, variable
, mtu
+ 1, 0);
821 r300
->hw
.tex
.format
.cmd
[R300_TEX_CMD_0
] =
822 cmdpacket0(r300
->radeon
.radeonScreen
, R300_TX_FORMAT_0
, 0);
824 ALLOC_STATE(tex
.pitch
, variable
, mtu
+ 1, 0);
825 r300
->hw
.tex
.pitch
.cmd
[R300_TEX_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_TX_FORMAT2_0
, 0);
827 ALLOC_STATE(tex
.offset
, tex_offsets
, 1, 0);
828 r300
->hw
.tex
.offset
.cmd
[R300_TEX_CMD_0
] =
829 cmdpacket0(r300
->radeon
.radeonScreen
, R300_TX_OFFSET_0
, 0);
830 r300
->hw
.tex
.offset
.emit
= &emit_tex_offsets
;
832 ALLOC_STATE(tex
.chroma_key
, variable
, mtu
+ 1, 0);
833 r300
->hw
.tex
.chroma_key
.cmd
[R300_TEX_CMD_0
] =
834 cmdpacket0(r300
->radeon
.radeonScreen
, R300_TX_CHROMA_KEY_0
, 0);
836 ALLOC_STATE(tex
.border_color
, variable
, mtu
+ 1, 0);
837 r300
->hw
.tex
.border_color
.cmd
[R300_TEX_CMD_0
] =
838 cmdpacket0(r300
->radeon
.radeonScreen
, R300_TX_BORDER_COLOR_0
, 0);
840 radeon_init_query_stateobj(&r300
->radeon
, R300_QUERYOBJ_CMDSIZE
);
841 if (r300
->radeon
.radeonScreen
->chip_family
== CHIP_FAMILY_RV530
) {
842 r300
->radeon
.query
.queryobj
.cmd
[R300_QUERYOBJ_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, RV530_FG_ZBREG_DEST
, 1);
843 r300
->radeon
.query
.queryobj
.cmd
[R300_QUERYOBJ_DATA_0
] = RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL
;
845 r300
->radeon
.query
.queryobj
.cmd
[R300_QUERYOBJ_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_SU_REG_DEST
, 1);
846 r300
->radeon
.query
.queryobj
.cmd
[R300_QUERYOBJ_DATA_0
] = R300_RASTER_PIPE_SELECT_ALL
;
848 r300
->radeon
.query
.queryobj
.cmd
[R300_QUERYOBJ_CMD_1
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_ZB_ZPASS_DATA
, 1);
849 r300
->radeon
.query
.queryobj
.cmd
[R300_QUERYOBJ_DATA_1
] = 0;
851 r300
->radeon
.hw
.is_dirty
= GL_TRUE
;
852 r300
->radeon
.hw
.all_dirty
= GL_TRUE
;
854 rcommonInitCmdBuf(&r300
->radeon
);