projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
radeon/r200/r300: another big merge upheavel.
[mesa.git] / src / mesa / drivers / dri / r300 / r300_cmdbuf.c
1 /*
2 Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
3
4 The Weather Channel (TM) funded Tungsten Graphics to develop the
5 initial release of the Radeon 8500 driver under the XFree86 license.
6 This notice must be preserved.
7
8 Permission is hereby granted, free of charge, to any person obtaining
9 a copy of this software and associated documentation files (the
10 "Software"), to deal in the Software without restriction, including
11 without limitation the rights to use, copy, modify, merge, publish,
12 distribute, sublicense, and/or sell copies of the Software, and to
13 permit persons to whom the Software is furnished to do so, subject to
14 the following conditions:
15
16 The above copyright notice and this permission notice (including the
17 next paragraph) shall be included in all copies or substantial
18 portions of the Software.
19
20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27
28 **************************************************************************/
29
30 /**
31 * \file
32 *
33 * \author Nicolai Haehnle <prefect_@gmx.net>
34 */
35
36 #include "main/glheader.h"
37 #include "main/state.h"
38 #include "main/imports.h"
39 #include "main/macros.h"
40 #include "main/context.h"
41 #include "main/simple_list.h"
42 #include "swrast/swrast.h"
43
44 #include "drm.h"
45 #include "radeon_drm.h"
46
47 #include "radeon_buffer.h"
48 #include "r300_context.h"
49 #include "r300_ioctl.h"
50 #include "radeon_reg.h"
51 #include "r300_reg.h"
52 #include "r300_cmdbuf.h"
53 #include "r300_emit.h"
54 #include "radeon_mipmap_tree.h"
55 #include "r300_state.h"
56 #include "radeon_cs_legacy.h"
57 #include "radeon_cs_gem.h"
58 #include "radeon_reg.h"
59
60 #define R300_VAP_PVS_UPLOAD_ADDRESS 0x2200
61 # define RADEON_ONE_REG_WR (1 << 15)
62
63 /** # of dwords reserved for additional instructions that may need to be written
64 * during flushing.
65 */
66 #define SPACE_FOR_FLUSHING 4
67
68 static unsigned packet0_count(r300ContextPtr r300, uint32_t *pkt)
69 {
70 if (r300->radeon.radeonScreen->kernel_mm) {
71 return ((((*pkt) >> 16) & 0x3FFF) + 1);
72 } else {
73 drm_r300_cmd_header_t *t = (drm_r300_cmd_header_t*)pkt;
74 return t->packet0.count;
75 }
76 return 0;
77 }
78
79 #define vpu_count(ptr) (((drm_r300_cmd_header_t*)(ptr))->vpu.count)
80 #define r500fp_count(ptr) (((drm_r300_cmd_header_t*)(ptr))->r500fp.count)
81
82 void emit_vpu(GLcontext *ctx, struct radeon_state_atom * atom)
83 {
84 r300ContextPtr r300 = R300_CONTEXT(ctx);
85 BATCH_LOCALS(&r300->radeon);
86 drm_r300_cmd_header_t cmd;
87 uint32_t addr, ndw, i;
88
89 if (!r300->radeon.radeonScreen->kernel_mm) {
90 uint32_t dwords;
91 dwords = (*atom->check) (ctx, atom);
92 BEGIN_BATCH_NO_AUTOSTATE(dwords);
93 OUT_BATCH_TABLE(atom->cmd, dwords);
94 END_BATCH();
95 return;
96 }
97
98 cmd.u = atom->cmd[0];
99 addr = (cmd.vpu.adrhi << 8) | cmd.vpu.adrlo;
100 ndw = cmd.vpu.count * 4;
101 if (ndw) {
102 BEGIN_BATCH_NO_AUTOSTATE(11 + ndw);
103
104 /* flush processing vertices */
105 OUT_BATCH(CP_PACKET0(R300_SC_SCREENDOOR, 0));
106 OUT_BATCH(0x0);
107 OUT_BATCH(CP_PACKET0(RADEON_WAIT_UNTIL, 0));
108 OUT_BATCH((1 << 15) | (1 << 28));
109 OUT_BATCH(CP_PACKET0(R300_SC_SCREENDOOR, 0));
110 OUT_BATCH(0x00FFFFFF);
111 OUT_BATCH(CP_PACKET0(R300_VAP_PVS_STATE_FLUSH_REG, 0));
112 OUT_BATCH(1);
113 /* write vpu */
114 OUT_BATCH(CP_PACKET0(R300_VAP_PVS_UPLOAD_ADDRESS, 0));
115 OUT_BATCH(addr);
116 OUT_BATCH(CP_PACKET0(R300_VAP_PVS_UPLOAD_DATA, ndw-1) | RADEON_ONE_REG_WR);
117 for (i = 0; i < ndw; i++) {
118 OUT_BATCH(atom->cmd[i+1]);
119 }
120 END_BATCH();
121 }
122 }
123
124 void emit_r500fp(GLcontext *ctx, struct radeon_state_atom * atom)
125 {
126 r300ContextPtr r300 = R300_CONTEXT(ctx);
127 BATCH_LOCALS(&r300->radeon);
128 drm_r300_cmd_header_t cmd;
129 uint32_t addr, ndw, i, sz;
130 int type, clamp, stride;
131
132 if (!r300->radeon.radeonScreen->kernel_mm) {
133 uint32_t dwords;
134 dwords = (*atom->check) (ctx, atom);
135 BEGIN_BATCH_NO_AUTOSTATE(dwords);
136 OUT_BATCH_TABLE(atom->cmd, dwords);
137 END_BATCH();
138 return;
139 }
140
141 cmd.u = atom->cmd[0];
142 sz = cmd.r500fp.count;
143 addr = ((cmd.r500fp.adrhi_flags & 1) << 8) | cmd.r500fp.adrlo;
144 type = !!(cmd.r500fp.adrhi_flags & R500FP_CONSTANT_TYPE);
145 clamp = !!(cmd.r500fp.adrhi_flags & R500FP_CONSTANT_CLAMP);
146
147 addr |= (type << 16);
148 addr |= (clamp << 17);
149
150 stride = type ? 4 : 6;
151
152 ndw = sz * stride;
153 if (ndw) {
154
155 BEGIN_BATCH_NO_AUTOSTATE(3 + ndw);
156 OUT_BATCH(CP_PACKET0(R500_GA_US_VECTOR_INDEX, 0));
157 OUT_BATCH(addr);
158 OUT_BATCH(CP_PACKET0(R500_GA_US_VECTOR_DATA, ndw-1) | RADEON_ONE_REG_WR);
159 for (i = 0; i < ndw; i++) {
160 OUT_BATCH(atom->cmd[i+1]);
161 }
162 END_BATCH();
163 }
164 }
165
166 static void emit_tex_offsets(GLcontext *ctx, struct radeon_state_atom * atom)
167 {
168 r300ContextPtr r300 = R300_CONTEXT(ctx);
169 BATCH_LOCALS(&r300->radeon);
170 int numtmus = packet0_count(r300, r300->hw.tex.offset.cmd);
171
172 if (numtmus) {
173 int i;
174
175 for(i = 0; i < numtmus; ++i) {
176 radeonTexObj *t = r300->hw.textures[i];
177 if (t && !t->image_override) {
178 BEGIN_BATCH_NO_AUTOSTATE(4);
179 OUT_BATCH_REGSEQ(R300_TX_OFFSET_0 + (i * 4), 1);
180 OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, 0,
181 RADEON_GEM_DOMAIN_VRAM, 0, 0);
182 END_BATCH();
183 } else if (!t) {
184 //assert(0);
185 } else {
186 if (t->bo) {
187 BEGIN_BATCH_NO_AUTOSTATE(4);
188 OUT_BATCH_REGSEQ(R300_TX_OFFSET_0 + (i * 4), 1);
189 OUT_BATCH_RELOC(t->tile_bits, t->bo, 0,
190 RADEON_GEM_DOMAIN_VRAM, 0, 0);
191 END_BATCH();
192 } else if (!r300->radeon.radeonScreen->kernel_mm) {
193 BEGIN_BATCH_NO_AUTOSTATE(2);
194 OUT_BATCH_REGSEQ(R300_TX_OFFSET_0 + (i * 4), 1);
195 OUT_BATCH(t->override_offset);
196 END_BATCH();
197 }
198 }
199 }
200 }
201 }
202
203 static void emit_cb_offset(GLcontext *ctx, struct radeon_state_atom * atom)
204 {
205 r300ContextPtr r300 = R300_CONTEXT(ctx);
206 BATCH_LOCALS(&r300->radeon);
207 struct radeon_renderbuffer *rrb;
208 uint32_t cbpitch;
209
210 rrb = radeon_get_colorbuffer(&r300->radeon);
211 if (!rrb || !rrb->bo) {
212 fprintf(stderr, "no rrb\n");
213 return;
214 }
215
216 cbpitch = (rrb->pitch / rrb->cpp);
217 if (rrb->cpp == 4)
218 cbpitch |= R300_COLOR_FORMAT_ARGB8888;
219 else
220 cbpitch |= R300_COLOR_FORMAT_RGB565;
221
222 if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE)
223 cbpitch |= R300_COLOR_TILE_ENABLE;
224
225 BEGIN_BATCH_NO_AUTOSTATE(6);
226 OUT_BATCH_REGSEQ(R300_RB3D_COLOROFFSET0, 1);
227 OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
228 OUT_BATCH_REGSEQ(R300_RB3D_COLORPITCH0, 1);
229 OUT_BATCH(cbpitch);
230 END_BATCH();
231 }
232
233 static void emit_zb_offset(GLcontext *ctx, struct radeon_state_atom * atom)
234 {
235 r300ContextPtr r300 = R300_CONTEXT(ctx);
236 BATCH_LOCALS(&r300->radeon);
237 struct radeon_renderbuffer *rrb;
238 uint32_t zbpitch;
239
240 rrb = radeon_get_depthbuffer(&r300->radeon);
241 if (!rrb)
242 return;
243
244 zbpitch = (rrb->pitch / rrb->cpp);
245 if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE) {
246 zbpitch |= R300_DEPTHMACROTILE_ENABLE;
247 }
248 if (rrb->bo->flags & RADEON_BO_FLAGS_MICRO_TILE){
249 zbpitch |= R300_DEPTHMICROTILE_TILED;
250 }
251
252 BEGIN_BATCH_NO_AUTOSTATE(6);
253 OUT_BATCH_REGSEQ(R300_ZB_DEPTHOFFSET, 1);
254 OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
255 OUT_BATCH_REGVAL(R300_ZB_DEPTHPITCH, zbpitch);
256 END_BATCH();
257 }
258
259 static int check_always(GLcontext *ctx, struct radeon_state_atom *atom)
260 {
261 return atom->cmd_size;
262 }
263
264 static int check_variable(GLcontext *ctx, struct radeon_state_atom *atom)
265 {
266 r300ContextPtr r300 = R300_CONTEXT(ctx);
267 int cnt;
268 if (atom->cmd[0] == CP_PACKET2) {
269 return 0;
270 }
271 cnt = packet0_count(r300, atom->cmd);
272 return cnt ? cnt + 1 : 0;
273 }
274
275 int check_vpu(GLcontext *ctx, struct radeon_state_atom *atom)
276 {
277 int cnt;
278
279 cnt = vpu_count(atom->cmd);
280 return cnt ? (cnt * 4) + 1 : 0;
281 }
282
283 int check_r500fp(GLcontext *ctx, struct radeon_state_atom *atom)
284 {
285 int cnt;
286
287 cnt = r500fp_count(atom->cmd);
288 return cnt ? (cnt * 6) + 1 : 0;
289 }
290
291 int check_r500fp_const(GLcontext *ctx, struct radeon_state_atom *atom)
292 {
293 int cnt;
294
295 cnt = r500fp_count(atom->cmd);
296 return cnt ? (cnt * 4) + 1 : 0;
297 }
298
299 #define ALLOC_STATE( ATOM, CHK, SZ, IDX ) \
300 do { \
301 r300->hw.ATOM.cmd_size = (SZ); \
302 r300->hw.ATOM.cmd = (uint32_t*)CALLOC((SZ) * sizeof(uint32_t)); \
303 r300->hw.ATOM.name = #ATOM; \
304 r300->hw.ATOM.idx = (IDX); \
305 r300->hw.ATOM.check = check_##CHK; \
306 r300->hw.ATOM.dirty = GL_FALSE; \
307 r300->radeon.hw.max_state_size += (SZ); \
308 insert_at_tail(&r300->radeon.hw.atomlist, &r300->hw.ATOM); \
309 } while (0)
310 /**
311 * Allocate memory for the command buffer and initialize the state atom
312 * list. Note that the initial hardware state is set by r300InitState().
313 */
314 void r300InitCmdBuf(r300ContextPtr r300)
315 {
316 int mtu;
317 int has_tcl = 1;
318 int is_r500 = 0;
319 int i;
320
321 if (!(r300->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL))
322 has_tcl = 0;
323
324 if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515)
325 is_r500 = 1;
326
327 r300->radeon.hw.max_state_size = 2 + 2; /* reserve extra space for WAIT_IDLE and tex cache flush */
328
329 mtu = r300->radeon.glCtx->Const.MaxTextureUnits;
330 if (RADEON_DEBUG & DEBUG_TEXTURE) {
331 fprintf(stderr, "Using %d maximum texture units..\n", mtu);
332 }
333
334 /* Setup the atom linked list */
335 make_empty_list(&r300->radeon.hw.atomlist);
336 r300->radeon.hw.atomlist.name = "atom-list";
337
338 /* Initialize state atoms */
339 ALLOC_STATE(vpt, always, R300_VPT_CMDSIZE, 0);
340 r300->hw.vpt.cmd[R300_VPT_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_SE_VPORT_XSCALE, 6);
341 ALLOC_STATE(vap_cntl, always, R300_VAP_CNTL_SIZE, 0);
342 r300->hw.vap_cntl.cmd[R300_VAP_CNTL_FLUSH] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PVS_STATE_FLUSH_REG, 1);
343 r300->hw.vap_cntl.cmd[R300_VAP_CNTL_FLUSH_1] = 0;
344 r300->hw.vap_cntl.cmd[R300_VAP_CNTL_CMD] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_CNTL, 1);
345 if (is_r500) {
346 ALLOC_STATE(vap_index_offset, always, 2, 0);
347 r300->hw.vap_index_offset.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R500_VAP_INDEX_OFFSET, 1);
348 r300->hw.vap_index_offset.cmd[1] = 0;
349 }
350 ALLOC_STATE(vte, always, 3, 0);
351 r300->hw.vte.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SE_VTE_CNTL, 2);
352 ALLOC_STATE(vap_vf_max_vtx_indx, always, 3, 0);
353 r300->hw.vap_vf_max_vtx_indx.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_VF_MAX_VTX_INDX, 2);
354 ALLOC_STATE(vap_cntl_status, always, 2, 0);
355 r300->hw.vap_cntl_status.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_CNTL_STATUS, 1);
356 ALLOC_STATE(vir[0], variable, R300_VIR_CMDSIZE, 0);
357 r300->hw.vir[0].cmd[R300_VIR_CMD_0] =
358 cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PROG_STREAM_CNTL_0, 1);
359 ALLOC_STATE(vir[1], variable, R300_VIR_CMDSIZE, 1);
360 r300->hw.vir[1].cmd[R300_VIR_CMD_0] =
361 cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PROG_STREAM_CNTL_EXT_0, 1);
362 ALLOC_STATE(vic, always, R300_VIC_CMDSIZE, 0);
363 r300->hw.vic.cmd[R300_VIC_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_VTX_STATE_CNTL, 2);
364 ALLOC_STATE(vap_psc_sgn_norm_cntl, always, 2, 0);
365 r300->hw.vap_psc_sgn_norm_cntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PSC_SGN_NORM_CNTL, SGN_NORM_ZERO_CLAMP_MINUS_ONE);
366
367 if (has_tcl) {
368 ALLOC_STATE(vap_clip_cntl, always, 2, 0);
369 r300->hw.vap_clip_cntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_CLIP_CNTL, 1);
370 ALLOC_STATE(vap_clip, always, 5, 0);
371 r300->hw.vap_clip.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_GB_VERT_CLIP_ADJ, 4);
372 ALLOC_STATE(vap_pvs_vtx_timeout_reg, always, 2, 0);
373 r300->hw.vap_pvs_vtx_timeout_reg.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, VAP_PVS_VTX_TIMEOUT_REG, 1);
374 }
375
376 ALLOC_STATE(vof, always, R300_VOF_CMDSIZE, 0);
377 r300->hw.vof.cmd[R300_VOF_CMD_0] =
378 cmdpacket0(r300->radeon.radeonScreen, R300_VAP_OUTPUT_VTX_FMT_0, 2);
379
380 if (has_tcl) {
381 ALLOC_STATE(pvs, always, R300_PVS_CMDSIZE, 0);
382 r300->hw.pvs.cmd[R300_PVS_CMD_0] =
383 cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PVS_CODE_CNTL_0, 3);
384 }
385
386 ALLOC_STATE(gb_enable, always, 2, 0);
387 r300->hw.gb_enable.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GB_ENABLE, 1);
388 ALLOC_STATE(gb_misc, always, R300_GB_MISC_CMDSIZE, 0);
389 r300->hw.gb_misc.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GB_MSPOS0, 5);
390 ALLOC_STATE(txe, always, R300_TXE_CMDSIZE, 0);
391 r300->hw.txe.cmd[R300_TXE_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_TX_ENABLE, 1);
392 ALLOC_STATE(ga_point_s0, always, 5, 0);
393 r300->hw.ga_point_s0.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_POINT_S0, 4);
394 ALLOC_STATE(ga_triangle_stipple, always, 2, 0);
395 r300->hw.ga_triangle_stipple.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_TRIANGLE_STIPPLE, 1);
396 ALLOC_STATE(ps, always, R300_PS_CMDSIZE, 0);
397 r300->hw.ps.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_POINT_SIZE, 1);
398 ALLOC_STATE(ga_point_minmax, always, 4, 0);
399 r300->hw.ga_point_minmax.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_POINT_MINMAX, 3);
400 ALLOC_STATE(lcntl, always, 2, 0);
401 r300->hw.lcntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_LINE_CNTL, 1);
402 ALLOC_STATE(ga_line_stipple, always, 4, 0);
403 r300->hw.ga_line_stipple.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_LINE_STIPPLE_VALUE, 3);
404 ALLOC_STATE(shade, always, 5, 0);
405 r300->hw.shade.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_ENHANCE, 4);
406 ALLOC_STATE(polygon_mode, always, 4, 0);
407 r300->hw.polygon_mode.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_POLY_MODE, 3);
408 ALLOC_STATE(fogp, always, 3, 0);
409 r300->hw.fogp.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_FOG_SCALE, 2);
410 ALLOC_STATE(zbias_cntl, always, 2, 0);
411 r300->hw.zbias_cntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SU_TEX_WRAP, 1);
412 ALLOC_STATE(zbs, always, R300_ZBS_CMDSIZE, 0);
413 r300->hw.zbs.cmd[R300_ZBS_CMD_0] =
414 cmdpacket0(r300->radeon.radeonScreen, R300_SU_POLY_OFFSET_FRONT_SCALE, 4);
415 ALLOC_STATE(occlusion_cntl, always, 2, 0);
416 r300->hw.occlusion_cntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SU_POLY_OFFSET_ENABLE, 1);
417 ALLOC_STATE(cul, always, R300_CUL_CMDSIZE, 0);
418 r300->hw.cul.cmd[R300_CUL_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_SU_CULL_MODE, 1);
419 ALLOC_STATE(su_depth_scale, always, 3, 0);
420 r300->hw.su_depth_scale.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SU_DEPTH_SCALE, 2);
421 ALLOC_STATE(rc, always, R300_RC_CMDSIZE, 0);
422 r300->hw.rc.cmd[R300_RC_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RS_COUNT, 2);
423 if (is_r500) {
424 ALLOC_STATE(ri, always, R500_RI_CMDSIZE, 0);
425 r300->hw.ri.cmd[R300_RI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R500_RS_IP_0, 16);
426 for (i = 0; i < 8; i++) {
427 r300->hw.ri.cmd[R300_RI_CMD_0 + i +1] =
428 (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_S_SHIFT) |
429 (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_T_SHIFT) |
430 (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT) |
431 (R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT);
432 }
433 ALLOC_STATE(rr, variable, R300_RR_CMDSIZE, 0);
434 r300->hw.rr.cmd[R300_RR_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R500_RS_INST_0, 1);
435 } else {
436 ALLOC_STATE(ri, always, R300_RI_CMDSIZE, 0);
437 r300->hw.ri.cmd[R300_RI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RS_IP_0, 8);
438 ALLOC_STATE(rr, variable, R300_RR_CMDSIZE, 0);
439 r300->hw.rr.cmd[R300_RR_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RS_INST_0, 1);
440 }
441 ALLOC_STATE(sc_hyperz, always, 3, 0);
442 r300->hw.sc_hyperz.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SC_HYPERZ, 2);
443 ALLOC_STATE(sc_screendoor, always, 2, 0);
444 r300->hw.sc_screendoor.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SC_SCREENDOOR, 1);
445 ALLOC_STATE(us_out_fmt, always, 6, 0);
446 r300->hw.us_out_fmt.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_OUT_FMT, 5);
447
448 if (is_r500) {
449 ALLOC_STATE(fp, always, R500_FP_CMDSIZE, 0);
450 r300->hw.fp.cmd[R500_FP_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R500_US_CONFIG, 2);
451 r300->hw.fp.cmd[R500_FP_CNTL] = R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO;
452 r300->hw.fp.cmd[R500_FP_CMD_1] = cmdpacket0(r300->radeon.radeonScreen, R500_US_CODE_ADDR, 3);
453 r300->hw.fp.cmd[R500_FP_CMD_2] = cmdpacket0(r300->radeon.radeonScreen, R500_US_FC_CTRL, 1);
454 r300->hw.fp.cmd[R500_FP_FC_CNTL] = 0; /* FIXME when we add flow control */
455
456 ALLOC_STATE(r500fp, r500fp, R500_FPI_CMDSIZE, 0);
457 r300->hw.r500fp.cmd[R300_FPI_CMD_0] =
458 cmdr500fp(r300->radeon.radeonScreen, 0, 0, 0, 0);
459 r300->hw.r500fp.emit = emit_r500fp;
460 ALLOC_STATE(r500fp_const, r500fp_const, R500_FPP_CMDSIZE, 0);
461 r300->hw.r500fp_const.cmd[R300_FPI_CMD_0] =
462 cmdr500fp(r300->radeon.radeonScreen, 0, 0, 1, 0);
463 r300->hw.r500fp_const.emit = emit_r500fp;
464 } else {
465 ALLOC_STATE(fp, always, R300_FP_CMDSIZE, 0);
466 r300->hw.fp.cmd[R300_FP_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_CONFIG, 3);
467 r300->hw.fp.cmd[R300_FP_CMD_1] = cmdpacket0(r300->radeon.radeonScreen, R300_US_CODE_ADDR_0, 4);
468
469 ALLOC_STATE(fpt, variable, R300_FPT_CMDSIZE, 0);
470 r300->hw.fpt.cmd[R300_FPT_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_TEX_INST_0, 0);
471
472 ALLOC_STATE(fpi[0], variable, R300_FPI_CMDSIZE, 0);
473 r300->hw.fpi[0].cmd[R300_FPI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_ALU_RGB_INST_0, 1);
474 ALLOC_STATE(fpi[1], variable, R300_FPI_CMDSIZE, 1);
475 r300->hw.fpi[1].cmd[R300_FPI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_ALU_RGB_ADDR_0, 1);
476 ALLOC_STATE(fpi[2], variable, R300_FPI_CMDSIZE, 2);
477 r300->hw.fpi[2].cmd[R300_FPI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_ALU_ALPHA_INST_0, 1);
478 ALLOC_STATE(fpi[3], variable, R300_FPI_CMDSIZE, 3);
479 r300->hw.fpi[3].cmd[R300_FPI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_ALU_ALPHA_ADDR_0, 1);
480 ALLOC_STATE(fpp, variable, R300_FPP_CMDSIZE, 0);
481 r300->hw.fpp.cmd[R300_FPP_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_PFS_PARAM_0_X, 0);
482 }
483 ALLOC_STATE(fogs, always, R300_FOGS_CMDSIZE, 0);
484 r300->hw.fogs.cmd[R300_FOGS_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_FG_FOG_BLEND, 1);
485 ALLOC_STATE(fogc, always, R300_FOGC_CMDSIZE, 0);
486 r300->hw.fogc.cmd[R300_FOGC_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_FG_FOG_COLOR_R, 3);
487 ALLOC_STATE(at, always, R300_AT_CMDSIZE, 0);
488 r300->hw.at.cmd[R300_AT_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_FG_ALPHA_FUNC, 2);
489 ALLOC_STATE(fg_depth_src, always, 2, 0);
490 r300->hw.fg_depth_src.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_FG_DEPTH_SRC, 1);
491 ALLOC_STATE(rb3d_cctl, always, 2, 0);
492 r300->hw.rb3d_cctl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_CCTL, 1);
493 ALLOC_STATE(bld, always, R300_BLD_CMDSIZE, 0);
494 r300->hw.bld.cmd[R300_BLD_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_CBLEND, 2);
495 ALLOC_STATE(cmk, always, R300_CMK_CMDSIZE, 0);
496 r300->hw.cmk.cmd[R300_CMK_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, RB3D_COLOR_CHANNEL_MASK, 1);
497 if (is_r500) {
498 ALLOC_STATE(blend_color, always, 3, 0);
499 r300->hw.blend_color.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R500_RB3D_CONSTANT_COLOR_AR, 2);
500 } else {
501 ALLOC_STATE(blend_color, always, 2, 0);
502 r300->hw.blend_color.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_BLEND_COLOR, 1);
503 }
504 ALLOC_STATE(rop, always, 2, 0);
505 r300->hw.rop.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_ROPCNTL, 1);
506 ALLOC_STATE(cb, always, R300_CB_CMDSIZE, 0);
507 r300->hw.cb.emit = &emit_cb_offset;
508 ALLOC_STATE(rb3d_dither_ctl, always, 10, 0);
509 r300->hw.rb3d_dither_ctl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_DITHER_CTL, 9);
510 ALLOC_STATE(rb3d_aaresolve_ctl, always, 2, 0);
511 r300->hw.rb3d_aaresolve_ctl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_AARESOLVE_CTL, 1);
512 ALLOC_STATE(rb3d_discard_src_pixel_lte_threshold, always, 3, 0);
513 r300->hw.rb3d_discard_src_pixel_lte_threshold.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R500_RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD, 2);
514 ALLOC_STATE(zs, always, R300_ZS_CMDSIZE, 0);
515 r300->hw.zs.cmd[R300_ZS_CMD_0] =
516 cmdpacket0(r300->radeon.radeonScreen, R300_ZB_CNTL, 3);
517 ALLOC_STATE(zstencil_format, always, 5, 0);
518 r300->hw.zstencil_format.cmd[0] =
519 cmdpacket0(r300->radeon.radeonScreen, R300_ZB_FORMAT, 4);
520 ALLOC_STATE(zb, always, R300_ZB_CMDSIZE, 0);
521 r300->hw.zb.emit = emit_zb_offset;
522 ALLOC_STATE(zb_depthclearvalue, always, 2, 0);
523 r300->hw.zb_depthclearvalue.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_ZB_DEPTHCLEARVALUE, 1);
524 ALLOC_STATE(unk4F30, always, 3, 0);
525 r300->hw.unk4F30.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, 0x4F30, 2);
526 ALLOC_STATE(zb_hiz_offset, always, 2, 0);
527 r300->hw.zb_hiz_offset.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_ZB_HIZ_OFFSET, 1);
528 ALLOC_STATE(zb_hiz_pitch, always, 2, 0);
529 r300->hw.zb_hiz_pitch.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_ZB_HIZ_PITCH, 1);
530
531 /* VPU only on TCL */
532 if (has_tcl) {
533 int i;
534 ALLOC_STATE(vpi, vpu, R300_VPI_CMDSIZE, 0);
535 r300->hw.vpi.cmd[0] =
536 cmdvpu(r300->radeon.radeonScreen, R300_PVS_CODE_START, 0);
537 r300->hw.vpi.emit = emit_vpu;
538
539 if (is_r500) {
540 ALLOC_STATE(vpp, vpu, R300_VPP_CMDSIZE, 0);
541 r300->hw.vpp.cmd[0] =
542 cmdvpu(r300->radeon.radeonScreen, R500_PVS_CONST_START, 0);
543 r300->hw.vpp.emit = emit_vpu;
544
545 ALLOC_STATE(vps, vpu, R300_VPS_CMDSIZE, 0);
546 r300->hw.vps.cmd[0] =
547 cmdvpu(r300->radeon.radeonScreen, R500_POINT_VPORT_SCALE_OFFSET, 1);
548 r300->hw.vps.emit = emit_vpu;
549
550 for (i = 0; i < 6; i++) {
551 ALLOC_STATE(vpucp[i], vpu, R300_VPUCP_CMDSIZE, 0);
552 r300->hw.vpucp[i].cmd[0] =
553 cmdvpu(r300->radeon.radeonScreen,
554 R500_PVS_UCP_START + i, 1);
555 r300->hw.vpucp[i].emit = emit_vpu;
556 }
557 } else {
558 ALLOC_STATE(vpp, vpu, R300_VPP_CMDSIZE, 0);
559 r300->hw.vpp.cmd[0] =
560 cmdvpu(r300->radeon.radeonScreen, R300_PVS_CONST_START, 0);
561 r300->hw.vpp.emit = emit_vpu;
562
563 ALLOC_STATE(vps, vpu, R300_VPS_CMDSIZE, 0);
564 r300->hw.vps.cmd[0] =
565 cmdvpu(r300->radeon.radeonScreen, R300_POINT_VPORT_SCALE_OFFSET, 1);
566 r300->hw.vps.emit = emit_vpu;
567
568 for (i = 0; i < 6; i++) {
569 ALLOC_STATE(vpucp[i], vpu, R300_VPUCP_CMDSIZE, 0);
570 r300->hw.vpucp[i].cmd[0] =
571 cmdvpu(r300->radeon.radeonScreen,
572 R300_PVS_UCP_START + i, 1);
573 r300->hw.vpucp[i].emit = emit_vpu;
574 }
575 }
576 }
577
578 /* Textures */
579 ALLOC_STATE(tex.filter, variable, mtu + 1, 0);
580 r300->hw.tex.filter.cmd[R300_TEX_CMD_0] =
581 cmdpacket0(r300->radeon.radeonScreen, R300_TX_FILTER0_0, 0);
582
583 ALLOC_STATE(tex.filter_1, variable, mtu + 1, 0);
584 r300->hw.tex.filter_1.cmd[R300_TEX_CMD_0] =
585 cmdpacket0(r300->radeon.radeonScreen, R300_TX_FILTER1_0, 0);
586
587 ALLOC_STATE(tex.size, variable, mtu + 1, 0);
588 r300->hw.tex.size.cmd[R300_TEX_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_TX_SIZE_0, 0);
589
590 ALLOC_STATE(tex.format, variable, mtu + 1, 0);
591 r300->hw.tex.format.cmd[R300_TEX_CMD_0] =
592 cmdpacket0(r300->radeon.radeonScreen, R300_TX_FORMAT_0, 0);
593
594 ALLOC_STATE(tex.pitch, variable, mtu + 1, 0);
595 r300->hw.tex.pitch.cmd[R300_TEX_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_TX_FORMAT2_0, 0);
596
597 ALLOC_STATE(tex.offset, variable, 1, 0);
598 r300->hw.tex.offset.cmd[R300_TEX_CMD_0] =
599 cmdpacket0(r300->radeon.radeonScreen, R300_TX_OFFSET_0, 0);
600 r300->hw.tex.offset.emit = &emit_tex_offsets;
601
602 ALLOC_STATE(tex.chroma_key, variable, mtu + 1, 0);
603 r300->hw.tex.chroma_key.cmd[R300_TEX_CMD_0] =
604 cmdpacket0(r300->radeon.radeonScreen, R300_TX_CHROMA_KEY_0, 0);
605
606 ALLOC_STATE(tex.border_color, variable, mtu + 1, 0);
607 r300->hw.tex.border_color.cmd[R300_TEX_CMD_0] =
608 cmdpacket0(r300->radeon.radeonScreen, R300_TX_BORDER_COLOR_0, 0);
609
610 r300->radeon.hw.is_dirty = GL_TRUE;
611 r300->radeon.hw.all_dirty = GL_TRUE;
612
613 rcommonInitCmdBuf(&r300->radeon);
614 }
615
616 /**
617 * Destroy the command buffer and state atoms.
618 */
619 void r300DestroyCmdBuf(r300ContextPtr r300)
620 {
621 struct radeon_state_atom *atom;
622
623 foreach(atom, &r300->radeon.hw.atomlist) {
624 FREE(atom->cmd);
625 }
626
627 }