projects / mesa.git / blob
? search:


d85f106c112312056ef0cd43545e6379996d13c1
[mesa.git] / src / mesa / drivers / dri / r300 / r300_cmdbuf.c
1 /*
2 Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
3
4 The Weather Channel (TM) funded Tungsten Graphics to develop the
5 initial release of the Radeon 8500 driver under the XFree86 license.
6 This notice must be preserved.
7
8 Permission is hereby granted, free of charge, to any person obtaining
9 a copy of this software and associated documentation files (the
10 "Software"), to deal in the Software without restriction, including
11 without limitation the rights to use, copy, modify, merge, publish,
12 distribute, sublicense, and/or sell copies of the Software, and to
13 permit persons to whom the Software is furnished to do so, subject to
14 the following conditions:
15
16 The above copyright notice and this permission notice (including the
17 next paragraph) shall be included in all copies or substantial
18 portions of the Software.
19
20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27
28 **************************************************************************/
29
30 /**
31 * \file
32 *
33 * \author Nicolai Haehnle <prefect_@gmx.net>
34 */
35
36 #include "main/glheader.h"
37 #include "main/state.h"
38 #include "main/imports.h"
39 #include "main/macros.h"
40 #include "main/context.h"
41 #include "main/simple_list.h"
42 #include "swrast/swrast.h"
43
44 #include "drm.h"
45 #include "radeon_drm.h"
46
47 #include "r300_context.h"
48 #include "r300_ioctl.h"
49 #include "radeon_reg.h"
50 #include "r300_reg.h"
51 #include "r300_cmdbuf.h"
52 #include "r300_emit.h"
53 #include "radeon_bocs_wrapper.h"
54 #include "radeon_mipmap_tree.h"
55 #include "r300_state.h"
56 #include "radeon_reg.h"
57
58 #define R300_VAP_PVS_UPLOAD_ADDRESS 0x2200
59 # define RADEON_ONE_REG_WR (1 << 15)
60
61 /** # of dwords reserved for additional instructions that may need to be written
62 * during flushing.
63 */
64 #define SPACE_FOR_FLUSHING 4
65
66 static unsigned packet0_count(r300ContextPtr r300, uint32_t *pkt)
67 {
68 if (r300->radeon.radeonScreen->kernel_mm) {
69 return ((((*pkt) >> 16) & 0x3FFF) + 1);
70 } else {
71 drm_r300_cmd_header_t *t = (drm_r300_cmd_header_t*)pkt;
72 return t->packet0.count;
73 }
74 return 0;
75 }
76
77 #define vpu_count(ptr) (((drm_r300_cmd_header_t*)(ptr))->vpu.count)
78 #define r500fp_count(ptr) (((drm_r300_cmd_header_t*)(ptr))->r500fp.count)
79
80 void emit_vpu(GLcontext *ctx, struct radeon_state_atom * atom)
81 {
82 r300ContextPtr r300 = R300_CONTEXT(ctx);
83 BATCH_LOCALS(&r300->radeon);
84 drm_r300_cmd_header_t cmd;
85 uint32_t addr, ndw, i;
86
87 if (!r300->radeon.radeonScreen->kernel_mm) {
88 uint32_t dwords;
89 dwords = (*atom->check) (ctx, atom);
90 BEGIN_BATCH_NO_AUTOSTATE(dwords);
91 OUT_BATCH_TABLE(atom->cmd, dwords);
92 END_BATCH();
93 return;
94 }
95
96 cmd.u = atom->cmd[0];
97 addr = (cmd.vpu.adrhi << 8) | cmd.vpu.adrlo;
98 ndw = cmd.vpu.count * 4;
99 if (ndw) {
100
101 if (r300->vap_flush_needed) {
102 BEGIN_BATCH_NO_AUTOSTATE(15 + ndw);
103
104 /* flush processing vertices */
105 OUT_BATCH_REGVAL(R300_SC_SCREENDOOR, 0);
106 OUT_BATCH_REGVAL(R300_RB3D_DSTCACHE_CTLSTAT, R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D);
107 OUT_BATCH_REGVAL(RADEON_WAIT_UNTIL, RADEON_WAIT_3D_IDLECLEAN);
108 OUT_BATCH_REGVAL(R300_SC_SCREENDOOR, 0xffffff);
109 OUT_BATCH_REGVAL(R300_VAP_PVS_STATE_FLUSH_REG, 0);
110 r300->vap_flush_needed = GL_FALSE;
111 } else {
112 BEGIN_BATCH_NO_AUTOSTATE(5 + ndw);
113 }
114 OUT_BATCH_REGVAL(R300_VAP_PVS_UPLOAD_ADDRESS, addr);
115 OUT_BATCH(CP_PACKET0(R300_VAP_PVS_UPLOAD_DATA, ndw-1) | RADEON_ONE_REG_WR);
116 for (i = 0; i < ndw; i++) {
117 OUT_BATCH(atom->cmd[i+1]);
118 }
119 OUT_BATCH_REGVAL(R300_VAP_PVS_STATE_FLUSH_REG, 0);
120 END_BATCH();
121 }
122 }
123
124 void emit_r500fp(GLcontext *ctx, struct radeon_state_atom * atom)
125 {
126 r300ContextPtr r300 = R300_CONTEXT(ctx);
127 BATCH_LOCALS(&r300->radeon);
128 drm_r300_cmd_header_t cmd;
129 uint32_t addr, ndw, i, sz;
130 int type, clamp, stride;
131
132 if (!r300->radeon.radeonScreen->kernel_mm) {
133 uint32_t dwords;
134 dwords = (*atom->check) (ctx, atom);
135 BEGIN_BATCH_NO_AUTOSTATE(dwords);
136 OUT_BATCH_TABLE(atom->cmd, dwords);
137 END_BATCH();
138 return;
139 }
140
141 cmd.u = atom->cmd[0];
142 sz = cmd.r500fp.count;
143 addr = ((cmd.r500fp.adrhi_flags & 1) << 8) | cmd.r500fp.adrlo;
144 type = !!(cmd.r500fp.adrhi_flags & R500FP_CONSTANT_TYPE);
145 clamp = !!(cmd.r500fp.adrhi_flags & R500FP_CONSTANT_CLAMP);
146
147 addr |= (type << 16);
148 addr |= (clamp << 17);
149
150 stride = type ? 4 : 6;
151
152 ndw = sz * stride;
153 if (ndw) {
154
155 BEGIN_BATCH_NO_AUTOSTATE(3 + ndw);
156 OUT_BATCH(CP_PACKET0(R500_GA_US_VECTOR_INDEX, 0));
157 OUT_BATCH(addr);
158 OUT_BATCH(CP_PACKET0(R500_GA_US_VECTOR_DATA, ndw-1) | RADEON_ONE_REG_WR);
159 for (i = 0; i < ndw; i++) {
160 OUT_BATCH(atom->cmd[i+1]);
161 }
162 END_BATCH();
163 }
164 }
165
166 static void emit_tex_offsets(GLcontext *ctx, struct radeon_state_atom * atom)
167 {
168 r300ContextPtr r300 = R300_CONTEXT(ctx);
169 BATCH_LOCALS(&r300->radeon);
170 int numtmus = packet0_count(r300, r300->hw.tex.offset.cmd);
171 int notexture = 0;
172
173 if (numtmus) {
174 int i;
175
176 for(i = 0; i < numtmus; ++i) {
177 radeonTexObj *t = r300->hw.textures[i];
178
179 if (!t)
180 notexture = 1;
181 }
182
183 if (r300->radeon.radeonScreen->kernel_mm && notexture) {
184 return;
185 }
186 BEGIN_BATCH_NO_AUTOSTATE(4 * numtmus);
187 for(i = 0; i < numtmus; ++i) {
188 radeonTexObj *t = r300->hw.textures[i];
189 OUT_BATCH_REGSEQ(R300_TX_OFFSET_0 + (i * 4), 1);
190 if (t && !t->image_override) {
191 OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, 0,
192 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
193 } else if (!t) {
194 OUT_BATCH(r300->radeon.radeonScreen->texOffset[0]);
195 } else { /* override cases */
196 if (t->bo) {
197 OUT_BATCH_RELOC(t->tile_bits, t->bo, 0,
198 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
199 } else if (!r300->radeon.radeonScreen->kernel_mm) {
200 OUT_BATCH(t->override_offset);
201 }
202 else
203 OUT_BATCH(r300->radeon.radeonScreen->texOffset[0]);
204 }
205 }
206 END_BATCH();
207 }
208 }
209
210 static void emit_cb_offset(GLcontext *ctx, struct radeon_state_atom * atom)
211 {
212 r300ContextPtr r300 = R300_CONTEXT(ctx);
213 BATCH_LOCALS(&r300->radeon);
214 struct radeon_renderbuffer *rrb;
215 uint32_t cbpitch;
216 uint32_t offset = r300->radeon.state.color.draw_offset;
217
218 rrb = radeon_get_colorbuffer(&r300->radeon);
219 if (!rrb || !rrb->bo) {
220 fprintf(stderr, "no rrb\n");
221 return;
222 }
223
224 cbpitch = (rrb->pitch / rrb->cpp);
225 if (rrb->cpp == 4)
226 cbpitch |= R300_COLOR_FORMAT_ARGB8888;
227 else
228 cbpitch |= R300_COLOR_FORMAT_RGB565;
229
230 if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE)
231 cbpitch |= R300_COLOR_TILE_ENABLE;
232
233 BEGIN_BATCH_NO_AUTOSTATE(6);
234 OUT_BATCH_REGSEQ(R300_RB3D_COLOROFFSET0, 1);
235 OUT_BATCH_RELOC(offset, rrb->bo, offset, 0, RADEON_GEM_DOMAIN_VRAM, 0);
236 OUT_BATCH_REGSEQ(R300_RB3D_COLORPITCH0, 1);
237 OUT_BATCH(cbpitch);
238 END_BATCH();
239 }
240
241 static void emit_zb_offset(GLcontext *ctx, struct radeon_state_atom * atom)
242 {
243 r300ContextPtr r300 = R300_CONTEXT(ctx);
244 BATCH_LOCALS(&r300->radeon);
245 struct radeon_renderbuffer *rrb;
246 uint32_t zbpitch;
247
248 rrb = radeon_get_depthbuffer(&r300->radeon);
249 if (!rrb)
250 return;
251
252 zbpitch = (rrb->pitch / rrb->cpp);
253 if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE) {
254 zbpitch |= R300_DEPTHMACROTILE_ENABLE;
255 }
256 if (rrb->bo->flags & RADEON_BO_FLAGS_MICRO_TILE){
257 zbpitch |= R300_DEPTHMICROTILE_TILED;
258 }
259
260 BEGIN_BATCH_NO_AUTOSTATE(6);
261 OUT_BATCH_REGSEQ(R300_ZB_DEPTHOFFSET, 1);
262 OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
263 OUT_BATCH_REGVAL(R300_ZB_DEPTHPITCH, zbpitch);
264 END_BATCH();
265 }
266
267 static void emit_zstencil_format(GLcontext *ctx, struct radeon_state_atom * atom)
268 {
269 r300ContextPtr r300 = R300_CONTEXT(ctx);
270 BATCH_LOCALS(&r300->radeon);
271 struct radeon_renderbuffer *rrb;
272 uint32_t format = 0;
273
274 rrb = radeon_get_depthbuffer(&r300->radeon);
275 if (!rrb)
276 format = 0;
277 else {
278 if (rrb->cpp == 2)
279 format = R300_DEPTHFORMAT_16BIT_INT_Z;
280 else if (rrb->cpp == 4)
281 format = R300_DEPTHFORMAT_24BIT_INT_Z_8BIT_STENCIL;
282 }
283
284 OUT_BATCH(atom->cmd[0]);
285 atom->cmd[1] &= ~(3 << 0);
286 atom->cmd[1] |= format;
287 OUT_BATCH(atom->cmd[1]);
288 OUT_BATCH(atom->cmd[2]);
289 OUT_BATCH(atom->cmd[3]);
290 OUT_BATCH(atom->cmd[4]);
291 }
292
293 static int check_always(GLcontext *ctx, struct radeon_state_atom *atom)
294 {
295 return atom->cmd_size;
296 }
297
298 static int check_variable(GLcontext *ctx, struct radeon_state_atom *atom)
299 {
300 r300ContextPtr r300 = R300_CONTEXT(ctx);
301 int cnt;
302 if (atom->cmd[0] == CP_PACKET2) {
303 return 0;
304 }
305 cnt = packet0_count(r300, atom->cmd);
306 return cnt ? cnt + 1 : 0;
307 }
308
309 int check_vpu(GLcontext *ctx, struct radeon_state_atom *atom)
310 {
311 int cnt;
312
313 cnt = vpu_count(atom->cmd);
314 return cnt ? (cnt * 4) + 1 : 0;
315 }
316
317 int check_r500fp(GLcontext *ctx, struct radeon_state_atom *atom)
318 {
319 int cnt;
320
321 cnt = r500fp_count(atom->cmd);
322 return cnt ? (cnt * 6) + 1 : 0;
323 }
324
325 int check_r500fp_const(GLcontext *ctx, struct radeon_state_atom *atom)
326 {
327 int cnt;
328
329 cnt = r500fp_count(atom->cmd);
330 return cnt ? (cnt * 4) + 1 : 0;
331 }
332
333 #define ALLOC_STATE( ATOM, CHK, SZ, IDX ) \
334 do { \
335 r300->hw.ATOM.cmd_size = (SZ); \
336 r300->hw.ATOM.cmd = (uint32_t*)CALLOC((SZ) * sizeof(uint32_t)); \
337 r300->hw.ATOM.name = #ATOM; \
338 r300->hw.ATOM.idx = (IDX); \
339 r300->hw.ATOM.check = check_##CHK; \
340 r300->hw.ATOM.dirty = GL_FALSE; \
341 r300->radeon.hw.max_state_size += (SZ); \
342 insert_at_tail(&r300->radeon.hw.atomlist, &r300->hw.ATOM); \
343 } while (0)
344 /**
345 * Allocate memory for the command buffer and initialize the state atom
346 * list. Note that the initial hardware state is set by r300InitState().
347 */
348 void r300InitCmdBuf(r300ContextPtr r300)
349 {
350 int mtu;
351 int has_tcl = 1;
352 int is_r500 = 0;
353 int i;
354
355 if (!(r300->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL))
356 has_tcl = 0;
357
358 if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515)
359 is_r500 = 1;
360
361 r300->radeon.hw.max_state_size = 2 + 2; /* reserve extra space for WAIT_IDLE and tex cache flush */
362
363 mtu = r300->radeon.glCtx->Const.MaxTextureUnits;
364 if (RADEON_DEBUG & DEBUG_TEXTURE) {
365 fprintf(stderr, "Using %d maximum texture units..\n", mtu);
366 }
367
368 /* Setup the atom linked list */
369 make_empty_list(&r300->radeon.hw.atomlist);
370 r300->radeon.hw.atomlist.name = "atom-list";
371
372 /* Initialize state atoms */
373 ALLOC_STATE(vpt, always, R300_VPT_CMDSIZE, 0);
374 r300->hw.vpt.cmd[R300_VPT_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_SE_VPORT_XSCALE, 6);
375 ALLOC_STATE(vap_cntl, always, R300_VAP_CNTL_SIZE, 0);
376 r300->hw.vap_cntl.cmd[R300_VAP_CNTL_FLUSH] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PVS_STATE_FLUSH_REG, 1);
377 r300->hw.vap_cntl.cmd[R300_VAP_CNTL_FLUSH_1] = 0;
378 r300->hw.vap_cntl.cmd[R300_VAP_CNTL_CMD] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_CNTL, 1);
379 if (is_r500) {
380 ALLOC_STATE(vap_index_offset, always, 2, 0);
381 r300->hw.vap_index_offset.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R500_VAP_INDEX_OFFSET, 1);
382 r300->hw.vap_index_offset.cmd[1] = 0;
383 }
384 ALLOC_STATE(vte, always, 3, 0);
385 r300->hw.vte.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SE_VTE_CNTL, 2);
386 ALLOC_STATE(vap_vf_max_vtx_indx, always, 3, 0);
387 r300->hw.vap_vf_max_vtx_indx.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_VF_MAX_VTX_INDX, 2);
388 ALLOC_STATE(vap_cntl_status, always, 2, 0);
389 r300->hw.vap_cntl_status.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_CNTL_STATUS, 1);
390 ALLOC_STATE(vir[0], variable, R300_VIR_CMDSIZE, 0);
391 r300->hw.vir[0].cmd[R300_VIR_CMD_0] =
392 cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PROG_STREAM_CNTL_0, 1);
393 ALLOC_STATE(vir[1], variable, R300_VIR_CMDSIZE, 1);
394 r300->hw.vir[1].cmd[R300_VIR_CMD_0] =
395 cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PROG_STREAM_CNTL_EXT_0, 1);
396 ALLOC_STATE(vic, always, R300_VIC_CMDSIZE, 0);
397 r300->hw.vic.cmd[R300_VIC_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_VTX_STATE_CNTL, 2);
398 ALLOC_STATE(vap_psc_sgn_norm_cntl, always, 2, 0);
399 r300->hw.vap_psc_sgn_norm_cntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PSC_SGN_NORM_CNTL, SGN_NORM_ZERO_CLAMP_MINUS_ONE);
400
401 if (has_tcl) {
402 ALLOC_STATE(vap_clip_cntl, always, 2, 0);
403 r300->hw.vap_clip_cntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_CLIP_CNTL, 1);
404 ALLOC_STATE(vap_clip, always, 5, 0);
405 r300->hw.vap_clip.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_GB_VERT_CLIP_ADJ, 4);
406 ALLOC_STATE(vap_pvs_vtx_timeout_reg, always, 2, 0);
407 r300->hw.vap_pvs_vtx_timeout_reg.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, VAP_PVS_VTX_TIMEOUT_REG, 1);
408 }
409
410 ALLOC_STATE(vof, always, R300_VOF_CMDSIZE, 0);
411 r300->hw.vof.cmd[R300_VOF_CMD_0] =
412 cmdpacket0(r300->radeon.radeonScreen, R300_VAP_OUTPUT_VTX_FMT_0, 2);
413
414 if (has_tcl) {
415 ALLOC_STATE(pvs, always, R300_PVS_CMDSIZE, 0);
416 r300->hw.pvs.cmd[R300_PVS_CMD_0] =
417 cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PVS_CODE_CNTL_0, 3);
418 }
419
420 ALLOC_STATE(gb_enable, always, 2, 0);
421 r300->hw.gb_enable.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GB_ENABLE, 1);
422 ALLOC_STATE(gb_misc, always, R300_GB_MISC_CMDSIZE, 0);
423 r300->hw.gb_misc.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GB_MSPOS0, 5);
424 ALLOC_STATE(txe, always, R300_TXE_CMDSIZE, 0);
425 r300->hw.txe.cmd[R300_TXE_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_TX_ENABLE, 1);
426 ALLOC_STATE(ga_point_s0, always, 5, 0);
427 r300->hw.ga_point_s0.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_POINT_S0, 4);
428 ALLOC_STATE(ga_triangle_stipple, always, 2, 0);
429 r300->hw.ga_triangle_stipple.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_TRIANGLE_STIPPLE, 1);
430 ALLOC_STATE(ps, always, R300_PS_CMDSIZE, 0);
431 r300->hw.ps.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_POINT_SIZE, 1);
432 ALLOC_STATE(ga_point_minmax, always, 4, 0);
433 r300->hw.ga_point_minmax.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_POINT_MINMAX, 3);
434 ALLOC_STATE(lcntl, always, 2, 0);
435 r300->hw.lcntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_LINE_CNTL, 1);
436 ALLOC_STATE(ga_line_stipple, always, 4, 0);
437 r300->hw.ga_line_stipple.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_LINE_STIPPLE_VALUE, 3);
438 ALLOC_STATE(shade, always, 5, 0);
439 r300->hw.shade.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_ENHANCE, 4);
440 ALLOC_STATE(polygon_mode, always, 4, 0);
441 r300->hw.polygon_mode.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_POLY_MODE, 3);
442 ALLOC_STATE(fogp, always, 3, 0);
443 r300->hw.fogp.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_FOG_SCALE, 2);
444 ALLOC_STATE(zbias_cntl, always, 2, 0);
445 r300->hw.zbias_cntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SU_TEX_WRAP, 1);
446 ALLOC_STATE(zbs, always, R300_ZBS_CMDSIZE, 0);
447 r300->hw.zbs.cmd[R300_ZBS_CMD_0] =
448 cmdpacket0(r300->radeon.radeonScreen, R300_SU_POLY_OFFSET_FRONT_SCALE, 4);
449 ALLOC_STATE(occlusion_cntl, always, 2, 0);
450 r300->hw.occlusion_cntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SU_POLY_OFFSET_ENABLE, 1);
451 ALLOC_STATE(cul, always, R300_CUL_CMDSIZE, 0);
452 r300->hw.cul.cmd[R300_CUL_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_SU_CULL_MODE, 1);
453 ALLOC_STATE(su_depth_scale, always, 3, 0);
454 r300->hw.su_depth_scale.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SU_DEPTH_SCALE, 2);
455 ALLOC_STATE(rc, always, R300_RC_CMDSIZE, 0);
456 r300->hw.rc.cmd[R300_RC_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RS_COUNT, 2);
457 if (is_r500) {
458 ALLOC_STATE(ri, always, R500_RI_CMDSIZE, 0);
459 r300->hw.ri.cmd[R300_RI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R500_RS_IP_0, 16);
460 for (i = 0; i < 8; i++) {
461 r300->hw.ri.cmd[R300_RI_CMD_0 + i +1] =
462 (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_S_SHIFT) |
463 (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_T_SHIFT) |
464 (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT) |
465 (R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT);
466 }
467 ALLOC_STATE(rr, variable, R300_RR_CMDSIZE, 0);
468 r300->hw.rr.cmd[R300_RR_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R500_RS_INST_0, 1);
469 } else {
470 ALLOC_STATE(ri, always, R300_RI_CMDSIZE, 0);
471 r300->hw.ri.cmd[R300_RI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RS_IP_0, 8);
472 ALLOC_STATE(rr, variable, R300_RR_CMDSIZE, 0);
473 r300->hw.rr.cmd[R300_RR_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RS_INST_0, 1);
474 }
475 ALLOC_STATE(sc_hyperz, always, 3, 0);
476 r300->hw.sc_hyperz.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SC_HYPERZ, 2);
477 ALLOC_STATE(sc_screendoor, always, 2, 0);
478 r300->hw.sc_screendoor.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SC_SCREENDOOR, 1);
479 ALLOC_STATE(us_out_fmt, always, 6, 0);
480 r300->hw.us_out_fmt.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_OUT_FMT, 5);
481
482 if (is_r500) {
483 ALLOC_STATE(fp, always, R500_FP_CMDSIZE, 0);
484 r300->hw.fp.cmd[R500_FP_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R500_US_CONFIG, 2);
485 r300->hw.fp.cmd[R500_FP_CNTL] = R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO;
486 r300->hw.fp.cmd[R500_FP_CMD_1] = cmdpacket0(r300->radeon.radeonScreen, R500_US_CODE_ADDR, 3);
487 r300->hw.fp.cmd[R500_FP_CMD_2] = cmdpacket0(r300->radeon.radeonScreen, R500_US_FC_CTRL, 1);
488 r300->hw.fp.cmd[R500_FP_FC_CNTL] = 0; /* FIXME when we add flow control */
489
490 ALLOC_STATE(r500fp, r500fp, R500_FPI_CMDSIZE, 0);
491 r300->hw.r500fp.cmd[R300_FPI_CMD_0] =
492 cmdr500fp(r300->radeon.radeonScreen, 0, 0, 0, 0);
493 r300->hw.r500fp.emit = emit_r500fp;
494 ALLOC_STATE(r500fp_const, r500fp_const, R500_FPP_CMDSIZE, 0);
495 r300->hw.r500fp_const.cmd[R300_FPI_CMD_0] =
496 cmdr500fp(r300->radeon.radeonScreen, 0, 0, 1, 0);
497 r300->hw.r500fp_const.emit = emit_r500fp;
498 } else {
499 ALLOC_STATE(fp, always, R300_FP_CMDSIZE, 0);
500 r300->hw.fp.cmd[R300_FP_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_CONFIG, 3);
501 r300->hw.fp.cmd[R300_FP_CMD_1] = cmdpacket0(r300->radeon.radeonScreen, R300_US_CODE_ADDR_0, 4);
502
503 ALLOC_STATE(fpt, variable, R300_FPT_CMDSIZE, 0);
504 r300->hw.fpt.cmd[R300_FPT_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_TEX_INST_0, 0);
505
506 ALLOC_STATE(fpi[0], variable, R300_FPI_CMDSIZE, 0);
507 r300->hw.fpi[0].cmd[R300_FPI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_ALU_RGB_INST_0, 1);
508 ALLOC_STATE(fpi[1], variable, R300_FPI_CMDSIZE, 1);
509 r300->hw.fpi[1].cmd[R300_FPI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_ALU_RGB_ADDR_0, 1);
510 ALLOC_STATE(fpi[2], variable, R300_FPI_CMDSIZE, 2);
511 r300->hw.fpi[2].cmd[R300_FPI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_ALU_ALPHA_INST_0, 1);
512 ALLOC_STATE(fpi[3], variable, R300_FPI_CMDSIZE, 3);
513 r300->hw.fpi[3].cmd[R300_FPI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_ALU_ALPHA_ADDR_0, 1);
514 ALLOC_STATE(fpp, variable, R300_FPP_CMDSIZE, 0);
515 r300->hw.fpp.cmd[R300_FPP_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_PFS_PARAM_0_X, 0);
516 }
517 ALLOC_STATE(fogs, always, R300_FOGS_CMDSIZE, 0);
518 r300->hw.fogs.cmd[R300_FOGS_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_FG_FOG_BLEND, 1);
519 ALLOC_STATE(fogc, always, R300_FOGC_CMDSIZE, 0);
520 r300->hw.fogc.cmd[R300_FOGC_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_FG_FOG_COLOR_R, 3);
521 ALLOC_STATE(at, always, R300_AT_CMDSIZE, 0);
522 r300->hw.at.cmd[R300_AT_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_FG_ALPHA_FUNC, 2);
523 ALLOC_STATE(fg_depth_src, always, 2, 0);
524 r300->hw.fg_depth_src.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_FG_DEPTH_SRC, 1);
525 ALLOC_STATE(rb3d_cctl, always, 2, 0);
526 r300->hw.rb3d_cctl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_CCTL, 1);
527 ALLOC_STATE(bld, always, R300_BLD_CMDSIZE, 0);
528 r300->hw.bld.cmd[R300_BLD_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_CBLEND, 2);
529 ALLOC_STATE(cmk, always, R300_CMK_CMDSIZE, 0);
530 r300->hw.cmk.cmd[R300_CMK_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, RB3D_COLOR_CHANNEL_MASK, 1);
531 if (is_r500) {
532 ALLOC_STATE(blend_color, always, 3, 0);
533 r300->hw.blend_color.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R500_RB3D_CONSTANT_COLOR_AR, 2);
534 } else {
535 ALLOC_STATE(blend_color, always, 2, 0);
536 r300->hw.blend_color.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_BLEND_COLOR, 1);
537 }
538 ALLOC_STATE(rop, always, 2, 0);
539 r300->hw.rop.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_ROPCNTL, 1);
540 ALLOC_STATE(cb, always, R300_CB_CMDSIZE, 0);
541 r300->hw.cb.emit = &emit_cb_offset;
542 ALLOC_STATE(rb3d_dither_ctl, always, 10, 0);
543 r300->hw.rb3d_dither_ctl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_DITHER_CTL, 9);
544 ALLOC_STATE(rb3d_aaresolve_ctl, always, 2, 0);
545 r300->hw.rb3d_aaresolve_ctl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_AARESOLVE_CTL, 1);
546 ALLOC_STATE(rb3d_discard_src_pixel_lte_threshold, always, 3, 0);
547 r300->hw.rb3d_discard_src_pixel_lte_threshold.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R500_RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD, 2);
548 ALLOC_STATE(zs, always, R300_ZS_CMDSIZE, 0);
549 r300->hw.zs.cmd[R300_ZS_CMD_0] =
550 cmdpacket0(r300->radeon.radeonScreen, R300_ZB_CNTL, 3);
551
552 ALLOC_STATE(zstencil_format, always, 5, 0);
553 r300->hw.zstencil_format.cmd[0] =
554 cmdpacket0(r300->radeon.radeonScreen, R300_ZB_FORMAT, 4);
555 r300->hw.zstencil_format.emit = emit_zstencil_format;
556
557 ALLOC_STATE(zb, always, R300_ZB_CMDSIZE, 0);
558 r300->hw.zb.emit = emit_zb_offset;
559 ALLOC_STATE(zb_depthclearvalue, always, 2, 0);
560 r300->hw.zb_depthclearvalue.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_ZB_DEPTHCLEARVALUE, 1);
561 ALLOC_STATE(unk4F30, always, 3, 0);
562 r300->hw.unk4F30.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, 0x4F30, 2);
563 ALLOC_STATE(zb_hiz_offset, always, 2, 0);
564 r300->hw.zb_hiz_offset.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_ZB_HIZ_OFFSET, 1);
565 ALLOC_STATE(zb_hiz_pitch, always, 2, 0);
566 r300->hw.zb_hiz_pitch.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_ZB_HIZ_PITCH, 1);
567
568 /* VPU only on TCL */
569 if (has_tcl) {
570 int i;
571 ALLOC_STATE(vpi, vpu, R300_VPI_CMDSIZE, 0);
572 r300->hw.vpi.cmd[0] =
573 cmdvpu(r300->radeon.radeonScreen, R300_PVS_CODE_START, 0);
574 r300->hw.vpi.emit = emit_vpu;
575
576 if (is_r500) {
577 ALLOC_STATE(vpp, vpu, R300_VPP_CMDSIZE, 0);
578 r300->hw.vpp.cmd[0] =
579 cmdvpu(r300->radeon.radeonScreen, R500_PVS_CONST_START, 0);
580 r300->hw.vpp.emit = emit_vpu;
581
582 ALLOC_STATE(vps, vpu, R300_VPS_CMDSIZE, 0);
583 r300->hw.vps.cmd[0] =
584 cmdvpu(r300->radeon.radeonScreen, R500_POINT_VPORT_SCALE_OFFSET, 1);
585 r300->hw.vps.emit = emit_vpu;
586
587 for (i = 0; i < 6; i++) {
588 ALLOC_STATE(vpucp[i], vpu, R300_VPUCP_CMDSIZE, 0);
589 r300->hw.vpucp[i].cmd[0] =
590 cmdvpu(r300->radeon.radeonScreen,
591 R500_PVS_UCP_START + i, 1);
592 r300->hw.vpucp[i].emit = emit_vpu;
593 }
594 } else {
595 ALLOC_STATE(vpp, vpu, R300_VPP_CMDSIZE, 0);
596 r300->hw.vpp.cmd[0] =
597 cmdvpu(r300->radeon.radeonScreen, R300_PVS_CONST_START, 0);
598 r300->hw.vpp.emit = emit_vpu;
599
600 ALLOC_STATE(vps, vpu, R300_VPS_CMDSIZE, 0);
601 r300->hw.vps.cmd[0] =
602 cmdvpu(r300->radeon.radeonScreen, R300_POINT_VPORT_SCALE_OFFSET, 1);
603 r300->hw.vps.emit = emit_vpu;
604
605 for (i = 0; i < 6; i++) {
606 ALLOC_STATE(vpucp[i], vpu, R300_VPUCP_CMDSIZE, 0);
607 r300->hw.vpucp[i].cmd[0] =
608 cmdvpu(r300->radeon.radeonScreen,
609 R300_PVS_UCP_START + i, 1);
610 r300->hw.vpucp[i].emit = emit_vpu;
611 }
612 }
613 }
614
615 /* Textures */
616 ALLOC_STATE(tex.filter, variable, mtu + 1, 0);
617 r300->hw.tex.filter.cmd[R300_TEX_CMD_0] =
618 cmdpacket0(r300->radeon.radeonScreen, R300_TX_FILTER0_0, 0);
619
620 ALLOC_STATE(tex.filter_1, variable, mtu + 1, 0);
621 r300->hw.tex.filter_1.cmd[R300_TEX_CMD_0] =
622 cmdpacket0(r300->radeon.radeonScreen, R300_TX_FILTER1_0, 0);
623
624 ALLOC_STATE(tex.size, variable, mtu + 1, 0);
625 r300->hw.tex.size.cmd[R300_TEX_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_TX_SIZE_0, 0);
626
627 ALLOC_STATE(tex.format, variable, mtu + 1, 0);
628 r300->hw.tex.format.cmd[R300_TEX_CMD_0] =
629 cmdpacket0(r300->radeon.radeonScreen, R300_TX_FORMAT_0, 0);
630
631 ALLOC_STATE(tex.pitch, variable, mtu + 1, 0);
632 r300->hw.tex.pitch.cmd[R300_TEX_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_TX_FORMAT2_0, 0);
633
634 ALLOC_STATE(tex.offset, variable, 1, 0);
635 r300->hw.tex.offset.cmd[R300_TEX_CMD_0] =
636 cmdpacket0(r300->radeon.radeonScreen, R300_TX_OFFSET_0, 0);
637 r300->hw.tex.offset.emit = &emit_tex_offsets;
638
639 ALLOC_STATE(tex.chroma_key, variable, mtu + 1, 0);
640 r300->hw.tex.chroma_key.cmd[R300_TEX_CMD_0] =
641 cmdpacket0(r300->radeon.radeonScreen, R300_TX_CHROMA_KEY_0, 0);
642
643 ALLOC_STATE(tex.border_color, variable, mtu + 1, 0);
644 r300->hw.tex.border_color.cmd[R300_TEX_CMD_0] =
645 cmdpacket0(r300->radeon.radeonScreen, R300_TX_BORDER_COLOR_0, 0);
646
647 r300->radeon.hw.is_dirty = GL_TRUE;
648 r300->radeon.hw.all_dirty = GL_TRUE;
649
650 rcommonInitCmdBuf(&r300->radeon);
651 }
652
653 /**
654 * Destroy the command buffer and state atoms.
655 */
656 void r300DestroyCmdBuf(r300ContextPtr r300)
657 {
658 struct radeon_state_atom *atom;
659
660 foreach(atom, &r300->radeon.hw.atomlist) {
661 FREE(atom->cmd);
662 }
663
664 }