src/mesa/drivers/dri/r300/r300_cmdbuf.c

   1 /*
   2 Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
   3
   4 The Weather Channel (TM) funded Tungsten Graphics to develop the
   5 initial release of the Radeon 8500 driver under the XFree86 license.
   6 This notice must be preserved.
   7
   8 Permission is hereby granted, free of charge, to any person obtaining
   9 a copy of this software and associated documentation files (the
  10 "Software"), to deal in the Software without restriction, including
  11 without limitation the rights to use, copy, modify, merge, publish,
  12 distribute, sublicense, and/or sell copies of the Software, and to
  13 permit persons to whom the Software is furnished to do so, subject to
  14 the following conditions:
  15
  16 The above copyright notice and this permission notice (including the
  17 next paragraph) shall be included in all copies or substantial
  18 portions of the Software.
  19
  20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27
  28 **************************************************************************/
  29
  30 /*
  31  * Authors:
  32  *   Nicolai Haehnle <prefect_@gmx.net>
  33  */
  34
  35 #include "glheader.h"
  36 #include "state.h"
  37 #include "imports.h"
  38 #include "macros.h"
  39 #include "context.h"
  40 #include "swrast/swrast.h"
  41 #include "simple_list.h"
  42
  43 #include "drm.h"
  44 #include "radeon_drm.h"
  45
  46 #include "radeon_ioctl.h"
  47 #include "r300_context.h"
  48 #include "r300_ioctl.h"
  49 #include "radeon_reg.h"
  50 #include "r300_reg.h"
  51 #include "r300_cmdbuf.h"
  52
  53
  54 // Set this to 1 for extremely verbose debugging of command buffers
  55 #define DEBUG_CMDBUF            0
  56
  57
  58 /**
  59  * Send the current command buffer via ioctl to the hardware.
  60  */
  61 int r300FlushCmdBuf(r300ContextPtr r300, const char* caller)
  62 {
  63         int ret;
  64         int i;
  65         drm_radeon_cmd_buffer_t cmd;
  66         int start;
  67
  68         if (r300->radeon.lost_context)
  69                 start = 0;
  70         else
  71                 start = r300->cmdbuf.count_reemit;
  72
  73         if (RADEON_DEBUG & DEBUG_IOCTL) {
  74                 fprintf(stderr, "%s from %s - %i cliprects\n",
  75                         __FUNCTION__, caller, r300->radeon.numClipRects);
  76
  77                 if (DEBUG_CMDBUF && RADEON_DEBUG & DEBUG_VERBOSE)
  78                         for (i = start; i < r300->cmdbuf.count_used; ++i)
  79                                 fprintf(stderr, "%d: %08x\n", i,
  80                                         r300->cmdbuf.cmd_buf[i]);
  81         }
  82
  83         LOCK_HARDWARE(&r300->radeon);
  84
  85         cmd.buf = (char*)(r300->cmdbuf.cmd_buf + start);
  86         cmd.bufsz = (r300->cmdbuf.count_used - start) * 4;
  87
  88         if (r300->radeon.state.scissor.enabled) {
  89                 cmd.nbox = r300->radeon.state.scissor.numClipRects;
  90                 cmd.boxes = (drm_clip_rect_t *)r300->radeon.state.scissor.pClipRects;
  91         } else {
  92                 cmd.nbox = r300->radeon.numClipRects;
  93                 cmd.boxes = (drm_clip_rect_t *)r300->radeon.pClipRects;
  94         }
  95
  96         if (cmd.nbox) {
  97                 ret = drmCommandWrite(r300->radeon.dri.fd,
  98                                 DRM_RADEON_CMDBUF, &cmd, sizeof(cmd));
  99                 if (ret) {
 100                         UNLOCK_HARDWARE(&r300->radeon);
 101                         fprintf(stderr, "drmCommandWrite: %d\n", ret);
 102                         exit(-1);
 103                 }
 104
 105                 if (RADEON_DEBUG & DEBUG_SYNC) {
 106                         fprintf(stderr, "Syncing in %s\n\n", __FUNCTION__);
 107                         radeonWaitForIdleLocked(&r300->radeon);
 108                 }
 109         } else {
 110                 if (RADEON_DEBUG & DEBUG_IOCTL)
 111                         fprintf(stderr, "%s: No cliprects\n", __FUNCTION__);
 112         }
 113
 114         UNLOCK_HARDWARE(&r300->radeon);
 115
 116         r300->cmdbuf.count_used = 0;
 117         r300->cmdbuf.count_reemit = 0;
 118
 119         return 0;
 120 }
 121
 122
 123 static void print_state_atom(struct r300_state_atom *state, int dwords)
 124 {
 125         int i;
 126
 127         fprintf(stderr, "  emit %s/%d/%d\n", state->name, dwords, state->cmd_size);
 128
 129         if (RADEON_DEBUG & DEBUG_VERBOSE)
 130                 for (i = 0; i < dwords; i++)
 131                         fprintf(stderr, "      %s[%d]: %08X\n", state->name, i,
 132                                 state->cmd[i]);
 133 }
 134
 135 /**
 136  * Emit all atoms with a dirty field equal to dirty.
 137  *
 138  * The caller must have ensured that there is enough space in the command
 139  * buffer.
 140  */
 141 static __inline__ void r300DoEmitState(r300ContextPtr r300, GLboolean dirty)
 142 {
 143         struct r300_state_atom* atom;
 144         uint32_t* dest;
 145
 146         dest = r300->cmdbuf.cmd_buf + r300->cmdbuf.count_used;
 147
 148         if (DEBUG_CMDBUF && RADEON_DEBUG & DEBUG_STATE) {
 149                 foreach(atom, &r300->hw.atomlist) {
 150                         if ((atom->dirty || r300->hw.all_dirty) == dirty) {
 151                                 int dwords = (*atom->check)(r300, atom);
 152
 153                                 if (dwords)
 154                                         print_state_atom(atom, dwords);
 155                                 else
 156                                         fprintf(stderr, "  skip state %s\n",
 157                                                 atom->name);
 158                         }
 159                 }
 160         }
 161
 162         foreach(atom, &r300->hw.atomlist) {
 163                 if ((atom->dirty || r300->hw.all_dirty) == dirty) {
 164                         int dwords = (*atom->check)(r300, atom);
 165
 166                         if (dwords) {
 167                                 memcpy(dest, atom->cmd, dwords*4);
 168                                 dest += dwords;
 169                                 r300->cmdbuf.count_used += dwords;
 170                                 atom->dirty = GL_FALSE;
 171                         }
 172                 }
 173         }
 174 }
 175
 176
 177 /**
 178  * Copy dirty hardware state atoms into the command buffer.
 179  *
 180  * We also copy out clean state if we're at the start of a buffer. That makes
 181  * it easy to recover from lost contexts.
 182  */
 183 void r300EmitState(r300ContextPtr r300)
 184 {
 185         if (RADEON_DEBUG & (DEBUG_STATE | DEBUG_PRIMS))
 186                 fprintf(stderr, "%s\n", __FUNCTION__);
 187
 188         if (r300->cmdbuf.count_used && !r300->hw.is_dirty && !r300->hw.all_dirty)
 189                 return;
 190
 191         /* To avoid going across the entire set of states multiple times, just check
 192          * for enough space for the case of emitting all state, and inline the
 193          * r300AllocCmdBuf code here without all the checks.
 194          */
 195         r300EnsureCmdBufSpace(r300, r300->hw.max_state_size, __FUNCTION__);
 196
 197         if (!r300->cmdbuf.count_used) {
 198                 if (RADEON_DEBUG & DEBUG_STATE)
 199                         fprintf(stderr, "Begin reemit state\n");
 200
 201                 r300DoEmitState(r300, GL_FALSE);
 202                 r300->cmdbuf.count_reemit = r300->cmdbuf.count_used;
 203         }
 204
 205         if (RADEON_DEBUG & DEBUG_STATE)
 206                 fprintf(stderr, "Begin dirty state\n");
 207
 208         r300DoEmitState(r300, GL_TRUE);
 209
 210         assert(r300->cmdbuf.count_used < r300->cmdbuf.size);
 211
 212         r300->hw.is_dirty = GL_FALSE;
 213         r300->hw.all_dirty = GL_FALSE;
 214 }
 215
 216
 217 static __inline__ uint32_t cmducs(int reg, int count)
 218 {
 219         drm_r300_cmd_header_t cmd;
 220
 221         cmd.unchecked_state.cmd_type = R300_CMD_UNCHECKED_STATE;
 222         cmd.unchecked_state.count = count;
 223         cmd.unchecked_state.reghi = ((unsigned int)reg & 0xFF00) >> 8;
 224         cmd.unchecked_state.reglo = ((unsigned int)reg & 0x00FF);
 225
 226         return cmd.u;
 227 }
 228
 229 static __inline__ uint32_t cmdvpu(int addr, int count)
 230 {
 231         drm_r300_cmd_header_t cmd;
 232
 233         cmd.vpu.cmd_type = R300_CMD_VPU;
 234         cmd.vpu.count = count;
 235         cmd.vpu.adrhi = ((unsigned int)addr & 0xFF00) >> 8;
 236         cmd.vpu.adrlo = ((unsigned int)addr & 0x00FF);
 237
 238         return cmd.u;
 239 }
 240
 241 #define CHECK( NM, COUNT )                              \
 242 static int check_##NM( r300ContextPtr r300,             \
 243                         struct r300_state_atom* atom )  \
 244 {                                                       \
 245    (void) atom; (void) r300;                            \
 246    return (COUNT);                                      \
 247 }
 248
 249 #define ucscount(ptr) (((drm_r300_cmd_header_t*)(ptr))->unchecked_state.count)
 250 #define vpucount(ptr) (((drm_r300_cmd_header_t*)(ptr))->vpu.count)
 251
 252 CHECK( always, atom->cmd_size )
 253 CHECK( never, 0 )
 254 CHECK( variable, ucscount(atom->cmd) ? (1 + ucscount(atom->cmd)) : 0 )
 255 CHECK( vpu, vpucount(atom->cmd) ? (1 + vpucount(atom->cmd)*4) : 0 )
 256
 257 #undef ucscount
 258
 259 #define ALLOC_STATE( ATOM, CHK, SZ, NM, IDX )                           \
 260    do {                                                                 \
 261       r300->hw.ATOM.cmd_size = SZ;                                      \
 262       r300->hw.ATOM.cmd = (uint32_t*)CALLOC(SZ * sizeof(uint32_t));     \
 263       r300->hw.ATOM.name = NM;                                          \
 264       r300->hw.ATOM.idx = IDX;                                          \
 265       r300->hw.ATOM.check = check_##CHK;                                \
 266       r300->hw.ATOM.dirty = GL_FALSE;                                   \
 267       r300->hw.max_state_size += SZ;                                    \
 268    } while (0)
 269
 270
 271 /**
 272  * Allocate memory for the command buffer and initialize the state atom
 273  * list. Note that the initial hardware state is set by r300InitState().
 274  */
 275 void r300InitCmdBuf(r300ContextPtr r300)
 276 {
 277         int size, i, mtu;
 278
 279         r300->hw.max_state_size = 0;
 280
 281         mtu = r300->radeon.glCtx->Const.MaxTextureUnits;
 282         fprintf(stderr, "Using %d maximum texture units..\n", mtu);
 283
 284         /* Initialize state atoms */
 285         ALLOC_STATE( vpt, always, R300_VPT_CMDSIZE, "vpt", 0 );
 286                 r300->hw.vpt.cmd[R300_VPT_CMD_0] = cmducs(R300_SE_VPORT_XSCALE, 6);
 287         ALLOC_STATE( unk2080, always, 2, "unk2080", 0 );
 288                 r300->hw.unk2080.cmd[0] = cmducs(0x2080, 1);
 289         ALLOC_STATE( ovf, always, R300_OVF_CMDSIZE, "ovf", 0 );
 290                 r300->hw.ovf.cmd[R300_OVF_CMD_0] = cmducs(R300_VAP_OUTPUT_VTX_FMT_0, 2);
 291         ALLOC_STATE( vte, always, 3, "vte", 0 );
 292                 r300->hw.vte.cmd[0] = cmducs(R300_SE_VTE_CNTL, 2);
 293         ALLOC_STATE( unk2134, always, 3, "unk2134", 0 );
 294                 r300->hw.unk2134.cmd[0] = cmducs(0x2134, 2);
 295         ALLOC_STATE( unk2140, always, 2, "unk2140", 0 );
 296                 r300->hw.unk2140.cmd[0] = cmducs(0x2140, 1);
 297         ALLOC_STATE( vir[0], variable, R300_VIR_CMDSIZE, "vir/0", 0 );
 298                 r300->hw.vir[0].cmd[R300_VIR_CMD_0] = cmducs(R300_VAP_INPUT_ROUTE_0_0, 1);
 299         ALLOC_STATE( vir[1], variable, R300_VIR_CMDSIZE, "vir/1", 1 );
 300                 r300->hw.vir[1].cmd[R300_VIR_CMD_0] = cmducs(R300_VAP_INPUT_ROUTE_1_0, 1);
 301         ALLOC_STATE( vic, always, R300_VIC_CMDSIZE, "vic", 0 );
 302                 r300->hw.vic.cmd[R300_VIC_CMD_0] = cmducs(R300_VAP_INPUT_CNTL_0, 2);
 303         ALLOC_STATE( unk21DC, always, 2, "unk21DC", 0 );
 304                 r300->hw.unk21DC.cmd[0] = cmducs(0x21DC, 1);
 305         ALLOC_STATE( unk221C, always, 2, "unk221C", 0 );
 306                 r300->hw.unk221C.cmd[0] = cmducs(0x221C, 1);
 307         ALLOC_STATE( unk2220, always, 5, "unk2220", 0 );
 308                 r300->hw.unk2220.cmd[0] = cmducs(0x2220, 4);
 309         ALLOC_STATE( unk2288, always, 2, "unk2288", 0 );
 310                 r300->hw.unk2288.cmd[0] = cmducs(0x2288, 1);
 311         ALLOC_STATE( vof, always, R300_VOF_CMDSIZE, "vof", 0 );
 312                 r300->hw.vof.cmd[R300_VOF_CMD_0] = cmducs(R300_VAP_OUTPUT_VTX_FMT_0, 2);
 313         ALLOC_STATE( pvs, always, R300_PVS_CMDSIZE, "pvs", 0 );
 314                 r300->hw.pvs.cmd[R300_PVS_CMD_0] = cmducs(R300_VAP_PVS_CNTL_1, 3);
 315         ALLOC_STATE( gb_enable, always, 2, "gb_enable", 0 );
 316                 r300->hw.gb_enable.cmd[0] = cmducs(R300_GB_ENABLE, 1);
 317         ALLOC_STATE( gb_misc, always, R300_GB_MISC_CMDSIZE, "gb_misc", 0 );
 318                 r300->hw.gb_misc.cmd[0] = cmducs(R300_GB_MSPOS0, 5);
 319         ALLOC_STATE( txe, always, R300_TXE_CMDSIZE, "txe", 0 );
 320                 r300->hw.txe.cmd[R300_TXE_CMD_0] = cmducs(R300_TX_ENABLE, 1);
 321         ALLOC_STATE( unk4200, always, 5, "unk4200", 0 );
 322                 r300->hw.unk4200.cmd[0] = cmducs(0x4200, 4);
 323         ALLOC_STATE( unk4214, always, 2, "unk4214", 0 );
 324                 r300->hw.unk4214.cmd[0] = cmducs(0x4214, 1);
 325         ALLOC_STATE( ps, always, R300_PS_CMDSIZE, "ps", 0 );
 326                 r300->hw.ps.cmd[0] = cmducs(R300_RE_POINTSIZE, 1);
 327         ALLOC_STATE( unk4230, always, 4, "unk4230", 0 );
 328                 r300->hw.unk4230.cmd[0] = cmducs(0x4230, 3);
 329         ALLOC_STATE( unk4260, always, 4, "unk4260", 0 );
 330                 r300->hw.unk4260.cmd[0] = cmducs(0x4260, 3);
 331         ALLOC_STATE( unk4274, always, 5, "unk4274", 0 );
 332                 r300->hw.unk4274.cmd[0] = cmducs(0x4274, 4);
 333         ALLOC_STATE( unk4288, always, 6, "unk4288", 0 );
 334                 r300->hw.unk4288.cmd[0] = cmducs(0x4288, 5);
 335         ALLOC_STATE( unk42A0, always, 2, "unk42A0", 0 );
 336                 r300->hw.unk42A0.cmd[0] = cmducs(0x42A0, 1);
 337         ALLOC_STATE( unk42B4, always, 2, "unk42B4", 0 );
 338                 r300->hw.unk42B4.cmd[0] = cmducs(0x42B4, 1);
 339         ALLOC_STATE( cul, always, R300_CUL_CMDSIZE, "cul", 0 );
 340                 r300->hw.cul.cmd[R300_CUL_CMD_0] = cmducs(R300_RE_CULL_CNTL, 1);
 341         ALLOC_STATE( unk42C0, always, 3, "unk42C0", 0 );
 342                 r300->hw.unk42C0.cmd[0] = cmducs(0x42C0, 2);
 343         ALLOC_STATE( rc, always, R300_RC_CMDSIZE, "rc", 0 );
 344                 r300->hw.rc.cmd[R300_RC_CMD_0] = cmducs(R300_RS_CNTL_0, 2);
 345         ALLOC_STATE( ri, always, R300_RI_CMDSIZE, "ri", 0 );
 346                 r300->hw.ri.cmd[R300_RI_CMD_0] = cmducs(R300_RS_INTERP_0, 8);
 347         ALLOC_STATE( rr, variable, R300_RR_CMDSIZE, "rr", 0 );
 348                 r300->hw.rr.cmd[R300_RR_CMD_0] = cmducs(R300_RS_ROUTE_0, 1);
 349         ALLOC_STATE( unk43A4, always, 3, "unk43A4", 0 );
 350                 r300->hw.unk43A4.cmd[0] = cmducs(0x43A4, 2);
 351         ALLOC_STATE( unk43E8, always, 2, "unk43E8", 0 );
 352                 r300->hw.unk43E8.cmd[0] = cmducs(0x43E8, 1);
 353         ALLOC_STATE( fp, always, R300_FP_CMDSIZE, "fp", 0 );
 354                 r300->hw.fp.cmd[R300_FP_CMD_0] = cmducs(R300_PFS_CNTL_0, 3);
 355                 r300->hw.fp.cmd[R300_FP_CMD_1] = cmducs(R300_PFS_NODE_0, 4);
 356         ALLOC_STATE( unk46A4, always, 6, "unk46A4", 0 );
 357                 r300->hw.unk46A4.cmd[0] = cmducs(0x46A4, 5);
 358         ALLOC_STATE( fpi[0], variable, R300_FPI_CMDSIZE, "fpi/0", 0 );
 359                 r300->hw.fpi[0].cmd[R300_FPI_CMD_0] = cmducs(R300_PFS_INSTR0_0, 1);
 360         ALLOC_STATE( fpi[1], variable, R300_FPI_CMDSIZE, "fpi/1", 1 );
 361                 r300->hw.fpi[1].cmd[R300_FPI_CMD_0] = cmducs(R300_PFS_INSTR1_0, 1);
 362         ALLOC_STATE( fpi[2], variable, R300_FPI_CMDSIZE, "fpi/2", 2 );
 363                 r300->hw.fpi[2].cmd[R300_FPI_CMD_0] = cmducs(R300_PFS_INSTR2_0, 1);
 364         ALLOC_STATE( fpi[3], variable, R300_FPI_CMDSIZE, "fpi/3", 3 );
 365                 r300->hw.fpi[3].cmd[R300_FPI_CMD_0] = cmducs(R300_PFS_INSTR3_0, 1);
 366         ALLOC_STATE( unk4BC0, always, 2, "unk4BC0", 0 );
 367                 r300->hw.unk4BC0.cmd[0] = cmducs(0x4BC0, 1);
 368         ALLOC_STATE( unk4BC8, always, 4, "unk4BC8", 0 );
 369                 r300->hw.unk4BC8.cmd[0] = cmducs(0x4BC8, 3);
 370         ALLOC_STATE( at, always, R300_AT_CMDSIZE, "at", 0 );
 371                 r300->hw.at.cmd[R300_AT_CMD_0] = cmducs(R300_PP_ALPHA_TEST, 1);
 372         ALLOC_STATE( unk4BD8, always, 2, "unk4BD8", 0 );
 373                 r300->hw.unk4BD8.cmd[0] = cmducs(0x4BD8, 1);
 374         ALLOC_STATE( unk4E00, always, 2, "unk4E00", 0 );
 375                 r300->hw.unk4E00.cmd[0] = cmducs(0x4E00, 1);
 376         ALLOC_STATE( bld, always, R300_BLD_CMDSIZE, "bld", 0 );
 377                 r300->hw.bld.cmd[R300_BLD_CMD_0] = cmducs(R300_RB3D_CBLEND, 2);
 378         ALLOC_STATE( cmk, always, R300_CMK_CMDSIZE, "cmk", 0 );
 379                 r300->hw.cmk.cmd[R300_CMK_CMD_0] = cmducs(R300_RB3D_COLORMASK, 1);
 380         ALLOC_STATE( unk4E10, always, 4, "unk4E10", 0 );
 381                 r300->hw.unk4E10.cmd[0] = cmducs(0x4E10, 3);
 382         ALLOC_STATE( cb, always, R300_CB_CMDSIZE, "cb", 0 );
 383                 r300->hw.cb.cmd[R300_CB_CMD_0] = cmducs(R300_RB3D_COLOROFFSET0, 1);
 384                 r300->hw.cb.cmd[R300_CB_CMD_1] = cmducs(R300_RB3D_COLORPITCH0, 1);
 385         ALLOC_STATE( unk4E50, always, 10, "unk4E50", 0 );
 386                 r300->hw.unk4E50.cmd[0] = cmducs(0x4E50, 9);
 387         ALLOC_STATE( unk4E88, always, 2, "unk4E88", 0 );
 388                 r300->hw.unk4E88.cmd[0] = cmducs(0x4E88, 1);
 389         ALLOC_STATE( unk4EA0, always, 3, "unk4EA0 R350 only", 0 );
 390                 r300->hw.unk4EA0.cmd[0] = cmducs(0x4EA0, 2);
 391         ALLOC_STATE( zc, always, R300_ZC_CMDSIZE, "zc", 0 );
 392                 r300->hw.zc.cmd[R300_ZC_CMD_0] = cmducs(R300_RB3D_ZCNTL_0, 2);
 393         ALLOC_STATE( unk4F08, always, 2, "unk4F08", 0 );
 394                 r300->hw.unk4F08.cmd[0] = cmducs(0x4F08, 1);
 395         ALLOC_STATE( unk4F10, always, 5, "unk4F10", 0 );
 396                 r300->hw.unk4F10.cmd[0] = cmducs(0x4F10, 4);
 397         ALLOC_STATE( zb, always, R300_ZB_CMDSIZE, "zb", 0 );
 398                 r300->hw.zb.cmd[R300_ZB_CMD_0] = cmducs(R300_RB3D_DEPTHOFFSET, 2);
 399         ALLOC_STATE( unk4F28, always, 2, "unk4F28", 0 );
 400                 r300->hw.unk4F28.cmd[0] = cmducs(0x4F28, 1);
 401         ALLOC_STATE( unk4F30, always, 3, "unk4F30", 0 );
 402                 r300->hw.unk4F30.cmd[0] = cmducs(0x4F30, 2);
 403         ALLOC_STATE( unk4F44, always, 2, "unk4F44", 0 );
 404                 r300->hw.unk4F44.cmd[0] = cmducs(0x4F44, 1);
 405         ALLOC_STATE( unk4F54, always, 2, "unk4F54", 0 );
 406                 r300->hw.unk4F54.cmd[0] = cmducs(0x4F54, 1);
 407
 408         ALLOC_STATE( vpi, vpu, R300_VPI_CMDSIZE, "vpi", 0 );
 409                 r300->hw.vpi.cmd[R300_VPI_CMD_0] = cmdvpu(R300_PVS_UPLOAD_PROGRAM, 0);
 410         ALLOC_STATE( vpp, vpu, R300_VPP_CMDSIZE, "vpp", 0 );
 411                 r300->hw.vpp.cmd[R300_VPP_CMD_0] = cmdvpu(R300_PVS_UPLOAD_PARAMETERS, 0);
 412         ALLOC_STATE( vps, vpu, R300_VPS_CMDSIZE, "vps", 0 );
 413                 r300->hw.vps.cmd[R300_VPS_CMD_0] = cmdvpu(R300_PVS_UPLOAD_POINTSIZE, 1);
 414
 415         /* Textures */
 416         ALLOC_STATE( tex.filter, always, mtu, "tex_filter", 0 );
 417                 r300->hw.tex.filter.cmd[R300_TEX_CMD_0] = cmducs(R300_TX_FILTER_0, mtu-1);
 418
 419         ALLOC_STATE( tex.unknown1, always, mtu, "tex_unknown1", 0 );
 420                 r300->hw.tex.unknown1.cmd[R300_TEX_CMD_0] = cmducs(R300_TX_UNK1_0, mtu-1);
 421
 422         ALLOC_STATE( tex.size, always, mtu, "tex_size", 0 );
 423                 r300->hw.tex.size.cmd[R300_TEX_CMD_0] = cmducs(R300_TX_SIZE_0, mtu-1);
 424
 425         ALLOC_STATE( tex.format, always, mtu, "tex_format", 0 );
 426                 r300->hw.tex.format.cmd[R300_TEX_CMD_0] = cmducs(R300_TX_FORMAT_0, mtu-1);
 427
 428         ALLOC_STATE( tex.offset, always, mtu, "tex_offset", 0 );
 429                 r300->hw.tex.offset.cmd[R300_TEX_CMD_0] = cmducs(R300_TX_OFFSET_0, mtu-1);
 430
 431         ALLOC_STATE( tex.unknown4, always, mtu, "tex_unknown4", 0 );
 432                 r300->hw.tex.unknown4.cmd[R300_TEX_CMD_0] = cmducs(R300_TX_UNK4_0, mtu-1);
 433
 434         ALLOC_STATE( tex.unknown5, always, mtu, "tex_unknown5", 0 );
 435                 r300->hw.tex.unknown5.cmd[R300_TEX_CMD_0] = cmducs(R300_TX_UNK5_0, mtu-1);
 436
 437
 438         /* Setup the atom linked list */
 439         make_empty_list(&r300->hw.atomlist);
 440         r300->hw.atomlist.name = "atom-list";
 441
 442         insert_at_tail(&r300->hw.atomlist, &r300->hw.vpt);
 443         insert_at_tail(&r300->hw.atomlist, &r300->hw.unk2080);
 444         insert_at_tail(&r300->hw.atomlist, &r300->hw.ovf);
 445         insert_at_tail(&r300->hw.atomlist, &r300->hw.vte);
 446         insert_at_tail(&r300->hw.atomlist, &r300->hw.unk2134);
 447         insert_at_tail(&r300->hw.atomlist, &r300->hw.unk2140);
 448         insert_at_tail(&r300->hw.atomlist, &r300->hw.vir[0]);
 449         insert_at_tail(&r300->hw.atomlist, &r300->hw.vir[1]);
 450         insert_at_tail(&r300->hw.atomlist, &r300->hw.vic);
 451         insert_at_tail(&r300->hw.atomlist, &r300->hw.unk21DC);
 452         insert_at_tail(&r300->hw.atomlist, &r300->hw.unk221C);
 453         insert_at_tail(&r300->hw.atomlist, &r300->hw.unk2220);
 454         insert_at_tail(&r300->hw.atomlist, &r300->hw.unk2288);
 455         insert_at_tail(&r300->hw.atomlist, &r300->hw.vof);
 456         insert_at_tail(&r300->hw.atomlist, &r300->hw.pvs);
 457         insert_at_tail(&r300->hw.atomlist, &r300->hw.gb_enable);
 458         insert_at_tail(&r300->hw.atomlist, &r300->hw.gb_misc);
 459         insert_at_tail(&r300->hw.atomlist, &r300->hw.txe);
 460         insert_at_tail(&r300->hw.atomlist, &r300->hw.unk4200);
 461         insert_at_tail(&r300->hw.atomlist, &r300->hw.unk4214);
 462         insert_at_tail(&r300->hw.atomlist, &r300->hw.ps);
 463         insert_at_tail(&r300->hw.atomlist, &r300->hw.unk4230);
 464         insert_at_tail(&r300->hw.atomlist, &r300->hw.unk4260);
 465         insert_at_tail(&r300->hw.atomlist, &r300->hw.unk4274);
 466         insert_at_tail(&r300->hw.atomlist, &r300->hw.unk4288);
 467         insert_at_tail(&r300->hw.atomlist, &r300->hw.unk42A0);
 468         insert_at_tail(&r300->hw.atomlist, &r300->hw.unk42B4);
 469         insert_at_tail(&r300->hw.atomlist, &r300->hw.cul);
 470         insert_at_tail(&r300->hw.atomlist, &r300->hw.unk42C0);
 471         insert_at_tail(&r300->hw.atomlist, &r300->hw.rc);
 472         insert_at_tail(&r300->hw.atomlist, &r300->hw.ri);
 473         insert_at_tail(&r300->hw.atomlist, &r300->hw.rr);
 474         insert_at_tail(&r300->hw.atomlist, &r300->hw.unk43A4);
 475         insert_at_tail(&r300->hw.atomlist, &r300->hw.unk43E8);
 476         insert_at_tail(&r300->hw.atomlist, &r300->hw.fp);
 477         insert_at_tail(&r300->hw.atomlist, &r300->hw.unk46A4);
 478         insert_at_tail(&r300->hw.atomlist, &r300->hw.fpi[0]);
 479         insert_at_tail(&r300->hw.atomlist, &r300->hw.fpi[1]);
 480         insert_at_tail(&r300->hw.atomlist, &r300->hw.fpi[2]);
 481         insert_at_tail(&r300->hw.atomlist, &r300->hw.fpi[3]);
 482         insert_at_tail(&r300->hw.atomlist, &r300->hw.unk4BC0);
 483         insert_at_tail(&r300->hw.atomlist, &r300->hw.unk4BC8);
 484         insert_at_tail(&r300->hw.atomlist, &r300->hw.at);
 485         insert_at_tail(&r300->hw.atomlist, &r300->hw.unk4BD8);
 486         insert_at_tail(&r300->hw.atomlist, &r300->hw.unk4E00);
 487         insert_at_tail(&r300->hw.atomlist, &r300->hw.bld);
 488         insert_at_tail(&r300->hw.atomlist, &r300->hw.cmk);
 489         insert_at_tail(&r300->hw.atomlist, &r300->hw.unk4E10);
 490         insert_at_tail(&r300->hw.atomlist, &r300->hw.cb);
 491         insert_at_tail(&r300->hw.atomlist, &r300->hw.unk4E50);
 492         insert_at_tail(&r300->hw.atomlist, &r300->hw.unk4E88);
 493         insert_at_tail(&r300->hw.atomlist, &r300->hw.unk4EA0);
 494         insert_at_tail(&r300->hw.atomlist, &r300->hw.zc);
 495         insert_at_tail(&r300->hw.atomlist, &r300->hw.unk4F08);
 496         insert_at_tail(&r300->hw.atomlist, &r300->hw.unk4F10);
 497         insert_at_tail(&r300->hw.atomlist, &r300->hw.zb);
 498         insert_at_tail(&r300->hw.atomlist, &r300->hw.unk4F28);
 499         insert_at_tail(&r300->hw.atomlist, &r300->hw.unk4F30);
 500         insert_at_tail(&r300->hw.atomlist, &r300->hw.unk4F44);
 501         insert_at_tail(&r300->hw.atomlist, &r300->hw.unk4F54);
 502
 503         insert_at_tail(&r300->hw.atomlist, &r300->hw.vpi);
 504         insert_at_tail(&r300->hw.atomlist, &r300->hw.vpp);
 505         insert_at_tail(&r300->hw.atomlist, &r300->hw.vps);
 506
 507         insert_at_tail(&r300->hw.atomlist, &r300->hw.tex.filter);
 508         insert_at_tail(&r300->hw.atomlist, &r300->hw.tex.unknown1);
 509         insert_at_tail(&r300->hw.atomlist, &r300->hw.tex.size);
 510         insert_at_tail(&r300->hw.atomlist, &r300->hw.tex.format);
 511         insert_at_tail(&r300->hw.atomlist, &r300->hw.tex.offset);
 512         insert_at_tail(&r300->hw.atomlist, &r300->hw.tex.unknown4);
 513         insert_at_tail(&r300->hw.atomlist, &r300->hw.tex.unknown5);
 514
 515         r300->hw.is_dirty = GL_TRUE;
 516         r300->hw.all_dirty = GL_TRUE;
 517
 518         /* Initialize command buffer */
 519         size = 256 * driQueryOptioni(&r300->radeon.optionCache, "command_buffer_size");
 520         if (size < 2*r300->hw.max_state_size)
 521                 size = 2*r300->hw.max_state_size;
 522
 523         if (RADEON_DEBUG & DEBUG_IOCTL)
 524                 fprintf(stderr,
 525                         "Allocating %d bytes command buffer (max state is %d bytes)\n",
 526                         size*4, r300->hw.max_state_size*4);
 527
 528         r300->cmdbuf.size = size;
 529         r300->cmdbuf.cmd_buf = (uint32_t*)CALLOC(size*4);
 530         r300->cmdbuf.count_used = 0;
 531         r300->cmdbuf.count_reemit = 0;
 532 }
 533
 534
 535 /**
 536  * Destroy the command buffer and state atoms.
 537  */
 538 void r300DestroyCmdBuf(r300ContextPtr r300)
 539 {
 540         struct r300_state_atom* atom;
 541
 542         FREE(r300->cmdbuf.cmd_buf);
 543
 544         foreach(atom, &r300->hw.atomlist) {
 545                 FREE(atom->cmd);
 546         }
 547 }
 548
 549 void r300EmitBlit(r300ContextPtr rmesa,
 550                   GLuint color_fmt,
 551                   GLuint src_pitch,
 552                   GLuint src_offset,
 553                   GLuint dst_pitch,
 554                   GLuint dst_offset,
 555                   GLint srcx, GLint srcy,
 556                   GLint dstx, GLint dsty, GLuint w, GLuint h)
 557 {
 558         drm_radeon_cmd_header_t *cmd;
 559
 560         if (RADEON_DEBUG & DEBUG_IOCTL)
 561                 fprintf(stderr,
 562                         "%s src %x/%x %d,%d dst: %x/%x %d,%d sz: %dx%d\n",
 563                         __FUNCTION__, src_pitch, src_offset, srcx, srcy,
 564                         dst_pitch, dst_offset, dstx, dsty, w, h);
 565
 566         assert((src_pitch & 63) == 0);
 567         assert((dst_pitch & 63) == 0);
 568         assert((src_offset & 1023) == 0);
 569         assert((dst_offset & 1023) == 0);
 570         assert(w < (1 << 16));
 571         assert(h < (1 << 16));
 572
 573         cmd =
 574             (drm_radeon_cmd_header_t *) r200AllocCmdBuf(rmesa, 8 * sizeof(int),
 575                                                         __FUNCTION__);
 576
 577         cmd[0].header.cmd_type = RADEON_CMD_PACKET3;
 578         cmd[1].i = R200_CP_CMD_BITBLT_MULTI | (5 << 16);
 579         cmd[2].i = (RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
 580                     RADEON_GMC_DST_PITCH_OFFSET_CNTL |
 581                     RADEON_GMC_BRUSH_NONE |
 582                     (color_fmt << 8) |
 583                     RADEON_GMC_SRC_DATATYPE_COLOR |
 584                     RADEON_ROP3_S |
 585                     RADEON_DP_SRC_SOURCE_MEMORY |
 586                     RADEON_GMC_CLR_CMP_CNTL_DIS | RADEON_GMC_WR_MSK_DIS);
 587
 588         cmd[3].i = ((src_pitch / 64) << 22) | (src_offset >> 10);
 589         cmd[4].i = ((dst_pitch / 64) << 22) | (dst_offset >> 10);
 590         cmd[5].i = (srcx << 16) | srcy;
 591         cmd[6].i = (dstx << 16) | dsty; /* dst */
 592         cmd[7].i = (w << 16) | h;
 593 }
 594
 595 void r300EmitWait(r300ContextPtr rmesa, GLuint flags)
 596 {
 597         if (rmesa->radeon.dri.drmMinor >= 6) {
 598                 drm_radeon_cmd_header_t *cmd;
 599
 600                 assert(!(flags & ~(RADEON_WAIT_2D | RADEON_WAIT_3D)));
 601
 602                 cmd =
 603                     (drm_radeon_cmd_header_t *) r200AllocCmdBuf(rmesa,
 604                                                                 1 * sizeof(int),
 605                                                                 __FUNCTION__);
 606                 cmd[0].i = 0;
 607                 cmd[0].wait.cmd_type = RADEON_CMD_WAIT;
 608                 cmd[0].wait.flags = flags;
 609         }
 610 }